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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_rcc_ex.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V1.0.1 |
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| 6 | * @date 31-July-2015 |
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| 7 | * @brief Extended RCC HAL module driver. |
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| 8 | * This file provides firmware functions to manage the following |
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| 9 | * functionalities RCC extension peripheral: |
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| 10 | * + Extended Peripheral Control functions |
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| 11 | * |
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| 12 | ****************************************************************************** |
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| 13 | * @attention |
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| 14 | * |
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| 15 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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| 16 | * |
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| 17 | * Redistribution and use in source and binary forms, with or without modification, |
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| 18 | * are permitted provided that the following conditions are met: |
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| 19 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 20 | * this list of conditions and the following disclaimer. |
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| 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 22 | * this list of conditions and the following disclaimer in the documentation |
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| 23 | * and/or other materials provided with the distribution. |
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| 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 25 | * may be used to endorse or promote products derived from this software |
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| 26 | * without specific prior written permission. |
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| 27 | * |
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| 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 38 | * |
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| 39 | ****************************************************************************** |
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| 40 | */ |
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| 41 | |||
| 42 | /* Includes ------------------------------------------------------------------*/ |
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| 43 | #include "stm32f1xx_hal.h" |
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| 44 | |||
| 45 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 46 | * @{ |
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| 47 | */ |
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| 48 | |||
| 49 | #ifdef HAL_RCC_MODULE_ENABLED |
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| 50 | |||
| 51 | /** @defgroup RCCEx RCCEx |
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| 52 | * @brief RCC Extension HAL module driver. |
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| 53 | * @{ |
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| 54 | */ |
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| 55 | |||
| 56 | /* Private typedef -----------------------------------------------------------*/ |
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| 57 | /* Private define ------------------------------------------------------------*/ |
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| 58 | /** @defgroup RCCEx_Private_Constants RCCEx Private Constants |
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| 59 | * @{ |
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| 60 | */ |
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| 61 | /** |
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| 62 | * @} |
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| 63 | */ |
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| 64 | |||
| 65 | /* Private macro -------------------------------------------------------------*/ |
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| 66 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
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| 67 | * @{ |
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| 68 | */ |
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| 69 | /** |
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| 70 | * @} |
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| 71 | */ |
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| 72 | |||
| 73 | /* Private variables ---------------------------------------------------------*/ |
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| 74 | /* Private function prototypes -----------------------------------------------*/ |
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| 75 | /* Private functions ---------------------------------------------------------*/ |
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| 76 | |||
| 77 | /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions |
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| 78 | * @{ |
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| 79 | */ |
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| 80 | |||
| 81 | /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions |
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| 82 | * @brief Extended Peripheral Control functions |
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| 83 | * |
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| 84 | @verbatim |
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| 85 | =============================================================================== |
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| 86 | ##### Extended Peripheral Control functions ##### |
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| 87 | =============================================================================== |
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| 88 | [..] |
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| 89 | This subsection provides a set of functions allowing to control the RCC Clocks |
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| 90 | frequencies. |
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| 91 | [..] |
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| 92 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
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| 93 | select the RTC clock source; in this case the Backup domain will be reset in |
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| 94 | order to modify the RTC Clock source, as consequence RTC registers (including |
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| 95 | the backup registers) and RCC_BDCR register are set to their reset values. |
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| 96 | |||
| 97 | @endverbatim |
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| 98 | * @{ |
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| 99 | */ |
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| 100 | |||
| 101 | /** |
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| 102 | * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the |
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| 103 | * RCC_PeriphCLKInitTypeDef. |
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| 104 | * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
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| 105 | * contains the configuration information for the Extended Peripherals clocks(RTC clock). |
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| 106 | * |
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| 107 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select |
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| 108 | * the RTC clock source; in this case the Backup domain will be reset in |
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| 109 | * order to modify the RTC Clock source, as consequence RTC registers (including |
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| 110 | * the backup registers) are set to their reset values. |
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| 111 | * |
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| 112 | * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on |
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| 113 | * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to |
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| 114 | * manually disable it. |
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| 115 | * |
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| 116 | * @retval HAL status |
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| 117 | */ |
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| 118 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
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| 119 | { |
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| 120 | uint32_t tickstart = 0, temp_reg = 0; |
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| 121 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 122 | uint32_t pllactive = 0; |
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| 123 | #endif /* STM32F105xC || STM32F107xC */ |
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| 124 | |||
| 125 | /* Check the parameters */ |
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| 126 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
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| 127 | |||
| 128 | /*------------------------------- RTC/LCD Configuration ------------------------*/ |
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| 129 | if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
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| 130 | { |
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| 131 | /* check for RTC Parameters used to output RTCCLK */ |
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| 132 | assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); |
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| 133 | |||
| 134 | /* Enable Power Clock*/ |
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| 135 | __HAL_RCC_PWR_CLK_ENABLE(); |
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| 136 | |||
| 137 | /* Enable write access to Backup domain */ |
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| 138 | SET_BIT(PWR->CR, PWR_CR_DBP); |
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| 139 | |||
| 140 | /* Wait for Backup domain Write protection disable */ |
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| 141 | tickstart = HAL_GetTick(); |
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| 142 | |||
| 143 | while((PWR->CR & PWR_CR_DBP) == RESET) |
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| 144 | { |
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| 145 | if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) |
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| 146 | { |
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| 147 | return HAL_TIMEOUT; |
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| 148 | } |
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| 149 | } |
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| 150 | |||
| 151 | /* Reset the Backup domain only if the RTC Clock source selection is modified */ |
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| 152 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) |
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| 153 | { |
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| 154 | /* Store the content of BDCR register before the reset of Backup Domain */ |
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| 155 | temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
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| 156 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
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| 157 | __HAL_RCC_BACKUPRESET_FORCE(); |
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| 158 | __HAL_RCC_BACKUPRESET_RELEASE(); |
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| 159 | /* Restore the Content of BDCR register */ |
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| 160 | RCC->BDCR = temp_reg; |
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| 161 | |||
| 162 | /* Wait for LSERDY if LSE was enabled */ |
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| 163 | if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)) |
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| 164 | { |
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| 165 | /* Get timeout */ |
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| 166 | tickstart = HAL_GetTick(); |
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| 167 | |||
| 168 | /* Wait till LSE is ready */ |
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| 169 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
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| 170 | { |
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| 171 | if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) |
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| 172 | { |
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| 173 | return HAL_TIMEOUT; |
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| 174 | } |
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| 175 | } |
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| 176 | } |
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| 177 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
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| 178 | } |
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| 179 | } |
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| 180 | |||
| 181 | /*------------------------------ ADC clock Configuration ------------------*/ |
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| 182 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) |
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| 183 | { |
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| 184 | /* Check the parameters */ |
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| 185 | assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); |
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| 186 | |||
| 187 | /* Configure the ADC clock source */ |
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| 188 | __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); |
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| 189 | } |
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| 190 | |||
| 191 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 192 | /*------------------------------ I2S2 Configuration ------------------------*/ |
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| 193 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) |
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| 194 | { |
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| 195 | /* Check the parameters */ |
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| 196 | assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); |
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| 197 | |||
| 198 | /* Configure the I2S2 clock source */ |
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| 199 | __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); |
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| 200 | } |
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| 201 | |||
| 202 | /*------------------------------ I2S3 Configuration ------------------------*/ |
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| 203 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) |
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| 204 | { |
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| 205 | /* Check the parameters */ |
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| 206 | assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); |
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| 207 | |||
| 208 | /* Configure the I2S3 clock source */ |
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| 209 | __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); |
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| 210 | } |
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| 211 | |||
| 212 | /*------------------------------ PLL I2S Configuration ----------------------*/ |
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| 213 | /* Check that PLLI2S need to be enabled */ |
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| 214 | if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) |
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| 215 | { |
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| 216 | /* Update flag to indicate that PLL I2S should be active */ |
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| 217 | pllactive = 1; |
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| 218 | } |
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| 219 | |||
| 220 | /* Check if PLL I2S need to be enabled */ |
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| 221 | if (pllactive == 1) |
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| 222 | { |
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| 223 | /* Enable PLL I2S only if not active */ |
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| 224 | if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) |
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| 225 | { |
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| 226 | /* Check the parameters */ |
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| 227 | assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); |
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| 228 | assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); |
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| 229 | |||
| 230 | /* Prediv2 can be written only when the PLL2 is disabled. */ |
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| 231 | /* Return an error only if new value is different from the programmed value */ |
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| 232 | if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \ |
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| 233 | (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) |
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| 234 | { |
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| 235 | return HAL_ERROR; |
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| 236 | } |
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| 237 | |||
| 238 | /* Configure the HSE prediv2 factor --------------------------------*/ |
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| 239 | __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); |
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| 240 | |||
| 241 | /* Configure the main PLLI2S multiplication factors. */ |
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| 242 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); |
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| 243 | |||
| 244 | /* Enable the main PLLI2S. */ |
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| 245 | __HAL_RCC_PLLI2S_ENABLE(); |
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| 246 | |||
| 247 | /* Get Start Tick*/ |
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| 248 | tickstart = HAL_GetTick(); |
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| 249 | |||
| 250 | /* Wait till PLLI2S is ready */ |
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| 251 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
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| 252 | { |
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| 253 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) |
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| 254 | { |
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| 255 | return HAL_TIMEOUT; |
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| 256 | } |
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| 257 | } |
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| 258 | } |
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| 259 | else |
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| 260 | { |
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| 261 | /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ |
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| 262 | if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) |
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| 263 | { |
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| 264 | return HAL_ERROR; |
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| 265 | } |
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| 266 | } |
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| 267 | } |
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| 268 | #endif /* STM32F105xC || STM32F107xC */ |
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| 269 | |||
| 270 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
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| 271 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
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| 272 | || defined(STM32F105xC) || defined(STM32F107xC) |
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| 273 | /*------------------------------ USB clock Configuration ------------------*/ |
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| 274 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) |
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| 275 | { |
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| 276 | /* Check the parameters */ |
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| 277 | assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); |
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| 278 | |||
| 279 | /* Configure the USB clock source */ |
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| 280 | __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); |
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| 281 | } |
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| 282 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
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| 283 | |||
| 284 | return HAL_OK; |
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| 285 | } |
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| 286 | |||
| 287 | /** |
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| 288 | * @brief Get the PeriphClkInit according to the internal |
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| 289 | * RCC configuration registers. |
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| 290 | * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
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| 291 | * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). |
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| 292 | * @retval None |
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| 293 | */ |
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| 294 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
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| 295 | { |
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| 296 | uint32_t srcclk = 0; |
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| 297 | |||
| 298 | /* Set all possible values for the extended clock type parameter------------*/ |
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| 299 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; |
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| 300 | |||
| 301 | /* Get the RTC configuration -----------------------------------------------*/ |
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| 302 | srcclk = __HAL_RCC_GET_RTC_SOURCE(); |
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| 303 | /* Source clock is LSE or LSI*/ |
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| 304 | PeriphClkInit->RTCClockSelection = srcclk; |
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| 305 | |||
| 306 | /* Get the ADC clock configuration -----------------------------------------*/ |
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| 307 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC; |
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| 308 | PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); |
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| 309 | |||
| 310 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 311 | /* Get the I2S2 clock configuration -----------------------------------------*/ |
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| 312 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; |
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| 313 | PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); |
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| 314 | |||
| 315 | /* Get the I2S3 clock configuration -----------------------------------------*/ |
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| 316 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; |
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| 317 | PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE(); |
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| 318 | |||
| 319 | #endif /* STM32F105xC || STM32F107xC */ |
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| 320 | |||
| 321 | #if defined(STM32F103xE) || defined(STM32F103xG) |
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| 322 | /* Get the I2S2 clock configuration -----------------------------------------*/ |
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| 323 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; |
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| 324 | PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK; |
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| 325 | |||
| 326 | /* Get the I2S3 clock configuration -----------------------------------------*/ |
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| 327 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; |
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| 328 | PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK; |
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| 329 | |||
| 330 | #endif /* STM32F103xE || STM32F103xG */ |
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| 331 | |||
| 332 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
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| 333 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
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| 334 | || defined(STM32F105xC) || defined(STM32F107xC) |
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| 335 | /* Get the USB clock configuration -----------------------------------------*/ |
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| 336 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; |
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| 337 | PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); |
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| 338 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
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| 339 | } |
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| 340 | |||
| 341 | /** |
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| 342 | * @brief Returns the peripheral clock frequency |
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| 343 | * @note Returns 0 if peripheral clock is unknown |
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| 344 | * @param PeriphClk Peripheral clock identifier |
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| 345 | * This parameter can be one of the following values: |
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| 346 | * @arg RCC_PERIPHCLK_RTC RTC peripheral clock |
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| 347 | * @arg RCC_PERIPHCLK_ADC ADC peripheral clock |
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| 348 | * @arg RCC_PERIPHCLK_I2S2 I2S2 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC) |
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| 349 | * @arg RCC_PERIPHCLK_I2S3 I2S3 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC) |
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| 350 | * @arg RCC_PERIPHCLK_USB USB peripheral clock (STM32F102xx, STM32F103xx, STM32F105xC & STM32F107xC) |
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| 351 | * @retval Frequency in Hz (0: means that no available frequency for the peripheral) |
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| 352 | */ |
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| 353 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) |
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| 354 | { |
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| 355 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
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| 356 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
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| 357 | || defined(STM32F105xC) || defined(STM32F107xC) |
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| 358 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 359 | const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13}; |
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| 360 | const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16}; |
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| 361 | #else |
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| 362 | const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; |
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| 363 | const uint8_t aPredivFactorTable[2] = { 1, 2}; |
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| 364 | #endif |
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| 365 | #endif |
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| 366 | uint32_t temp_reg = 0, frequency = 0; |
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| 367 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
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| 368 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
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| 369 | || defined(STM32F105xC) || defined(STM32F107xC) |
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| 370 | uint32_t prediv1 = 0, pllclk = 0, pllmul = 0; |
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| 371 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
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| 372 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 373 | uint32_t pll2mul = 0, pll3mul = 0, prediv2 = 0; |
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| 374 | #endif /* STM32F105xC || STM32F107xC */ |
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| 375 | |||
| 376 | /* Check the parameters */ |
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| 377 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); |
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| 378 | |||
| 379 | switch (PeriphClk) |
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| 380 | { |
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| 381 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
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| 382 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
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| 383 | || defined(STM32F105xC) || defined(STM32F107xC) |
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| 384 | case RCC_PERIPHCLK_USB: |
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| 385 | { |
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| 386 | /* Get RCC configuration ------------------------------------------------------*/ |
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| 387 | temp_reg = RCC->CFGR; |
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| 388 | |||
| 389 | /* Check if PLL is enabled */ |
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| 390 | if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON)) |
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| 391 | { |
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| 392 | pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)]; |
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| 393 | if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) |
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| 394 | { |
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| 395 | #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ |
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| 396 | || defined(STM32F100xE) |
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| 397 | prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)]; |
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| 398 | #else |
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| 399 | prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)]; |
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| 400 | #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ |
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| 401 | |||
| 402 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 403 | if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) |
||
| 404 | { |
||
| 405 | /* PLL2 selected as Prediv1 source */ |
||
| 406 | /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ |
||
| 407 | prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1; |
||
| 408 | pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2; |
||
| 409 | pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); |
||
| 410 | } |
||
| 411 | else |
||
| 412 | { |
||
| 413 | /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ |
||
| 414 | pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); |
||
| 415 | } |
||
| 416 | |||
| 417 | /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ |
||
| 418 | /* In this case need to divide pllclk by 2 */ |
||
| 419 | if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)]) |
||
| 420 | { |
||
| 421 | pllclk = pllclk / 2; |
||
| 422 | } |
||
| 423 | #else |
||
| 424 | if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) |
||
| 425 | { |
||
| 426 | /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ |
||
| 427 | pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); |
||
| 428 | } |
||
| 429 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 430 | } |
||
| 431 | else |
||
| 432 | { |
||
| 433 | /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ |
||
| 434 | pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); |
||
| 435 | } |
||
| 436 | |||
| 437 | /* Calcul of the USB frequency*/ |
||
| 438 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 439 | /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ |
||
| 440 | if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) |
||
| 441 | { |
||
| 442 | /* Prescaler of 2 selected for USB */ |
||
| 443 | frequency = pllclk; |
||
| 444 | } |
||
| 445 | else |
||
| 446 | { |
||
| 447 | /* Prescaler of 3 selected for USB */ |
||
| 448 | frequency = (2 * pllclk) / 3; |
||
| 449 | } |
||
| 450 | #else |
||
| 451 | /* USBCLK = PLLCLK / USB prescaler */ |
||
| 452 | if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) |
||
| 453 | { |
||
| 454 | /* No prescaler selected for USB */ |
||
| 455 | frequency = pllclk; |
||
| 456 | } |
||
| 457 | else |
||
| 458 | { |
||
| 459 | /* Prescaler of 1.5 selected for USB */ |
||
| 460 | frequency = (pllclk * 2) / 3; |
||
| 461 | } |
||
| 462 | #endif |
||
| 463 | } |
||
| 464 | break; |
||
| 465 | } |
||
| 466 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||
| 467 | #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ |
||
| 468 | || defined(STM32F107xC) |
||
| 469 | case RCC_PERIPHCLK_I2S2: |
||
| 470 | { |
||
| 471 | #if defined(STM32F103xE) || defined(STM32F103xG) |
||
| 472 | /* SYSCLK used as source clock for I2S2 */ |
||
| 473 | frequency = HAL_RCC_GetSysClockFreq(); |
||
| 474 | #else |
||
| 475 | if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) |
||
| 476 | { |
||
| 477 | /* SYSCLK used as source clock for I2S2 */ |
||
| 478 | frequency = HAL_RCC_GetSysClockFreq(); |
||
| 479 | } |
||
| 480 | else |
||
| 481 | { |
||
| 482 | /* Check if PLLI2S is enabled */ |
||
| 483 | if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) |
||
| 484 | { |
||
| 485 | /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ |
||
| 486 | prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1; |
||
| 487 | pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2; |
||
| 488 | frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); |
||
| 489 | } |
||
| 490 | } |
||
| 491 | #endif /* STM32F103xE || STM32F103xG */ |
||
| 492 | break; |
||
| 493 | } |
||
| 494 | case RCC_PERIPHCLK_I2S3: |
||
| 495 | { |
||
| 496 | #if defined(STM32F103xE) || defined(STM32F103xG) |
||
| 497 | /* SYSCLK used as source clock for I2S3 */ |
||
| 498 | frequency = HAL_RCC_GetSysClockFreq(); |
||
| 499 | #else |
||
| 500 | if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) |
||
| 501 | { |
||
| 502 | /* SYSCLK used as source clock for I2S3 */ |
||
| 503 | frequency = HAL_RCC_GetSysClockFreq(); |
||
| 504 | } |
||
| 505 | else |
||
| 506 | { |
||
| 507 | /* Check if PLLI2S is enabled */ |
||
| 508 | if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) |
||
| 509 | { |
||
| 510 | /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ |
||
| 511 | prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1; |
||
| 512 | pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2; |
||
| 513 | frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); |
||
| 514 | } |
||
| 515 | } |
||
| 516 | #endif /* STM32F103xE || STM32F103xG */ |
||
| 517 | break; |
||
| 518 | } |
||
| 519 | #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||
| 520 | case RCC_PERIPHCLK_RTC: |
||
| 521 | { |
||
| 522 | /* Get RCC BDCR configuration ------------------------------------------------------*/ |
||
| 523 | temp_reg = RCC->BDCR; |
||
| 524 | |||
| 525 | /* Check if LSE is ready if RTC clock selection is LSE */ |
||
| 526 | if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) |
||
| 527 | { |
||
| 528 | frequency = LSE_VALUE; |
||
| 529 | } |
||
| 530 | /* Check if LSI is ready if RTC clock selection is LSI */ |
||
| 531 | else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) |
||
| 532 | { |
||
| 533 | frequency = LSI_VALUE; |
||
| 534 | } |
||
| 535 | else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) |
||
| 536 | { |
||
| 537 | frequency = HSE_VALUE / 128; |
||
| 538 | } |
||
| 539 | /* Clock not enabled for RTC*/ |
||
| 540 | else |
||
| 541 | { |
||
| 542 | frequency = 0; |
||
| 543 | } |
||
| 544 | break; |
||
| 545 | } |
||
| 546 | case RCC_PERIPHCLK_ADC: |
||
| 547 | { |
||
| 548 | frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2); |
||
| 549 | break; |
||
| 550 | } |
||
| 551 | default: |
||
| 552 | { |
||
| 553 | break; |
||
| 554 | } |
||
| 555 | } |
||
| 556 | return(frequency); |
||
| 557 | } |
||
| 558 | |||
| 559 | /** |
||
| 560 | * @} |
||
| 561 | */ |
||
| 562 | |||
| 563 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 564 | /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function |
||
| 565 | * @brief PLLI2S Management functions |
||
| 566 | * |
||
| 567 | @verbatim |
||
| 568 | =============================================================================== |
||
| 569 | ##### Extended PLLI2S Management functions ##### |
||
| 570 | =============================================================================== |
||
| 571 | [..] |
||
| 572 | This subsection provides a set of functions allowing to control the PLLI2S |
||
| 573 | activation or deactivation |
||
| 574 | @endverbatim |
||
| 575 | * @{ |
||
| 576 | */ |
||
| 577 | |||
| 578 | /** |
||
| 579 | * @brief Enable PLLI2S |
||
| 580 | * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that |
||
| 581 | * contains the configuration information for the PLLI2S |
||
| 582 | * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface. |
||
| 583 | * @retval HAL status |
||
| 584 | */ |
||
| 585 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) |
||
| 586 | { |
||
| 587 | uint32_t tickstart = 0; |
||
| 588 | |||
| 589 | /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ |
||
| 590 | if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) |
||
| 591 | { |
||
| 592 | /* Check the parameters */ |
||
| 593 | assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL)); |
||
| 594 | assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value)); |
||
| 595 | |||
| 596 | /* Prediv2 can be written only when the PLL2 is disabled. */ |
||
| 597 | /* Return an error only if new value is different from the programmed value */ |
||
| 598 | if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \ |
||
| 599 | (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) |
||
| 600 | { |
||
| 601 | return HAL_ERROR; |
||
| 602 | } |
||
| 603 | |||
| 604 | /* Disable the main PLLI2S. */ |
||
| 605 | __HAL_RCC_PLLI2S_DISABLE(); |
||
| 606 | |||
| 607 | /* Get Start Tick*/ |
||
| 608 | tickstart = HAL_GetTick(); |
||
| 609 | |||
| 610 | /* Wait till PLLI2S is ready */ |
||
| 611 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
||
| 612 | { |
||
| 613 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) |
||
| 614 | { |
||
| 615 | return HAL_TIMEOUT; |
||
| 616 | } |
||
| 617 | } |
||
| 618 | |||
| 619 | /* Configure the HSE prediv2 factor --------------------------------*/ |
||
| 620 | __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); |
||
| 621 | |||
| 622 | |||
| 623 | /* Configure the main PLLI2S multiplication factors. */ |
||
| 624 | __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); |
||
| 625 | |||
| 626 | /* Enable the main PLLI2S. */ |
||
| 627 | __HAL_RCC_PLLI2S_ENABLE(); |
||
| 628 | |||
| 629 | /* Get Start Tick*/ |
||
| 630 | tickstart = HAL_GetTick(); |
||
| 631 | |||
| 632 | /* Wait till PLLI2S is ready */ |
||
| 633 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
||
| 634 | { |
||
| 635 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) |
||
| 636 | { |
||
| 637 | return HAL_TIMEOUT; |
||
| 638 | } |
||
| 639 | } |
||
| 640 | } |
||
| 641 | else |
||
| 642 | { |
||
| 643 | /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */ |
||
| 644 | return HAL_ERROR; |
||
| 645 | } |
||
| 646 | |||
| 647 | return HAL_OK; |
||
| 648 | } |
||
| 649 | |||
| 650 | /** |
||
| 651 | * @brief Disable PLLI2S |
||
| 652 | * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface. |
||
| 653 | * @retval HAL status |
||
| 654 | */ |
||
| 655 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) |
||
| 656 | { |
||
| 657 | uint32_t tickstart = 0; |
||
| 658 | |||
| 659 | /* Disable PLL I2S as not requested by I2S2 or I2S3*/ |
||
| 660 | if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) |
||
| 661 | { |
||
| 662 | /* Disable the main PLLI2S. */ |
||
| 663 | __HAL_RCC_PLLI2S_DISABLE(); |
||
| 664 | |||
| 665 | /* Get Start Tick*/ |
||
| 666 | tickstart = HAL_GetTick(); |
||
| 667 | |||
| 668 | /* Wait till PLLI2S is ready */ |
||
| 669 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
||
| 670 | { |
||
| 671 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) |
||
| 672 | { |
||
| 673 | return HAL_TIMEOUT; |
||
| 674 | } |
||
| 675 | } |
||
| 676 | } |
||
| 677 | else |
||
| 678 | { |
||
| 679 | /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ |
||
| 680 | return HAL_ERROR; |
||
| 681 | } |
||
| 682 | |||
| 683 | return HAL_OK; |
||
| 684 | } |
||
| 685 | |||
| 686 | /** |
||
| 687 | * @} |
||
| 688 | */ |
||
| 689 | |||
| 690 | /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function |
||
| 691 | * @brief PLL2 Management functions |
||
| 692 | * |
||
| 693 | @verbatim |
||
| 694 | =============================================================================== |
||
| 695 | ##### Extended PLL2 Management functions ##### |
||
| 696 | =============================================================================== |
||
| 697 | [..] |
||
| 698 | This subsection provides a set of functions allowing to control the PLL2 |
||
| 699 | activation or deactivation |
||
| 700 | @endverbatim |
||
| 701 | * @{ |
||
| 702 | */ |
||
| 703 | |||
| 704 | /** |
||
| 705 | * @brief Enable PLL2 |
||
| 706 | * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that |
||
| 707 | * contains the configuration information for the PLL2 |
||
| 708 | * @note The PLL2 configuration not modified if used indirectly as system clock. |
||
| 709 | * @retval HAL status |
||
| 710 | */ |
||
| 711 | HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) |
||
| 712 | { |
||
| 713 | uint32_t tickstart = 0; |
||
| 714 | |||
| 715 | /* This bit can not be cleared if the PLL2 clock is used indirectly as system |
||
| 716 | clock (i.e. it is used as PLL clock entry that is used as system clock). */ |
||
| 717 | if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ |
||
| 718 | (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ |
||
| 719 | ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) |
||
| 720 | { |
||
| 721 | return HAL_ERROR; |
||
| 722 | } |
||
| 723 | else |
||
| 724 | { |
||
| 725 | /* Check the parameters */ |
||
| 726 | assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL)); |
||
| 727 | assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value)); |
||
| 728 | |||
| 729 | /* Prediv2 can be written only when the PLLI2S is disabled. */ |
||
| 730 | /* Return an error only if new value is different from the programmed value */ |
||
| 731 | if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \ |
||
| 732 | (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) |
||
| 733 | { |
||
| 734 | return HAL_ERROR; |
||
| 735 | } |
||
| 736 | |||
| 737 | /* Disable the main PLL2. */ |
||
| 738 | __HAL_RCC_PLL2_DISABLE(); |
||
| 739 | |||
| 740 | /* Get Start Tick*/ |
||
| 741 | tickstart = HAL_GetTick(); |
||
| 742 | |||
| 743 | /* Wait till PLL2 is disabled */ |
||
| 744 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) |
||
| 745 | { |
||
| 746 | if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) |
||
| 747 | { |
||
| 748 | return HAL_TIMEOUT; |
||
| 749 | } |
||
| 750 | } |
||
| 751 | |||
| 752 | /* Configure the HSE prediv2 factor --------------------------------*/ |
||
| 753 | __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); |
||
| 754 | |||
| 755 | /* Configure the main PLL2 multiplication factors. */ |
||
| 756 | __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); |
||
| 757 | |||
| 758 | /* Enable the main PLL2. */ |
||
| 759 | __HAL_RCC_PLL2_ENABLE(); |
||
| 760 | |||
| 761 | /* Get Start Tick*/ |
||
| 762 | tickstart = HAL_GetTick(); |
||
| 763 | |||
| 764 | /* Wait till PLL2 is ready */ |
||
| 765 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) |
||
| 766 | { |
||
| 767 | if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) |
||
| 768 | { |
||
| 769 | return HAL_TIMEOUT; |
||
| 770 | } |
||
| 771 | } |
||
| 772 | } |
||
| 773 | |||
| 774 | return HAL_OK; |
||
| 775 | } |
||
| 776 | |||
| 777 | /** |
||
| 778 | * @brief Disable PLL2 |
||
| 779 | * @note PLL2 is not disabled if used indirectly as system clock. |
||
| 780 | * @retval HAL status |
||
| 781 | */ |
||
| 782 | HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) |
||
| 783 | { |
||
| 784 | uint32_t tickstart = 0; |
||
| 785 | |||
| 786 | /* This bit can not be cleared if the PLL2 clock is used indirectly as system |
||
| 787 | clock (i.e. it is used as PLL clock entry that is used as system clock). */ |
||
| 788 | if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ |
||
| 789 | (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ |
||
| 790 | ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) |
||
| 791 | { |
||
| 792 | return HAL_ERROR; |
||
| 793 | } |
||
| 794 | else |
||
| 795 | { |
||
| 796 | /* Disable the main PLL2. */ |
||
| 797 | __HAL_RCC_PLL2_DISABLE(); |
||
| 798 | |||
| 799 | /* Get Start Tick*/ |
||
| 800 | tickstart = HAL_GetTick(); |
||
| 801 | |||
| 802 | /* Wait till PLL2 is disabled */ |
||
| 803 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) |
||
| 804 | { |
||
| 805 | if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) |
||
| 806 | { |
||
| 807 | return HAL_TIMEOUT; |
||
| 808 | } |
||
| 809 | } |
||
| 810 | } |
||
| 811 | |||
| 812 | return HAL_OK; |
||
| 813 | } |
||
| 814 | |||
| 815 | /** |
||
| 816 | * @} |
||
| 817 | */ |
||
| 818 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 819 | |||
| 820 | /** |
||
| 821 | * @} |
||
| 822 | */ |
||
| 823 | |||
| 824 | /** |
||
| 825 | * @} |
||
| 826 | */ |
||
| 827 | |||
| 828 | #endif /* HAL_RCC_MODULE_ENABLED */ |
||
| 829 | |||
| 830 | /** |
||
| 831 | * @} |
||
| 832 | */ |
||
| 833 | |||
| 834 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||
| 835 |