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/**

  ******************************************************************************

  * @file    stm32f1xx_hal_rcc.c

  * @author  MCD Application Team

  * @brief   RCC HAL module driver.

  *          This file provides firmware functions to manage the following

  *          functionalities of the Reset and Clock Control (RCC) peripheral:

  *           + Initialization and de-initialization functions

  *           + Peripheral Control functions

  *

  @verbatim

  ==============================================================================

                      ##### RCC specific features #####

  ==============================================================================

    [..]

      After reset the device is running from Internal High Speed oscillator

      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,

      and all peripherals are off except internal SRAM, Flash and JTAG.

      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;

          all peripherals mapped on these buses are running at HSI speed.

      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.

      (+) All GPIOs are in input floating state, except the JTAG pins which

          are assigned to be used for debug purpose.

    [..] Once the device started from reset, the user application has to:

      (+) Configure the clock source to be used to drive the System clock

          (if the application needs higher frequency/performance)

      (+) Configure the System clock frequency and Flash settings  

      (+) Configure the AHB and APB buses prescalers

      (+) Enable the clock for the peripheral(s) to be used

      (+) Configure the clock source(s) for peripherals whose clocks are not

          derived from the System clock (I2S, RTC, ADC, USB OTG FS)

                      ##### RCC Limitations #####

  ==============================================================================

    [..]

      A delay between an RCC peripheral clock enable and the effective peripheral

      enabling should be taken into account in order to manage the peripheral read/write

      from/to registers.

      (+) This delay depends on the peripheral mapping.

        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]  

      Workarounds:

      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been

          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.

  @endverbatim

  ******************************************************************************

  * @attention

  *

  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

  *

  * Redistribution and use in source and binary forms, with or without modification,

  * are permitted provided that the following conditions are met:

  *   1. Redistributions of source code must retain the above copyright notice,

  *      this list of conditions and the following disclaimer.

  *   2. Redistributions in binary form must reproduce the above copyright notice,

  *      this list of conditions and the following disclaimer in the documentation

  *      and/or other materials provided with the distribution.

  *   3. Neither the name of STMicroelectronics nor the names of its contributors

  *      may be used to endorse or promote products derived from this software

  *      without specific prior written permission.

  *

  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  *

  ******************************************************************************  

*/

/* Includes ------------------------------------------------------------------*/

#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver

  * @{

  */

/** @defgroup RCC RCC

* @brief RCC HAL module driver

  * @{

  */

#ifdef HAL_RCC_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/

/* Private define ------------------------------------------------------------*/

/** @defgroup RCC_Private_Constants RCC Private Constants

 * @{

 */

/**

  * @}

  */

/* Private macro -------------------------------------------------------------*/

/** @defgroup RCC_Private_Macros RCC Private Macros

  * @{

  */

#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()

#define MCO1_GPIO_PORT        GPIOA

#define MCO1_PIN              GPIO_PIN_8

/**

  * @}

  */

/* Private variables ---------------------------------------------------------*/

/** @defgroup RCC_Private_Variables RCC Private Variables

  * @{

  */

/**

  * @}

  */

/* Private function prototypes -----------------------------------------------*/

static void RCC_Delay(uint32_t mdelay);

/* Exported functions --------------------------------------------------------*/

/** @defgroup RCC_Exported_Functions RCC Exported Functions

  * @{

  */

/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions

  *  @brief    Initialization and Configuration functions

  *

  @verbatim    

  ===============================================================================

           ##### Initialization and de-initialization functions #####

  ===============================================================================

    [..]

      This section provides functions allowing to configure the internal/external oscillators

      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1

      and APB2).

    [..] Internal/external clock and PLL configuration

      (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through

          the PLL as System clock source.

      (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC

          clock source.

      (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x)  crystal oscillator used directly or

          through the PLL as System clock source. Can be used also as RTC clock source.

      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

      (#) PLL (clocked by HSI or HSE), featuring different output clocks:

        (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)

        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)

      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()

          and if a HSE clock failure occurs(HSE used directly or through PLL as System

          clock source), the System clocks automatically switched to HSI and an interrupt

          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI

          (Non-Maskable Interrupt) exception vector.

      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,

          HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x

    [..] System, AHB and APB buses clocks configuration

      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,

          HSE and PLL.

          The AHB clock (HCLK) is derived from System clock through configurable

          prescaler and used to clock the CPU, memory and peripherals mapped

          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived

          from AHB clock through configurable prescalers and used to clock

          the peripherals mapped on these buses. You can use

          "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:

          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock

              divided by 128.

          (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz

              to work correctly. This clock is derived of the main PLL through PLL Multiplier.

          (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK

          (+@) IWDG clock which is always the LSI clock.

      (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.

          For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.  

          Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.

  @endverbatim

  * @{

  */

/*

  Additional consideration on the SYSCLK based on Latency settings:

        +-----------------------------------------------+

        | Latency       | SYSCLK clock frequency (MHz)  |

        |---------------|-------------------------------|

        |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |

        |---------------|-------------------------------|

        |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |

        |---------------|-------------------------------|

        |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |

        +-----------------------------------------------+

  */

/**

  * @brief  Resets the RCC clock configuration to the default reset state.

  * @note   The default reset state of the clock configuration is given below:

  *            - HSI ON and used as system clock source

  *            - HSE, PLL, PLL2 and PLL3 are OFF

  *            - AHB, APB1 and APB2 prescaler set to 1.

  *            - CSS and MCO1 OFF

  *            - All interrupts disabled

  *            - All flags are cleared

  * @note   This function does not modify the configuration of the

  *            - Peripheral clocks

  *            - LSI, LSE and RTC clocks

  * @retval HAL_StatusTypeDef

  */

HAL_StatusTypeDef HAL_RCC_DeInit(void)

{

  uint32_t tickstart;

  /* Get Start Tick */

  tickstart = HAL_GetTick();

  /* Set HSION bit */

  SET_BIT(RCC->CR, RCC_CR_HSION);

  /* Wait till HSI is ready */

  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)

  {

    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Set HSITRIM bits to the reset value */

  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));

  /* Get Start Tick */

  tickstart = HAL_GetTick();

  /* Reset CFGR register */

  CLEAR_REG(RCC->CFGR);

  /* Wait till clock switch is ready */

  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)

  {

    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Update the SystemCoreClock global variable */

  SystemCoreClock = HSI_VALUE;

  /* Adapt Systick interrupt period */

  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)

  {

    return HAL_ERROR;

  }

  /* Get Start Tick */

  tickstart = HAL_GetTick();

  /* Second step is to clear PLLON bit */

  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);

  /* Wait till PLL is disabled */

  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)

  {

    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Ensure to reset PLLSRC and PLLMUL bits */

  CLEAR_REG(RCC->CFGR);

  /* Get Start Tick */

  tickstart = HAL_GetTick();

  /* Reset HSEON & CSSON bits */

  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);

  /* Wait till HSE is disabled */

  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)

  {

    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Reset HSEBYP bit */

  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);

#if defined(RCC_PLL2_SUPPORT)

  /* Get Start Tick */

  tickstart = HAL_GetTick();

  /* Clear PLL2ON bit */

  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);

  /* Wait till PLL2 is disabled */

  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET)

  {

    if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

#endif /* RCC_PLL2_SUPPORT */

#if defined(RCC_PLLI2S_SUPPORT)

  /* Get Start Tick */

  tickstart = HAL_GetTick();

  /* Clear PLL3ON bit */

  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);

  /* Wait till PLL3 is disabled */

  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET)

  {

    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

#endif /* RCC_PLLI2S_SUPPORT */

#if defined(RCC_CFGR2_PREDIV1)

  /* Reset CFGR2 register */

  CLEAR_REG(RCC->CFGR2);

#endif /* RCC_CFGR2_PREDIV1 */

  /* Reset all CSR flags */

  SET_BIT(RCC->CSR, RCC_CSR_RMVF);

  /* Disable all interrupts */

  CLEAR_REG(RCC->CIR);

  return HAL_OK;

}

/**

  * @brief  Initializes the RCC Oscillators according to the specified parameters in the

  *         RCC_OscInitTypeDef.

  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that

  *         contains the configuration information for the RCC Oscillators.

  * @note   The PLL is not disabled when used as system clock.

  * @note   The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)

  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not

  *         supported by this macro. User should request a transition to LSE Off

  *         first and then LSE On or LSE Bypass.

  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not

  *         supported by this macro. User should request a transition to HSE Off

  *         first and then HSE On or HSE Bypass.

  * @retval HAL status

  */

HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)

{

   uint32_t tickstart = 0U;

  /* Check the parameters */

  assert_param(RCC_OscInitStruct != NULL);

  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  /*------------------------------- HSE Configuration ------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)

  {

    /* Check the parameters */

    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */

    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)

       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))

    {

      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))

      {

        return HAL_ERROR;

      }

    }

    else

    {

      /* Set the new HSE configuration ---------------------------------------*/

      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);

       /* Check the HSE State */

      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)

      {

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSE is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)

        {

          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

      else

      {

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSE is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)

        {

           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

  }

  /*----------------------------- HSI Configuration --------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)

  {

    /* Check the parameters */

    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));

    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */

    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)

       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))

    {

      /* When HSI is used as system clock it will not disabled */

      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))

      {

        return HAL_ERROR;

      }

      /* Otherwise, just the calibration is allowed */

      else

      {

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/

        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);

      }

    }

    else

    {

      /* Check the HSI State */

      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)

      {

       /* Enable the Internal High Speed oscillator (HSI). */

        __HAL_RCC_HSI_ENABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSI is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)

        {

          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/

        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);

      }

      else

      {

        /* Disable the Internal High Speed oscillator (HSI). */

        __HAL_RCC_HSI_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSI is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)

        {

          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

  }

  /*------------------------------ LSI Configuration -------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)

  {

    /* Check the parameters */

    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */

    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)

    {

      /* Enable the Internal Low Speed oscillator (LSI). */

      __HAL_RCC_LSI_ENABLE();

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSI is ready */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)

      {

        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

      /*  To have a fully stabilized clock in the specified range, a software delay of 1ms

          should be added.*/

      RCC_Delay(1);

    }

    else

    {

      /* Disable the Internal Low Speed oscillator (LSI). */

      __HAL_RCC_LSI_DISABLE();

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSI is disabled */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)

      {

        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

  }

  /*------------------------------ LSE Configuration -------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)

  {

    FlagStatus       pwrclkchanged = RESET;

    /* Check the parameters */

    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */

    /* Requires to enable write access to Backup Domain of necessary */

    if(__HAL_RCC_PWR_IS_CLK_DISABLED())

    {

      __HAL_RCC_PWR_CLK_ENABLE();

      pwrclkchanged = SET;

    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))

    {

      /* Enable write access to Backup domain */

      SET_BIT(PWR->CR, PWR_CR_DBP);

      /* Wait for Backup domain Write protection disable */

      tickstart = HAL_GetTick();

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))

      {

        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    /* Set the new LSE configuration -----------------------------------------*/

    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);

    /* Check the LSE State */

    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)

    {

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSE is ready */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)

      {

        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    else

    {

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSE is disabled */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)

      {

        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    /* Require to disable power clock if necessary */

    if(pwrclkchanged == SET)

    {

      __HAL_RCC_PWR_CLK_DISABLE();

    }

  }

#if defined(RCC_CR_PLL2ON)

  /*-------------------------------- PLL2 Configuration -----------------------*/

  /* Check the parameters */

  assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));

  if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)

  {

    /* This bit can not be cleared if the PLL2 clock is used indirectly as system

      clock (i.e. it is used as PLL clock entry that is used as system clock). */

    if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \

        (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \

        ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))

    {

      return HAL_ERROR;

    }

    else

    {

      if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)

      {

        /* Check the parameters */

        assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));

        assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));

        /* Prediv2 can be written only when the PLLI2S is disabled. */

        /* Return an error only if new value is different from the programmed value */

        if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \

          (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))

        {

          return HAL_ERROR;

        }

        /* Disable the main PLL2. */

        __HAL_RCC_PLL2_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL2 is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)

        {

          if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

        /* Configure the HSE prediv2 factor --------------------------------*/

        __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);

        /* Configure the main PLL2 multiplication factors. */

        __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);

        /* Enable the main PLL2. */

        __HAL_RCC_PLL2_ENABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL2 is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)

        {

          if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

      else

      {

       /* Set PREDIV1 source to HSE */

        CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);

        /* Disable the main PLL2. */

        __HAL_RCC_PLL2_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL2 is disabled */  

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)

        {

          if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

  }

#endif /* RCC_CR_PLL2ON */

  /*-------------------------------- PLL Configuration -----------------------*/

  /* Check the parameters */

  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)

  {

    /* Check if the PLL is used as system clock or not */

    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)

    {

      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)

      {

        /* Check the parameters */

        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));

        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));

        /* Disable the main PLL. */

        __HAL_RCC_PLL_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)

        {

          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

        /* Configure the HSE prediv factor --------------------------------*/

        /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */

        if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)

        {

          /* Check the parameter */

          assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));

#if defined(RCC_CFGR2_PREDIV1SRC)

          assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));

          /* Set PREDIV1 source */

          SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);

#endif /* RCC_CFGR2_PREDIV1SRC */

          /* Set PREDIV1 Value */

          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);

        }

        /* Configure the main PLL clock source and multiplication factors. */

        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,

                             RCC_OscInitStruct->PLL.PLLMUL);

        /* Enable the main PLL. */

        __HAL_RCC_PLL_ENABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)

        {

          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

      else

      {

        /* Disable the main PLL. */

        __HAL_RCC_PLL_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL is disabled */  

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)

        {

          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

    else

    {

      return HAL_ERROR;

    }

  }

  return HAL_OK;

}

/**

  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified

  *         parameters in the RCC_ClkInitStruct.

  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that

  *         contains the configuration information for the RCC peripheral.

  * @param  FLatency FLASH Latency                  

  *          The value of this parameter depend on device used within the same series

  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency

  *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function

  *

  * @note   The HSI is used (enabled by hardware) as system clock source after

  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case

  *         of failure of the HSE used directly or indirectly as system clock

  *         (if the Clock Security System CSS is enabled).

  *          

  * @note   A switch from one clock source to another occurs only if the target

  *         clock source is ready (clock stable after start-up delay or PLL locked).

  *         If a clock source which is not yet ready is selected, the switch will

  *         occur when the clock source will be ready.

  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is

  *         currently used as system clock source.

  * @retval HAL status

  */

HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)

{

  uint32_t tickstart = 0U;

  /* Check the parameters */

  assert_param(RCC_ClkInitStruct != NULL);

  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));

  assert_param(IS_FLASH_LATENCY(FLatency));

  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)

  must be correctly programmed according to the frequency of the CPU clock

    (HCLK) of the device. */

#if defined(FLASH_ACR_LATENCY)

  /* Increasing the number of wait states because of higher CPU frequency */

  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))

  {    

    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */

    __HAL_FLASH_SET_LATENCY(FLatency);

    /* Check that the new number of wait states is taken into account to access the Flash

    memory by reading the FLASH_ACR register */

    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)

    {

      return HAL_ERROR;

    }

  }

#endif /* FLASH_ACR_LATENCY */

  /*-------------------------- HCLK Configuration --------------------------*/

  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)

  {

    /* Set the highest APBx dividers in order to ensure that we do not go through

    a non-spec phase whatever we decrease or increase HCLK. */

    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)

    {

      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);

    }

    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)

    {

      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));

    }

    /* Set the new HCLK clock divider */

    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));

    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);

  }

  /*------------------------- SYSCLK Configuration ---------------------------*/

  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)

  {    

    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */

    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)

    {

      /* Check the HSE ready flag */  

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)

      {

        return HAL_ERROR;

      }

    }

    /* PLL is selected as System Clock Source */

    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)

    {

      /* Check the PLL ready flag */  

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)

      {

        return HAL_ERROR;

      }

    }

    /* HSI is selected as System Clock Source */

    else

    {

      /* Check the HSI ready flag */  

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)