WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_nor.c
		4	* @author MCD Application Team
		5	* @brief NOR HAL module driver.
9	mjames	6	* This file provides a generic firmware to drive NOR memories mounted
2	mjames	7	* as external device.
9	mjames	8	*
2	mjames	9	@verbatim
		10	==============================================================================
		11	##### How to use this driver #####
9	mjames	12	==============================================================================
2	mjames	13	[..]
9	mjames	14	This driver is a generic layered driver which contains a set of APIs used to
		15	control NOR flash memories. It uses the FSMC layer functions to interface
2	mjames	16	with NOR devices. This driver is used as follows:
9	mjames	17
		18	(+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
2	mjames	19	with control and timing parameters for both normal and extended mode.
9	mjames	20
2	mjames	21	(+) Read NOR flash memory manufacturer code and device IDs using the function
9	mjames	22	HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
		23	structure declared by the function caller.
		24
2	mjames	25	(+) Access NOR flash memory by read/write data unit operations using the functions
		26	HAL_NOR_Read(), HAL_NOR_Program().
9	mjames	27
		28	(+) Perform NOR flash erase block/chip operations using the functions
2	mjames	29	HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
9	mjames	30
2	mjames	31	(+) Read the NOR flash CFI (common flash interface) IDs using the function
		32	HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
		33	structure declared by the function caller.
9	mjames	34
2	mjames	35	(+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
9	mjames	36	HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
		37
2	mjames	38	(+) You can monitor the NOR device HAL state by calling the function
9	mjames	39	HAL_NOR_GetState()
2	mjames	40	[..]
		41	(@) This driver is a set of generic APIs which handle standard NOR flash operations.
9	mjames	42	If a NOR flash device contains different operations and/or implementations,
2	mjames	43	it should be implemented separately.
		44
		45	* NOR HAL driver macros list *
9	mjames	46	=============================================
2	mjames	47	[..]
		48	Below the list of most used macros in NOR HAL driver.
9	mjames	49
2	mjames	50	(+) NOR_WRITE : NOR memory write data to specified address
		51
9	mjames	52	* Callback registration *
		53	=============================================
		54	[..]
		55	The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
		56	allows the user to configure dynamically the driver callbacks.
		57
		58	Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
		59	it allows to register following callbacks:
		60	(+) MspInitCallback : NOR MspInit.
		61	(+) MspDeInitCallback : NOR MspDeInit.
		62	This function takes as parameters the HAL peripheral handle, the Callback ID
		63	and a pointer to the user callback function.
		64
		65	Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
		66	weak (surcharged) function. It allows to reset following callbacks:
		67	(+) MspInitCallback : NOR MspInit.
		68	(+) MspDeInitCallback : NOR MspDeInit.
		69	This function) takes as parameters the HAL peripheral handle and the Callback ID.
		70
		71	By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
		72	all callbacks are reset to the corresponding legacy weak (surcharged) functions.
		73	Exception done for MspInit and MspDeInit callbacks that are respectively
		74	reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
		75	and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
		76	If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
		77	keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
		78
		79	Callbacks can be registered/unregistered in READY state only.
		80	Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
		81	in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
		82	during the Init/DeInit.
		83	In that case first register the MspInit/MspDeInit user callbacks
		84	using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
		85	or @ref HAL_NOR_Init function.
		86
		87	When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
		88	not defined, the callback registering feature is not available
		89	and weak (surcharged) callbacks are used.
		90
2	mjames	91	@endverbatim
		92	******************************************************************************
		93	* @attention
		94	*
9	mjames	95	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		96	* All rights reserved.</center></h2>
2	mjames	97	*
9	mjames	98	* This software component is licensed by ST under BSD 3-Clause license,
		99	* the "License"; You may not use this file except in compliance with the
		100	* License. You may obtain a copy of the License at:
		101	* opensource.org/licenses/BSD-3-Clause
2	mjames	102	*
		103	******************************************************************************
9	mjames	104	*/
2	mjames	105
		106	/* Includes ------------------------------------------------------------------*/
		107	#include "stm32f1xx_hal.h"
		108
9	mjames	109	#if defined FSMC_BANK1
		110
2	mjames	111	/** @addtogroup STM32F1xx_HAL_Driver
		112	* @{
		113	*/
		114
		115	#ifdef HAL_NOR_MODULE_ENABLED
		116
		117	/** @defgroup NOR NOR
		118	* @brief NOR driver modules
		119	* @{
		120	*/
9	mjames	121
2	mjames	122	/* Private typedef -----------------------------------------------------------*/
		123	/* Private define ------------------------------------------------------------*/
9	mjames	124
		125	/** @defgroup NOR_Private_Defines NOR Private Defines
2	mjames	126	* @{
		127	*/
		128
		129	/* Constants to define address to set to write a command */
		130	#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
		131	#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
		132	#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
		133	#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
		134	#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
		135	#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
		136	#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
		137
		138	/* Constants to define data to program a command */
		139	#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
		140	#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
		141	#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
		142	#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
		143	#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
		144	#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
		145	#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
		146	#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
		147	#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
		148	#define NOR_CMD_DATA_CFI (uint16_t)0x0098
		149
		150	#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
		151	#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
		152	#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
		153
9	mjames	154	#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
		155	#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
		156	#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
		157	#define NOR_CMD_CONFIRM (uint16_t)0x00D0
		158	#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
		159	#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
		160	#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
		161	#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
		162
2	mjames	163	/* Mask on NOR STATUS REGISTER */
9	mjames	164	#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
2	mjames	165	#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
		166	#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
9	mjames	167	#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
2	mjames	168
9	mjames	169	/* Address of the primary command set */
		170	#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
2	mjames	171
9	mjames	172	/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
		173	#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
		174	#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
		175	#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
		176	#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
		177	#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
		178	#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
		179	#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
		180	#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
		181	#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
		182	#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
2	mjames	183
		184	/**
		185	* @}
		186	*/
		187
9	mjames	188	/* Private macro -------------------------------------------------------------*/
2	mjames	189	/* Private variables ---------------------------------------------------------*/
		190	/** @defgroup NOR_Private_Variables NOR Private Variables
		191	* @{
		192	*/
		193
		194	static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
		195
		196	/**
		197	* @}
		198	*/
		199
		200	/* Private functions ---------------------------------------------------------*/
9	mjames	201	/* Exported functions --------------------------------------------------------*/
2	mjames	202	/** @defgroup NOR_Exported_Functions NOR Exported Functions
		203	* @{
		204	*/
		205
9	mjames	206	/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
		207	* @brief Initialization and Configuration functions
2	mjames	208	*
9	mjames	209	@verbatim
2	mjames	210	==============================================================================
		211	##### NOR Initialization and de_initialization functions #####
		212	==============================================================================
9	mjames	213	[..]
2	mjames	214	This section provides functions allowing to initialize/de-initialize
		215	the NOR memory
9	mjames	216
2	mjames	217	@endverbatim
		218	* @{
		219	*/
9	mjames	220
2	mjames	221	/**
		222	* @brief Perform the NOR memory Initialization sequence
9	mjames	223	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	224	* the configuration information for NOR module.
9	mjames	225	* @param Timing pointer to NOR control timing structure
		226	* @param ExtTiming pointer to NOR extended mode timing structure
2	mjames	227	* @retval HAL status
		228	*/
9	mjames	229	HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef hnor, FSMC_NORSRAM_TimingTypeDef Timing,
		230	FSMC_NORSRAM_TimingTypeDef *ExtTiming)
2	mjames	231	{
9	mjames	232	uint32_t deviceaddress;
		233
2	mjames	234	/* Check the NOR handle parameter */
9	mjames	235	if (hnor == NULL)
2	mjames	236	{
9	mjames	237	return HAL_ERROR;
2	mjames	238	}
9	mjames	239
		240	if (hnor->State == HAL_NOR_STATE_RESET)
2	mjames	241	{
		242	/* Allocate lock resource and initialize it */
		243	hnor->Lock = HAL_UNLOCKED;
9	mjames	244
		245	#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
		246	if (hnor->MspInitCallback == NULL)
		247	{
		248	hnor->MspInitCallback = HAL_NOR_MspInit;
		249	}
		250
		251	/* Init the low level hardware */
		252	hnor->MspInitCallback(hnor);
		253	#else
2	mjames	254	/* Initialize the low level hardware (MSP) */
		255	HAL_NOR_MspInit(hnor);
9	mjames	256	#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
2	mjames	257	}
		258
		259	/* Initialize NOR control Interface */
9	mjames	260	(void)FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
2	mjames	261
		262	/* Initialize NOR timing Interface */
9	mjames	263	(void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
2	mjames	264
		265	/* Initialize NOR extended mode timing Interface */
9	mjames	266	(void)FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
2	mjames	267
		268	/* Enable the NORSRAM device */
9	mjames	269	__FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
2	mjames	270
		271	/* Initialize NOR Memory Data Width*/
		272	if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
		273	{
		274	uwNORMemoryDataWidth = NOR_MEMORY_8B;
		275	}
		276	else
		277	{
		278	uwNORMemoryDataWidth = NOR_MEMORY_16B;
		279	}
		280
9	mjames	281	/* Initialize the NOR controller state */
		282	hnor->State = HAL_NOR_STATE_READY;
		283
		284	/* Select the NOR device address */
		285	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		286	{
		287	deviceaddress = NOR_MEMORY_ADRESS1;
		288	}
		289	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		290	{
		291	deviceaddress = NOR_MEMORY_ADRESS2;
		292	}
		293	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		294	{
		295	deviceaddress = NOR_MEMORY_ADRESS3;
		296	}
		297	else /* FSMC_NORSRAM_BANK4 */
		298	{
		299	deviceaddress = NOR_MEMORY_ADRESS4;
		300	}
		301
		302	/* Get the value of the command set */
		303	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
		304	hnor->CommandSet = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
		305
		306	return HAL_NOR_ReturnToReadMode(hnor);
2	mjames	307	}
		308
		309	/**
		310	* @brief Perform NOR memory De-Initialization sequence
9	mjames	311	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	312	* the configuration information for NOR module.
		313	* @retval HAL status
		314	*/
9	mjames	315	HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
2	mjames	316	{
9	mjames	317	#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
		318	if (hnor->MspDeInitCallback == NULL)
		319	{
		320	hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
		321	}
		322
		323	/* DeInit the low level hardware */
		324	hnor->MspDeInitCallback(hnor);
		325	#else
2	mjames	326	/* De-Initialize the low level hardware (MSP) */
		327	HAL_NOR_MspDeInit(hnor);
9	mjames	328	#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
		329
2	mjames	330	/* Configure the NOR registers with their reset values */
9	mjames	331	(void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
		332
		333	/* Reset the NOR controller state */
2	mjames	334	hnor->State = HAL_NOR_STATE_RESET;
		335
		336	/* Release Lock */
		337	__HAL_UNLOCK(hnor);
		338
		339	return HAL_OK;
		340	}
		341
		342	/**
		343	* @brief NOR MSP Init
9	mjames	344	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	345	* the configuration information for NOR module.
		346	* @retval None
		347	*/
		348	__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
		349	{
		350	/* Prevent unused argument(s) compilation warning */
		351	UNUSED(hnor);
9	mjames	352
2	mjames	353	/* NOTE : This function Should not be modified, when the callback is needed,
		354	the HAL_NOR_MspInit could be implemented in the user file
9	mjames	355	*/
2	mjames	356	}
		357
		358	/**
		359	* @brief NOR MSP DeInit
9	mjames	360	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	361	* the configuration information for NOR module.
		362	* @retval None
		363	*/
		364	__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
		365	{
		366	/* Prevent unused argument(s) compilation warning */
		367	UNUSED(hnor);
9	mjames	368
2	mjames	369	/* NOTE : This function Should not be modified, when the callback is needed,
		370	the HAL_NOR_MspDeInit could be implemented in the user file
9	mjames	371	*/
2	mjames	372	}
		373
		374	/**
9	mjames	375	* @brief NOR MSP Wait for Ready/Busy signal
		376	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	377	* the configuration information for NOR module.
9	mjames	378	* @param Timeout Maximum timeout value
2	mjames	379	* @retval None
		380	*/
		381	__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
		382	{
		383	/* Prevent unused argument(s) compilation warning */
		384	UNUSED(hnor);
		385	UNUSED(Timeout);
9	mjames	386
2	mjames	387	/* NOTE : This function Should not be modified, when the callback is needed,
		388	the HAL_NOR_MspWait could be implemented in the user file
9	mjames	389	*/
2	mjames	390	}
9	mjames	391
2	mjames	392	/**
		393	* @}
		394	*/
		395
9	mjames	396	/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
		397	* @brief Input Output and memory control functions
2	mjames	398	*
9	mjames	399	@verbatim
2	mjames	400	==============================================================================
		401	##### NOR Input and Output functions #####
		402	==============================================================================
9	mjames	403	[..]
2	mjames	404	This section provides functions allowing to use and control the NOR memory
9	mjames	405
2	mjames	406	@endverbatim
		407	* @{
		408	*/
9	mjames	409
2	mjames	410	/**
		411	* @brief Read NOR flash IDs
9	mjames	412	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	413	* the configuration information for NOR module.
9	mjames	414	* @param pNOR_ID pointer to NOR ID structure
2	mjames	415	* @retval HAL status
		416	*/
		417	HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef hnor, NOR_IDTypeDef pNOR_ID)
		418	{
9	mjames	419	uint32_t deviceaddress;
		420	HAL_NOR_StateTypeDef state;
		421	HAL_StatusTypeDef status = HAL_OK;
		422
2	mjames	423	/* Check the NOR controller state */
9	mjames	424	state = hnor->State;
		425	if (state == HAL_NOR_STATE_BUSY)
2	mjames	426	{
9	mjames	427	return HAL_BUSY;
2	mjames	428	}
9	mjames	429	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
2	mjames	430	{
9	mjames	431	/* Process Locked */
		432	__HAL_LOCK(hnor);
		433
		434	/* Update the NOR controller state */
		435	hnor->State = HAL_NOR_STATE_BUSY;
		436
		437	/* Select the NOR device address */
		438	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		439	{
		440	deviceaddress = NOR_MEMORY_ADRESS1;
		441	}
		442	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		443	{
		444	deviceaddress = NOR_MEMORY_ADRESS2;
		445	}
		446	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		447	{
		448	deviceaddress = NOR_MEMORY_ADRESS3;
		449	}
		450	else /* FSMC_NORSRAM_BANK4 */
		451	{
		452	deviceaddress = NOR_MEMORY_ADRESS4;
		453	}
		454
		455	/* Send read ID command */
		456	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		457	{
		458	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		459	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		460	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
		461	}
		462	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		463	{
		464	NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
		465	}
		466	else
		467	{
		468	/* Primary command set not supported by the driver */
		469	status = HAL_ERROR;
		470	}
		471
		472	if (status != HAL_ERROR)
		473	{
		474	/* Read the NOR IDs */
		475	pNOR_ID->Manufacturer_Code = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
		476	pNOR_ID->Device_Code1 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
		477	pNOR_ID->Device_Code2 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
		478	pNOR_ID->Device_Code3 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
		479	}
		480
		481	/* Check the NOR controller state */
		482	hnor->State = state;
		483
		484	/* Process unlocked */
		485	__HAL_UNLOCK(hnor);
2	mjames	486	}
9	mjames	487	else
2	mjames	488	{
9	mjames	489	return HAL_ERROR;
2	mjames	490	}
		491
9	mjames	492	return status;
2	mjames	493	}
		494
		495	/**
		496	* @brief Returns the NOR memory to Read mode.
9	mjames	497	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	498	* the configuration information for NOR module.
		499	* @retval HAL status
		500	*/
		501	HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
		502	{
9	mjames	503	uint32_t deviceaddress;
		504	HAL_NOR_StateTypeDef state;
		505	HAL_StatusTypeDef status = HAL_OK;
		506
2	mjames	507	/* Check the NOR controller state */
9	mjames	508	state = hnor->State;
		509	if (state == HAL_NOR_STATE_BUSY)
2	mjames	510	{
9	mjames	511	return HAL_BUSY;
2	mjames	512	}
9	mjames	513	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
2	mjames	514	{
9	mjames	515	/* Process Locked */
		516	__HAL_LOCK(hnor);
		517
		518	/* Update the NOR controller state */
		519	hnor->State = HAL_NOR_STATE_BUSY;
		520
		521	/* Select the NOR device address */
		522	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		523	{
		524	deviceaddress = NOR_MEMORY_ADRESS1;
		525	}
		526	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		527	{
		528	deviceaddress = NOR_MEMORY_ADRESS2;
		529	}
		530	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		531	{
		532	deviceaddress = NOR_MEMORY_ADRESS3;
		533	}
		534	else /* FSMC_NORSRAM_BANK4 */
		535	{
		536	deviceaddress = NOR_MEMORY_ADRESS4;
		537	}
		538
		539	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		540	{
		541	NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
		542	}
		543	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		544	{
		545	NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
		546	}
		547	else
		548	{
		549	/* Primary command set not supported by the driver */
		550	status = HAL_ERROR;
		551	}
		552
		553	/* Check the NOR controller state */
		554	hnor->State = state;
		555
		556	/* Process unlocked */
		557	__HAL_UNLOCK(hnor);
2	mjames	558	}
9	mjames	559	else
2	mjames	560	{
9	mjames	561	return HAL_ERROR;
2	mjames	562	}
		563
9	mjames	564	return status;
2	mjames	565	}
		566
		567	/**
9	mjames	568	* @brief Read data from NOR memory
		569	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	570	* the configuration information for NOR module.
9	mjames	571	* @param pAddress pointer to Device address
		572	* @param pData pointer to read data
2	mjames	573	* @retval HAL status
		574	*/
		575	HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef hnor, uint32_t pAddress, uint16_t *pData)
		576	{
9	mjames	577	uint32_t deviceaddress;
		578	HAL_NOR_StateTypeDef state;
		579	HAL_StatusTypeDef status = HAL_OK;
		580
2	mjames	581	/* Check the NOR controller state */
9	mjames	582	state = hnor->State;
		583	if (state == HAL_NOR_STATE_BUSY)
2	mjames	584	{
9	mjames	585	return HAL_BUSY;
2	mjames	586	}
9	mjames	587	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
2	mjames	588	{
9	mjames	589	/* Process Locked */
		590	__HAL_LOCK(hnor);
		591
		592	/* Update the NOR controller state */
		593	hnor->State = HAL_NOR_STATE_BUSY;
		594
		595	/* Select the NOR device address */
		596	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		597	{
		598	deviceaddress = NOR_MEMORY_ADRESS1;
		599	}
		600	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		601	{
		602	deviceaddress = NOR_MEMORY_ADRESS2;
		603	}
		604	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		605	{
		606	deviceaddress = NOR_MEMORY_ADRESS3;
		607	}
		608	else /* FSMC_NORSRAM_BANK4 */
		609	{
		610	deviceaddress = NOR_MEMORY_ADRESS4;
		611	}
		612
		613	/* Send read data command */
		614	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		615	{
		616	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		617	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		618	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
		619	}
		620	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		621	{
		622	NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
		623	}
		624	else
		625	{
		626	/* Primary command set not supported by the driver */
		627	status = HAL_ERROR;
		628	}
		629
		630	if (status != HAL_ERROR)
		631	{
		632	/* Read the data */
		633	pData = (uint16_t)((__IO uint32_t *)pAddress);
		634	}
		635
		636	/* Check the NOR controller state */
		637	hnor->State = state;
		638
		639	/* Process unlocked */
		640	__HAL_UNLOCK(hnor);
2	mjames	641	}
9	mjames	642	else
2	mjames	643	{
9	mjames	644	return HAL_ERROR;
2	mjames	645	}
		646
9	mjames	647	return status;
2	mjames	648	}
		649
		650	/**
9	mjames	651	* @brief Program data to NOR memory
		652	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	653	* the configuration information for NOR module.
9	mjames	654	* @param pAddress Device address
		655	* @param pData pointer to the data to write
2	mjames	656	* @retval HAL status
		657	*/
		658	HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef hnor, uint32_t pAddress, uint16_t *pData)
		659	{
9	mjames	660	uint32_t deviceaddress;
		661	HAL_StatusTypeDef status = HAL_OK;
		662
2	mjames	663	/* Check the NOR controller state */
9	mjames	664	if (hnor->State == HAL_NOR_STATE_BUSY)
2	mjames	665	{
9	mjames	666	return HAL_BUSY;
2	mjames	667	}
9	mjames	668	else if (hnor->State == HAL_NOR_STATE_READY)
2	mjames	669	{
9	mjames	670	/* Process Locked */
		671	__HAL_LOCK(hnor);
		672
		673	/* Update the NOR controller state */
		674	hnor->State = HAL_NOR_STATE_BUSY;
		675
		676	/* Select the NOR device address */
		677	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		678	{
		679	deviceaddress = NOR_MEMORY_ADRESS1;
		680	}
		681	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		682	{
		683	deviceaddress = NOR_MEMORY_ADRESS2;
		684	}
		685	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		686	{
		687	deviceaddress = NOR_MEMORY_ADRESS3;
		688	}
		689	else /* FSMC_NORSRAM_BANK4 */
		690	{
		691	deviceaddress = NOR_MEMORY_ADRESS4;
		692	}
		693
		694	/* Send program data command */
		695	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		696	{
		697	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		698	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		699	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
		700	}
		701	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		702	{
		703	NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
		704	}
		705	else
		706	{
		707	/* Primary command set not supported by the driver */
		708	status = HAL_ERROR;
		709	}
		710
		711	if (status != HAL_ERROR)
		712	{
		713	/* Write the data */
		714	NOR_WRITE(pAddress, *pData);
		715	}
		716
		717	/* Check the NOR controller state */
		718	hnor->State = HAL_NOR_STATE_READY;
		719
		720	/* Process unlocked */
		721	__HAL_UNLOCK(hnor);
2	mjames	722	}
9	mjames	723	else
2	mjames	724	{
9	mjames	725	return HAL_ERROR;
2	mjames	726	}
		727
9	mjames	728	return status;
2	mjames	729	}
		730
		731	/**
9	mjames	732	* @brief Reads a half-word buffer from the NOR memory.
		733	* @param hnor pointer to the NOR handle
		734	* @param uwAddress NOR memory internal address to read from.
		735	* @param pData pointer to the buffer that receives the data read from the
2	mjames	736	* NOR memory.
9	mjames	737	* @param uwBufferSize number of Half word to read.
2	mjames	738	* @retval HAL status
		739	*/
9	mjames	740	HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef hnor, uint32_t uwAddress, uint16_t pData,
		741	uint32_t uwBufferSize)
2	mjames	742	{
9	mjames	743	uint32_t deviceaddress;
		744	uint32_t size = uwBufferSize;
		745	uint32_t address = uwAddress;
		746	uint16_t *data = pData;
		747	HAL_NOR_StateTypeDef state;
		748	HAL_StatusTypeDef status = HAL_OK;
		749
2	mjames	750	/* Check the NOR controller state */
9	mjames	751	state = hnor->State;
		752	if (state == HAL_NOR_STATE_BUSY)
2	mjames	753	{
9	mjames	754	return HAL_BUSY;
2	mjames	755	}
9	mjames	756	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
2	mjames	757	{
9	mjames	758	/* Process Locked */
		759	__HAL_LOCK(hnor);
		760
		761	/* Update the NOR controller state */
		762	hnor->State = HAL_NOR_STATE_BUSY;
		763
		764	/* Select the NOR device address */
		765	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		766	{
		767	deviceaddress = NOR_MEMORY_ADRESS1;
		768	}
		769	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		770	{
		771	deviceaddress = NOR_MEMORY_ADRESS2;
		772	}
		773	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		774	{
		775	deviceaddress = NOR_MEMORY_ADRESS3;
		776	}
		777	else /* FSMC_NORSRAM_BANK4 */
		778	{
		779	deviceaddress = NOR_MEMORY_ADRESS4;
		780	}
		781
		782	/* Send read data command */
		783	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		784	{
		785	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		786	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		787	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
		788	}
		789	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		790	{
		791	NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
		792	}
		793	else
		794	{
		795	/* Primary command set not supported by the driver */
		796	status = HAL_ERROR;
		797	}
		798
		799	if (status != HAL_ERROR)
		800	{
		801	/* Read buffer */
		802	while (size > 0U)
		803	{
		804	data = (__IO uint16_t *)address;
		805	data++;
		806	address += 2U;
		807	size--;
		808	}
		809	}
		810
		811	/* Check the NOR controller state */
		812	hnor->State = state;
		813
		814	/* Process unlocked */
		815	__HAL_UNLOCK(hnor);
2	mjames	816	}
9	mjames	817	else
2	mjames	818	{
9	mjames	819	return HAL_ERROR;
2	mjames	820	}
9	mjames	821
		822	return status;
2	mjames	823	}
		824
		825	/**
9	mjames	826	* @brief Writes a half-word buffer to the NOR memory. This function must be used
		827	only with S29GL128P NOR memory.
		828	* @param hnor pointer to the NOR handle
		829	* @param uwAddress NOR memory internal start write address
		830	* @param pData pointer to source data buffer.
		831	* @param uwBufferSize Size of the buffer to write
2	mjames	832	* @retval HAL status
9	mjames	833	*/
		834	HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef hnor, uint32_t uwAddress, uint16_t pData,
		835	uint32_t uwBufferSize)
2	mjames	836	{
9	mjames	837	uint16_t *p_currentaddress;
		838	const uint16_t *p_endaddress;
		839	uint16_t *data = pData;
		840	uint32_t deviceaddress;
		841	HAL_StatusTypeDef status = HAL_OK;
		842
2	mjames	843	/* Check the NOR controller state */
9	mjames	844	if (hnor->State == HAL_NOR_STATE_BUSY)
2	mjames	845	{
9	mjames	846	return HAL_BUSY;
2	mjames	847	}
9	mjames	848	else if (hnor->State == HAL_NOR_STATE_READY)
2	mjames	849	{
9	mjames	850	/* Process Locked */
		851	__HAL_LOCK(hnor);
2	mjames	852
9	mjames	853	/* Update the NOR controller state */
		854	hnor->State = HAL_NOR_STATE_BUSY;
2	mjames	855
9	mjames	856	/* Select the NOR device address */
		857	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		858	{
		859	deviceaddress = NOR_MEMORY_ADRESS1;
		860	}
		861	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		862	{
		863	deviceaddress = NOR_MEMORY_ADRESS2;
		864	}
		865	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		866	{
		867	deviceaddress = NOR_MEMORY_ADRESS3;
		868	}
		869	else /* FSMC_NORSRAM_BANK4 */
		870	{
		871	deviceaddress = NOR_MEMORY_ADRESS4;
		872	}
2	mjames	873
9	mjames	874	/* Initialize variables */
		875	p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
		876	p_endaddress = (uint16_t )(deviceaddress + uwAddress + (2U (uwBufferSize - 1U)));
		877
		878	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		879	{
		880	/* Issue unlock command sequence */
		881	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		882	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		883
		884	/* Write Buffer Load Command */
		885	NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
		886	NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
		887	}
		888	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		889	{
		890	/* Write Buffer Load Command */
		891	NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
		892	NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
		893	}
		894	else
		895	{
		896	/* Primary command set not supported by the driver */
		897	status = HAL_ERROR;
		898	}
		899
		900	if (status != HAL_ERROR)
		901	{
		902	/* Load Data into NOR Buffer */
		903	while (p_currentaddress <= p_endaddress)
		904	{
		905	NOR_WRITE(p_currentaddress, *data);
		906
		907	data++;
		908	p_currentaddress ++;
		909	}
		910
		911	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		912	{
		913	NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
		914	}
		915	else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
		916	{
		917	NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
		918	}
		919	}
		920
		921	/* Check the NOR controller state */
		922	hnor->State = HAL_NOR_STATE_READY;
		923
		924	/* Process unlocked */
		925	__HAL_UNLOCK(hnor);
		926	}
		927	else
2	mjames	928	{
9	mjames	929	return HAL_ERROR;
2	mjames	930	}
		931
9	mjames	932	return status;
		933
2	mjames	934	}
		935
		936	/**
9	mjames	937	* @brief Erase the specified block of the NOR memory
		938	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	939	* the configuration information for NOR module.
9	mjames	940	* @param BlockAddress Block to erase address
		941	* @param Address Device address
2	mjames	942	* @retval HAL status
		943	*/
		944	HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
		945	{
9	mjames	946	uint32_t deviceaddress;
		947	HAL_StatusTypeDef status = HAL_OK;
2	mjames	948
		949	/* Check the NOR controller state */
9	mjames	950	if (hnor->State == HAL_NOR_STATE_BUSY)
2	mjames	951	{
9	mjames	952	return HAL_BUSY;
2	mjames	953	}
9	mjames	954	else if (hnor->State == HAL_NOR_STATE_READY)
2	mjames	955	{
9	mjames	956	/* Process Locked */
		957	__HAL_LOCK(hnor);
		958
		959	/* Update the NOR controller state */
		960	hnor->State = HAL_NOR_STATE_BUSY;
		961
		962	/* Select the NOR device address */
		963	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		964	{
		965	deviceaddress = NOR_MEMORY_ADRESS1;
		966	}
		967	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		968	{
		969	deviceaddress = NOR_MEMORY_ADRESS2;
		970	}
		971	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		972	{
		973	deviceaddress = NOR_MEMORY_ADRESS3;
		974	}
		975	else /* FSMC_NORSRAM_BANK4 */
		976	{
		977	deviceaddress = NOR_MEMORY_ADRESS4;
		978	}
		979
		980	/* Send block erase command sequence */
		981	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		982	{
		983	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		984	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		985	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
		986	NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
		987	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
		988	NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
		989	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
		990	NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
		991	NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
		992	}
		993	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		994	{
		995	NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
		996	NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
		997	NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
		998	NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
		999	}
		1000	else
		1001	{
		1002	/* Primary command set not supported by the driver */
		1003	status = HAL_ERROR;
		1004	}
		1005
		1006	/* Check the NOR memory status and update the controller state */
		1007	hnor->State = HAL_NOR_STATE_READY;
		1008
		1009	/* Process unlocked */
		1010	__HAL_UNLOCK(hnor);
2	mjames	1011	}
9	mjames	1012	else
2	mjames	1013	{
9	mjames	1014	return HAL_ERROR;
2	mjames	1015	}
		1016
9	mjames	1017	return status;
		1018
2	mjames	1019	}
		1020
		1021	/**
		1022	* @brief Erase the entire NOR chip.
9	mjames	1023	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	1024	* the configuration information for NOR module.
9	mjames	1025	* @param Address Device address
2	mjames	1026	* @retval HAL status
		1027	*/
		1028	HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
		1029	{
9	mjames	1030	uint32_t deviceaddress;
		1031	HAL_StatusTypeDef status = HAL_OK;
2	mjames	1032	UNUSED(Address);
		1033
		1034	/* Check the NOR controller state */
9	mjames	1035	if (hnor->State == HAL_NOR_STATE_BUSY)
2	mjames	1036	{
9	mjames	1037	return HAL_BUSY;
2	mjames	1038	}
9	mjames	1039	else if (hnor->State == HAL_NOR_STATE_READY)
2	mjames	1040	{
9	mjames	1041	/* Process Locked */
		1042	__HAL_LOCK(hnor);
		1043
		1044	/* Update the NOR controller state */
		1045	hnor->State = HAL_NOR_STATE_BUSY;
		1046
		1047	/* Select the NOR device address */
		1048	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		1049	{
		1050	deviceaddress = NOR_MEMORY_ADRESS1;
		1051	}
		1052	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		1053	{
		1054	deviceaddress = NOR_MEMORY_ADRESS2;
		1055	}
		1056	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		1057	{
		1058	deviceaddress = NOR_MEMORY_ADRESS3;
		1059	}
		1060	else /* FSMC_NORSRAM_BANK4 */
		1061	{
		1062	deviceaddress = NOR_MEMORY_ADRESS4;
		1063	}
		1064
		1065	/* Send NOR chip erase command sequence */
		1066	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		1067	{
		1068	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		1069	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		1070	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
		1071	NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
		1072	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
		1073	NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
		1074	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
		1075	NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
		1076	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
		1077	}
		1078	else
		1079	{
		1080	/* Primary command set not supported by the driver */
		1081	status = HAL_ERROR;
		1082	}
		1083
		1084	/* Check the NOR memory status and update the controller state */
		1085	hnor->State = HAL_NOR_STATE_READY;
		1086
		1087	/* Process unlocked */
		1088	__HAL_UNLOCK(hnor);
2	mjames	1089	}
9	mjames	1090	else
2	mjames	1091	{
9	mjames	1092	return HAL_ERROR;
2	mjames	1093	}
9	mjames	1094
		1095	return status;
2	mjames	1096	}
		1097
		1098	/**
		1099	* @brief Read NOR flash CFI IDs
9	mjames	1100	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	1101	* the configuration information for NOR module.
9	mjames	1102	* @param pNOR_CFI pointer to NOR CFI IDs structure
2	mjames	1103	* @retval HAL status
		1104	*/
		1105	HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef hnor, NOR_CFITypeDef pNOR_CFI)
		1106	{
9	mjames	1107	uint32_t deviceaddress;
		1108	HAL_NOR_StateTypeDef state;
		1109
2	mjames	1110	/* Check the NOR controller state */
9	mjames	1111	state = hnor->State;
		1112	if (state == HAL_NOR_STATE_BUSY)
2	mjames	1113	{
9	mjames	1114	return HAL_BUSY;
2	mjames	1115	}
9	mjames	1116	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
2	mjames	1117	{
9	mjames	1118	/* Process Locked */
		1119	__HAL_LOCK(hnor);
		1120
		1121	/* Update the NOR controller state */
		1122	hnor->State = HAL_NOR_STATE_BUSY;
		1123
		1124	/* Select the NOR device address */
		1125	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		1126	{
		1127	deviceaddress = NOR_MEMORY_ADRESS1;
		1128	}
		1129	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		1130	{
		1131	deviceaddress = NOR_MEMORY_ADRESS2;
		1132	}
		1133	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		1134	{
		1135	deviceaddress = NOR_MEMORY_ADRESS3;
		1136	}
		1137	else /* FSMC_NORSRAM_BANK4 */
		1138	{
		1139	deviceaddress = NOR_MEMORY_ADRESS4;
		1140	}
		1141
		1142	/* Send read CFI query command */
		1143	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
		1144
		1145	/* read the NOR CFI information */
		1146	pNOR_CFI->CFI_1 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
		1147	pNOR_CFI->CFI_2 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
		1148	pNOR_CFI->CFI_3 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
		1149	pNOR_CFI->CFI_4 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
		1150
		1151	/* Check the NOR controller state */
		1152	hnor->State = state;
		1153
		1154	/* Process unlocked */
		1155	__HAL_UNLOCK(hnor);
2	mjames	1156	}
9	mjames	1157	else
2	mjames	1158	{
9	mjames	1159	return HAL_ERROR;
2	mjames	1160	}
9	mjames	1161
		1162	return HAL_OK;
		1163	}
		1164
		1165	#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
		1166	/**
		1167	* @brief Register a User NOR Callback
		1168	* To be used instead of the weak (surcharged) predefined callback
		1169	* @param hnor : NOR handle
		1170	* @param CallbackId : ID of the callback to be registered
		1171	* This parameter can be one of the following values:
		1172	* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
		1173	* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
		1174	* @param pCallback : pointer to the Callback function
		1175	* @retval status
		1176	*/
		1177	HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
		1178	pNOR_CallbackTypeDef pCallback)
		1179	{
		1180	HAL_StatusTypeDef status = HAL_OK;
		1181	HAL_NOR_StateTypeDef state;
		1182
		1183	if (pCallback == NULL)
2	mjames	1184	{
9	mjames	1185	return HAL_ERROR;
2	mjames	1186	}
9	mjames	1187
		1188	/* Process locked */
		1189	__HAL_LOCK(hnor);
		1190
		1191	state = hnor->State;
		1192	if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_RESET) \|\| (state == HAL_NOR_STATE_PROTECTED))
2	mjames	1193	{
9	mjames	1194	switch (CallbackId)
		1195	{
		1196	case HAL_NOR_MSP_INIT_CB_ID :
		1197	hnor->MspInitCallback = pCallback;
		1198	break;
		1199	case HAL_NOR_MSP_DEINIT_CB_ID :
		1200	hnor->MspDeInitCallback = pCallback;
		1201	break;
		1202	default :
		1203	/* update return status */
		1204	status = HAL_ERROR;
		1205	break;
		1206	}
		1207	}
		1208	else
		1209	{
		1210	/* update return status */
		1211	status = HAL_ERROR;
		1212	}
2	mjames	1213
9	mjames	1214	/* Release Lock */
		1215	__HAL_UNLOCK(hnor);
		1216	return status;
		1217	}
2	mjames	1218
9	mjames	1219	/**
		1220	* @brief Unregister a User NOR Callback
		1221	* NOR Callback is redirected to the weak (surcharged) predefined callback
		1222	* @param hnor : NOR handle
		1223	* @param CallbackId : ID of the callback to be unregistered
		1224	* This parameter can be one of the following values:
		1225	* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
		1226	* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
		1227	* @retval status
		1228	*/
		1229	HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
		1230	{
		1231	HAL_StatusTypeDef status = HAL_OK;
		1232	HAL_NOR_StateTypeDef state;
		1233
		1234	/* Process locked */
		1235	__HAL_LOCK(hnor);
		1236
		1237	state = hnor->State;
		1238	if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_RESET) \|\| (state == HAL_NOR_STATE_PROTECTED))
		1239	{
		1240	switch (CallbackId)
		1241	{
		1242	case HAL_NOR_MSP_INIT_CB_ID :
		1243	hnor->MspInitCallback = HAL_NOR_MspInit;
		1244	break;
		1245	case HAL_NOR_MSP_DEINIT_CB_ID :
		1246	hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
		1247	break;
		1248	default :
		1249	/* update return status */
		1250	status = HAL_ERROR;
		1251	break;
		1252	}
		1253	}
		1254	else
		1255	{
		1256	/* update return status */
		1257	status = HAL_ERROR;
		1258	}
		1259
		1260	/* Release Lock */
2	mjames	1261	__HAL_UNLOCK(hnor);
9	mjames	1262	return status;
2	mjames	1263	}
9	mjames	1264	#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
2	mjames	1265
		1266	/**
		1267	* @}
		1268	*/
9	mjames	1269
		1270	/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
		1271	* @brief management functions
		1272	*
		1273	@verbatim
2	mjames	1274	==============================================================================
		1275	##### NOR Control functions #####
		1276	==============================================================================
		1277	[..]
		1278	This subsection provides a set of functions allowing to control dynamically
		1279	the NOR interface.
		1280
		1281	@endverbatim
		1282	* @{
		1283	*/
9	mjames	1284
2	mjames	1285	/**
		1286	* @brief Enables dynamically NOR write operation.
9	mjames	1287	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	1288	* the configuration information for NOR module.
		1289	* @retval HAL status
		1290	*/
		1291	HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
		1292	{
9	mjames	1293	/* Check the NOR controller state */
		1294	if (hnor->State == HAL_NOR_STATE_PROTECTED)
		1295	{
		1296	/* Process Locked */
		1297	__HAL_LOCK(hnor);
2	mjames	1298
9	mjames	1299	/* Update the NOR controller state */
		1300	hnor->State = HAL_NOR_STATE_BUSY;
		1301
		1302	/* Enable write operation */
		1303	(void)FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
		1304
		1305	/* Update the NOR controller state */
		1306	hnor->State = HAL_NOR_STATE_READY;
		1307
		1308	/* Process unlocked */
		1309	__HAL_UNLOCK(hnor);
		1310	}
		1311	else
		1312	{
		1313	return HAL_ERROR;
		1314	}
		1315
		1316	return HAL_OK;
2	mjames	1317	}
		1318
		1319	/**
		1320	* @brief Disables dynamically NOR write operation.
9	mjames	1321	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	1322	* the configuration information for NOR module.
		1323	* @retval HAL status
		1324	*/
		1325	HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
		1326	{
9	mjames	1327	/* Check the NOR controller state */
		1328	if (hnor->State == HAL_NOR_STATE_READY)
		1329	{
		1330	/* Process Locked */
		1331	__HAL_LOCK(hnor);
2	mjames	1332
9	mjames	1333	/* Update the NOR controller state */
		1334	hnor->State = HAL_NOR_STATE_BUSY;
		1335
		1336	/* Disable write operation */
		1337	(void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
		1338
		1339	/* Update the NOR controller state */
		1340	hnor->State = HAL_NOR_STATE_PROTECTED;
		1341
		1342	/* Process unlocked */
		1343	__HAL_UNLOCK(hnor);
		1344	}
		1345	else
		1346	{
		1347	return HAL_ERROR;
		1348	}
		1349
		1350	return HAL_OK;
2	mjames	1351	}
		1352
		1353	/**
		1354	* @}
9	mjames	1355	*/
		1356
		1357	/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
		1358	* @brief Peripheral State functions
		1359	*
		1360	@verbatim
2	mjames	1361	==============================================================================
		1362	##### NOR State functions #####
9	mjames	1363	==============================================================================
2	mjames	1364	[..]
9	mjames	1365	This subsection permits to get in run-time the status of the NOR controller
2	mjames	1366	and the data flow.
		1367
		1368	@endverbatim
		1369	* @{
		1370	*/
9	mjames	1371
2	mjames	1372	/**
		1373	* @brief return the NOR controller state
9	mjames	1374	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
2	mjames	1375	* the configuration information for NOR module.
		1376	* @retval NOR controller state
		1377	*/
		1378	HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
		1379	{
		1380	return hnor->State;
		1381	}
		1382
		1383	/**
		1384	* @brief Returns the NOR operation status.
9	mjames	1385	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1386	* the configuration information for NOR module.
		1387	* @param Address Device address
		1388	* @param Timeout NOR programming Timeout
		1389	* @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
2	mjames	1390	* or HAL_NOR_STATUS_TIMEOUT
		1391	*/
		1392	HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
9	mjames	1393	{
2	mjames	1394	HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
9	mjames	1395	uint16_t tmpsr1;
		1396	uint16_t tmpsr2;
		1397	uint32_t tickstart;
2	mjames	1398
		1399	/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
		1400	HAL_NOR_MspWait(hnor, Timeout);
9	mjames	1401
		1402	/* Get the NOR memory operation status -------------------------------------*/
		1403
2	mjames	1404	/* Get tick */
		1405	tickstart = HAL_GetTick();
9	mjames	1406
		1407	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
2	mjames	1408	{
9	mjames	1409	while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
2	mjames	1410	{
9	mjames	1411	/* Check for the Timeout */
		1412	if (Timeout != HAL_MAX_DELAY)
2	mjames	1413	{
9	mjames	1414	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
		1415	{
		1416	status = HAL_NOR_STATUS_TIMEOUT;
		1417	}
		1418	}
2	mjames	1419
9	mjames	1420	/* Read NOR status register (DQ6 and DQ5) */
		1421	tmpsr1 = (__IO uint16_t )Address;
		1422	tmpsr2 = (__IO uint16_t )Address;
2	mjames	1423
9	mjames	1424	/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
		1425	if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
		1426	{
		1427	return HAL_NOR_STATUS_SUCCESS ;
		1428	}
		1429
		1430	if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
		1431	{
		1432	status = HAL_NOR_STATUS_ONGOING;
		1433	}
		1434
		1435	tmpsr1 = (__IO uint16_t )Address;
		1436	tmpsr2 = (__IO uint16_t )Address;
		1437
		1438	/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
		1439	if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
		1440	{
		1441	return HAL_NOR_STATUS_SUCCESS;
		1442	}
		1443	if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
		1444	{
		1445	return HAL_NOR_STATUS_ERROR;
		1446	}
2	mjames	1447	}
9	mjames	1448	}
		1449	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		1450	{
		1451	do
2	mjames	1452	{
9	mjames	1453	NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
		1454	tmpsr2 = (__IO uint16_t )(Address);
2	mjames	1455
9	mjames	1456	/* Check for the Timeout */
		1457	if (Timeout != HAL_MAX_DELAY)
		1458	{
		1459	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
		1460	{
		1461	return HAL_NOR_STATUS_TIMEOUT;
		1462	}
		1463	}
		1464	} while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
		1465
		1466	NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
		1467	tmpsr1 = (__IO uint16_t )(Address);
		1468	if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 \| NOR_MASK_STATUS_DQ4)) != 0U)
2	mjames	1469	{
9	mjames	1470	/* Clear the Status Register */
		1471	NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
		1472	status = HAL_NOR_STATUS_ERROR;
2	mjames	1473	}
9	mjames	1474	else
2	mjames	1475	{
9	mjames	1476	status = HAL_NOR_STATUS_SUCCESS;
		1477	}
2	mjames	1478	}
9	mjames	1479	else
		1480	{
		1481	/* Primary command set not supported by the driver */
		1482	status = HAL_NOR_STATUS_ERROR;
		1483	}
2	mjames	1484
		1485	/* Return the operation status */
		1486	return status;
		1487	}
		1488
		1489	/**
		1490	* @}
		1491	*/
		1492
		1493	/**
		1494	* @}
		1495	*/
9	mjames	1496
2	mjames	1497	/**
		1498	* @}
		1499	*/
9	mjames	1500
2	mjames	1501	#endif /* HAL_NOR_MODULE_ENABLED */
		1502
		1503	/**
		1504	* @}
		1505	*/
		1506
9	mjames	1507	#endif /* FSMC_BANK1 */
		1508
2	mjames	1509	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c – Rev 9