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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_nor.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V1.0.1 |
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| 6 | * @date 31-July-2015 |
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| 7 | * @brief NOR HAL module driver. |
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| 8 | * This file provides a generic firmware to drive NOR memories mounted |
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| 9 | * as external device. |
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| 10 | * |
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| 11 | @verbatim |
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| 12 | ============================================================================== |
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| 13 | ##### How to use this driver ##### |
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| 14 | ============================================================================== |
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| 15 | [..] |
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| 16 | This driver is a generic layered driver which contains a set of APIs used to |
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| 17 | control NOR flash memories. It uses the FSMC layer functions to interface |
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| 18 | with NOR devices. This driver is used as follows: |
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| 19 | |||
| 20 | (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() |
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| 21 | with control and timing parameters for both normal and extended mode. |
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| 22 | |||
| 23 | (+) Read NOR flash memory manufacturer code and device IDs using the function |
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| 24 | HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef |
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| 25 | structure declared by the function caller. |
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| 26 | |||
| 27 | (+) Access NOR flash memory by read/write data unit operations using the functions |
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| 28 | HAL_NOR_Read(), HAL_NOR_Program(). |
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| 29 | |||
| 30 | (+) Perform NOR flash erase block/chip operations using the functions |
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| 31 | HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). |
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| 32 | |||
| 33 | (+) Read the NOR flash CFI (common flash interface) IDs using the function |
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| 34 | HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef |
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| 35 | structure declared by the function caller. |
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| 36 | |||
| 37 | (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ |
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| 38 | HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation |
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| 39 | |||
| 40 | (+) You can monitor the NOR device HAL state by calling the function |
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| 41 | HAL_NOR_GetState() |
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| 42 | [..] |
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| 43 | (@) This driver is a set of generic APIs which handle standard NOR flash operations. |
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| 44 | If a NOR flash device contains different operations and/or implementations, |
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| 45 | it should be implemented separately. |
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| 46 | |||
| 47 | *** NOR HAL driver macros list *** |
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| 48 | ============================================= |
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| 49 | [..] |
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| 50 | Below the list of most used macros in NOR HAL driver. |
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| 51 | |||
| 52 | (+) NOR_WRITE : NOR memory write data to specified address |
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| 53 | |||
| 54 | @endverbatim |
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| 55 | ****************************************************************************** |
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| 56 | * @attention |
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| 57 | * |
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| 58 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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| 59 | * |
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| 60 | * Redistribution and use in source and binary forms, with or without modification, |
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| 61 | * are permitted provided that the following conditions are met: |
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| 62 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 63 | * this list of conditions and the following disclaimer. |
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| 64 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 65 | * this list of conditions and the following disclaimer in the documentation |
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| 66 | * and/or other materials provided with the distribution. |
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| 67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 68 | * may be used to endorse or promote products derived from this software |
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| 69 | * without specific prior written permission. |
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| 70 | * |
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| 71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 81 | * |
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| 82 | ****************************************************************************** |
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| 83 | */ |
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| 84 | |||
| 85 | /* Includes ------------------------------------------------------------------*/ |
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| 86 | #include "stm32f1xx_hal.h" |
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| 87 | |||
| 88 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 89 | * @{ |
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| 90 | */ |
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| 91 | |||
| 92 | #ifdef HAL_NOR_MODULE_ENABLED |
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| 93 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE) |
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| 94 | |||
| 95 | /** @defgroup NOR NOR |
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| 96 | * @brief NOR driver modules |
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| 97 | * @{ |
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| 98 | */ |
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| 99 | /* Private typedef -----------------------------------------------------------*/ |
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| 100 | /* Private define ------------------------------------------------------------*/ |
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| 101 | /** @defgroup NOR_Private_Constants NOR Private Constants |
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| 102 | * @{ |
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| 103 | */ |
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| 104 | |||
| 105 | /* Constants to define address to set to write a command */ |
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| 106 | #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 |
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| 107 | #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 |
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| 108 | #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA |
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| 109 | #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555 |
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| 110 | #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555 |
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| 111 | #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA |
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| 112 | #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555 |
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| 113 | |||
| 114 | /* Constants to define data to program a command */ |
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| 115 | #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0 |
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| 116 | #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA |
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| 117 | #define NOR_CMD_DATA_SECOND (uint16_t)0x0055 |
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| 118 | #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090 |
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| 119 | #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0 |
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| 120 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080 |
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| 121 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA |
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| 122 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055 |
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| 123 | #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010 |
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| 124 | #define NOR_CMD_DATA_CFI (uint16_t)0x0098 |
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| 125 | |||
| 126 | #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25 |
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| 127 | #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 |
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| 128 | #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 |
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| 129 | |||
| 130 | /* Mask on NOR STATUS REGISTER */ |
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| 131 | #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 |
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| 132 | #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 |
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| 133 | |||
| 134 | /** |
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| 135 | * @} |
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| 136 | */ |
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| 137 | |||
| 138 | /* Private macro -------------------------------------------------------------*/ |
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| 139 | /** @defgroup NOR_Private_Macros NOR Private Macros |
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| 140 | * @{ |
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| 141 | */ |
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| 142 | |||
| 143 | /** |
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| 144 | * @} |
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| 145 | */ |
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| 146 | |||
| 147 | /* Private variables ---------------------------------------------------------*/ |
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| 148 | |||
| 149 | /** @defgroup NOR_Private_Variables NOR Private Variables |
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| 150 | * @{ |
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| 151 | */ |
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| 152 | |||
| 153 | static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; |
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| 154 | |||
| 155 | /** |
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| 156 | * @} |
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| 157 | */ |
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| 158 | |||
| 159 | /* Private function prototypes -----------------------------------------------*/ |
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| 160 | /* Private functions ---------------------------------------------------------*/ |
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| 161 | |||
| 162 | /** @defgroup NOR_Exported_Functions NOR Exported Functions |
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| 163 | * @{ |
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| 164 | */ |
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| 165 | |||
| 166 | /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 167 | * @brief Initialization and Configuration functions |
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| 168 | * |
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| 169 | @verbatim |
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| 170 | ============================================================================== |
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| 171 | ##### NOR Initialization and de_initialization functions ##### |
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| 172 | ============================================================================== |
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| 173 | [..] |
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| 174 | This section provides functions allowing to initialize/de-initialize |
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| 175 | the NOR memory |
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| 176 | |||
| 177 | @endverbatim |
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| 178 | * @{ |
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| 179 | */ |
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| 180 | |||
| 181 | /** |
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| 182 | * @brief Perform the NOR memory Initialization sequence |
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| 183 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 184 | * the configuration information for NOR module. |
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| 185 | * @param Timing: pointer to NOR control timing structure |
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| 186 | * @param ExtTiming: pointer to NOR extended mode timing structure |
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| 187 | * @retval HAL status |
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| 188 | */ |
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| 189 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming) |
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| 190 | { |
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| 191 | /* Check the NOR handle parameter */ |
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| 192 | if(hnor == NULL) |
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| 193 | { |
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| 194 | return HAL_ERROR; |
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| 195 | } |
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| 196 | |||
| 197 | if(hnor->State == HAL_NOR_STATE_RESET) |
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| 198 | { |
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| 199 | /* Allocate lock resource and initialize it */ |
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| 200 | hnor->Lock = HAL_UNLOCKED; |
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| 201 | |||
| 202 | /* Initialize the low level hardware (MSP) */ |
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| 203 | HAL_NOR_MspInit(hnor); |
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| 204 | } |
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| 205 | |||
| 206 | /* Initialize NOR control Interface */ |
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| 207 | FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); |
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| 208 | |||
| 209 | /* Initialize NOR timing Interface */ |
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| 210 | FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); |
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| 211 | |||
| 212 | /* Initialize NOR extended mode timing Interface */ |
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| 213 | FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); |
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| 214 | |||
| 215 | /* Enable the NORSRAM device */ |
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| 216 | __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); |
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| 217 | |||
| 218 | /* Initialize NOR Memory Data Width*/ |
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| 219 | if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8) |
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| 220 | { |
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| 221 | uwNORMemoryDataWidth = NOR_MEMORY_8B; |
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| 222 | } |
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| 223 | else |
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| 224 | { |
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| 225 | uwNORMemoryDataWidth = NOR_MEMORY_16B; |
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| 226 | } |
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| 227 | |||
| 228 | /* Check the NOR controller state */ |
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| 229 | hnor->State = HAL_NOR_STATE_READY; |
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| 230 | |||
| 231 | return HAL_OK; |
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| 232 | } |
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| 233 | |||
| 234 | /** |
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| 235 | * @brief Perform NOR memory De-Initialization sequence |
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| 236 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 237 | * the configuration information for NOR module. |
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| 238 | * @retval HAL status |
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| 239 | */ |
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| 240 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) |
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| 241 | { |
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| 242 | /* De-Initialize the low level hardware (MSP) */ |
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| 243 | HAL_NOR_MspDeInit(hnor); |
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| 244 | |||
| 245 | /* Configure the NOR registers with their reset values */ |
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| 246 | FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); |
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| 247 | |||
| 248 | /* Update the NOR controller state */ |
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| 249 | hnor->State = HAL_NOR_STATE_RESET; |
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| 250 | |||
| 251 | /* Release Lock */ |
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| 252 | __HAL_UNLOCK(hnor); |
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| 253 | |||
| 254 | return HAL_OK; |
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| 255 | } |
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| 256 | |||
| 257 | /** |
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| 258 | * @brief NOR MSP Init |
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| 259 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 260 | * the configuration information for NOR module. |
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| 261 | * @retval None |
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| 262 | */ |
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| 263 | __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) |
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| 264 | { |
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| 265 | /* NOTE : This function Should not be modified, when the callback is needed, |
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| 266 | the HAL_NOR_MspInit could be implemented in the user file |
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| 267 | */ |
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| 268 | } |
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| 269 | |||
| 270 | /** |
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| 271 | * @brief NOR MSP DeInit |
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| 272 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 273 | * the configuration information for NOR module. |
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| 274 | * @retval None |
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| 275 | */ |
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| 276 | __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) |
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| 277 | { |
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| 278 | /* NOTE : This function Should not be modified, when the callback is needed, |
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| 279 | the HAL_NOR_MspDeInit could be implemented in the user file |
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| 280 | */ |
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| 281 | } |
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| 282 | |||
| 283 | /** |
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| 284 | * @brief NOR MSP Wait fro Ready/Busy signal |
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| 285 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 286 | * the configuration information for NOR module. |
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| 287 | * @param Timeout: Maximum timeout value |
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| 288 | * @retval None |
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| 289 | */ |
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| 290 | __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) |
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| 291 | { |
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| 292 | /* NOTE : This function Should not be modified, when the callback is needed, |
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| 293 | the HAL_NOR_MspWait could be implemented in the user file |
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| 294 | */ |
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| 295 | } |
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| 296 | |||
| 297 | /** |
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| 298 | * @} |
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| 299 | */ |
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| 300 | |||
| 301 | /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions |
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| 302 | * @brief Input Output and memory control functions |
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| 303 | * |
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| 304 | @verbatim |
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| 305 | ============================================================================== |
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| 306 | ##### NOR Input and Output functions ##### |
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| 307 | ============================================================================== |
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| 308 | [..] |
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| 309 | This section provides functions allowing to use and control the NOR memory |
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| 310 | |||
| 311 | @endverbatim |
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| 312 | * @{ |
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| 313 | */ |
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| 314 | |||
| 315 | /** |
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| 316 | * @brief Read NOR flash IDs |
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| 317 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 318 | * the configuration information for NOR module. |
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| 319 | * @param pNOR_ID : pointer to NOR ID structure |
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| 320 | * @retval HAL status |
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| 321 | */ |
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| 322 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) |
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| 323 | { |
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| 324 | uint32_t deviceaddress = 0; |
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| 325 | |||
| 326 | /* Process Locked */ |
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| 327 | __HAL_LOCK(hnor); |
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| 328 | |||
| 329 | /* Check the NOR controller state */ |
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| 330 | if(hnor->State == HAL_NOR_STATE_BUSY) |
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| 331 | { |
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| 332 | return HAL_BUSY; |
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| 333 | } |
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| 334 | |||
| 335 | /* Select the NOR device address */ |
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| 336 | if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) |
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| 337 | { |
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| 338 | deviceaddress = NOR_MEMORY_ADRESS1; |
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| 339 | } |
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| 340 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) |
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| 341 | { |
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| 342 | deviceaddress = NOR_MEMORY_ADRESS2; |
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| 343 | } |
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| 344 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) |
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| 345 | { |
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| 346 | deviceaddress = NOR_MEMORY_ADRESS3; |
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| 347 | } |
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| 348 | else /* FSMC_NORSRAM_BANK4 */ |
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| 349 | { |
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| 350 | deviceaddress = NOR_MEMORY_ADRESS4; |
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| 351 | } |
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| 352 | |||
| 353 | /* Update the NOR controller state */ |
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| 354 | hnor->State = HAL_NOR_STATE_BUSY; |
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| 355 | |||
| 356 | /* Send read ID command */ |
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| 357 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
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| 358 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
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| 359 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); |
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| 360 | |||
| 361 | /* Read the NOR IDs */ |
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| 362 | pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); |
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| 363 | pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); |
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| 364 | pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); |
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| 365 | pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); |
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| 366 | |||
| 367 | /* Check the NOR controller state */ |
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| 368 | hnor->State = HAL_NOR_STATE_READY; |
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| 369 | |||
| 370 | /* Process unlocked */ |
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| 371 | __HAL_UNLOCK(hnor); |
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| 372 | |||
| 373 | return HAL_OK; |
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| 374 | } |
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| 375 | |||
| 376 | /** |
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| 377 | * @brief Returns the NOR memory to Read mode. |
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| 378 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 379 | * the configuration information for NOR module. |
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| 380 | * @retval HAL status |
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| 381 | */ |
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| 382 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) |
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| 383 | { |
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| 384 | uint32_t deviceaddress = 0; |
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| 385 | |||
| 386 | /* Process Locked */ |
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| 387 | __HAL_LOCK(hnor); |
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| 388 | |||
| 389 | /* Check the NOR controller state */ |
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| 390 | if(hnor->State == HAL_NOR_STATE_BUSY) |
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| 391 | { |
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| 392 | return HAL_BUSY; |
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| 393 | } |
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| 394 | |||
| 395 | /* Select the NOR device address */ |
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| 396 | if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) |
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| 397 | { |
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| 398 | deviceaddress = NOR_MEMORY_ADRESS1; |
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| 399 | } |
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| 400 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) |
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| 401 | { |
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| 402 | deviceaddress = NOR_MEMORY_ADRESS2; |
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| 403 | } |
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| 404 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) |
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| 405 | { |
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| 406 | deviceaddress = NOR_MEMORY_ADRESS3; |
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| 407 | } |
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| 408 | else /* FSMC_NORSRAM_BANK4 */ |
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| 409 | { |
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| 410 | deviceaddress = NOR_MEMORY_ADRESS4; |
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| 411 | } |
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| 412 | |||
| 413 | NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); |
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| 414 | |||
| 415 | /* Check the NOR controller state */ |
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| 416 | hnor->State = HAL_NOR_STATE_READY; |
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| 417 | |||
| 418 | /* Process unlocked */ |
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| 419 | __HAL_UNLOCK(hnor); |
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| 420 | |||
| 421 | return HAL_OK; |
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| 422 | } |
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| 423 | |||
| 424 | /** |
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| 425 | * @brief Read data from NOR memory |
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| 426 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 427 | * the configuration information for NOR module. |
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| 428 | * @param pAddress: pointer to Device address |
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| 429 | * @param pData : pointer to read data |
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| 430 | * @retval HAL status |
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| 431 | */ |
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| 432 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) |
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| 433 | { |
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| 434 | uint32_t deviceaddress = 0; |
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| 435 | |||
| 436 | /* Process Locked */ |
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| 437 | __HAL_LOCK(hnor); |
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| 438 | |||
| 439 | /* Check the NOR controller state */ |
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| 440 | if(hnor->State == HAL_NOR_STATE_BUSY) |
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| 441 | { |
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| 442 | return HAL_BUSY; |
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| 443 | } |
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| 444 | |||
| 445 | /* Select the NOR device address */ |
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| 446 | if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) |
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| 447 | { |
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| 448 | deviceaddress = NOR_MEMORY_ADRESS1; |
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| 449 | } |
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| 450 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) |
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| 451 | { |
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| 452 | deviceaddress = NOR_MEMORY_ADRESS2; |
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| 453 | } |
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| 454 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) |
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| 455 | { |
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| 456 | deviceaddress = NOR_MEMORY_ADRESS3; |
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| 457 | } |
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| 458 | else /* FSMC_NORSRAM_BANK4 */ |
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| 459 | { |
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| 460 | deviceaddress = NOR_MEMORY_ADRESS4; |
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| 461 | } |
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| 462 | |||
| 463 | /* Update the NOR controller state */ |
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| 464 | hnor->State = HAL_NOR_STATE_BUSY; |
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| 465 | |||
| 466 | /* Send read data command */ |
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| 467 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
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| 468 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
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| 469 | NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET); |
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| 470 | |||
| 471 | /* Read the data */ |
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| 472 | *pData = *(__IO uint32_t *)(uint32_t)pAddress; |
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| 473 | |||
| 474 | /* Check the NOR controller state */ |
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| 475 | hnor->State = HAL_NOR_STATE_READY; |
||
| 476 | |||
| 477 | /* Process unlocked */ |
||
| 478 | __HAL_UNLOCK(hnor); |
||
| 479 | |||
| 480 | return HAL_OK; |
||
| 481 | } |
||
| 482 | |||
| 483 | /** |
||
| 484 | * @brief Program data to NOR memory |
||
| 485 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
||
| 486 | * the configuration information for NOR module. |
||
| 487 | * @param pAddress: Device address |
||
| 488 | * @param pData : pointer to the data to write |
||
| 489 | * @retval HAL status |
||
| 490 | */ |
||
| 491 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) |
||
| 492 | { |
||
| 493 | uint32_t deviceaddress = 0; |
||
| 494 | |||
| 495 | /* Process Locked */ |
||
| 496 | __HAL_LOCK(hnor); |
||
| 497 | |||
| 498 | /* Check the NOR controller state */ |
||
| 499 | if(hnor->State == HAL_NOR_STATE_BUSY) |
||
| 500 | { |
||
| 501 | return HAL_BUSY; |
||
| 502 | } |
||
| 503 | |||
| 504 | /* Select the NOR device address */ |
||
| 505 | if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) |
||
| 506 | { |
||
| 507 | deviceaddress = NOR_MEMORY_ADRESS1; |
||
| 508 | } |
||
| 509 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) |
||
| 510 | { |
||
| 511 | deviceaddress = NOR_MEMORY_ADRESS2; |
||
| 512 | } |
||
| 513 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) |
||
| 514 | { |
||
| 515 | deviceaddress = NOR_MEMORY_ADRESS3; |
||
| 516 | } |
||
| 517 | else /* FSMC_NORSRAM_BANK4 */ |
||
| 518 | { |
||
| 519 | deviceaddress = NOR_MEMORY_ADRESS4; |
||
| 520 | } |
||
| 521 | |||
| 522 | /* Update the NOR controller state */ |
||
| 523 | hnor->State = HAL_NOR_STATE_BUSY; |
||
| 524 | |||
| 525 | /* Send program data command */ |
||
| 526 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
||
| 527 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
||
| 528 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); |
||
| 529 | |||
| 530 | /* Write the data */ |
||
| 531 | NOR_WRITE(pAddress, *pData); |
||
| 532 | |||
| 533 | /* Check the NOR controller state */ |
||
| 534 | hnor->State = HAL_NOR_STATE_READY; |
||
| 535 | |||
| 536 | /* Process unlocked */ |
||
| 537 | __HAL_UNLOCK(hnor); |
||
| 538 | |||
| 539 | return HAL_OK; |
||
| 540 | } |
||
| 541 | |||
| 542 | /** |
||
| 543 | * @brief Reads a block of data from the FSMC NOR memory. |
||
| 544 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
||
| 545 | * the configuration information for NOR module. |
||
| 546 | * @param uwAddress: NOR memory internal address to read from. |
||
| 547 | * @param pData: pointer to the buffer that receives the data read from the |
||
| 548 | * NOR memory. |
||
| 549 | * @param uwBufferSize : number of Half word to read. |
||
| 550 | * @retval HAL status |
||
| 551 | */ |
||
| 552 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) |
||
| 553 | { |
||
| 554 | uint32_t deviceaddress = 0; |
||
| 555 | |||
| 556 | /* Process Locked */ |
||
| 557 | __HAL_LOCK(hnor); |
||
| 558 | |||
| 559 | /* Check the NOR controller state */ |
||
| 560 | if(hnor->State == HAL_NOR_STATE_BUSY) |
||
| 561 | { |
||
| 562 | return HAL_BUSY; |
||
| 563 | } |
||
| 564 | |||
| 565 | /* Select the NOR device address */ |
||
| 566 | if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) |
||
| 567 | { |
||
| 568 | deviceaddress = NOR_MEMORY_ADRESS1; |
||
| 569 | } |
||
| 570 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) |
||
| 571 | { |
||
| 572 | deviceaddress = NOR_MEMORY_ADRESS2; |
||
| 573 | } |
||
| 574 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) |
||
| 575 | { |
||
| 576 | deviceaddress = NOR_MEMORY_ADRESS3; |
||
| 577 | } |
||
| 578 | else /* FSMC_NORSRAM_BANK4 */ |
||
| 579 | { |
||
| 580 | deviceaddress = NOR_MEMORY_ADRESS4; |
||
| 581 | } |
||
| 582 | |||
| 583 | /* Update the NOR controller state */ |
||
| 584 | hnor->State = HAL_NOR_STATE_BUSY; |
||
| 585 | |||
| 586 | /* Send read data command */ |
||
| 587 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
||
| 588 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
||
| 589 | NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET); |
||
| 590 | |||
| 591 | /* Read buffer */ |
||
| 592 | while( uwBufferSize > 0) |
||
| 593 | { |
||
| 594 | *pData++ = *(__IO uint16_t *)uwAddress; |
||
| 595 | uwAddress += 2; |
||
| 596 | uwBufferSize--; |
||
| 597 | } |
||
| 598 | |||
| 599 | /* Check the NOR controller state */ |
||
| 600 | hnor->State = HAL_NOR_STATE_READY; |
||
| 601 | |||
| 602 | /* Process unlocked */ |
||
| 603 | __HAL_UNLOCK(hnor); |
||
| 604 | |||
| 605 | return HAL_OK; |
||
| 606 | } |
||
| 607 | |||
| 608 | /** |
||
| 609 | * @brief Writes a half-word buffer to the FSMC NOR memory. This function |
||
| 610 | * must be used only with S29GL128P NOR memory. |
||
| 611 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
||
| 612 | * the configuration information for NOR module. |
||
| 613 | * @param uwAddress: NOR memory internal address from which the data |
||
| 614 | * @note Some NOR memory need Address aligned to xx bytes (can be aligned to |
||
| 615 | * 64 bytes boundary for example). |
||
| 616 | * @param pData: pointer to source data buffer. |
||
| 617 | * @param uwBufferSize: number of Half words to write. |
||
| 618 | * @note The maximum buffer size allowed is NOR memory dependent |
||
| 619 | * (can be 64 Bytes max for example). |
||
| 620 | * @retval HAL status |
||
| 621 | */ |
||
| 622 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) |
||
| 623 | { |
||
| 624 | uint16_t * p_currentaddress = (uint16_t *)NULL; |
||
| 625 | uint16_t * p_endaddress = (uint16_t *)NULL; |
||
| 626 | uint32_t lastloadedaddress = 0, deviceaddress = 0; |
||
| 627 | |||
| 628 | /* Process Locked */ |
||
| 629 | __HAL_LOCK(hnor); |
||
| 630 | |||
| 631 | /* Check the NOR controller state */ |
||
| 632 | if(hnor->State == HAL_NOR_STATE_BUSY) |
||
| 633 | { |
||
| 634 | return HAL_BUSY; |
||
| 635 | } |
||
| 636 | |||
| 637 | /* Select the NOR device address */ |
||
| 638 | if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) |
||
| 639 | { |
||
| 640 | deviceaddress = NOR_MEMORY_ADRESS1; |
||
| 641 | } |
||
| 642 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) |
||
| 643 | { |
||
| 644 | deviceaddress = NOR_MEMORY_ADRESS2; |
||
| 645 | } |
||
| 646 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) |
||
| 647 | { |
||
| 648 | deviceaddress = NOR_MEMORY_ADRESS3; |
||
| 649 | } |
||
| 650 | else /* FSMC_NORSRAM_BANK4 */ |
||
| 651 | { |
||
| 652 | deviceaddress = NOR_MEMORY_ADRESS4; |
||
| 653 | } |
||
| 654 | |||
| 655 | /* Update the NOR controller state */ |
||
| 656 | hnor->State = HAL_NOR_STATE_BUSY; |
||
| 657 | |||
| 658 | /* Initialize variables */ |
||
| 659 | p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); |
||
| 660 | p_endaddress = p_currentaddress + (uwBufferSize-1); |
||
| 661 | lastloadedaddress = (uint32_t)(uwAddress); |
||
| 662 | |||
| 663 | /* Issue unlock command sequence */ |
||
| 664 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
||
| 665 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
||
| 666 | |||
| 667 | /* Write Buffer Load Command */ |
||
| 668 | NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); |
||
| 669 | NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); |
||
| 670 | |||
| 671 | /* Load Data into NOR Buffer */ |
||
| 672 | while(p_currentaddress <= p_endaddress) |
||
| 673 | { |
||
| 674 | /* Store last loaded address & data value (for polling) */ |
||
| 675 | lastloadedaddress = (uint32_t)p_currentaddress; |
||
| 676 | |||
| 677 | NOR_WRITE(p_currentaddress, *pData++); |
||
| 678 | |||
| 679 | p_currentaddress++; |
||
| 680 | } |
||
| 681 | |||
| 682 | NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); |
||
| 683 | |||
| 684 | /* Check the NOR controller state */ |
||
| 685 | hnor->State = HAL_NOR_STATE_READY; |
||
| 686 | |||
| 687 | /* Process unlocked */ |
||
| 688 | __HAL_UNLOCK(hnor); |
||
| 689 | |||
| 690 | return HAL_OK; |
||
| 691 | |||
| 692 | } |
||
| 693 | |||
| 694 | /** |
||
| 695 | * @brief Erase the specified block of the NOR memory |
||
| 696 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
||
| 697 | * the configuration information for NOR module. |
||
| 698 | * @param BlockAddress : Block to erase address |
||
| 699 | * @param Address: Device address |
||
| 700 | * @retval HAL status |
||
| 701 | */ |
||
| 702 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) |
||
| 703 | { |
||
| 704 | uint32_t deviceaddress = 0; |
||
| 705 | |||
| 706 | /* Process Locked */ |
||
| 707 | __HAL_LOCK(hnor); |
||
| 708 | |||
| 709 | /* Check the NOR controller state */ |
||
| 710 | if(hnor->State == HAL_NOR_STATE_BUSY) |
||
| 711 | { |
||
| 712 | return HAL_BUSY; |
||
| 713 | } |
||
| 714 | |||
| 715 | /* Select the NOR device address */ |
||
| 716 | if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) |
||
| 717 | { |
||
| 718 | deviceaddress = NOR_MEMORY_ADRESS1; |
||
| 719 | } |
||
| 720 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) |
||
| 721 | { |
||
| 722 | deviceaddress = NOR_MEMORY_ADRESS2; |
||
| 723 | } |
||
| 724 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) |
||
| 725 | { |
||
| 726 | deviceaddress = NOR_MEMORY_ADRESS3; |
||
| 727 | } |
||
| 728 | else /* FSMC_NORSRAM_BANK4 */ |
||
| 729 | { |
||
| 730 | deviceaddress = NOR_MEMORY_ADRESS4; |
||
| 731 | } |
||
| 732 | |||
| 733 | /* Update the NOR controller state */ |
||
| 734 | hnor->State = HAL_NOR_STATE_BUSY; |
||
| 735 | |||
| 736 | /* Send block erase command sequence */ |
||
| 737 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
||
| 738 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
||
| 739 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); |
||
| 740 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); |
||
| 741 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); |
||
| 742 | NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); |
||
| 743 | |||
| 744 | /* Check the NOR memory status and update the controller state */ |
||
| 745 | hnor->State = HAL_NOR_STATE_READY; |
||
| 746 | |||
| 747 | /* Process unlocked */ |
||
| 748 | __HAL_UNLOCK(hnor); |
||
| 749 | |||
| 750 | return HAL_OK; |
||
| 751 | |||
| 752 | } |
||
| 753 | |||
| 754 | /** |
||
| 755 | * @brief Erase the entire NOR chip. |
||
| 756 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
||
| 757 | * the configuration information for NOR module. |
||
| 758 | * @param Address : Device address |
||
| 759 | * @retval HAL status |
||
| 760 | */ |
||
| 761 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) |
||
| 762 | { |
||
| 763 | uint32_t deviceaddress = 0; |
||
| 764 | |||
| 765 | /* Process Locked */ |
||
| 766 | __HAL_LOCK(hnor); |
||
| 767 | |||
| 768 | /* Check the NOR controller state */ |
||
| 769 | if(hnor->State == HAL_NOR_STATE_BUSY) |
||
| 770 | { |
||
| 771 | return HAL_BUSY; |
||
| 772 | } |
||
| 773 | |||
| 774 | /* Select the NOR device address */ |
||
| 775 | if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) |
||
| 776 | { |
||
| 777 | deviceaddress = NOR_MEMORY_ADRESS1; |
||
| 778 | } |
||
| 779 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) |
||
| 780 | { |
||
| 781 | deviceaddress = NOR_MEMORY_ADRESS2; |
||
| 782 | } |
||
| 783 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) |
||
| 784 | { |
||
| 785 | deviceaddress = NOR_MEMORY_ADRESS3; |
||
| 786 | } |
||
| 787 | else /* FSMC_NORSRAM_BANK4 */ |
||
| 788 | { |
||
| 789 | deviceaddress = NOR_MEMORY_ADRESS4; |
||
| 790 | } |
||
| 791 | |||
| 792 | /* Update the NOR controller state */ |
||
| 793 | hnor->State = HAL_NOR_STATE_BUSY; |
||
| 794 | |||
| 795 | /* Send NOR chip erase command sequence */ |
||
| 796 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
||
| 797 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
||
| 798 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); |
||
| 799 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); |
||
| 800 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); |
||
| 801 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); |
||
| 802 | |||
| 803 | /* Check the NOR memory status and update the controller state */ |
||
| 804 | hnor->State = HAL_NOR_STATE_READY; |
||
| 805 | |||
| 806 | /* Process unlocked */ |
||
| 807 | __HAL_UNLOCK(hnor); |
||
| 808 | |||
| 809 | return HAL_OK; |
||
| 810 | } |
||
| 811 | |||
| 812 | /** |
||
| 813 | * @brief Read NOR flash CFI IDs |
||
| 814 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
||
| 815 | * the configuration information for NOR module. |
||
| 816 | * @param pNOR_CFI : pointer to NOR CFI IDs structure |
||
| 817 | * @retval HAL status |
||
| 818 | */ |
||
| 819 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) |
||
| 820 | { |
||
| 821 | uint32_t deviceaddress = 0; |
||
| 822 | |||
| 823 | /* Process Locked */ |
||
| 824 | __HAL_LOCK(hnor); |
||
| 825 | |||
| 826 | /* Check the NOR controller state */ |
||
| 827 | if(hnor->State == HAL_NOR_STATE_BUSY) |
||
| 828 | { |
||
| 829 | return HAL_BUSY; |
||
| 830 | } |
||
| 831 | |||
| 832 | /* Select the NOR device address */ |
||
| 833 | if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) |
||
| 834 | { |
||
| 835 | deviceaddress = NOR_MEMORY_ADRESS1; |
||
| 836 | } |
||
| 837 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) |
||
| 838 | { |
||
| 839 | deviceaddress = NOR_MEMORY_ADRESS2; |
||
| 840 | } |
||
| 841 | else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) |
||
| 842 | { |
||
| 843 | deviceaddress = NOR_MEMORY_ADRESS3; |
||
| 844 | } |
||
| 845 | else /* FSMC_NORSRAM_BANK4 */ |
||
| 846 | { |
||
| 847 | deviceaddress = NOR_MEMORY_ADRESS4; |
||
| 848 | } |
||
| 849 | |||
| 850 | /* Update the NOR controller state */ |
||
| 851 | hnor->State = HAL_NOR_STATE_BUSY; |
||
| 852 | |||
| 853 | /* Send read CFI query command */ |
||
| 854 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); |
||
| 855 | |||
| 856 | /* read the NOR CFI information */ |
||
| 857 | pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); |
||
| 858 | pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); |
||
| 859 | pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); |
||
| 860 | pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); |
||
| 861 | |||
| 862 | /* Check the NOR controller state */ |
||
| 863 | hnor->State = HAL_NOR_STATE_READY; |
||
| 864 | |||
| 865 | /* Process unlocked */ |
||
| 866 | __HAL_UNLOCK(hnor); |
||
| 867 | |||
| 868 | return HAL_OK; |
||
| 869 | } |
||
| 870 | |||
| 871 | /** |
||
| 872 | * @} |
||
| 873 | */ |
||
| 874 | |||
| 875 | /** @defgroup NOR_Exported_Functions_Group3 Control functions |
||
| 876 | * @brief management functions |
||
| 877 | * |
||
| 878 | @verbatim |
||
| 879 | ============================================================================== |
||
| 880 | ##### NOR Control functions ##### |
||
| 881 | ============================================================================== |
||
| 882 | [..] |
||
| 883 | This subsection provides a set of functions allowing to control dynamically |
||
| 884 | the NOR interface. |
||
| 885 | |||
| 886 | @endverbatim |
||
| 887 | * @{ |
||
| 888 | */ |
||
| 889 | |||
| 890 | /** |
||
| 891 | * @brief Enables dynamically NOR write operation. |
||
| 892 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
||
| 893 | * the configuration information for NOR module. |
||
| 894 | * @retval HAL status |
||
| 895 | */ |
||
| 896 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) |
||
| 897 | { |
||
| 898 | /* Process Locked */ |
||
| 899 | __HAL_LOCK(hnor); |
||
| 900 | |||
| 901 | /* Enable write operation */ |
||
| 902 | FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); |
||
| 903 | |||
| 904 | /* Update the NOR controller state */ |
||
| 905 | hnor->State = HAL_NOR_STATE_READY; |
||
| 906 | |||
| 907 | /* Process unlocked */ |
||
| 908 | __HAL_UNLOCK(hnor); |
||
| 909 | |||
| 910 | return HAL_OK; |
||
| 911 | } |
||
| 912 | |||
| 913 | /** |
||
| 914 | * @brief Disables dynamically NOR write operation. |
||
| 915 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
||
| 916 | * the configuration information for NOR module. |
||
| 917 | * @retval HAL status |
||
| 918 | */ |
||
| 919 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) |
||
| 920 | { |
||
| 921 | /* Process Locked */ |
||
| 922 | __HAL_LOCK(hnor); |
||
| 923 | |||
| 924 | /* Update the SRAM controller state */ |
||
| 925 | hnor->State = HAL_NOR_STATE_BUSY; |
||
| 926 | |||
| 927 | /* Disable write operation */ |
||
| 928 | FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); |
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| 929 | |||
| 930 | /* Update the NOR controller state */ |
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| 931 | hnor->State = HAL_NOR_STATE_PROTECTED; |
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| 932 | |||
| 933 | /* Process unlocked */ |
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| 934 | __HAL_UNLOCK(hnor); |
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| 935 | |||
| 936 | return HAL_OK; |
||
| 937 | } |
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| 938 | |||
| 939 | /** |
||
| 940 | * @} |
||
| 941 | */ |
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| 942 | |||
| 943 | /** @defgroup NOR_Exported_Functions_Group4 State functions |
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| 944 | * @brief Peripheral State functions |
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| 945 | * |
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| 946 | @verbatim |
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| 947 | ============================================================================== |
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| 948 | ##### NOR State functions ##### |
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| 949 | ============================================================================== |
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| 950 | [..] |
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| 951 | This subsection permits to get in run-time the status of the NOR controller |
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| 952 | and the data flow. |
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| 953 | |||
| 954 | @endverbatim |
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| 955 | * @{ |
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| 956 | */ |
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| 957 | |||
| 958 | /** |
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| 959 | * @brief return the NOR controller state |
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| 960 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 961 | * the configuration information for NOR module. |
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| 962 | * @retval NOR controller state |
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| 963 | */ |
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| 964 | HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) |
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| 965 | { |
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| 966 | return hnor->State; |
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| 967 | } |
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| 968 | |||
| 969 | /** |
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| 970 | * @brief Returns the NOR operation status. |
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| 971 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
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| 972 | * the configuration information for NOR module. |
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| 973 | * @param Address: Device address |
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| 974 | * @param Timeout: NOR progamming Timeout |
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| 975 | * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR |
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| 976 | * or HAL_NOR_STATUS_TIMEOUT |
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| 977 | */ |
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| 978 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) |
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| 979 | { |
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| 980 | HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; |
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| 981 | uint16_t tmp_sr1 = 0, tmp_sr2 = 0; |
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| 982 | uint32_t tickstart = 0; |
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| 983 | |||
| 984 | /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ |
||
| 985 | HAL_NOR_MspWait(hnor, Timeout); |
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| 986 | |||
| 987 | /* Get tick */ |
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| 988 | tickstart = HAL_GetTick(); |
||
| 989 | while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) |
||
| 990 | { |
||
| 991 | /* Check for the Timeout */ |
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| 992 | if(Timeout != HAL_MAX_DELAY) |
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| 993 | { |
||
| 994 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
||
| 995 | { |
||
| 996 | status = HAL_NOR_STATUS_TIMEOUT; |
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| 997 | } |
||
| 998 | } |
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| 999 | |||
| 1000 | /* Read NOR status register (DQ6 and DQ5) */ |
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| 1001 | tmp_sr1 = *(__IO uint16_t *)Address; |
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| 1002 | tmp_sr2 = *(__IO uint16_t *)Address; |
||
| 1003 | |||
| 1004 | /* If DQ6 did not toggle between the two reads then return NOR_Success */ |
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| 1005 | if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) |
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| 1006 | { |
||
| 1007 | return HAL_NOR_STATUS_SUCCESS; |
||
| 1008 | } |
||
| 1009 | |||
| 1010 | if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5) |
||
| 1011 | { |
||
| 1012 | status = HAL_NOR_STATUS_ONGOING; |
||
| 1013 | } |
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| 1014 | |||
| 1015 | tmp_sr1 = *(__IO uint16_t *)Address; |
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| 1016 | tmp_sr2 = *(__IO uint16_t *)Address; |
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| 1017 | |||
| 1018 | /* If DQ6 did not toggle between the two reads then return NOR_Success */ |
||
| 1019 | if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) |
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| 1020 | { |
||
| 1021 | return HAL_NOR_STATUS_SUCCESS; |
||
| 1022 | } |
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| 1023 | else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) |
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| 1024 | { |
||
| 1025 | return HAL_NOR_STATUS_ERROR; |
||
| 1026 | } |
||
| 1027 | } |
||
| 1028 | |||
| 1029 | /* Return the operation status */ |
||
| 1030 | return status; |
||
| 1031 | } |
||
| 1032 | |||
| 1033 | /** |
||
| 1034 | * @} |
||
| 1035 | */ |
||
| 1036 | |||
| 1037 | /** |
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| 1038 | * @} |
||
| 1039 | */ |
||
| 1040 | /** |
||
| 1041 | * @} |
||
| 1042 | */ |
||
| 1043 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ |
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| 1044 | #endif /* HAL_NOR_MODULE_ENABLED */ |
||
| 1045 | |||
| 1046 | /** |
||
| 1047 | * @} |
||
| 1048 | */ |
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| 1049 | |||
| 1050 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |