WebSVN – AFRtranscoder – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_nor.c
		4	* @author MCD Application Team
		5	* @brief NOR HAL module driver.
		6	* This file provides a generic firmware to drive NOR memories mounted
		7	* as external device.
		8	*
		9	******************************************************************************
		10	* @attention
		11	*
		12	* Copyright (c) 2016 STMicroelectronics.
		13	* All rights reserved.
		14	*
		15	* This software is licensed under terms that can be found in the LICENSE file
		16	* in the root directory of this software component.
		17	* If no LICENSE file comes with this software, it is provided AS-IS.
		18	*
		19	******************************************************************************
		20	@verbatim
		21	==============================================================================
		22	##### How to use this driver #####
		23	==============================================================================
		24	[..]
		25	This driver is a generic layered driver which contains a set of APIs used to
		26	control NOR flash memories. It uses the FSMC layer functions to interface
		27	with NOR devices. This driver is used as follows:
		28
		29	(+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
		30	with control and timing parameters for both normal and extended mode.
		31
		32	(+) Read NOR flash memory manufacturer code and device IDs using the function
		33	HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
		34	structure declared by the function caller.
		35
		36	(+) Access NOR flash memory by read/write data unit operations using the functions
		37	HAL_NOR_Read(), HAL_NOR_Program().
		38
		39	(+) Perform NOR flash erase block/chip operations using the functions
		40	HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
		41
		42	(+) Read the NOR flash CFI (common flash interface) IDs using the function
		43	HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
		44	structure declared by the function caller.
		45
		46	(+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
		47	HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
		48
		49	(+) You can monitor the NOR device HAL state by calling the function
		50	HAL_NOR_GetState()
		51	[..]
		52	(@) This driver is a set of generic APIs which handle standard NOR flash operations.
		53	If a NOR flash device contains different operations and/or implementations,
		54	it should be implemented separately.
		55
		56	* NOR HAL driver macros list *
		57	=============================================
		58	[..]
		59	Below the list of most used macros in NOR HAL driver.
		60
		61	(+) NOR_WRITE : NOR memory write data to specified address
		62
		63	* Callback registration *
		64	=============================================
		65	[..]
		66	The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
		67	allows the user to configure dynamically the driver callbacks.
		68
		69	Use Functions HAL_NOR_RegisterCallback() to register a user callback,
		70	it allows to register following callbacks:
		71	(+) MspInitCallback : NOR MspInit.
		72	(+) MspDeInitCallback : NOR MspDeInit.
		73	This function takes as parameters the HAL peripheral handle, the Callback ID
		74	and a pointer to the user callback function.
		75
		76	Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
		77	weak (overridden) function. It allows to reset following callbacks:
		78	(+) MspInitCallback : NOR MspInit.
		79	(+) MspDeInitCallback : NOR MspDeInit.
		80	This function) takes as parameters the HAL peripheral handle and the Callback ID.
		81
		82	By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
		83	all callbacks are reset to the corresponding legacy weak (overridden) functions.
		84	Exception done for MspInit and MspDeInit callbacks that are respectively
		85	reset to the legacy weak (overridden) functions in the HAL_NOR_Init
		86	and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
		87	If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
		88	keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
		89
		90	Callbacks can be registered/unregistered in READY state only.
		91	Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
		92	in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
		93	during the Init/DeInit.
		94	In that case first register the MspInit/MspDeInit user callbacks
		95	using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
		96	or HAL_NOR_Init function.
		97
		98	When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
		99	not defined, the callback registering feature is not available
		100	and weak (overridden) callbacks are used.
		101
		102	@endverbatim
		103	******************************************************************************
		104	*/
		105
		106	/* Includes ------------------------------------------------------------------*/
		107	#include "stm32f1xx_hal.h"
		108
		109	#if defined(FSMC_BANK1)
		110
		111	/** @addtogroup STM32F1xx_HAL_Driver
		112	* @{
		113	*/
		114
		115	#ifdef HAL_NOR_MODULE_ENABLED
		116
		117	/** @defgroup NOR NOR
		118	* @brief NOR driver modules
		119	* @{
		120	*/
		121
		122	/* Private typedef -----------------------------------------------------------*/
		123	/* Private define ------------------------------------------------------------*/
		124
		125	/** @defgroup NOR_Private_Defines NOR Private Defines
		126	* @{
		127	*/
		128
		129	/* Constants to define address to set to write a command */
		130	#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA
		131	#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA
		132	#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555
		133	#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA
		134
		135	#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
		136	#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
		137	#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
		138	#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
		139	#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
		140	#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
		141	#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
		142
		143	/* Constants to define data to program a command */
		144	#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
		145	#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
		146	#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
		147	#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
		148	#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
		149	#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
		150	#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
		151	#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
		152	#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
		153	#define NOR_CMD_DATA_CFI (uint16_t)0x0098
		154
		155	#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
		156	#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
		157	#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
		158
		159	#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
		160	#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
		161	#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
		162	#define NOR_CMD_CONFIRM (uint16_t)0x00D0
		163	#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
		164	#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
		165	#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
		166	#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
		167
		168	/* Mask on NOR STATUS REGISTER */
		169	#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
		170	#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
		171	#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
		172	#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
		173
		174	/* Address of the primary command set */
		175	#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
		176
		177	/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
		178	#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
		179	#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
		180	#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
		181	#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
		182	#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
		183	#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
		184	#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
		185	#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
		186	#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
		187	#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
		188
		189	/**
		190	* @}
		191	*/
		192
		193	/* Private macro -------------------------------------------------------------*/
		194	/* Private variables ---------------------------------------------------------*/
		195	/** @defgroup NOR_Private_Variables NOR Private Variables
		196	* @{
		197	*/
		198
		199	static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
		200
		201	/**
		202	* @}
		203	*/
		204
		205	/* Private functions ---------------------------------------------------------*/
		206	/* Exported functions --------------------------------------------------------*/
		207	/** @defgroup NOR_Exported_Functions NOR Exported Functions
		208	* @{
		209	*/
		210
		211	/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
		212	* @brief Initialization and Configuration functions
		213	*
		214	@verbatim
		215	==============================================================================
		216	##### NOR Initialization and de_initialization functions #####
		217	==============================================================================
		218	[..]
		219	This section provides functions allowing to initialize/de-initialize
		220	the NOR memory
		221
		222	@endverbatim
		223	* @{
		224	*/
		225
		226	/**
		227	* @brief Perform the NOR memory Initialization sequence
		228	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		229	* the configuration information for NOR module.
		230	* @param Timing pointer to NOR control timing structure
		231	* @param ExtTiming pointer to NOR extended mode timing structure
		232	* @retval HAL status
		233	*/
		234	HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef hnor, FSMC_NORSRAM_TimingTypeDef Timing,
		235	FSMC_NORSRAM_TimingTypeDef *ExtTiming)
		236	{
		237	uint32_t deviceaddress;
		238	HAL_StatusTypeDef status = HAL_OK;
		239
		240	/* Check the NOR handle parameter */
		241	if (hnor == NULL)
		242	{
		243	return HAL_ERROR;
		244	}
		245
		246	if (hnor->State == HAL_NOR_STATE_RESET)
		247	{
		248	/* Allocate lock resource and initialize it */
		249	hnor->Lock = HAL_UNLOCKED;
		250
		251	#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
		252	if (hnor->MspInitCallback == NULL)
		253	{
		254	hnor->MspInitCallback = HAL_NOR_MspInit;
		255	}
		256
		257	/* Init the low level hardware */
		258	hnor->MspInitCallback(hnor);
		259	#else
		260	/* Initialize the low level hardware (MSP) */
		261	HAL_NOR_MspInit(hnor);
		262	#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
		263	}
		264
		265	/* Initialize NOR control Interface */
		266	(void)FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
		267
		268	/* Initialize NOR timing Interface */
		269	(void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
		270
		271	/* Initialize NOR extended mode timing Interface */
		272	(void)FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming,
		273	hnor->Init.NSBank, hnor->Init.ExtendedMode);
		274
		275	/* Enable the NORSRAM device */
		276	__FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
		277
		278	/* Initialize NOR Memory Data Width*/
		279	if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
		280	{
		281	uwNORMemoryDataWidth = NOR_MEMORY_8B;
		282	}
		283	else
		284	{
		285	uwNORMemoryDataWidth = NOR_MEMORY_16B;
		286	}
		287
		288	/* Initialize the NOR controller state */
		289	hnor->State = HAL_NOR_STATE_READY;
		290
		291	/* Select the NOR device address */
		292	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		293	{
		294	deviceaddress = NOR_MEMORY_ADRESS1;
		295	}
		296	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		297	{
		298	deviceaddress = NOR_MEMORY_ADRESS2;
		299	}
		300	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		301	{
		302	deviceaddress = NOR_MEMORY_ADRESS3;
		303	}
		304	else /* FSMC_NORSRAM_BANK4 */
		305	{
		306	deviceaddress = NOR_MEMORY_ADRESS4;
		307	}
		308
		309	if (hnor->Init.WriteOperation == FSMC_WRITE_OPERATION_DISABLE)
		310	{
		311	(void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
		312
		313	/* Update the NOR controller state */
		314	hnor->State = HAL_NOR_STATE_PROTECTED;
		315	}
		316	else
		317	{
		318	/* Get the value of the command set */
		319	if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
		320	{
		321	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
		322	NOR_CMD_DATA_CFI);
		323	}
		324	else
		325	{
		326	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
		327	}
		328
		329	hnor->CommandSet = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
		330
		331	status = HAL_NOR_ReturnToReadMode(hnor);
		332	}
		333
		334	return status;
		335	}
		336
		337	/**
		338	* @brief Perform NOR memory De-Initialization sequence
		339	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		340	* the configuration information for NOR module.
		341	* @retval HAL status
		342	*/
		343	HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
		344	{
		345	#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
		346	if (hnor->MspDeInitCallback == NULL)
		347	{
		348	hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
		349	}
		350
		351	/* DeInit the low level hardware */
		352	hnor->MspDeInitCallback(hnor);
		353	#else
		354	/* De-Initialize the low level hardware (MSP) */
		355	HAL_NOR_MspDeInit(hnor);
		356	#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
		357
		358	/* Configure the NOR registers with their reset values */
		359	(void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
		360
		361	/* Reset the NOR controller state */
		362	hnor->State = HAL_NOR_STATE_RESET;
		363
		364	/* Release Lock */
		365	__HAL_UNLOCK(hnor);
		366
		367	return HAL_OK;
		368	}
		369
		370	/**
		371	* @brief NOR MSP Init
		372	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		373	* the configuration information for NOR module.
		374	* @retval None
		375	*/
		376	__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
		377	{
		378	/* Prevent unused argument(s) compilation warning */
		379	UNUSED(hnor);
		380
		381	/* NOTE : This function Should not be modified, when the callback is needed,
		382	the HAL_NOR_MspInit could be implemented in the user file
		383	*/
		384	}
		385
		386	/**
		387	* @brief NOR MSP DeInit
		388	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		389	* the configuration information for NOR module.
		390	* @retval None
		391	*/
		392	__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
		393	{
		394	/* Prevent unused argument(s) compilation warning */
		395	UNUSED(hnor);
		396
		397	/* NOTE : This function Should not be modified, when the callback is needed,
		398	the HAL_NOR_MspDeInit could be implemented in the user file
		399	*/
		400	}
		401
		402	/**
		403	* @brief NOR MSP Wait for Ready/Busy signal
		404	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		405	* the configuration information for NOR module.
		406	* @param Timeout Maximum timeout value
		407	* @retval None
		408	*/
		409	__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
		410	{
		411	/* Prevent unused argument(s) compilation warning */
		412	UNUSED(hnor);
		413	UNUSED(Timeout);
		414
		415	/* NOTE : This function Should not be modified, when the callback is needed,
		416	the HAL_NOR_MspWait could be implemented in the user file
		417	*/
		418	}
		419
		420	/**
		421	* @}
		422	*/
		423
		424	/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
		425	* @brief Input Output and memory control functions
		426	*
		427	@verbatim
		428	==============================================================================
		429	##### NOR Input and Output functions #####
		430	==============================================================================
		431	[..]
		432	This section provides functions allowing to use and control the NOR memory
		433
		434	@endverbatim
		435	* @{
		436	*/
		437
		438	/**
		439	* @brief Read NOR flash IDs
		440	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		441	* the configuration information for NOR module.
		442	* @param pNOR_ID pointer to NOR ID structure
		443	* @retval HAL status
		444	*/
		445	HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef hnor, NOR_IDTypeDef pNOR_ID)
		446	{
		447	uint32_t deviceaddress;
		448	HAL_NOR_StateTypeDef state;
		449	HAL_StatusTypeDef status = HAL_OK;
		450
		451	/* Check the NOR controller state */
		452	state = hnor->State;
		453	if (state == HAL_NOR_STATE_BUSY)
		454	{
		455	return HAL_BUSY;
		456	}
		457	else if (state == HAL_NOR_STATE_PROTECTED)
		458	{
		459	return HAL_ERROR;
		460	}
		461	else if (state == HAL_NOR_STATE_READY)
		462	{
		463	/* Process Locked */
		464	__HAL_LOCK(hnor);
		465
		466	/* Update the NOR controller state */
		467	hnor->State = HAL_NOR_STATE_BUSY;
		468
		469	/* Select the NOR device address */
		470	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		471	{
		472	deviceaddress = NOR_MEMORY_ADRESS1;
		473	}
		474	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		475	{
		476	deviceaddress = NOR_MEMORY_ADRESS2;
		477	}
		478	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		479	{
		480	deviceaddress = NOR_MEMORY_ADRESS3;
		481	}
		482	else /* FSMC_NORSRAM_BANK4 */
		483	{
		484	deviceaddress = NOR_MEMORY_ADRESS4;
		485	}
		486
		487	/* Send read ID command */
		488	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		489	{
		490	if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
		491	{
		492	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
		493	NOR_CMD_DATA_FIRST);
		494	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
		495	NOR_CMD_DATA_SECOND);
		496	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
		497	NOR_CMD_DATA_AUTO_SELECT);
		498	}
		499	else
		500	{
		501	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		502	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		503	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
		504	NOR_CMD_DATA_AUTO_SELECT);
		505	}
		506	}
		507	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		508	{
		509	NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
		510	}
		511	else
		512	{
		513	/* Primary command set not supported by the driver */
		514	status = HAL_ERROR;
		515	}
		516
		517	if (status != HAL_ERROR)
		518	{
		519	/* Read the NOR IDs */
		520	pNOR_ID->Manufacturer_Code = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
		521	pNOR_ID->Device_Code1 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
		522	DEVICE_CODE1_ADDR);
		523	pNOR_ID->Device_Code2 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
		524	DEVICE_CODE2_ADDR);
		525	pNOR_ID->Device_Code3 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
		526	DEVICE_CODE3_ADDR);
		527	}
		528
		529	/* Check the NOR controller state */
		530	hnor->State = state;
		531
		532	/* Process unlocked */
		533	__HAL_UNLOCK(hnor);
		534	}
		535	else
		536	{
		537	return HAL_ERROR;
		538	}
		539
		540	return status;
		541	}
		542
		543	/**
		544	* @brief Returns the NOR memory to Read mode.
		545	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		546	* the configuration information for NOR module.
		547	* @retval HAL status
		548	*/
		549	HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
		550	{
		551	uint32_t deviceaddress;
		552	HAL_NOR_StateTypeDef state;
		553	HAL_StatusTypeDef status = HAL_OK;
		554
		555	/* Check the NOR controller state */
		556	state = hnor->State;
		557	if (state == HAL_NOR_STATE_BUSY)
		558	{
		559	return HAL_BUSY;
		560	}
		561	else if (state == HAL_NOR_STATE_PROTECTED)
		562	{
		563	return HAL_ERROR;
		564	}
		565	else if (state == HAL_NOR_STATE_READY)
		566	{
		567	/* Process Locked */
		568	__HAL_LOCK(hnor);
		569
		570	/* Update the NOR controller state */
		571	hnor->State = HAL_NOR_STATE_BUSY;
		572
		573	/* Select the NOR device address */
		574	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		575	{
		576	deviceaddress = NOR_MEMORY_ADRESS1;
		577	}
		578	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		579	{
		580	deviceaddress = NOR_MEMORY_ADRESS2;
		581	}
		582	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		583	{
		584	deviceaddress = NOR_MEMORY_ADRESS3;
		585	}
		586	else /* FSMC_NORSRAM_BANK4 */
		587	{
		588	deviceaddress = NOR_MEMORY_ADRESS4;
		589	}
		590
		591	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		592	{
		593	NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
		594	}
		595	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		596	{
		597	NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
		598	}
		599	else
		600	{
		601	/* Primary command set not supported by the driver */
		602	status = HAL_ERROR;
		603	}
		604
		605	/* Check the NOR controller state */
		606	hnor->State = state;
		607
		608	/* Process unlocked */
		609	__HAL_UNLOCK(hnor);
		610	}
		611	else
		612	{
		613	return HAL_ERROR;
		614	}
		615
		616	return status;
		617	}
		618
		619	/**
		620	* @brief Read data from NOR memory
		621	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		622	* the configuration information for NOR module.
		623	* @param pAddress pointer to Device address
		624	* @param pData pointer to read data
		625	* @retval HAL status
		626	*/
		627	HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef hnor, uint32_t pAddress, uint16_t *pData)
		628	{
		629	uint32_t deviceaddress;
		630	HAL_NOR_StateTypeDef state;
		631	HAL_StatusTypeDef status = HAL_OK;
		632
		633	/* Check the NOR controller state */
		634	state = hnor->State;
		635	if (state == HAL_NOR_STATE_BUSY)
		636	{
		637	return HAL_BUSY;
		638	}
		639	else if (state == HAL_NOR_STATE_PROTECTED)
		640	{
		641	return HAL_ERROR;
		642	}
		643	else if (state == HAL_NOR_STATE_READY)
		644	{
		645	/* Process Locked */
		646	__HAL_LOCK(hnor);
		647
		648	/* Update the NOR controller state */
		649	hnor->State = HAL_NOR_STATE_BUSY;
		650
		651	/* Select the NOR device address */
		652	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		653	{
		654	deviceaddress = NOR_MEMORY_ADRESS1;
		655	}
		656	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		657	{
		658	deviceaddress = NOR_MEMORY_ADRESS2;
		659	}
		660	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		661	{
		662	deviceaddress = NOR_MEMORY_ADRESS3;
		663	}
		664	else /* FSMC_NORSRAM_BANK4 */
		665	{
		666	deviceaddress = NOR_MEMORY_ADRESS4;
		667	}
		668
		669	/* Send read data command */
		670	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		671	{
		672	if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
		673	{
		674	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
		675	NOR_CMD_DATA_FIRST);
		676	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
		677	NOR_CMD_DATA_SECOND);
		678	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
		679	NOR_CMD_DATA_READ_RESET);
		680	}
		681	else
		682	{
		683	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		684	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		685	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
		686	NOR_CMD_DATA_READ_RESET);
		687	}
		688	}
		689	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		690	{
		691	NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
		692	}
		693	else
		694	{
		695	/* Primary command set not supported by the driver */
		696	status = HAL_ERROR;
		697	}
		698
		699	if (status != HAL_ERROR)
		700	{
		701	/* Read the data */
		702	pData = (uint16_t)((__IO uint32_t *)pAddress);
		703	}
		704
		705	/* Check the NOR controller state */
		706	hnor->State = state;
		707
		708	/* Process unlocked */
		709	__HAL_UNLOCK(hnor);
		710	}
		711	else
		712	{
		713	return HAL_ERROR;
		714	}
		715
		716	return status;
		717	}
		718
		719	/**
		720	* @brief Program data to NOR memory
		721	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		722	* the configuration information for NOR module.
		723	* @param pAddress Device address
		724	* @param pData pointer to the data to write
		725	* @retval HAL status
		726	*/
		727	HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef hnor, uint32_t pAddress, uint16_t *pData)
		728	{
		729	uint32_t deviceaddress;
		730	HAL_StatusTypeDef status = HAL_OK;
		731
		732	/* Check the NOR controller state */
		733	if (hnor->State == HAL_NOR_STATE_BUSY)
		734	{
		735	return HAL_BUSY;
		736	}
		737	else if (hnor->State == HAL_NOR_STATE_READY)
		738	{
		739	/* Process Locked */
		740	__HAL_LOCK(hnor);
		741
		742	/* Update the NOR controller state */
		743	hnor->State = HAL_NOR_STATE_BUSY;
		744
		745	/* Select the NOR device address */
		746	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		747	{
		748	deviceaddress = NOR_MEMORY_ADRESS1;
		749	}
		750	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		751	{
		752	deviceaddress = NOR_MEMORY_ADRESS2;
		753	}
		754	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		755	{
		756	deviceaddress = NOR_MEMORY_ADRESS3;
		757	}
		758	else /* FSMC_NORSRAM_BANK4 */
		759	{
		760	deviceaddress = NOR_MEMORY_ADRESS4;
		761	}
		762
		763	/* Send program data command */
		764	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		765	{
		766	if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
		767	{
		768	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
		769	NOR_CMD_DATA_FIRST);
		770	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
		771	NOR_CMD_DATA_SECOND);
		772	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
		773	NOR_CMD_DATA_PROGRAM);
		774	}
		775	else
		776	{
		777	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		778	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		779	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
		780	}
		781	}
		782	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		783	{
		784	NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
		785	}
		786	else
		787	{
		788	/* Primary command set not supported by the driver */
		789	status = HAL_ERROR;
		790	}
		791
		792	if (status != HAL_ERROR)
		793	{
		794	/* Write the data */
		795	NOR_WRITE(pAddress, *pData);
		796	}
		797
		798	/* Check the NOR controller state */
		799	hnor->State = HAL_NOR_STATE_READY;
		800
		801	/* Process unlocked */
		802	__HAL_UNLOCK(hnor);
		803	}
		804	else
		805	{
		806	return HAL_ERROR;
		807	}
		808
		809	return status;
		810	}
		811
		812	/**
		813	* @brief Reads a half-word buffer from the NOR memory.
		814	* @param hnor pointer to the NOR handle
		815	* @param uwAddress NOR memory internal address to read from.
		816	* @param pData pointer to the buffer that receives the data read from the
		817	* NOR memory.
		818	* @param uwBufferSize number of Half word to read.
		819	* @retval HAL status
		820	*/
		821	HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef hnor, uint32_t uwAddress, uint16_t pData,
		822	uint32_t uwBufferSize)
		823	{
		824	uint32_t deviceaddress;
		825	uint32_t size = uwBufferSize;
		826	uint32_t address = uwAddress;
		827	uint16_t *data = pData;
		828	HAL_NOR_StateTypeDef state;
		829	HAL_StatusTypeDef status = HAL_OK;
		830
		831	/* Check the NOR controller state */
		832	state = hnor->State;
		833	if (state == HAL_NOR_STATE_BUSY)
		834	{
		835	return HAL_BUSY;
		836	}
		837	else if (state == HAL_NOR_STATE_PROTECTED)
		838	{
		839	return HAL_ERROR;
		840	}
		841	else if (state == HAL_NOR_STATE_READY)
		842	{
		843	/* Process Locked */
		844	__HAL_LOCK(hnor);
		845
		846	/* Update the NOR controller state */
		847	hnor->State = HAL_NOR_STATE_BUSY;
		848
		849	/* Select the NOR device address */
		850	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		851	{
		852	deviceaddress = NOR_MEMORY_ADRESS1;
		853	}
		854	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		855	{
		856	deviceaddress = NOR_MEMORY_ADRESS2;
		857	}
		858	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		859	{
		860	deviceaddress = NOR_MEMORY_ADRESS3;
		861	}
		862	else /* FSMC_NORSRAM_BANK4 */
		863	{
		864	deviceaddress = NOR_MEMORY_ADRESS4;
		865	}
		866
		867	/* Send read data command */
		868	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		869	{
		870	if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
		871	{
		872	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
		873	NOR_CMD_DATA_FIRST);
		874	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
		875	NOR_CMD_DATA_SECOND);
		876	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
		877	NOR_CMD_DATA_READ_RESET);
		878	}
		879	else
		880	{
		881	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		882	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		883	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
		884	NOR_CMD_DATA_READ_RESET);
		885	}
		886	}
		887	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		888	{
		889	NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
		890	}
		891	else
		892	{
		893	/* Primary command set not supported by the driver */
		894	status = HAL_ERROR;
		895	}
		896
		897	if (status != HAL_ERROR)
		898	{
		899	/* Read buffer */
		900	while (size > 0U)
		901	{
		902	data = (__IO uint16_t *)address;
		903	data++;
		904	address += 2U;
		905	size--;
		906	}
		907	}
		908
		909	/* Check the NOR controller state */
		910	hnor->State = state;
		911
		912	/* Process unlocked */
		913	__HAL_UNLOCK(hnor);
		914	}
		915	else
		916	{
		917	return HAL_ERROR;
		918	}
		919
		920	return status;
		921	}
		922
		923	/**
		924	* @brief Writes a half-word buffer to the NOR memory. This function must be used
		925	only with S29GL128P NOR memory.
		926	* @param hnor pointer to the NOR handle
		927	* @param uwAddress NOR memory internal start write address
		928	* @param pData pointer to source data buffer.
		929	* @param uwBufferSize Size of the buffer to write
		930	* @retval HAL status
		931	*/
		932	HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef hnor, uint32_t uwAddress, uint16_t pData,
		933	uint32_t uwBufferSize)
		934	{
		935	uint16_t *p_currentaddress;
		936	const uint16_t *p_endaddress;
		937	uint16_t *data = pData;
		938	uint32_t deviceaddress;
		939	HAL_StatusTypeDef status = HAL_OK;
		940
		941	/* Check the NOR controller state */
		942	if (hnor->State == HAL_NOR_STATE_BUSY)
		943	{
		944	return HAL_BUSY;
		945	}
		946	else if (hnor->State == HAL_NOR_STATE_READY)
		947	{
		948	/* Process Locked */
		949	__HAL_LOCK(hnor);
		950
		951	/* Update the NOR controller state */
		952	hnor->State = HAL_NOR_STATE_BUSY;
		953
		954	/* Select the NOR device address */
		955	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		956	{
		957	deviceaddress = NOR_MEMORY_ADRESS1;
		958	}
		959	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		960	{
		961	deviceaddress = NOR_MEMORY_ADRESS2;
		962	}
		963	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		964	{
		965	deviceaddress = NOR_MEMORY_ADRESS3;
		966	}
		967	else /* FSMC_NORSRAM_BANK4 */
		968	{
		969	deviceaddress = NOR_MEMORY_ADRESS4;
		970	}
		971
		972	/* Initialize variables */
		973	p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
		974	p_endaddress = (uint16_t )(deviceaddress + uwAddress + (2U (uwBufferSize - 1U)));
		975
		976	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		977	{
		978	if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
		979	{
		980	/* Issue unlock command sequence */
		981	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
		982	NOR_CMD_DATA_FIRST);
		983	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
		984	NOR_CMD_DATA_SECOND);
		985	}
		986	else
		987	{
		988	/* Issue unlock command sequence */
		989	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		990	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		991	}
		992	/* Write Buffer Load Command */
		993	NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
		994	NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
		995	}
		996	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		997	{
		998	/* Write Buffer Load Command */
		999	NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
		1000	NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
		1001	}
		1002	else
		1003	{
		1004	/* Primary command set not supported by the driver */
		1005	status = HAL_ERROR;
		1006	}
		1007
		1008	if (status != HAL_ERROR)
		1009	{
		1010	/* Load Data into NOR Buffer */
		1011	while (p_currentaddress <= p_endaddress)
		1012	{
		1013	NOR_WRITE(p_currentaddress, *data);
		1014
		1015	data++;
		1016	p_currentaddress ++;
		1017	}
		1018
		1019	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		1020	{
		1021	NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
		1022	}
		1023	else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
		1024	{
		1025	NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
		1026	}
		1027	}
		1028
		1029	/* Check the NOR controller state */
		1030	hnor->State = HAL_NOR_STATE_READY;
		1031
		1032	/* Process unlocked */
		1033	__HAL_UNLOCK(hnor);
		1034	}
		1035	else
		1036	{
		1037	return HAL_ERROR;
		1038	}
		1039
		1040	return status;
		1041
		1042	}
		1043
		1044	/**
		1045	* @brief Erase the specified block of the NOR memory
		1046	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1047	* the configuration information for NOR module.
		1048	* @param BlockAddress Block to erase address
		1049	* @param Address Device address
		1050	* @retval HAL status
		1051	*/
		1052	HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
		1053	{
		1054	uint32_t deviceaddress;
		1055	HAL_StatusTypeDef status = HAL_OK;
		1056
		1057	/* Check the NOR controller state */
		1058	if (hnor->State == HAL_NOR_STATE_BUSY)
		1059	{
		1060	return HAL_BUSY;
		1061	}
		1062	else if (hnor->State == HAL_NOR_STATE_READY)
		1063	{
		1064	/* Process Locked */
		1065	__HAL_LOCK(hnor);
		1066
		1067	/* Update the NOR controller state */
		1068	hnor->State = HAL_NOR_STATE_BUSY;
		1069
		1070	/* Select the NOR device address */
		1071	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		1072	{
		1073	deviceaddress = NOR_MEMORY_ADRESS1;
		1074	}
		1075	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		1076	{
		1077	deviceaddress = NOR_MEMORY_ADRESS2;
		1078	}
		1079	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		1080	{
		1081	deviceaddress = NOR_MEMORY_ADRESS3;
		1082	}
		1083	else /* FSMC_NORSRAM_BANK4 */
		1084	{
		1085	deviceaddress = NOR_MEMORY_ADRESS4;
		1086	}
		1087
		1088	/* Send block erase command sequence */
		1089	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		1090	{
		1091	if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
		1092	{
		1093	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
		1094	NOR_CMD_DATA_FIRST);
		1095	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
		1096	NOR_CMD_DATA_SECOND);
		1097	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
		1098	NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
		1099	}
		1100	else
		1101	{
		1102	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		1103	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		1104	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
		1105	NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
		1106	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
		1107	NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
		1108	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
		1109	NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
		1110	}
		1111	NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
		1112	}
		1113	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		1114	{
		1115	NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
		1116	NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
		1117	NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
		1118	NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
		1119	}
		1120	else
		1121	{
		1122	/* Primary command set not supported by the driver */
		1123	status = HAL_ERROR;
		1124	}
		1125
		1126	/* Check the NOR memory status and update the controller state */
		1127	hnor->State = HAL_NOR_STATE_READY;
		1128
		1129	/* Process unlocked */
		1130	__HAL_UNLOCK(hnor);
		1131	}
		1132	else
		1133	{
		1134	return HAL_ERROR;
		1135	}
		1136
		1137	return status;
		1138
		1139	}
		1140
		1141	/**
		1142	* @brief Erase the entire NOR chip.
		1143	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1144	* the configuration information for NOR module.
		1145	* @param Address Device address
		1146	* @retval HAL status
		1147	*/
		1148	HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
		1149	{
		1150	uint32_t deviceaddress;
		1151	HAL_StatusTypeDef status = HAL_OK;
		1152	UNUSED(Address);
		1153
		1154	/* Check the NOR controller state */
		1155	if (hnor->State == HAL_NOR_STATE_BUSY)
		1156	{
		1157	return HAL_BUSY;
		1158	}
		1159	else if (hnor->State == HAL_NOR_STATE_READY)
		1160	{
		1161	/* Process Locked */
		1162	__HAL_LOCK(hnor);
		1163
		1164	/* Update the NOR controller state */
		1165	hnor->State = HAL_NOR_STATE_BUSY;
		1166
		1167	/* Select the NOR device address */
		1168	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		1169	{
		1170	deviceaddress = NOR_MEMORY_ADRESS1;
		1171	}
		1172	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		1173	{
		1174	deviceaddress = NOR_MEMORY_ADRESS2;
		1175	}
		1176	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		1177	{
		1178	deviceaddress = NOR_MEMORY_ADRESS3;
		1179	}
		1180	else /* FSMC_NORSRAM_BANK4 */
		1181	{
		1182	deviceaddress = NOR_MEMORY_ADRESS4;
		1183	}
		1184
		1185	/* Send NOR chip erase command sequence */
		1186	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		1187	{
		1188	if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
		1189	{
		1190	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
		1191	NOR_CMD_DATA_FIRST);
		1192	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
		1193	NOR_CMD_DATA_SECOND);
		1194	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
		1195	NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
		1196	}
		1197	else
		1198	{
		1199	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		1200	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		1201	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
		1202	NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
		1203	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
		1204	NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
		1205	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
		1206	NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
		1207	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH),
		1208	NOR_CMD_DATA_CHIP_ERASE);
		1209	}
		1210	}
		1211	else
		1212	{
		1213	/* Primary command set not supported by the driver */
		1214	status = HAL_ERROR;
		1215	}
		1216
		1217	/* Check the NOR memory status and update the controller state */
		1218	hnor->State = HAL_NOR_STATE_READY;
		1219
		1220	/* Process unlocked */
		1221	__HAL_UNLOCK(hnor);
		1222	}
		1223	else
		1224	{
		1225	return HAL_ERROR;
		1226	}
		1227
		1228	return status;
		1229	}
		1230
		1231	/**
		1232	* @brief Read NOR flash CFI IDs
		1233	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1234	* the configuration information for NOR module.
		1235	* @param pNOR_CFI pointer to NOR CFI IDs structure
		1236	* @retval HAL status
		1237	*/
		1238	HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef hnor, NOR_CFITypeDef pNOR_CFI)
		1239	{
		1240	uint32_t deviceaddress;
		1241	HAL_NOR_StateTypeDef state;
		1242
		1243	/* Check the NOR controller state */
		1244	state = hnor->State;
		1245	if (state == HAL_NOR_STATE_BUSY)
		1246	{
		1247	return HAL_BUSY;
		1248	}
		1249	else if (state == HAL_NOR_STATE_PROTECTED)
		1250	{
		1251	return HAL_ERROR;
		1252	}
		1253	else if (state == HAL_NOR_STATE_READY)
		1254	{
		1255	/* Process Locked */
		1256	__HAL_LOCK(hnor);
		1257
		1258	/* Update the NOR controller state */
		1259	hnor->State = HAL_NOR_STATE_BUSY;
		1260
		1261	/* Select the NOR device address */
		1262	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		1263	{
		1264	deviceaddress = NOR_MEMORY_ADRESS1;
		1265	}
		1266	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		1267	{
		1268	deviceaddress = NOR_MEMORY_ADRESS2;
		1269	}
		1270	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		1271	{
		1272	deviceaddress = NOR_MEMORY_ADRESS3;
		1273	}
		1274	else /* FSMC_NORSRAM_BANK4 */
		1275	{
		1276	deviceaddress = NOR_MEMORY_ADRESS4;
		1277	}
		1278
		1279	/* Send read CFI query command */
		1280	if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
		1281	{
		1282	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
		1283	NOR_CMD_DATA_CFI);
		1284	}
		1285	else
		1286	{
		1287	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
		1288	}
		1289	/* read the NOR CFI information */
		1290	pNOR_CFI->CFI_1 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
		1291	pNOR_CFI->CFI_2 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
		1292	pNOR_CFI->CFI_3 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
		1293	pNOR_CFI->CFI_4 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
		1294
		1295	/* Check the NOR controller state */
		1296	hnor->State = state;
		1297
		1298	/* Process unlocked */
		1299	__HAL_UNLOCK(hnor);
		1300	}
		1301	else
		1302	{
		1303	return HAL_ERROR;
		1304	}
		1305
		1306	return HAL_OK;
		1307	}
		1308
		1309	#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
		1310	/**
		1311	* @brief Register a User NOR Callback
		1312	* To be used to override the weak predefined callback
		1313	* @param hnor : NOR handle
		1314	* @param CallbackId : ID of the callback to be registered
		1315	* This parameter can be one of the following values:
		1316	* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
		1317	* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
		1318	* @param pCallback : pointer to the Callback function
		1319	* @retval status
		1320	*/
		1321	HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
		1322	pNOR_CallbackTypeDef pCallback)
		1323	{
		1324	HAL_StatusTypeDef status = HAL_OK;
		1325	HAL_NOR_StateTypeDef state;
		1326
		1327	if (pCallback == NULL)
		1328	{
		1329	return HAL_ERROR;
		1330	}
		1331
		1332	state = hnor->State;
		1333	if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_RESET) \|\| (state == HAL_NOR_STATE_PROTECTED))
		1334	{
		1335	switch (CallbackId)
		1336	{
		1337	case HAL_NOR_MSP_INIT_CB_ID :
		1338	hnor->MspInitCallback = pCallback;
		1339	break;
		1340	case HAL_NOR_MSP_DEINIT_CB_ID :
		1341	hnor->MspDeInitCallback = pCallback;
		1342	break;
		1343	default :
		1344	/* update return status */
		1345	status = HAL_ERROR;
		1346	break;
		1347	}
		1348	}
		1349	else
		1350	{
		1351	/* update return status */
		1352	status = HAL_ERROR;
		1353	}
		1354
		1355	return status;
		1356	}
		1357
		1358	/**
		1359	* @brief Unregister a User NOR Callback
		1360	* NOR Callback is redirected to the weak predefined callback
		1361	* @param hnor : NOR handle
		1362	* @param CallbackId : ID of the callback to be unregistered
		1363	* This parameter can be one of the following values:
		1364	* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
		1365	* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
		1366	* @retval status
		1367	*/
		1368	HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
		1369	{
		1370	HAL_StatusTypeDef status = HAL_OK;
		1371	HAL_NOR_StateTypeDef state;
		1372
		1373	state = hnor->State;
		1374	if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_RESET) \|\| (state == HAL_NOR_STATE_PROTECTED))
		1375	{
		1376	switch (CallbackId)
		1377	{
		1378	case HAL_NOR_MSP_INIT_CB_ID :
		1379	hnor->MspInitCallback = HAL_NOR_MspInit;
		1380	break;
		1381	case HAL_NOR_MSP_DEINIT_CB_ID :
		1382	hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
		1383	break;
		1384	default :
		1385	/* update return status */
		1386	status = HAL_ERROR;
		1387	break;
		1388	}
		1389	}
		1390	else
		1391	{
		1392	/* update return status */
		1393	status = HAL_ERROR;
		1394	}
		1395
		1396	return status;
		1397	}
		1398	#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
		1399
		1400	/**
		1401	* @}
		1402	*/
		1403
		1404	/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
		1405	* @brief management functions
		1406	*
		1407	@verbatim
		1408	==============================================================================
		1409	##### NOR Control functions #####
		1410	==============================================================================
		1411	[..]
		1412	This subsection provides a set of functions allowing to control dynamically
		1413	the NOR interface.
		1414
		1415	@endverbatim
		1416	* @{
		1417	*/
		1418
		1419	/**
		1420	* @brief Enables dynamically NOR write operation.
		1421	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1422	* the configuration information for NOR module.
		1423	* @retval HAL status
		1424	*/
		1425	HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
		1426	{
		1427	/* Check the NOR controller state */
		1428	if (hnor->State == HAL_NOR_STATE_PROTECTED)
		1429	{
		1430	/* Process Locked */
		1431	__HAL_LOCK(hnor);
		1432
		1433	/* Update the NOR controller state */
		1434	hnor->State = HAL_NOR_STATE_BUSY;
		1435
		1436	/* Enable write operation */
		1437	(void)FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
		1438
		1439	/* Update the NOR controller state */
		1440	hnor->State = HAL_NOR_STATE_READY;
		1441
		1442	/* Process unlocked */
		1443	__HAL_UNLOCK(hnor);
		1444	}
		1445	else
		1446	{
		1447	return HAL_ERROR;
		1448	}
		1449
		1450	return HAL_OK;
		1451	}
		1452
		1453	/**
		1454	* @brief Disables dynamically NOR write operation.
		1455	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1456	* the configuration information for NOR module.
		1457	* @retval HAL status
		1458	*/
		1459	HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
		1460	{
		1461	/* Check the NOR controller state */
		1462	if (hnor->State == HAL_NOR_STATE_READY)
		1463	{
		1464	/* Process Locked */
		1465	__HAL_LOCK(hnor);
		1466
		1467	/* Update the NOR controller state */
		1468	hnor->State = HAL_NOR_STATE_BUSY;
		1469
		1470	/* Disable write operation */
		1471	(void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
		1472
		1473	/* Update the NOR controller state */
		1474	hnor->State = HAL_NOR_STATE_PROTECTED;
		1475
		1476	/* Process unlocked */
		1477	__HAL_UNLOCK(hnor);
		1478	}
		1479	else
		1480	{
		1481	return HAL_ERROR;
		1482	}
		1483
		1484	return HAL_OK;
		1485	}
		1486
		1487	/**
		1488	* @}
		1489	*/
		1490
		1491	/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
		1492	* @brief Peripheral State functions
		1493	*
		1494	@verbatim
		1495	==============================================================================
		1496	##### NOR State functions #####
		1497	==============================================================================
		1498	[..]
		1499	This subsection permits to get in run-time the status of the NOR controller
		1500	and the data flow.
		1501
		1502	@endverbatim
		1503	* @{
		1504	*/
		1505
		1506	/**
		1507	* @brief return the NOR controller state
		1508	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1509	* the configuration information for NOR module.
		1510	* @retval NOR controller state
		1511	*/
		1512	HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
		1513	{
		1514	return hnor->State;
		1515	}
		1516
		1517	/**
		1518	* @brief Returns the NOR operation status.
		1519	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1520	* the configuration information for NOR module.
		1521	* @param Address Device address
		1522	* @param Timeout NOR programming Timeout
		1523	* @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
		1524	* or HAL_NOR_STATUS_TIMEOUT
		1525	*/
		1526	HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
		1527	{
		1528	HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
		1529	uint16_t tmpsr1;
		1530	uint16_t tmpsr2;
		1531	uint32_t tickstart;
		1532
		1533	/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
		1534	HAL_NOR_MspWait(hnor, Timeout);
		1535
		1536	/* Get the NOR memory operation status -------------------------------------*/
		1537
		1538	/* Get tick */
		1539	tickstart = HAL_GetTick();
		1540
		1541	if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
		1542	{
		1543	while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
		1544	{
		1545	/* Check for the Timeout */
		1546	if (Timeout != HAL_MAX_DELAY)
		1547	{
		1548	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
		1549	{
		1550	status = HAL_NOR_STATUS_TIMEOUT;
		1551	}
		1552	}
		1553
		1554	/* Read NOR status register (DQ6 and DQ5) */
		1555	tmpsr1 = (__IO uint16_t )Address;
		1556	tmpsr2 = (__IO uint16_t )Address;
		1557
		1558	/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
		1559	if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
		1560	{
		1561	return HAL_NOR_STATUS_SUCCESS ;
		1562	}
		1563
		1564	if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
		1565	{
		1566	status = HAL_NOR_STATUS_ONGOING;
		1567	}
		1568
		1569	tmpsr1 = (__IO uint16_t )Address;
		1570	tmpsr2 = (__IO uint16_t )Address;
		1571
		1572	/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
		1573	if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
		1574	{
		1575	return HAL_NOR_STATUS_SUCCESS;
		1576	}
		1577	if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
		1578	{
		1579	return HAL_NOR_STATUS_ERROR;
		1580	}
		1581	}
		1582	}
		1583	else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
		1584	{
		1585	do
		1586	{
		1587	NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
		1588	tmpsr2 = (__IO uint16_t )(Address);
		1589
		1590	/* Check for the Timeout */
		1591	if (Timeout != HAL_MAX_DELAY)
		1592	{
		1593	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
		1594	{
		1595	return HAL_NOR_STATUS_TIMEOUT;
		1596	}
		1597	}
		1598	} while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
		1599
		1600	NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
		1601	tmpsr1 = (__IO uint16_t )(Address);
		1602	if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 \| NOR_MASK_STATUS_DQ4)) != 0U)
		1603	{
		1604	/* Clear the Status Register */
		1605	NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
		1606	status = HAL_NOR_STATUS_ERROR;
		1607	}
		1608	else
		1609	{
		1610	status = HAL_NOR_STATUS_SUCCESS;
		1611	}
		1612	}
		1613	else
		1614	{
		1615	/* Primary command set not supported by the driver */
		1616	status = HAL_NOR_STATUS_ERROR;
		1617	}
		1618
		1619	/* Return the operation status */
		1620	return status;
		1621	}
		1622
		1623	/**
		1624	* @}
		1625	*/
		1626
		1627	/**
		1628	* @}
		1629	*/
		1630
		1631	/**
		1632	* @}
		1633	*/
		1634
		1635	#endif /* HAL_NOR_MODULE_ENABLED */
		1636
		1637	/**
		1638	* @}
		1639	*/
		1640
		1641	#endif /* FSMC_BANK1 */

Subversion Repositories AFRtranscoder

(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c – Rev 2