WebSVN – dashGPS – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_nand.c
		4	* @author MCD Application Team
		5	* @brief NAND HAL module driver.
		6	* This file provides a generic firmware to drive NAND memories mounted
		7	* as external device.
		8	*
		9	@verbatim
		10	==============================================================================
		11	##### How to use this driver #####
		12	==============================================================================
		13	[..]
		14	This driver is a generic layered driver which contains a set of APIs used to
		15	control NAND flash memories. It uses the FSMC layer functions to interface
		16	with NAND devices. This driver is used as follows:
		17
		18	(+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
		19	with control and timing parameters for both common and attribute spaces.
		20
		21	(+) Read NAND flash memory maker and device IDs using the function
		22	HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
		23	structure declared by the function caller.
		24
		25	(+) Access NAND flash memory by read/write operations using the functions
		26	HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
		27	HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
		28	HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
		29	HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
		30	to read/write page(s)/spare area(s). These functions use specific device
		31	information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
		32	structure. The read/write address information is contained by the Nand_Address_Typedef
		33	structure passed as parameter.
		34
		35	(+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
		36
		37	(+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
		38	The erase block address information is contained in the Nand_Address_Typedef
		39	structure passed as parameter.
		40
		41	(+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
		42
		43	(+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
		44	HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
		45	feature or the function HAL_NAND_GetECC() to get the ECC correction code.
		46
		47	(+) You can monitor the NAND device HAL state by calling the function
		48	HAL_NAND_GetState()
		49
		50	[..]
		51	(@) This driver is a set of generic APIs which handle standard NAND flash operations.
		52	If a NAND flash device contains different operations and/or implementations,
		53	it should be implemented separately.
		54
		55	* Callback registration *
		56	=============================================
		57	[..]
		58	The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
		59	allows the user to configure dynamically the driver callbacks.
		60
		61	Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
		62	it allows to register following callbacks:
		63	(+) MspInitCallback : NAND MspInit.
		64	(+) MspDeInitCallback : NAND MspDeInit.
		65	This function takes as parameters the HAL peripheral handle, the Callback ID
		66	and a pointer to the user callback function.
		67
		68	Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
		69	weak (surcharged) function. It allows to reset following callbacks:
		70	(+) MspInitCallback : NAND MspInit.
		71	(+) MspDeInitCallback : NAND MspDeInit.
		72	This function) takes as parameters the HAL peripheral handle and the Callback ID.
		73
		74	By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
		75	all callbacks are reset to the corresponding legacy weak (surcharged) functions.
		76	Exception done for MspInit and MspDeInit callbacks that are respectively
		77	reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
		78	and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
		79	If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
		80	keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
		81
		82	Callbacks can be registered/unregistered in READY state only.
		83	Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
		84	in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
		85	during the Init/DeInit.
		86	In that case first register the MspInit/MspDeInit user callbacks
		87	using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
		88	or @ref HAL_NAND_Init function.
		89
		90	When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
		91	not defined, the callback registering feature is not available
		92	and weak (surcharged) callbacks are used.
		93
		94	@endverbatim
		95	******************************************************************************
		96	* @attention
		97	*
		98	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		99	* All rights reserved.</center></h2>
		100	*
		101	* This software component is licensed by ST under BSD 3-Clause license,
		102	* the "License"; You may not use this file except in compliance with the
		103	* License. You may obtain a copy of the License at:
		104	* opensource.org/licenses/BSD-3-Clause
		105	*
		106	******************************************************************************
		107	*/
		108
		109	/* Includes ------------------------------------------------------------------*/
		110	#include "stm32f1xx_hal.h"
		111
		112	#if defined(FSMC_BANK3)
		113
		114	/** @addtogroup STM32F1xx_HAL_Driver
		115	* @{
		116	*/
		117
		118	#ifdef HAL_NAND_MODULE_ENABLED
		119
		120	/** @defgroup NAND NAND
		121	* @brief NAND HAL module driver
		122	* @{
		123	*/
		124
		125	/* Private typedef -----------------------------------------------------------*/
		126	/* Private Constants ------------------------------------------------------------*/
		127	/* Private macro -------------------------------------------------------------*/
		128	/* Private variables ---------------------------------------------------------*/
		129	/* Private function prototypes -----------------------------------------------*/
		130	/* Exported functions ---------------------------------------------------------*/
		131
		132	/** @defgroup NAND_Exported_Functions NAND Exported Functions
		133	* @{
		134	*/
		135
		136	/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
		137	* @brief Initialization and Configuration functions
		138	*
		139	@verbatim
		140	==============================================================================
		141	##### NAND Initialization and de-initialization functions #####
		142	==============================================================================
		143	[..]
		144	This section provides functions allowing to initialize/de-initialize
		145	the NAND memory
		146
		147	@endverbatim
		148	* @{
		149	*/
		150
		151	/**
		152	* @brief Perform NAND memory Initialization sequence
		153	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		154	* the configuration information for NAND module.
		155	* @param ComSpace_Timing pointer to Common space timing structure
		156	* @param AttSpace_Timing pointer to Attribute space timing structure
		157	* @retval HAL status
		158	*/
		159	HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef hnand, FSMC_NAND_PCC_TimingTypeDef ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
		160	{
		161	/* Check the NAND handle state */
		162	if (hnand == NULL)
		163	{
		164	return HAL_ERROR;
		165	}
		166
		167	if (hnand->State == HAL_NAND_STATE_RESET)
		168	{
		169	/* Allocate lock resource and initialize it */
		170	hnand->Lock = HAL_UNLOCKED;
		171
		172	#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
		173	if(hnand->MspInitCallback == NULL)
		174	{
		175	hnand->MspInitCallback = HAL_NAND_MspInit;
		176	}
		177	hnand->ItCallback = HAL_NAND_ITCallback;
		178
		179	/* Init the low level hardware */
		180	hnand->MspInitCallback(hnand);
		181	#else
		182	/* Initialize the low level hardware (MSP) */
		183	HAL_NAND_MspInit(hnand);
		184	#endif
		185	}
		186
		187	/* Initialize NAND control Interface */
		188	(void)FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
		189
		190	/* Initialize NAND common space timing Interface */
		191	(void)FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
		192
		193	/* Initialize NAND attribute space timing Interface */
		194	(void)FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
		195
		196	/* Enable the NAND device */
		197	__FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
		198
		199	/* Update the NAND controller state */
		200	hnand->State = HAL_NAND_STATE_READY;
		201
		202	return HAL_OK;
		203	}
		204
		205	/**
		206	* @brief Perform NAND memory De-Initialization sequence
		207	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		208	* the configuration information for NAND module.
		209	* @retval HAL status
		210	*/
		211	HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
		212	{
		213	#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
		214	if(hnand->MspDeInitCallback == NULL)
		215	{
		216	hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
		217	}
		218
		219	/* DeInit the low level hardware */
		220	hnand->MspDeInitCallback(hnand);
		221	#else
		222	/* Initialize the low level hardware (MSP) */
		223	HAL_NAND_MspDeInit(hnand);
		224	#endif
		225
		226	/* Configure the NAND registers with their reset values */
		227	(void)FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
		228
		229	/* Reset the NAND controller state */
		230	hnand->State = HAL_NAND_STATE_RESET;
		231
		232	/* Release Lock */
		233	__HAL_UNLOCK(hnand);
		234
		235	return HAL_OK;
		236	}
		237
		238	/**
		239	* @brief NAND MSP Init
		240	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		241	* the configuration information for NAND module.
		242	* @retval None
		243	*/
		244	__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
		245	{
		246	/* Prevent unused argument(s) compilation warning */
		247	UNUSED(hnand);
		248
		249	/* NOTE : This function Should not be modified, when the callback is needed,
		250	the HAL_NAND_MspInit could be implemented in the user file
		251	*/
		252	}
		253
		254	/**
		255	* @brief NAND MSP DeInit
		256	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		257	* the configuration information for NAND module.
		258	* @retval None
		259	*/
		260	__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
		261	{
		262	/* Prevent unused argument(s) compilation warning */
		263	UNUSED(hnand);
		264
		265	/* NOTE : This function Should not be modified, when the callback is needed,
		266	the HAL_NAND_MspDeInit could be implemented in the user file
		267	*/
		268	}
		269
		270
		271	/**
		272	* @brief This function handles NAND device interrupt request.
		273	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		274	* the configuration information for NAND module.
		275	* @retval HAL status
		276	*/
		277	void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
		278	{
		279	/* Check NAND interrupt Rising edge flag */
		280	if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
		281	{
		282	/* NAND interrupt callback*/
		283	#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
		284	hnand->ItCallback(hnand);
		285	#else
		286	HAL_NAND_ITCallback(hnand);
		287	#endif
		288
		289	/* Clear NAND interrupt Rising edge pending bit */
		290	__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
		291	}
		292
		293	/* Check NAND interrupt Level flag */
		294	if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
		295	{
		296	/* NAND interrupt callback*/
		297	#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
		298	hnand->ItCallback(hnand);
		299	#else
		300	HAL_NAND_ITCallback(hnand);
		301	#endif
		302
		303	/* Clear NAND interrupt Level pending bit */
		304	__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
		305	}
		306
		307	/* Check NAND interrupt Falling edge flag */
		308	if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
		309	{
		310	/* NAND interrupt callback*/
		311	#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
		312	hnand->ItCallback(hnand);
		313	#else
		314	HAL_NAND_ITCallback(hnand);
		315	#endif
		316
		317	/* Clear NAND interrupt Falling edge pending bit */
		318	__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
		319	}
		320
		321	/* Check NAND interrupt FIFO empty flag */
		322	if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
		323	{
		324	/* NAND interrupt callback*/
		325	#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
		326	hnand->ItCallback(hnand);
		327	#else
		328	HAL_NAND_ITCallback(hnand);
		329	#endif
		330
		331	/* Clear NAND interrupt FIFO empty pending bit */
		332	__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
		333	}
		334
		335	}
		336
		337	/**
		338	* @brief NAND interrupt feature callback
		339	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		340	* the configuration information for NAND module.
		341	* @retval None
		342	*/
		343	__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
		344	{
		345	/* Prevent unused argument(s) compilation warning */
		346	UNUSED(hnand);
		347
		348	/* NOTE : This function Should not be modified, when the callback is needed,
		349	the HAL_NAND_ITCallback could be implemented in the user file
		350	*/
		351	}
		352
		353	/**
		354	* @}
		355	*/
		356
		357	/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
		358	* @brief Input Output and memory control functions
		359	*
		360	@verbatim
		361	==============================================================================
		362	##### NAND Input and Output functions #####
		363	==============================================================================
		364	[..]
		365	This section provides functions allowing to use and control the NAND
		366	memory
		367
		368	@endverbatim
		369	* @{
		370	*/
		371
		372	/**
		373	* @brief Read the NAND memory electronic signature
		374	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		375	* the configuration information for NAND module.
		376	* @param pNAND_ID NAND ID structure
		377	* @retval HAL status
		378	*/
		379	HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef hnand, NAND_IDTypeDef pNAND_ID)
		380	{
		381	__IO uint32_t data = 0;
		382	__IO uint32_t data1 = 0;
		383	uint32_t deviceAddress;
		384
		385	/* Check the NAND controller state */
		386	if (hnand->State == HAL_NAND_STATE_BUSY)
		387	{
		388	return HAL_BUSY;
		389	}
		390	else if (hnand->State == HAL_NAND_STATE_READY)
		391	{
		392	/* Process Locked */
		393	__HAL_LOCK(hnand);
		394
		395	/* Update the NAND controller state */
		396	hnand->State = HAL_NAND_STATE_BUSY;
		397
		398	/* Identify the device address */
		399	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		400	{
		401	deviceAddress = NAND_DEVICE1;
		402	}
		403	else
		404	{
		405	deviceAddress = NAND_DEVICE2;
		406	}
		407
		408	/* Send Read ID command sequence */
		409	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_READID;
		410	__DSB();
		411	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
		412	__DSB();
		413
		414	/* Read the electronic signature from NAND flash */
		415	if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
		416	{
		417	data = (__IO uint32_t )deviceAddress;
		418
		419	/* Return the data read */
		420	pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
		421	pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
		422	pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
		423	pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
		424	}
		425	else
		426	{
		427	data = (__IO uint32_t )deviceAddress;
		428	data1 = ((__IO uint32_t )deviceAddress + 4);
		429
		430	/* Return the data read */
		431	pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
		432	pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
		433	pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
		434	pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
		435	}
		436
		437	/* Update the NAND controller state */
		438	hnand->State = HAL_NAND_STATE_READY;
		439
		440	/* Process unlocked */
		441	__HAL_UNLOCK(hnand);
		442	}
		443	else
		444	{
		445	return HAL_ERROR;
		446	}
		447
		448	return HAL_OK;
		449	}
		450
		451	/**
		452	* @brief NAND memory reset
		453	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		454	* the configuration information for NAND module.
		455	* @retval HAL status
		456	*/
		457	HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
		458	{
		459	uint32_t deviceAddress;
		460
		461	/* Check the NAND controller state */
		462	if (hnand->State == HAL_NAND_STATE_BUSY)
		463	{
		464	return HAL_BUSY;
		465	}
		466	else if (hnand->State == HAL_NAND_STATE_READY)
		467	{
		468	/* Process Locked */
		469	__HAL_LOCK(hnand);
		470
		471	/* Update the NAND controller state */
		472	hnand->State = HAL_NAND_STATE_BUSY;
		473
		474	/* Identify the device address */
		475	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		476	{
		477	deviceAddress = NAND_DEVICE1;
		478	}
		479	else
		480	{
		481	deviceAddress = NAND_DEVICE2;
		482	}
		483
		484	/* Send NAND reset command */
		485	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = 0xFF;
		486
		487	/* Update the NAND controller state */
		488	hnand->State = HAL_NAND_STATE_READY;
		489
		490	/* Process unlocked */
		491	__HAL_UNLOCK(hnand);
		492	}
		493	else
		494	{
		495	return HAL_ERROR;
		496	}
		497
		498	return HAL_OK;
		499
		500	}
		501
		502	/**
		503	* @brief Configure the device: Enter the physical parameters of the device
		504	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		505	* the configuration information for NAND module.
		506	* @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
		507	* @retval HAL status
		508	*/
		509	HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef hnand, NAND_DeviceConfigTypeDef pDeviceConfig)
		510	{
		511	hnand->Config.PageSize = pDeviceConfig->PageSize;
		512	hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
		513	hnand->Config.BlockSize = pDeviceConfig->BlockSize;
		514	hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
		515	hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
		516	hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
		517	hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
		518
		519	return HAL_OK;
		520	}
		521
		522	/**
		523	* @brief Read Page(s) from NAND memory block (8-bits addressing)
		524	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		525	* the configuration information for NAND module.
		526	* @param pAddress pointer to NAND address structure
		527	* @param pBuffer pointer to destination read buffer
		528	* @param NumPageToRead number of pages to read from block
		529	* @retval HAL status
		530	*/
		531	HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
		532	{
		533	uint32_t index;
		534	uint32_t tickstart;
		535	uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead;
		536	uint8_t * buff = pBuffer;
		537
		538	/* Check the NAND controller state */
		539	if (hnand->State == HAL_NAND_STATE_BUSY)
		540	{
		541	return HAL_BUSY;
		542	}
		543	else if (hnand->State == HAL_NAND_STATE_READY)
		544	{
		545	/* Process Locked */
		546	__HAL_LOCK(hnand);
		547
		548	/* Update the NAND controller state */
		549	hnand->State = HAL_NAND_STATE_BUSY;
		550
		551	/* Identify the device address */
		552	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		553	{
		554	deviceAddress = NAND_DEVICE1;
		555	}
		556	else
		557	{
		558	deviceAddress = NAND_DEVICE2;
		559	}
		560
		561	/* NAND raw address calculation */
		562	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
		563
		564	/* Page(s) read loop */
		565	while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
		566	{
		567	/* Send read page command sequence */
		568	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
		569	__DSB();
		570
		571	/* Cards with page size <= 512 bytes */
		572	if ((hnand->Config.PageSize) <= 512U)
		573	{
		574	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		575	{
		576	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		577	__DSB();
		578	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		579	__DSB();
		580	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		581	__DSB();
		582	}
		583	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		584	{
		585	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		586	__DSB();
		587	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		588	__DSB();
		589	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		590	__DSB();
		591	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		592	__DSB();
		593	}
		594	}
		595	else /* (hnand->Config.PageSize) > 512 */
		596	{
		597	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		598	{
		599	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		600	__DSB();
		601	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		602	__DSB();
		603	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		604	__DSB();
		605	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		606	__DSB();
		607	}
		608	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		609	{
		610	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		611	__DSB();
		612	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		613	__DSB();
		614	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		615	__DSB();
		616	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		617	__DSB();
		618	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		619	__DSB();
		620	}
		621	}
		622
		623	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
		624	__DSB();
		625
		626
		627	if (hnand->Config.ExtraCommandEnable == ENABLE)
		628	{
		629	/* Get tick */
		630	tickstart = HAL_GetTick();
		631
		632	/* Read status until NAND is ready */
		633	while (HAL_NAND_Read_Status(hnand) != NAND_READY)
		634	{
		635	if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
		636	{
		637	/* Update the NAND controller state */
		638	hnand->State = HAL_NAND_STATE_ERROR;
		639
		640	/* Process unlocked */
		641	__HAL_UNLOCK(hnand);
		642
		643	return HAL_TIMEOUT;
		644	}
		645	}
		646
		647	/* Go back to read mode */
		648	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = ((uint8_t)0x00U);
		649	__DSB();
		650	}
		651
		652	/* Get Data into Buffer */
		653	for (index = 0U; index < hnand->Config.PageSize; index++)
		654	{
		655	buff = (uint8_t *)deviceAddress;
		656	buff++;
		657	}
		658
		659	/* Increment read pages number */
		660	numPagesRead++;
		661
		662	/* Decrement pages to read */
		663	nbpages--;
		664
		665	/* Increment the NAND address */
		666	nandAddress = (uint32_t)(nandAddress + 1U);
		667	}
		668
		669	/* Update the NAND controller state */
		670	hnand->State = HAL_NAND_STATE_READY;
		671
		672	/* Process unlocked */
		673	__HAL_UNLOCK(hnand);
		674	}
		675	else
		676	{
		677	return HAL_ERROR;
		678	}
		679
		680	return HAL_OK;
		681	}
		682
		683	/**
		684	* @brief Read Page(s) from NAND memory block (16-bits addressing)
		685	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		686	* the configuration information for NAND module.
		687	* @param pAddress pointer to NAND address structure
		688	* @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
		689	* @param NumPageToRead number of pages to read from block
		690	* @retval HAL status
		691	*/
		692	HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
		693	{
		694	uint32_t index;
		695	uint32_t tickstart;
		696	uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead;
		697	uint16_t * buff = pBuffer;
		698
		699	/* Check the NAND controller state */
		700	if (hnand->State == HAL_NAND_STATE_BUSY)
		701	{
		702	return HAL_BUSY;
		703	}
		704	else if (hnand->State == HAL_NAND_STATE_READY)
		705	{
		706	/* Process Locked */
		707	__HAL_LOCK(hnand);
		708
		709	/* Update the NAND controller state */
		710	hnand->State = HAL_NAND_STATE_BUSY;
		711
		712	/* Identify the device address */
		713	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		714	{
		715	deviceAddress = NAND_DEVICE1;
		716	}
		717	else
		718	{
		719	deviceAddress = NAND_DEVICE2;
		720	}
		721
		722	/* NAND raw address calculation */
		723	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
		724
		725	/* Page(s) read loop */
		726	while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
		727	{
		728	/* Send read page command sequence */
		729	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
		730	__DSB();
		731
		732	/* Cards with page size <= 512 bytes */
		733	if ((hnand->Config.PageSize) <= 512U)
		734	{
		735	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		736	{
		737	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		738	__DSB();
		739	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		740	__DSB();
		741	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		742	__DSB();
		743	}
		744	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		745	{
		746	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		747	__DSB();
		748	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		749	__DSB();
		750	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		751	__DSB();
		752	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		753	__DSB();
		754	}
		755	}
		756	else /* (hnand->Config.PageSize) > 512 */
		757	{
		758	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		759	{
		760	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		761	__DSB();
		762	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		763	__DSB();
		764	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		765	__DSB();
		766	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		767	__DSB();
		768	}
		769	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		770	{
		771	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		772	__DSB();
		773	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		774	__DSB();
		775	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		776	__DSB();
		777	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		778	__DSB();
		779	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		780	__DSB();
		781	}
		782	}
		783
		784	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
		785	__DSB();
		786
		787	if (hnand->Config.ExtraCommandEnable == ENABLE)
		788	{
		789	/* Get tick */
		790	tickstart = HAL_GetTick();
		791
		792	/* Read status until NAND is ready */
		793	while (HAL_NAND_Read_Status(hnand) != NAND_READY)
		794	{
		795	if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
		796	{
		797	/* Update the NAND controller state */
		798	hnand->State = HAL_NAND_STATE_ERROR;
		799
		800	/* Process unlocked */
		801	__HAL_UNLOCK(hnand);
		802
		803	return HAL_TIMEOUT;
		804	}
		805	}
		806
		807	/* Go back to read mode */
		808	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = ((uint8_t)0x00U);
		809	__DSB();
		810	}
		811
		812	/* Get Data into Buffer */
		813	for (index = 0U; index < hnand->Config.PageSize; index++)
		814	{
		815	buff = (uint16_t *)deviceAddress;
		816	buff++;
		817	}
		818
		819	/* Increment read pages number */
		820	numPagesRead++;
		821
		822	/* Decrement pages to read */
		823	nbpages--;
		824
		825	/* Increment the NAND address */
		826	nandAddress = (uint32_t)(nandAddress + 1U);
		827	}
		828
		829	/* Update the NAND controller state */
		830	hnand->State = HAL_NAND_STATE_READY;
		831
		832	/* Process unlocked */
		833	__HAL_UNLOCK(hnand);
		834	}
		835	else
		836	{
		837	return HAL_ERROR;
		838	}
		839
		840	return HAL_OK;
		841	}
		842
		843	/**
		844	* @brief Write Page(s) to NAND memory block (8-bits addressing)
		845	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		846	* the configuration information for NAND module.
		847	* @param pAddress pointer to NAND address structure
		848	* @param pBuffer pointer to source buffer to write
		849	* @param NumPageToWrite number of pages to write to block
		850	* @retval HAL status
		851	*/
		852	HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
		853	{
		854	uint32_t index;
		855	uint32_t tickstart;
		856	uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
		857	uint8_t * buff = pBuffer;
		858
		859	/* Check the NAND controller state */
		860	if (hnand->State == HAL_NAND_STATE_BUSY)
		861	{
		862	return HAL_BUSY;
		863	}
		864	else if (hnand->State == HAL_NAND_STATE_READY)
		865	{
		866	/* Process Locked */
		867	__HAL_LOCK(hnand);
		868
		869	/* Update the NAND controller state */
		870	hnand->State = HAL_NAND_STATE_BUSY;
		871
		872	/* Identify the device address */
		873	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		874	{
		875	deviceAddress = NAND_DEVICE1;
		876	}
		877	else
		878	{
		879	deviceAddress = NAND_DEVICE2;
		880	}
		881
		882	/* NAND raw address calculation */
		883	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
		884
		885	/* Page(s) write loop */
		886	while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
		887	{
		888	/* Send write page command sequence */
		889	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
		890	__DSB();
		891	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
		892	__DSB();
		893
		894	/* Cards with page size <= 512 bytes */
		895	if ((hnand->Config.PageSize) <= 512U)
		896	{
		897	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		898	{
		899	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		900	__DSB();
		901	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		902	__DSB();
		903	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		904	__DSB();
		905	}
		906	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		907	{
		908	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		909	__DSB();
		910	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		911	__DSB();
		912	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		913	__DSB();
		914	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		915	__DSB();
		916	}
		917	}
		918	else /* (hnand->Config.PageSize) > 512 */
		919	{
		920	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		921	{
		922	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		923	__DSB();
		924	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		925	__DSB();
		926	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		927	__DSB();
		928	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		929	__DSB();
		930	}
		931	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		932	{
		933	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		934	__DSB();
		935	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		936	__DSB();
		937	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		938	__DSB();
		939	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		940	__DSB();
		941	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		942	__DSB();
		943	}
		944	}
		945
		946	/* Write data to memory */
		947	for (index = 0U; index < hnand->Config.PageSize; index++)
		948	{
		949	(__IO uint8_t )deviceAddress = *buff;
		950	buff++;
		951	__DSB();
		952	}
		953
		954	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
		955	__DSB();
		956
		957	/* Get tick */
		958	tickstart = HAL_GetTick();
		959
		960	/* Read status until NAND is ready */
		961	while (HAL_NAND_Read_Status(hnand) != NAND_READY)
		962	{
		963	if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
		964	{
		965	/* Update the NAND controller state */
		966	hnand->State = HAL_NAND_STATE_ERROR;
		967
		968	/* Process unlocked */
		969	__HAL_UNLOCK(hnand);
		970
		971	return HAL_TIMEOUT;
		972	}
		973	}
		974
		975	/* Increment written pages number */
		976	numPagesWritten++;
		977
		978	/* Decrement pages to write */
		979	nbpages--;
		980
		981	/* Increment the NAND address */
		982	nandAddress = (uint32_t)(nandAddress + 1U);
		983	}
		984
		985	/* Update the NAND controller state */
		986	hnand->State = HAL_NAND_STATE_READY;
		987
		988	/* Process unlocked */
		989	__HAL_UNLOCK(hnand);
		990	}
		991	else
		992	{
		993	return HAL_ERROR;
		994	}
		995
		996	return HAL_OK;
		997	}
		998
		999	/**
		1000	* @brief Write Page(s) to NAND memory block (16-bits addressing)
		1001	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		1002	* the configuration information for NAND module.
		1003	* @param pAddress pointer to NAND address structure
		1004	* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
		1005	* @param NumPageToWrite number of pages to write to block
		1006	* @retval HAL status
		1007	*/
		1008	HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
		1009	{
		1010	uint32_t index;
		1011	uint32_t tickstart;
		1012	uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
		1013	uint16_t * buff = pBuffer;
		1014
		1015	/* Check the NAND controller state */
		1016	if (hnand->State == HAL_NAND_STATE_BUSY)
		1017	{
		1018	return HAL_BUSY;
		1019	}
		1020	else if (hnand->State == HAL_NAND_STATE_READY)
		1021	{
		1022	/* Process Locked */
		1023	__HAL_LOCK(hnand);
		1024
		1025	/* Update the NAND controller state */
		1026	hnand->State = HAL_NAND_STATE_BUSY;
		1027
		1028	/* Identify the device address */
		1029	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		1030	{
		1031	deviceAddress = NAND_DEVICE1;
		1032	}
		1033	else
		1034	{
		1035	deviceAddress = NAND_DEVICE2;
		1036	}
		1037
		1038	/* NAND raw address calculation */
		1039	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
		1040
		1041	/* Page(s) write loop */
		1042	while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
		1043	{
		1044	/* Send write page command sequence */
		1045	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
		1046	__DSB();
		1047	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
		1048	__DSB();
		1049
		1050	/* Cards with page size <= 512 bytes */
		1051	if ((hnand->Config.PageSize) <= 512U)
		1052	{
		1053	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1054	{
		1055	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1056	__DSB();
		1057	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1058	__DSB();
		1059	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1060	__DSB();
		1061	}
		1062	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1063	{
		1064	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1065	__DSB();
		1066	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1067	__DSB();
		1068	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1069	__DSB();
		1070	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1071	__DSB();
		1072	}
		1073	}
		1074	else /* (hnand->Config.PageSize) > 512 */
		1075	{
		1076	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1077	{
		1078	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1079	__DSB();
		1080	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1081	__DSB();
		1082	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1083	__DSB();
		1084	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1085	__DSB();
		1086	}
		1087	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1088	{
		1089	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1090	__DSB();
		1091	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1092	__DSB();
		1093	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1094	__DSB();
		1095	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1096	__DSB();
		1097	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1098	__DSB();
		1099	}
		1100	}
		1101
		1102	/* Write data to memory */
		1103	for (index = 0U; index < hnand->Config.PageSize; index++)
		1104	{
		1105	(__IO uint16_t )deviceAddress = *buff;
		1106	buff++;
		1107	__DSB();
		1108	}
		1109
		1110	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
		1111	__DSB();
		1112
		1113	/* Get tick */
		1114	tickstart = HAL_GetTick();
		1115
		1116	/* Read status until NAND is ready */
		1117	while (HAL_NAND_Read_Status(hnand) != NAND_READY)
		1118	{
		1119	if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
		1120	{
		1121	/* Update the NAND controller state */
		1122	hnand->State = HAL_NAND_STATE_ERROR;
		1123
		1124	/* Process unlocked */
		1125	__HAL_UNLOCK(hnand);
		1126
		1127	return HAL_TIMEOUT;
		1128	}
		1129	}
		1130
		1131	/* Increment written pages number */
		1132	numPagesWritten++;
		1133
		1134	/* Decrement pages to write */
		1135	nbpages--;
		1136
		1137	/* Increment the NAND address */
		1138	nandAddress = (uint32_t)(nandAddress + 1U);
		1139	}
		1140
		1141	/* Update the NAND controller state */
		1142	hnand->State = HAL_NAND_STATE_READY;
		1143
		1144	/* Process unlocked */
		1145	__HAL_UNLOCK(hnand);
		1146	}
		1147	else
		1148	{
		1149	return HAL_ERROR;
		1150	}
		1151
		1152	return HAL_OK;
		1153	}
		1154
		1155	/**
		1156	* @brief Read Spare area(s) from NAND memory (8-bits addressing)
		1157	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		1158	* the configuration information for NAND module.
		1159	* @param pAddress pointer to NAND address structure
		1160	* @param pBuffer pointer to source buffer to write
		1161	* @param NumSpareAreaToRead Number of spare area to read
		1162	* @retval HAL status
		1163	*/
		1164	HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
		1165	{
		1166	uint32_t index;
		1167	uint32_t tickstart;
		1168	uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
		1169	uint8_t * buff = pBuffer;
		1170
		1171	/* Check the NAND controller state */
		1172	if (hnand->State == HAL_NAND_STATE_BUSY)
		1173	{
		1174	return HAL_BUSY;
		1175	}
		1176	else if (hnand->State == HAL_NAND_STATE_READY)
		1177	{
		1178	/* Process Locked */
		1179	__HAL_LOCK(hnand);
		1180
		1181	/* Update the NAND controller state */
		1182	hnand->State = HAL_NAND_STATE_BUSY;
		1183
		1184	/* Identify the device address */
		1185	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		1186	{
		1187	deviceAddress = NAND_DEVICE1;
		1188	}
		1189	else
		1190	{
		1191	deviceAddress = NAND_DEVICE2;
		1192	}
		1193
		1194	/* NAND raw address calculation */
		1195	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
		1196
		1197	/* Column in page address */
		1198	columnAddress = COLUMN_ADDRESS(hnand);
		1199
		1200	/* Spare area(s) read loop */
		1201	while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
		1202	{
		1203	/* Cards with page size <= 512 bytes */
		1204	if ((hnand->Config.PageSize) <= 512U)
		1205	{
		1206	/* Send read spare area command sequence */
		1207	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_C;
		1208	__DSB();
		1209
		1210	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1211	{
		1212	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1213	__DSB();
		1214	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1215	__DSB();
		1216	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1217	__DSB();
		1218	}
		1219	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1220	{
		1221	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1222	__DSB();
		1223	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1224	__DSB();
		1225	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1226	__DSB();
		1227	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1228	__DSB();
		1229	}
		1230	}
		1231	else /* (hnand->Config.PageSize) > 512 */
		1232	{
		1233	/* Send read spare area command sequence */
		1234	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
		1235	__DSB();
		1236
		1237	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1238	{
		1239	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
		1240	__DSB();
		1241	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
		1242	__DSB();
		1243	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1244	__DSB();
		1245	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1246	__DSB();
		1247	}
		1248	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1249	{
		1250	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
		1251	__DSB();
		1252	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
		1253	__DSB();
		1254	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1255	__DSB();
		1256	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1257	__DSB();
		1258	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1259	__DSB();
		1260	}
		1261	}
		1262
		1263	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
		1264	__DSB();
		1265
		1266	if (hnand->Config.ExtraCommandEnable == ENABLE)
		1267	{
		1268	/* Get tick */
		1269	tickstart = HAL_GetTick();
		1270
		1271	/* Read status until NAND is ready */
		1272	while (HAL_NAND_Read_Status(hnand) != NAND_READY)
		1273	{
		1274	if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
		1275	{
		1276	/* Update the NAND controller state */
		1277	hnand->State = HAL_NAND_STATE_ERROR;
		1278
		1279	/* Process unlocked */
		1280	__HAL_UNLOCK(hnand);
		1281
		1282	return HAL_TIMEOUT;
		1283	}
		1284	}
		1285
		1286	/* Go back to read mode */
		1287	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = ((uint8_t)0x00U);
		1288	__DSB();
		1289	}
		1290
		1291	/* Get Data into Buffer */
		1292	for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
		1293	{
		1294	buff = (uint8_t *)deviceAddress;
		1295	buff++;
		1296	}
		1297
		1298	/* Increment read spare areas number */
		1299	numSpareAreaRead++;
		1300
		1301	/* Decrement spare areas to read */
		1302	nbspare--;
		1303
		1304	/* Increment the NAND address */
		1305	nandAddress = (uint32_t)(nandAddress + 1U);
		1306	}
		1307
		1308	/* Update the NAND controller state */
		1309	hnand->State = HAL_NAND_STATE_READY;
		1310
		1311	/* Process unlocked */
		1312	__HAL_UNLOCK(hnand);
		1313	}
		1314	else
		1315	{
		1316	return HAL_ERROR;
		1317	}
		1318
		1319	return HAL_OK;
		1320	}
		1321
		1322	/**
		1323	* @brief Read Spare area(s) from NAND memory (16-bits addressing)
		1324	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		1325	* the configuration information for NAND module.
		1326	* @param pAddress pointer to NAND address structure
		1327	* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
		1328	* @param NumSpareAreaToRead Number of spare area to read
		1329	* @retval HAL status
		1330	*/
		1331	HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
		1332	{
		1333	uint32_t index;
		1334	uint32_t tickstart;
		1335	uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
		1336	uint16_t * buff = pBuffer;
		1337
		1338	/* Check the NAND controller state */
		1339	if (hnand->State == HAL_NAND_STATE_BUSY)
		1340	{
		1341	return HAL_BUSY;
		1342	}
		1343	else if (hnand->State == HAL_NAND_STATE_READY)
		1344	{
		1345	/* Process Locked */
		1346	__HAL_LOCK(hnand);
		1347
		1348	/* Update the NAND controller state */
		1349	hnand->State = HAL_NAND_STATE_BUSY;
		1350
		1351	/* Identify the device address */
		1352	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		1353	{
		1354	deviceAddress = NAND_DEVICE1;
		1355	}
		1356	else
		1357	{
		1358	deviceAddress = NAND_DEVICE2;
		1359	}
		1360
		1361	/* NAND raw address calculation */
		1362	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
		1363
		1364	/* Column in page address */
		1365	columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
		1366
		1367	/* Spare area(s) read loop */
		1368	while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
		1369	{
		1370	/* Cards with page size <= 512 bytes */
		1371	if ((hnand->Config.PageSize) <= 512U)
		1372	{
		1373	/* Send read spare area command sequence */
		1374	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_C;
		1375	__DSB();
		1376
		1377	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1378	{
		1379	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1380	__DSB();
		1381	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1382	__DSB();
		1383	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1384	__DSB();
		1385	}
		1386	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1387	{
		1388	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1389	__DSB();
		1390	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1391	__DSB();
		1392	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1393	__DSB();
		1394	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1395	__DSB();
		1396	}
		1397	}
		1398	else /* (hnand->Config.PageSize) > 512 */
		1399	{
		1400	/* Send read spare area command sequence */
		1401	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
		1402	__DSB();
		1403
		1404	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1405	{
		1406	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
		1407	__DSB();
		1408	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
		1409	__DSB();
		1410	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1411	__DSB();
		1412	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1413	__DSB();
		1414	}
		1415	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1416	{
		1417	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
		1418	__DSB();
		1419	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
		1420	__DSB();
		1421	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1422	__DSB();
		1423	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1424	__DSB();
		1425	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1426	__DSB();
		1427	}
		1428	}
		1429
		1430	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
		1431	__DSB();
		1432
		1433	if (hnand->Config.ExtraCommandEnable == ENABLE)
		1434	{
		1435	/* Get tick */
		1436	tickstart = HAL_GetTick();
		1437
		1438	/* Read status until NAND is ready */
		1439	while (HAL_NAND_Read_Status(hnand) != NAND_READY)
		1440	{
		1441	if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
		1442	{
		1443	/* Update the NAND controller state */
		1444	hnand->State = HAL_NAND_STATE_ERROR;
		1445
		1446	/* Process unlocked */
		1447	__HAL_UNLOCK(hnand);
		1448
		1449	return HAL_TIMEOUT;
		1450	}
		1451	}
		1452
		1453	/* Go back to read mode */
		1454	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = ((uint8_t)0x00U);
		1455	__DSB();
		1456	}
		1457
		1458	/* Get Data into Buffer */
		1459	for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
		1460	{
		1461	buff = (uint16_t *)deviceAddress;
		1462	buff++;
		1463	}
		1464
		1465	/* Increment read spare areas number */
		1466	numSpareAreaRead++;
		1467
		1468	/* Decrement spare areas to read */
		1469	nbspare--;
		1470
		1471	/* Increment the NAND address */
		1472	nandAddress = (uint32_t)(nandAddress + 1U);
		1473	}
		1474
		1475	/* Update the NAND controller state */
		1476	hnand->State = HAL_NAND_STATE_READY;
		1477
		1478	/* Process unlocked */
		1479	__HAL_UNLOCK(hnand);
		1480	}
		1481	else
		1482	{
		1483	return HAL_ERROR;
		1484	}
		1485
		1486	return HAL_OK;
		1487	}
		1488
		1489	/**
		1490	* @brief Write Spare area(s) to NAND memory (8-bits addressing)
		1491	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		1492	* the configuration information for NAND module.
		1493	* @param pAddress pointer to NAND address structure
		1494	* @param pBuffer pointer to source buffer to write
		1495	* @param NumSpareAreaTowrite number of spare areas to write to block
		1496	* @retval HAL status
		1497	*/
		1498	HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
		1499	{
		1500	uint32_t index;
		1501	uint32_t tickstart;
		1502	uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
		1503	uint8_t * buff = pBuffer;
		1504
		1505	/* Check the NAND controller state */
		1506	if (hnand->State == HAL_NAND_STATE_BUSY)
		1507	{
		1508	return HAL_BUSY;
		1509	}
		1510	else if (hnand->State == HAL_NAND_STATE_READY)
		1511	{
		1512	/* Process Locked */
		1513	__HAL_LOCK(hnand);
		1514
		1515	/* Update the NAND controller state */
		1516	hnand->State = HAL_NAND_STATE_BUSY;
		1517
		1518	/* Identify the device address */
		1519	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		1520	{
		1521	deviceAddress = NAND_DEVICE1;
		1522	}
		1523	else
		1524	{
		1525	deviceAddress = NAND_DEVICE2;
		1526	}
		1527
		1528	/* Page address calculation */
		1529	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
		1530
		1531	/* Column in page address */
		1532	columnAddress = COLUMN_ADDRESS(hnand);
		1533
		1534	/* Spare area(s) write loop */
		1535	while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
		1536	{
		1537	/* Cards with page size <= 512 bytes */
		1538	if ((hnand->Config.PageSize) <= 512U)
		1539	{
		1540	/* Send write Spare area command sequence */
		1541	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_C;
		1542	__DSB();
		1543	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
		1544	__DSB();
		1545
		1546	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1547	{
		1548	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1549	__DSB();
		1550	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1551	__DSB();
		1552	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1553	__DSB();
		1554	}
		1555	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1556	{
		1557	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1558	__DSB();
		1559	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1560	__DSB();
		1561	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1562	__DSB();
		1563	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1564	__DSB();
		1565	}
		1566	}
		1567	else /* (hnand->Config.PageSize) > 512 */
		1568	{
		1569	/* Send write Spare area command sequence */
		1570	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
		1571	__DSB();
		1572	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
		1573	__DSB();
		1574
		1575	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1576	{
		1577	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
		1578	__DSB();
		1579	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
		1580	__DSB();
		1581	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1582	__DSB();
		1583	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1584	__DSB();
		1585	}
		1586	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1587	{
		1588	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
		1589	__DSB();
		1590	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
		1591	__DSB();
		1592	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1593	__DSB();
		1594	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1595	__DSB();
		1596	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1597	__DSB();
		1598	}
		1599	}
		1600
		1601	/* Write data to memory */
		1602	for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
		1603	{
		1604	(__IO uint8_t )deviceAddress = *buff;
		1605	buff++;
		1606	__DSB();
		1607	}
		1608
		1609	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
		1610	__DSB();
		1611
		1612	/* Get tick */
		1613	tickstart = HAL_GetTick();
		1614
		1615	/* Read status until NAND is ready */
		1616	while (HAL_NAND_Read_Status(hnand) != NAND_READY)
		1617	{
		1618	if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
		1619	{
		1620	/* Update the NAND controller state */
		1621	hnand->State = HAL_NAND_STATE_ERROR;
		1622
		1623	/* Process unlocked */
		1624	__HAL_UNLOCK(hnand);
		1625
		1626	return HAL_TIMEOUT;
		1627	}
		1628	}
		1629
		1630	/* Increment written spare areas number */
		1631	numSpareAreaWritten++;
		1632
		1633	/* Decrement spare areas to write */
		1634	nbspare--;
		1635
		1636	/* Increment the NAND address */
		1637	nandAddress = (uint32_t)(nandAddress + 1U);
		1638	}
		1639
		1640	/* Update the NAND controller state */
		1641	hnand->State = HAL_NAND_STATE_READY;
		1642
		1643	/* Process unlocked */
		1644	__HAL_UNLOCK(hnand);
		1645	}
		1646	else
		1647	{
		1648	return HAL_ERROR;
		1649	}
		1650
		1651	return HAL_OK;
		1652	}
		1653
		1654	/**
		1655	* @brief Write Spare area(s) to NAND memory (16-bits addressing)
		1656	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		1657	* the configuration information for NAND module.
		1658	* @param pAddress pointer to NAND address structure
		1659	* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
		1660	* @param NumSpareAreaTowrite number of spare areas to write to block
		1661	* @retval HAL status
		1662	*/
		1663	HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
		1664	{
		1665	uint32_t index;
		1666	uint32_t tickstart;
		1667	uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
		1668	uint16_t * buff = pBuffer;
		1669
		1670	/* Check the NAND controller state */
		1671	if (hnand->State == HAL_NAND_STATE_BUSY)
		1672	{
		1673	return HAL_BUSY;
		1674	}
		1675	else if (hnand->State == HAL_NAND_STATE_READY)
		1676	{
		1677	/* Process Locked */
		1678	__HAL_LOCK(hnand);
		1679
		1680	/* Update the NAND controller state */
		1681	hnand->State = HAL_NAND_STATE_BUSY;
		1682
		1683	/* Identify the device address */
		1684	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		1685	{
		1686	deviceAddress = NAND_DEVICE1;
		1687	}
		1688	else
		1689	{
		1690	deviceAddress = NAND_DEVICE2;
		1691	}
		1692
		1693	/* NAND raw address calculation */
		1694	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
		1695
		1696	/* Column in page address */
		1697	columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
		1698
		1699	/* Spare area(s) write loop */
		1700	while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
		1701	{
		1702	/* Cards with page size <= 512 bytes */
		1703	if ((hnand->Config.PageSize) <= 512U)
		1704	{
		1705	/* Send write Spare area command sequence */
		1706	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_C;
		1707	__DSB();
		1708	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
		1709	__DSB();
		1710
		1711	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1712	{
		1713	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1714	__DSB();
		1715	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1716	__DSB();
		1717	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1718	__DSB();
		1719	}
		1720	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1721	{
		1722	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00U;
		1723	__DSB();
		1724	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1725	__DSB();
		1726	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1727	__DSB();
		1728	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1729	__DSB();
		1730	}
		1731	}
		1732	else /* (hnand->Config.PageSize) > 512 */
		1733	{
		1734	/* Send write Spare area command sequence */
		1735	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
		1736	__DSB();
		1737	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
		1738	__DSB();
		1739
		1740	if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
		1741	{
		1742	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
		1743	__DSB();
		1744	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
		1745	__DSB();
		1746	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1747	__DSB();
		1748	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1749	__DSB();
		1750	}
		1751	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
		1752	{
		1753	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
		1754	__DSB();
		1755	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
		1756	__DSB();
		1757	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
		1758	__DSB();
		1759	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
		1760	__DSB();
		1761	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
		1762	__DSB();
		1763	}
		1764	}
		1765
		1766	/* Write data to memory */
		1767	for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
		1768	{
		1769	(__IO uint16_t )deviceAddress = *buff;
		1770	buff++;
		1771	__DSB();
		1772	}
		1773
		1774	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
		1775	__DSB();
		1776
		1777	/* Get tick */
		1778	tickstart = HAL_GetTick();
		1779
		1780	/* Read status until NAND is ready */
		1781	while (HAL_NAND_Read_Status(hnand) != NAND_READY)
		1782	{
		1783	if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
		1784	{
		1785	/* Update the NAND controller state */
		1786	hnand->State = HAL_NAND_STATE_ERROR;
		1787
		1788	/* Process unlocked */
		1789	__HAL_UNLOCK(hnand);
		1790
		1791	return HAL_TIMEOUT;
		1792	}
		1793	}
		1794
		1795	/* Increment written spare areas number */
		1796	numSpareAreaWritten++;
		1797
		1798	/* Decrement spare areas to write */
		1799	nbspare--;
		1800
		1801	/* Increment the NAND address */
		1802	nandAddress = (uint32_t)(nandAddress + 1U);
		1803	}
		1804
		1805	/* Update the NAND controller state */
		1806	hnand->State = HAL_NAND_STATE_READY;
		1807
		1808	/* Process unlocked */
		1809	__HAL_UNLOCK(hnand);
		1810	}
		1811	else
		1812	{
		1813	return HAL_ERROR;
		1814	}
		1815
		1816	return HAL_OK;
		1817	}
		1818
		1819	/**
		1820	* @brief NAND memory Block erase
		1821	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		1822	* the configuration information for NAND module.
		1823	* @param pAddress pointer to NAND address structure
		1824	* @retval HAL status
		1825	*/
		1826	HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress)
		1827	{
		1828	uint32_t DeviceAddress;
		1829
		1830	/* Check the NAND controller state */
		1831	if (hnand->State == HAL_NAND_STATE_BUSY)
		1832	{
		1833	return HAL_BUSY;
		1834	}
		1835	else if (hnand->State == HAL_NAND_STATE_READY)
		1836	{
		1837	/* Process Locked */
		1838	__HAL_LOCK(hnand);
		1839
		1840	/* Update the NAND controller state */
		1841	hnand->State = HAL_NAND_STATE_BUSY;
		1842
		1843	/* Identify the device address */
		1844	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		1845	{
		1846	DeviceAddress = NAND_DEVICE1;
		1847	}
		1848	else
		1849	{
		1850	DeviceAddress = NAND_DEVICE2;
		1851	}
		1852
		1853	/* Send Erase block command sequence */
		1854	(__IO uint8_t )((uint32_t)(DeviceAddress \| CMD_AREA)) = NAND_CMD_ERASE0;
		1855	__DSB();
		1856	(__IO uint8_t )((uint32_t)(DeviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
		1857	__DSB();
		1858	(__IO uint8_t )((uint32_t)(DeviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
		1859	__DSB();
		1860	(__IO uint8_t )((uint32_t)(DeviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
		1861	__DSB();
		1862
		1863	(__IO uint8_t )((uint32_t)(DeviceAddress \| CMD_AREA)) = NAND_CMD_ERASE1;
		1864	__DSB();
		1865
		1866	/* Update the NAND controller state */
		1867	hnand->State = HAL_NAND_STATE_READY;
		1868
		1869	/* Process unlocked */
		1870	__HAL_UNLOCK(hnand);
		1871	}
		1872	else
		1873	{
		1874	return HAL_ERROR;
		1875	}
		1876
		1877	return HAL_OK;
		1878	}
		1879
		1880	/**
		1881	* @brief Increment the NAND memory address
		1882	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		1883	* the configuration information for NAND module.
		1884	* @param pAddress pointer to NAND address structure
		1885	* @retval The new status of the increment address operation. It can be:
		1886	* - NAND_VALID_ADDRESS: When the new address is valid address
		1887	* - NAND_INVALID_ADDRESS: When the new address is invalid address
		1888	*/
		1889	uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress)
		1890	{
		1891	uint32_t status = NAND_VALID_ADDRESS;
		1892
		1893	/* Increment page address */
		1894	pAddress->Page++;
		1895
		1896	/* Check NAND address is valid */
		1897	if (pAddress->Page == hnand->Config.BlockSize)
		1898	{
		1899	pAddress->Page = 0;
		1900	pAddress->Block++;
		1901
		1902	if (pAddress->Block == hnand->Config.PlaneSize)
		1903	{
		1904	pAddress->Block = 0;
		1905	pAddress->Plane++;
		1906
		1907	if (pAddress->Plane == (hnand->Config.PlaneNbr))
		1908	{
		1909	status = NAND_INVALID_ADDRESS;
		1910	}
		1911	}
		1912	}
		1913
		1914	return (status);
		1915	}
		1916
		1917	#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
		1918	/**
		1919	* @brief Register a User NAND Callback
		1920	* To be used instead of the weak (surcharged) predefined callback
		1921	* @param hnand : NAND handle
		1922	* @param CallbackId : ID of the callback to be registered
		1923	* This parameter can be one of the following values:
		1924	* @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
		1925	* @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
		1926	* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
		1927	* @param pCallback : pointer to the Callback function
		1928	* @retval status
		1929	*/
		1930	HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
		1931	{
		1932	HAL_StatusTypeDef status = HAL_OK;
		1933
		1934	if(pCallback == NULL)
		1935	{
		1936	return HAL_ERROR;
		1937	}
		1938
		1939	/* Process locked */
		1940	__HAL_LOCK(hnand);
		1941
		1942	if(hnand->State == HAL_NAND_STATE_READY)
		1943	{
		1944	switch (CallbackId)
		1945	{
		1946	case HAL_NAND_MSP_INIT_CB_ID :
		1947	hnand->MspInitCallback = pCallback;
		1948	break;
		1949	case HAL_NAND_MSP_DEINIT_CB_ID :
		1950	hnand->MspDeInitCallback = pCallback;
		1951	break;
		1952	case HAL_NAND_IT_CB_ID :
		1953	hnand->ItCallback = pCallback;
		1954	break;
		1955	default :
		1956	/* update return status */
		1957	status = HAL_ERROR;
		1958	break;
		1959	}
		1960	}
		1961	else if(hnand->State == HAL_NAND_STATE_RESET)
		1962	{
		1963	switch (CallbackId)
		1964	{
		1965	case HAL_NAND_MSP_INIT_CB_ID :
		1966	hnand->MspInitCallback = pCallback;
		1967	break;
		1968	case HAL_NAND_MSP_DEINIT_CB_ID :
		1969	hnand->MspDeInitCallback = pCallback;
		1970	break;
		1971	default :
		1972	/* update return status */
		1973	status = HAL_ERROR;
		1974	break;
		1975	}
		1976	}
		1977	else
		1978	{
		1979	/* update return status */
		1980	status = HAL_ERROR;
		1981	}
		1982
		1983	/* Release Lock */
		1984	__HAL_UNLOCK(hnand);
		1985	return status;
		1986	}
		1987
		1988	/**
		1989	* @brief Unregister a User NAND Callback
		1990	* NAND Callback is redirected to the weak (surcharged) predefined callback
		1991	* @param hnand : NAND handle
		1992	* @param CallbackId : ID of the callback to be unregistered
		1993	* This parameter can be one of the following values:
		1994	* @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
		1995	* @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
		1996	* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
		1997	* @retval status
		1998	*/
		1999	HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
		2000	{
		2001	HAL_StatusTypeDef status = HAL_OK;
		2002
		2003	/* Process locked */
		2004	__HAL_LOCK(hnand);
		2005
		2006	if(hnand->State == HAL_NAND_STATE_READY)
		2007	{
		2008	switch (CallbackId)
		2009	{
		2010	case HAL_NAND_MSP_INIT_CB_ID :
		2011	hnand->MspInitCallback = HAL_NAND_MspInit;
		2012	break;
		2013	case HAL_NAND_MSP_DEINIT_CB_ID :
		2014	hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
		2015	break;
		2016	case HAL_NAND_IT_CB_ID :
		2017	hnand->ItCallback = HAL_NAND_ITCallback;
		2018	break;
		2019	default :
		2020	/* update return status */
		2021	status = HAL_ERROR;
		2022	break;
		2023	}
		2024	}
		2025	else if(hnand->State == HAL_NAND_STATE_RESET)
		2026	{
		2027	switch (CallbackId)
		2028	{
		2029	case HAL_NAND_MSP_INIT_CB_ID :
		2030	hnand->MspInitCallback = HAL_NAND_MspInit;
		2031	break;
		2032	case HAL_NAND_MSP_DEINIT_CB_ID :
		2033	hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
		2034	break;
		2035	default :
		2036	/* update return status */
		2037	status = HAL_ERROR;
		2038	break;
		2039	}
		2040	}
		2041	else
		2042	{
		2043	/* update return status */
		2044	status = HAL_ERROR;
		2045	}
		2046
		2047	/* Release Lock */
		2048	__HAL_UNLOCK(hnand);
		2049	return status;
		2050	}
		2051	#endif
		2052
		2053	/**
		2054	* @}
		2055	*/
		2056
		2057	/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
		2058	* @brief management functions
		2059	*
		2060	@verbatim
		2061	==============================================================================
		2062	##### NAND Control functions #####
		2063	==============================================================================
		2064	[..]
		2065	This subsection provides a set of functions allowing to control dynamically
		2066	the NAND interface.
		2067
		2068	@endverbatim
		2069	* @{
		2070	*/
		2071
		2072
		2073	/**
		2074	* @brief Enables dynamically NAND ECC feature.
		2075	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		2076	* the configuration information for NAND module.
		2077	* @retval HAL status
		2078	*/
		2079	HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
		2080	{
		2081	/* Check the NAND controller state */
		2082	if (hnand->State == HAL_NAND_STATE_BUSY)
		2083	{
		2084	return HAL_BUSY;
		2085	}
		2086	else if (hnand->State == HAL_NAND_STATE_READY)
		2087	{
		2088	/* Update the NAND state */
		2089	hnand->State = HAL_NAND_STATE_BUSY;
		2090
		2091	/* Enable ECC feature */
		2092	(void)FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
		2093
		2094	/* Update the NAND state */
		2095	hnand->State = HAL_NAND_STATE_READY;
		2096	}
		2097	else
		2098	{
		2099	return HAL_ERROR;
		2100	}
		2101
		2102	return HAL_OK;
		2103	}
		2104
		2105	/**
		2106	* @brief Disables dynamically FSMC_NAND ECC feature.
		2107	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		2108	* the configuration information for NAND module.
		2109	* @retval HAL status
		2110	*/
		2111	HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
		2112	{
		2113	/* Check the NAND controller state */
		2114	if (hnand->State == HAL_NAND_STATE_BUSY)
		2115	{
		2116	return HAL_BUSY;
		2117	}
		2118	else if (hnand->State == HAL_NAND_STATE_READY)
		2119	{
		2120	/* Update the NAND state */
		2121	hnand->State = HAL_NAND_STATE_BUSY;
		2122
		2123	/* Disable ECC feature */
		2124	(void)FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
		2125
		2126	/* Update the NAND state */
		2127	hnand->State = HAL_NAND_STATE_READY;
		2128	}
		2129	else
		2130	{
		2131	return HAL_ERROR;
		2132	}
		2133
		2134	return HAL_OK;
		2135	}
		2136
		2137	/**
		2138	* @brief Disables dynamically NAND ECC feature.
		2139	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		2140	* the configuration information for NAND module.
		2141	* @param ECCval pointer to ECC value
		2142	* @param Timeout maximum timeout to wait
		2143	* @retval HAL status
		2144	*/
		2145	HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef hnand, uint32_t ECCval, uint32_t Timeout)
		2146	{
		2147	HAL_StatusTypeDef status;
		2148
		2149	/* Check the NAND controller state */
		2150	if (hnand->State == HAL_NAND_STATE_BUSY)
		2151	{
		2152	return HAL_BUSY;
		2153	}
		2154	else if (hnand->State == HAL_NAND_STATE_READY)
		2155	{
		2156	/* Update the NAND state */
		2157	hnand->State = HAL_NAND_STATE_BUSY;
		2158
		2159	/* Get NAND ECC value */
		2160	status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
		2161
		2162	/* Update the NAND state */
		2163	hnand->State = HAL_NAND_STATE_READY;
		2164	}
		2165	else
		2166	{
		2167	return HAL_ERROR;
		2168	}
		2169
		2170	return status;
		2171	}
		2172
		2173	/**
		2174	* @}
		2175	*/
		2176
		2177
		2178	/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
		2179	* @brief Peripheral State functions
		2180	*
		2181	@verbatim
		2182	==============================================================================
		2183	##### NAND State functions #####
		2184	==============================================================================
		2185	[..]
		2186	This subsection permits to get in run-time the status of the NAND controller
		2187	and the data flow.
		2188
		2189	@endverbatim
		2190	* @{
		2191	*/
		2192
		2193	/**
		2194	* @brief return the NAND state
		2195	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		2196	* the configuration information for NAND module.
		2197	* @retval HAL state
		2198	*/
		2199	HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
		2200	{
		2201	return hnand->State;
		2202	}
		2203
		2204	/**
		2205	* @brief NAND memory read status
		2206	* @param hnand pointer to a NAND_HandleTypeDef structure that contains
		2207	* the configuration information for NAND module.
		2208	* @retval NAND status
		2209	*/
		2210	uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
		2211	{
		2212	uint32_t data;
		2213	uint32_t DeviceAddress;
		2214	UNUSED(hnand);
		2215
		2216	/* Identify the device address */
		2217	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
		2218	{
		2219	DeviceAddress = NAND_DEVICE1;
		2220	}
		2221	else
		2222	{
		2223	DeviceAddress = NAND_DEVICE2;
		2224	}
		2225
		2226	/* Send Read status operation command */
		2227	(__IO uint8_t )((uint32_t)(DeviceAddress \| CMD_AREA)) = NAND_CMD_STATUS;
		2228
		2229	/* Read status register data */
		2230	data = (__IO uint8_t )DeviceAddress;
		2231
		2232	/* Return the status */
		2233	if ((data & NAND_ERROR) == NAND_ERROR)
		2234	{
		2235	return NAND_ERROR;
		2236	}
		2237	else if ((data & NAND_READY) == NAND_READY)
		2238	{
		2239	return NAND_READY;
		2240	}
		2241	else
		2242	{
		2243	return NAND_BUSY;
		2244	}
		2245	}
		2246
		2247	/**
		2248	* @}
		2249	*/
		2250
		2251	/**
		2252	* @}
		2253	*/
		2254
		2255	/**
		2256	* @}
		2257	*/
		2258
		2259	#endif /* HAL_NAND_MODULE_ENABLED */
		2260
		2261	/**
		2262	* @}
		2263	*/
		2264
		2265	#endif /* FSMC_BANK3 */
		2266
		2267	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c – Rev 2