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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_iwdg.c
		4	* @author MCD Application Team
		5	* @brief IWDG HAL module driver.
		6	* This file provides firmware functions to manage the following
		7	* functionalities of the Independent Watchdog (IWDG) peripheral:
		8	* + Initialization and Start functions
		9	* + IO operation functions
		10	*
		11	@verbatim
		12	==============================================================================
		13	##### IWDG Generic features #####
		14	==============================================================================
		15	[..]
		16	(+) The IWDG can be started by either software or hardware (configurable
		17	through option byte).
		18
9	mjames	19	(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
		20	active even if the main clock fails.
2	mjames	21
9	mjames	22	(+) Once the IWDG is started, the LSI is forced ON and both cannot be
2	mjames	23	disabled. The counter starts counting down from the reset value (0xFFF).
		24	When it reaches the end of count value (0x000) a reset signal is
		25	generated (IWDG reset).
		26
		27	(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
9	mjames	28	the IWDG_RLR value is reloaded into the counter and the watchdog reset
		29	is prevented.
2	mjames	30
		31	(+) The IWDG is implemented in the VDD voltage domain that is still functional
9	mjames	32	in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
2	mjames	33	IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
		34	reset occurs.
		35
9	mjames	36	(+) Debug mode: When the microcontroller enters debug mode (core halted),
2	mjames	37	the IWDG counter either continues to work normally or stops, depending
		38	on DBG_IWDG_STOP configuration bit in DBG module, accessible through
9	mjames	39	__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
2	mjames	40
		41	[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
9	mjames	42	The IWDG timeout may vary due to LSI clock frequency dispersion.
		43	STM32F1xx devices provide the capability to measure the LSI clock
		44	frequency (LSI clock is internally connected to TIM5 CH4 input capture).
		45	The measured value can be used to have an IWDG timeout with an
		46	acceptable accuracy.
2	mjames	47
9	mjames	48	[..] Default timeout value (necessary for IWDG_SR status register update):
		49	Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
		50	This frequency being subject to variations as mentioned above, the
		51	default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
		52	below) may become too short or too long.
		53	In such cases, this default timeout value can be tuned by redefining
		54	the constant LSI_VALUE at user-application level (based, for instance,
		55	on the measured LSI clock frequency as explained above).
		56
2	mjames	57	##### How to use this driver #####
		58	==============================================================================
		59	[..]
		60	(#) Use IWDG using HAL_IWDG_Init() function to :
		61	(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
9	mjames	62	clock is forced ON and IWDG counter starts counting down.
		63	(++) Enable write access to configuration registers:
		64	IWDG_PR and IWDG_RLR.
2	mjames	65	(++) Configure the IWDG prescaler and counter reload value. This reload
		66	value will be loaded in the IWDG counter each time the watchdog is
		67	reloaded, then the IWDG will start counting down from this value.
9	mjames	68	(++) Wait for status flags to be reset.
2	mjames	69
		70	(#) Then the application program must refresh the IWDG counter at regular
		71	intervals during normal operation to prevent an MCU reset, using
		72	HAL_IWDG_Refresh() function.
		73
		74	* IWDG HAL driver macros list *
		75	====================================
		76	[..]
		77	Below the list of most used macros in IWDG HAL driver:
		78	(+) __HAL_IWDG_START: Enable the IWDG peripheral
		79	(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
		80	the reload register
		81
		82	@endverbatim
		83	******************************************************************************
		84	* @attention
		85	*
9	mjames	86	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		87	* All rights reserved.</center></h2>
2	mjames	88	*
9	mjames	89	* This software component is licensed by ST under BSD 3-Clause license,
		90	* the "License"; You may not use this file except in compliance with the
		91	* License. You may obtain a copy of the License at:
		92	* opensource.org/licenses/BSD-3-Clause
2	mjames	93	*
		94	******************************************************************************
		95	*/
		96
		97	/* Includes ------------------------------------------------------------------*/
		98	#include "stm32f1xx_hal.h"
		99
		100	/** @addtogroup STM32F1xx_HAL_Driver
		101	* @{
		102	*/
		103
		104	#ifdef HAL_IWDG_MODULE_ENABLED
9	mjames	105	/** @addtogroup IWDG
2	mjames	106	* @brief IWDG HAL module driver.
		107	* @{
		108	*/
		109
		110	/* Private typedef -----------------------------------------------------------*/
		111	/* Private define ------------------------------------------------------------*/
		112	/** @defgroup IWDG_Private_Defines IWDG Private Defines
		113	* @{
		114	*/
9	mjames	115	/* Status register needs up to 5 LSI clock periods divided by the clock
		116	prescaler to be updated. The number of LSI clock periods is upper-rounded to
		117	6 for the timeout value calculation.
		118	The timeout value is also calculated using the highest prescaler (256) and
		119	the LSI_VALUE constant. The value of this constant can be changed by the user
		120	to take into account possible LSI clock period variations.
		121	The timeout value is multiplied by 1000 to be converted in milliseconds. */
		122	#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
2	mjames	123	/**
		124	* @}
		125	*/
		126
		127	/* Private macro -------------------------------------------------------------*/
		128	/* Private variables ---------------------------------------------------------*/
		129	/* Private function prototypes -----------------------------------------------*/
		130	/* Exported functions --------------------------------------------------------*/
		131
		132	/** @addtogroup IWDG_Exported_Functions
		133	* @{
		134	*/
		135
		136	/** @addtogroup IWDG_Exported_Functions_Group1
		137	* @brief Initialization and Start functions.
		138	*
		139	@verbatim
		140	===============================================================================
		141	##### Initialization and Start functions #####
		142	===============================================================================
		143	[..] This section provides functions allowing to:
		144	(+) Initialize the IWDG according to the specified parameters in the
		145	IWDG_InitTypeDef of associated handle.
		146	(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
		147	is reloaded in order to exit function with correct time base.
		148
		149	@endverbatim
		150	* @{
		151	*/
		152
		153	/**
		154	* @brief Initialize the IWDG according to the specified parameters in the
		155	* IWDG_InitTypeDef and start watchdog. Before exiting function,
		156	* watchdog is refreshed in order to have correct time base.
		157	* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
		158	* the configuration information for the specified IWDG module.
		159	* @retval HAL status
		160	*/
		161	HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
		162	{
		163	uint32_t tickstart;
		164
		165	/* Check the IWDG handle allocation */
		166	if (hiwdg == NULL)
		167	{
		168	return HAL_ERROR;
		169	}
		170
		171	/* Check the parameters */
		172	assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
		173	assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
		174	assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
		175
9	mjames	176	/* Enable IWDG. LSI is turned on automatically */
2	mjames	177	__HAL_IWDG_START(hiwdg);
		178
9	mjames	179	/* Enable write access to IWDG_PR and IWDG_RLR registers by writing
		180	0x5555 in KR */
2	mjames	181	IWDG_ENABLE_WRITE_ACCESS(hiwdg);
		182
		183	/* Write to IWDG registers the Prescaler & Reload values to work with */
		184	hiwdg->Instance->PR = hiwdg->Init.Prescaler;
		185	hiwdg->Instance->RLR = hiwdg->Init.Reload;
		186
		187	/* Check pending flag, if previous update not done, return timeout */
		188	tickstart = HAL_GetTick();
		189
		190	/* Wait for register to be updated */
9	mjames	191	while (hiwdg->Instance->SR != 0x00u)
2	mjames	192	{
		193	if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
		194	{
		195	return HAL_TIMEOUT;
		196	}
		197	}
		198
		199	/* Reload IWDG counter with value defined in the reload register */
		200	__HAL_IWDG_RELOAD_COUNTER(hiwdg);
		201
		202	/* Return function status */
		203	return HAL_OK;
		204	}
		205
		206	/**
		207	* @}
		208	*/
		209
9	mjames	210
2	mjames	211	/** @addtogroup IWDG_Exported_Functions_Group2
		212	* @brief IO operation functions
		213	*
		214	@verbatim
		215	===============================================================================
		216	##### IO operation functions #####
		217	===============================================================================
		218	[..] This section provides functions allowing to:
		219	(+) Refresh the IWDG.
		220
		221	@endverbatim
		222	* @{
		223	*/
		224
9	mjames	225
2	mjames	226	/**
		227	* @brief Refresh the IWDG.
		228	* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
		229	* the configuration information for the specified IWDG module.
		230	* @retval HAL status
		231	*/
		232	HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
		233	{
		234	/* Reload IWDG counter with value defined in the reload register */
		235	__HAL_IWDG_RELOAD_COUNTER(hiwdg);
		236
		237	/* Return function status */
		238	return HAL_OK;
		239	}
		240
		241	/**
		242	* @}
		243	*/
		244
		245	/**
		246	* @}
		247	*/
		248
		249	#endif /* HAL_IWDG_MODULE_ENABLED */
		250	/**
		251	* @}
		252	*/
		253
		254	/**
		255	* @}
		256	*/
		257
		258	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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