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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f1xx_hal_i2s.c |
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4 | * @author MCD Application Team |
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5 | * @brief I2S HAL module driver. |
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6 | * This file provides firmware functions to manage the following |
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7 | * functionalities of the Integrated Interchip Sound (I2S) peripheral: |
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8 | * + Initialization and de-initialization functions |
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9 | * + IO operation functions |
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10 | * + Peripheral State and Errors functions |
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11 | @verbatim |
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12 | =============================================================================== |
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13 | ##### How to use this driver ##### |
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14 | =============================================================================== |
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15 | [..] |
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16 | The I2S HAL driver can be used as follow: |
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17 | |||
18 | (#) Declare a I2S_HandleTypeDef handle structure. |
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19 | (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: |
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20 | (##) Enable the SPIx interface clock. |
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21 | (##) I2S pins configuration: |
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22 | (+++) Enable the clock for the I2S GPIOs. |
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23 | (+++) Configure these I2S pins as alternate function pull-up. |
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24 | (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() |
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25 | and HAL_I2S_Receive_IT() APIs). |
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26 | (+++) Configure the I2Sx interrupt priority. |
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27 | (+++) Enable the NVIC I2S IRQ handle. |
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28 | (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() |
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29 | and HAL_I2S_Receive_DMA() APIs: |
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30 | (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel. |
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31 | (+++) Enable the DMAx interface clock. |
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32 | (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. |
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33 | (+++) Configure the DMA Tx/Rx Stream/Channel. |
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34 | (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. |
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35 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the |
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36 | DMA Tx/Rx Stream/Channel. |
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37 | |||
38 | (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity |
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39 | using HAL_I2S_Init() function. |
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40 | |||
41 | -@- The specific I2S interrupts (Transmission complete interrupt, |
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42 | RXNE interrupt and Error Interrupts) will be managed using the macros |
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43 | __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. |
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44 | -@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock). |
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45 | For connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO (2 x PLL3CLK) clock |
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46 | in order to achieve the maximum accuracy. |
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47 | -@- Make sure that either: |
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48 | (+@) External clock source is configured after setting correctly |
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49 | the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file. |
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50 | |||
51 | (#) Three mode of operations are available within this driver : |
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52 | |||
53 | *** Polling mode IO operation *** |
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54 | ================================= |
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55 | [..] |
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56 | (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() |
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57 | (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() |
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58 | |||
59 | *** Interrupt mode IO operation *** |
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60 | =================================== |
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61 | [..] |
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62 | (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() |
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63 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
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64 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
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65 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
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66 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
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67 | (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() |
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68 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
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69 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
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70 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
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71 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
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72 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
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73 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
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74 | |||
75 | *** DMA mode IO operation *** |
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76 | ============================== |
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77 | [..] |
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78 | (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() |
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79 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
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80 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
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81 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
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82 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
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83 | (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() |
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84 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
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85 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
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86 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
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87 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
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88 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
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89 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
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90 | (+) Pause the DMA Transfer using HAL_I2S_DMAPause() |
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91 | (+) Resume the DMA Transfer using HAL_I2S_DMAResume() |
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92 | (+) Stop the DMA Transfer using HAL_I2S_DMAStop() |
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93 | |||
94 | *** I2S HAL driver macros list *** |
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95 | =================================== |
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96 | [..] |
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97 | Below the list of most used macros in I2S HAL driver. |
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98 | |||
99 | (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) |
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100 | (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) |
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101 | (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts |
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102 | (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts |
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103 | (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not |
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104 | |||
105 | [..] |
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106 | (@) You can refer to the I2S HAL driver header file for more useful macros |
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107 | |||
108 | *** I2S HAL driver macros list *** |
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109 | =================================== |
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110 | [..] |
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111 | Callback registration: |
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112 | |||
113 | (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U |
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114 | allows the user to configure dynamically the driver callbacks. |
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115 | Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback. |
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116 | |||
117 | Function HAL_I2S_RegisterCallback() allows to register following callbacks: |
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118 | (++) TxCpltCallback : I2S Tx Completed callback |
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119 | (++) RxCpltCallback : I2S Rx Completed callback |
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120 | (++) TxHalfCpltCallback : I2S Tx Half Completed callback |
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121 | (++) RxHalfCpltCallback : I2S Rx Half Completed callback |
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122 | (++) ErrorCallback : I2S Error callback |
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123 | (++) MspInitCallback : I2S Msp Init callback |
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124 | (++) MspDeInitCallback : I2S Msp DeInit callback |
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125 | This function takes as parameters the HAL peripheral handle, the Callback ID |
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126 | and a pointer to the user callback function. |
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127 | |||
128 | |||
129 | (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default |
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130 | weak function. |
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131 | HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle, |
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132 | and the Callback ID. |
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133 | This function allows to reset following callbacks: |
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134 | (++) TxCpltCallback : I2S Tx Completed callback |
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135 | (++) RxCpltCallback : I2S Rx Completed callback |
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136 | (++) TxHalfCpltCallback : I2S Tx Half Completed callback |
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137 | (++) RxHalfCpltCallback : I2S Rx Half Completed callback |
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138 | (++) ErrorCallback : I2S Error callback |
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139 | (++) MspInitCallback : I2S Msp Init callback |
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140 | (++) MspDeInitCallback : I2S Msp DeInit callback |
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141 | |||
142 | [..] |
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143 | By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET |
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144 | all callbacks are set to the corresponding weak functions: |
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145 | examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback(). |
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146 | Exception done for MspInit and MspDeInit functions that are |
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147 | reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when |
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148 | these callbacks are null (not registered beforehand). |
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149 | If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit() |
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150 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
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151 | |||
152 | [..] |
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153 | Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only. |
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154 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
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155 | in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state, |
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156 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
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157 | Then, the user first registers the MspInit/MspDeInit user callbacks |
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158 | using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit() |
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159 | or HAL_I2S_Init() function. |
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160 | |||
161 | [..] |
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162 | When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or |
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163 | not defined, the callback registering feature is not available |
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164 | and weak (surcharged) callbacks are used. |
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165 | |||
166 | *** I2S Workarounds linked to Silicon Limitation *** |
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167 | ==================================================== |
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168 | [..] |
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169 | (@) Only the 16-bit mode with no data extension can be used when the I2S |
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170 | is in Master and used the PCM long synchronization mode. |
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171 | |||
172 | @endverbatim |
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173 | ****************************************************************************** |
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174 | * @attention |
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175 | * |
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176 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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177 | * All rights reserved.</center></h2> |
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178 | * |
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179 | * This software component is licensed by ST under BSD 3-Clause license, |
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180 | * the "License"; You may not use this file except in compliance with the |
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181 | * License. You may obtain a copy of the License at: |
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182 | * opensource.org/licenses/BSD-3-Clause |
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183 | * |
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184 | ****************************************************************************** |
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185 | */ |
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186 | |||
187 | /* Includes ------------------------------------------------------------------*/ |
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188 | #include "stm32f1xx_hal.h" |
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189 | |||
190 | #ifdef HAL_I2S_MODULE_ENABLED |
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191 | |||
192 | #if defined(SPI_I2S_SUPPORT) |
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193 | /** @addtogroup STM32F1xx_HAL_Driver |
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194 | * @{ |
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195 | */ |
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196 | |||
197 | /** @defgroup I2S I2S |
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198 | * @brief I2S HAL module driver |
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199 | * @{ |
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200 | */ |
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201 | |||
202 | /* Private typedef -----------------------------------------------------------*/ |
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203 | /* Private define ------------------------------------------------------------*/ |
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204 | /* Private macro -------------------------------------------------------------*/ |
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205 | /* Private variables ---------------------------------------------------------*/ |
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206 | /* Private function prototypes -----------------------------------------------*/ |
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207 | /** @defgroup I2S_Private_Functions I2S Private Functions |
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208 | * @{ |
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209 | */ |
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210 | static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); |
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211 | static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); |
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212 | static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); |
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213 | static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); |
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214 | static void I2S_DMAError(DMA_HandleTypeDef *hdma); |
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215 | static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); |
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216 | static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); |
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217 | static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, |
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218 | uint32_t Timeout); |
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219 | /** |
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220 | * @} |
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221 | */ |
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222 | |||
223 | /* Exported functions ---------------------------------------------------------*/ |
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224 | |||
225 | /** @defgroup I2S_Exported_Functions I2S Exported Functions |
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226 | * @{ |
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227 | */ |
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228 | |||
229 | /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions |
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230 | * @brief Initialization and Configuration functions |
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231 | * |
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232 | @verbatim |
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233 | =============================================================================== |
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234 | ##### Initialization and de-initialization functions ##### |
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235 | =============================================================================== |
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236 | [..] This subsection provides a set of functions allowing to initialize and |
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237 | de-initialize the I2Sx peripheral in simplex mode: |
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238 | |||
239 | (+) User must Implement HAL_I2S_MspInit() function in which he configures |
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240 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). |
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241 | |||
242 | (+) Call the function HAL_I2S_Init() to configure the selected device with |
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243 | the selected configuration: |
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244 | (++) Mode |
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245 | (++) Standard |
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246 | (++) Data Format |
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247 | (++) MCLK Output |
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248 | (++) Audio frequency |
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249 | (++) Polarity |
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250 | |||
251 | (+) Call the function HAL_I2S_DeInit() to restore the default configuration |
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252 | of the selected I2Sx peripheral. |
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253 | @endverbatim |
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254 | * @{ |
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255 | */ |
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256 | |||
257 | /** |
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258 | * @brief Initializes the I2S according to the specified parameters |
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259 | * in the I2S_InitTypeDef and create the associated handle. |
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260 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
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261 | * the configuration information for I2S module |
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262 | * @retval HAL status |
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263 | */ |
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264 | HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) |
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265 | { |
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266 | uint32_t i2sdiv; |
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267 | uint32_t i2sodd; |
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268 | uint32_t packetlength; |
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269 | uint32_t tmp; |
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270 | uint32_t i2sclk; |
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271 | |||
272 | /* Check the I2S handle allocation */ |
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273 | if (hi2s == NULL) |
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274 | { |
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275 | return HAL_ERROR; |
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276 | } |
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277 | |||
278 | /* Check the I2S parameters */ |
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279 | assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); |
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280 | assert_param(IS_I2S_MODE(hi2s->Init.Mode)); |
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281 | assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); |
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282 | assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); |
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283 | assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); |
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284 | assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); |
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285 | assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); |
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286 | |||
287 | if (hi2s->State == HAL_I2S_STATE_RESET) |
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288 | { |
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289 | /* Allocate lock resource and initialize it */ |
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290 | hi2s->Lock = HAL_UNLOCKED; |
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291 | |||
292 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
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293 | /* Init the I2S Callback settings */ |
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294 | hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ |
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295 | hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ |
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296 | hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ |
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297 | hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ |
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298 | hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ |
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299 | |||
300 | if (hi2s->MspInitCallback == NULL) |
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301 | { |
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302 | hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ |
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303 | } |
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304 | |||
305 | /* Init the low level hardware : GPIO, CLOCK, NVIC... */ |
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306 | hi2s->MspInitCallback(hi2s); |
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307 | #else |
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308 | /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ |
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309 | HAL_I2S_MspInit(hi2s); |
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310 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
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311 | } |
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312 | |||
313 | hi2s->State = HAL_I2S_STATE_BUSY; |
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314 | |||
315 | /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ |
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316 | /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ |
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317 | CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ |
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318 | SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ |
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319 | SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); |
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320 | hi2s->Instance->I2SPR = 0x0002U; |
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321 | |||
322 | /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/ |
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323 | /* If the requested audio frequency is not the default, compute the prescaler */ |
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324 | if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) |
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325 | { |
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326 | /* Check the frame length (For the Prescaler computing) ********************/ |
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327 | if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) |
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328 | { |
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329 | /* Packet length is 16 bits */ |
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330 | packetlength = 16U; |
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331 | } |
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332 | else |
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333 | { |
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334 | /* Packet length is 32 bits */ |
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335 | packetlength = 32U; |
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336 | } |
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337 | |||
338 | /* I2S standard */ |
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339 | if (hi2s->Init.Standard <= I2S_STANDARD_LSB) |
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340 | { |
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341 | /* In I2S standard packet lenght is multiplied by 2 */ |
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342 | packetlength = packetlength * 2U; |
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343 | } |
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344 | |||
345 | /* Get the source clock value **********************************************/ |
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346 | if (hi2s->Instance == SPI2) |
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347 | { |
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348 | /* Get the source clock value: based on SPI2 Instance */ |
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349 | i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S2); |
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350 | } |
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351 | else if (hi2s->Instance == SPI3) |
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352 | { |
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353 | /* Get the source clock value: based on SPI3 Instance */ |
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354 | i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S3); |
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355 | } |
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356 | else |
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357 | { |
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358 | /* Get the source clock value: based on System Clock value */ |
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359 | i2sclk = HAL_RCC_GetSysClockFreq(); |
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360 | } |
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361 | /* Compute the Real divider depending on the MCLK output state, with a floating point */ |
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362 | if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) |
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363 | { |
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364 | /* MCLK output is enabled */ |
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365 | if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) |
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366 | { |
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367 | tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); |
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368 | } |
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369 | else |
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370 | { |
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371 | tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); |
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372 | } |
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373 | } |
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374 | else |
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375 | { |
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376 | /* MCLK output is disabled */ |
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377 | tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U); |
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378 | } |
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379 | |||
380 | /* Remove the flatting point */ |
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381 | tmp = tmp / 10U; |
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382 | |||
383 | /* Check the parity of the divider */ |
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384 | i2sodd = (uint32_t)(tmp & (uint32_t)1U); |
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385 | |||
386 | /* Compute the i2sdiv prescaler */ |
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387 | i2sdiv = (uint32_t)((tmp - i2sodd) / 2U); |
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388 | |||
389 | /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ |
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390 | i2sodd = (uint32_t)(i2sodd << 8U); |
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391 | } |
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392 | else |
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393 | { |
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394 | /* Set the default values */ |
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395 | i2sdiv = 2U; |
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396 | i2sodd = 0U; |
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397 | } |
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398 | |||
399 | /* Test if the divider is 1 or 0 or greater than 0xFF */ |
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400 | if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) |
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401 | { |
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402 | /* Set the error code and execute error callback*/ |
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403 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); |
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404 | return HAL_ERROR; |
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405 | } |
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406 | |||
407 | /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ |
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408 | |||
409 | /* Write to SPIx I2SPR register the computed value */ |
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410 | hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); |
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411 | |||
412 | /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ |
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413 | /* And configure the I2S with the I2S_InitStruct values */ |
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414 | MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ |
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415 | SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ |
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416 | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ |
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417 | SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \ |
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418 | (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \ |
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419 | hi2s->Init.Standard | hi2s->Init.DataFormat | \ |
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420 | hi2s->Init.CPOL)); |
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421 | |||
422 | #if defined(SPI_I2SCFGR_ASTRTEN) |
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423 | if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))) |
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424 | { |
||
425 | /* Write to SPIx I2SCFGR */ |
||
426 | SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN); |
||
427 | } |
||
428 | #endif /* SPI_I2SCFGR_ASTRTEN */ |
||
429 | |||
430 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
||
431 | hi2s->State = HAL_I2S_STATE_READY; |
||
432 | |||
433 | return HAL_OK; |
||
434 | } |
||
435 | |||
436 | /** |
||
437 | * @brief DeInitializes the I2S peripheral |
||
438 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
439 | * the configuration information for I2S module |
||
440 | * @retval HAL status |
||
441 | */ |
||
442 | HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) |
||
443 | { |
||
444 | /* Check the I2S handle allocation */ |
||
445 | if (hi2s == NULL) |
||
446 | { |
||
447 | return HAL_ERROR; |
||
448 | } |
||
449 | |||
450 | /* Check the parameters */ |
||
451 | assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); |
||
452 | |||
453 | hi2s->State = HAL_I2S_STATE_BUSY; |
||
454 | |||
455 | /* Disable the I2S Peripheral Clock */ |
||
456 | __HAL_I2S_DISABLE(hi2s); |
||
457 | |||
458 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
459 | if (hi2s->MspDeInitCallback == NULL) |
||
460 | { |
||
461 | hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ |
||
462 | } |
||
463 | |||
464 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ |
||
465 | hi2s->MspDeInitCallback(hi2s); |
||
466 | #else |
||
467 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ |
||
468 | HAL_I2S_MspDeInit(hi2s); |
||
469 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
470 | |||
471 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
||
472 | hi2s->State = HAL_I2S_STATE_RESET; |
||
473 | |||
474 | /* Release Lock */ |
||
475 | __HAL_UNLOCK(hi2s); |
||
476 | |||
477 | return HAL_OK; |
||
478 | } |
||
479 | |||
480 | /** |
||
481 | * @brief I2S MSP Init |
||
482 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
483 | * the configuration information for I2S module |
||
484 | * @retval None |
||
485 | */ |
||
486 | __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) |
||
487 | { |
||
488 | /* Prevent unused argument(s) compilation warning */ |
||
489 | UNUSED(hi2s); |
||
490 | |||
491 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
492 | the HAL_I2S_MspInit could be implemented in the user file |
||
493 | */ |
||
494 | } |
||
495 | |||
496 | /** |
||
497 | * @brief I2S MSP DeInit |
||
498 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
499 | * the configuration information for I2S module |
||
500 | * @retval None |
||
501 | */ |
||
502 | __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) |
||
503 | { |
||
504 | /* Prevent unused argument(s) compilation warning */ |
||
505 | UNUSED(hi2s); |
||
506 | |||
507 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
508 | the HAL_I2S_MspDeInit could be implemented in the user file |
||
509 | */ |
||
510 | } |
||
511 | |||
512 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
513 | /** |
||
514 | * @brief Register a User I2S Callback |
||
515 | * To be used instead of the weak predefined callback |
||
516 | * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains |
||
517 | * the configuration information for the specified I2S. |
||
518 | * @param CallbackID ID of the callback to be registered |
||
519 | * @param pCallback pointer to the Callback function |
||
520 | * @retval HAL status |
||
521 | */ |
||
522 | HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, |
||
523 | pI2S_CallbackTypeDef pCallback) |
||
524 | { |
||
525 | HAL_StatusTypeDef status = HAL_OK; |
||
526 | |||
527 | if (pCallback == NULL) |
||
528 | { |
||
529 | /* Update the error code */ |
||
530 | hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK; |
||
531 | |||
532 | return HAL_ERROR; |
||
533 | } |
||
534 | /* Process locked */ |
||
535 | __HAL_LOCK(hi2s); |
||
536 | |||
537 | if (HAL_I2S_STATE_READY == hi2s->State) |
||
538 | { |
||
539 | switch (CallbackID) |
||
540 | { |
||
541 | case HAL_I2S_TX_COMPLETE_CB_ID : |
||
542 | hi2s->TxCpltCallback = pCallback; |
||
543 | break; |
||
544 | |||
545 | case HAL_I2S_RX_COMPLETE_CB_ID : |
||
546 | hi2s->RxCpltCallback = pCallback; |
||
547 | break; |
||
548 | |||
549 | case HAL_I2S_TX_HALF_COMPLETE_CB_ID : |
||
550 | hi2s->TxHalfCpltCallback = pCallback; |
||
551 | break; |
||
552 | |||
553 | case HAL_I2S_RX_HALF_COMPLETE_CB_ID : |
||
554 | hi2s->RxHalfCpltCallback = pCallback; |
||
555 | break; |
||
556 | |||
557 | case HAL_I2S_ERROR_CB_ID : |
||
558 | hi2s->ErrorCallback = pCallback; |
||
559 | break; |
||
560 | |||
561 | case HAL_I2S_MSPINIT_CB_ID : |
||
562 | hi2s->MspInitCallback = pCallback; |
||
563 | break; |
||
564 | |||
565 | case HAL_I2S_MSPDEINIT_CB_ID : |
||
566 | hi2s->MspDeInitCallback = pCallback; |
||
567 | break; |
||
568 | |||
569 | default : |
||
570 | /* Update the error code */ |
||
571 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); |
||
572 | |||
573 | /* Return error status */ |
||
574 | status = HAL_ERROR; |
||
575 | break; |
||
576 | } |
||
577 | } |
||
578 | else if (HAL_I2S_STATE_RESET == hi2s->State) |
||
579 | { |
||
580 | switch (CallbackID) |
||
581 | { |
||
582 | case HAL_I2S_MSPINIT_CB_ID : |
||
583 | hi2s->MspInitCallback = pCallback; |
||
584 | break; |
||
585 | |||
586 | case HAL_I2S_MSPDEINIT_CB_ID : |
||
587 | hi2s->MspDeInitCallback = pCallback; |
||
588 | break; |
||
589 | |||
590 | default : |
||
591 | /* Update the error code */ |
||
592 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); |
||
593 | |||
594 | /* Return error status */ |
||
595 | status = HAL_ERROR; |
||
596 | break; |
||
597 | } |
||
598 | } |
||
599 | else |
||
600 | { |
||
601 | /* Update the error code */ |
||
602 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); |
||
603 | |||
604 | /* Return error status */ |
||
605 | status = HAL_ERROR; |
||
606 | } |
||
607 | |||
608 | /* Release Lock */ |
||
609 | __HAL_UNLOCK(hi2s); |
||
610 | return status; |
||
611 | } |
||
612 | |||
613 | /** |
||
614 | * @brief Unregister an I2S Callback |
||
615 | * I2S callback is redirected to the weak predefined callback |
||
616 | * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains |
||
617 | * the configuration information for the specified I2S. |
||
618 | * @param CallbackID ID of the callback to be unregistered |
||
619 | * @retval HAL status |
||
620 | */ |
||
621 | HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID) |
||
622 | { |
||
623 | HAL_StatusTypeDef status = HAL_OK; |
||
624 | |||
625 | /* Process locked */ |
||
626 | __HAL_LOCK(hi2s); |
||
627 | |||
628 | if (HAL_I2S_STATE_READY == hi2s->State) |
||
629 | { |
||
630 | switch (CallbackID) |
||
631 | { |
||
632 | case HAL_I2S_TX_COMPLETE_CB_ID : |
||
633 | hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ |
||
634 | break; |
||
635 | |||
636 | case HAL_I2S_RX_COMPLETE_CB_ID : |
||
637 | hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ |
||
638 | break; |
||
639 | |||
640 | case HAL_I2S_TX_HALF_COMPLETE_CB_ID : |
||
641 | hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ |
||
642 | break; |
||
643 | |||
644 | case HAL_I2S_RX_HALF_COMPLETE_CB_ID : |
||
645 | hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ |
||
646 | break; |
||
647 | |||
648 | case HAL_I2S_ERROR_CB_ID : |
||
649 | hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ |
||
650 | break; |
||
651 | |||
652 | case HAL_I2S_MSPINIT_CB_ID : |
||
653 | hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ |
||
654 | break; |
||
655 | |||
656 | case HAL_I2S_MSPDEINIT_CB_ID : |
||
657 | hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ |
||
658 | break; |
||
659 | |||
660 | default : |
||
661 | /* Update the error code */ |
||
662 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); |
||
663 | |||
664 | /* Return error status */ |
||
665 | status = HAL_ERROR; |
||
666 | break; |
||
667 | } |
||
668 | } |
||
669 | else if (HAL_I2S_STATE_RESET == hi2s->State) |
||
670 | { |
||
671 | switch (CallbackID) |
||
672 | { |
||
673 | case HAL_I2S_MSPINIT_CB_ID : |
||
674 | hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ |
||
675 | break; |
||
676 | |||
677 | case HAL_I2S_MSPDEINIT_CB_ID : |
||
678 | hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ |
||
679 | break; |
||
680 | |||
681 | default : |
||
682 | /* Update the error code */ |
||
683 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); |
||
684 | |||
685 | /* Return error status */ |
||
686 | status = HAL_ERROR; |
||
687 | break; |
||
688 | } |
||
689 | } |
||
690 | else |
||
691 | { |
||
692 | /* Update the error code */ |
||
693 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); |
||
694 | |||
695 | /* Return error status */ |
||
696 | status = HAL_ERROR; |
||
697 | } |
||
698 | |||
699 | /* Release Lock */ |
||
700 | __HAL_UNLOCK(hi2s); |
||
701 | return status; |
||
702 | } |
||
703 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
704 | /** |
||
705 | * @} |
||
706 | */ |
||
707 | |||
708 | /** @defgroup I2S_Exported_Functions_Group2 IO operation functions |
||
709 | * @brief Data transfers functions |
||
710 | * |
||
711 | @verbatim |
||
712 | =============================================================================== |
||
713 | ##### IO operation functions ##### |
||
714 | =============================================================================== |
||
715 | [..] |
||
716 | This subsection provides a set of functions allowing to manage the I2S data |
||
717 | transfers. |
||
718 | |||
719 | (#) There are two modes of transfer: |
||
720 | (++) Blocking mode : The communication is performed in the polling mode. |
||
721 | The status of all data processing is returned by the same function |
||
722 | after finishing transfer. |
||
723 | (++) No-Blocking mode : The communication is performed using Interrupts |
||
724 | or DMA. These functions return the status of the transfer startup. |
||
725 | The end of the data processing will be indicated through the |
||
726 | dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when |
||
727 | using DMA mode. |
||
728 | |||
729 | (#) Blocking mode functions are : |
||
730 | (++) HAL_I2S_Transmit() |
||
731 | (++) HAL_I2S_Receive() |
||
732 | |||
733 | (#) No-Blocking mode functions with Interrupt are : |
||
734 | (++) HAL_I2S_Transmit_IT() |
||
735 | (++) HAL_I2S_Receive_IT() |
||
736 | |||
737 | (#) No-Blocking mode functions with DMA are : |
||
738 | (++) HAL_I2S_Transmit_DMA() |
||
739 | (++) HAL_I2S_Receive_DMA() |
||
740 | |||
741 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
||
742 | (++) HAL_I2S_TxCpltCallback() |
||
743 | (++) HAL_I2S_RxCpltCallback() |
||
744 | (++) HAL_I2S_ErrorCallback() |
||
745 | |||
746 | @endverbatim |
||
747 | * @{ |
||
748 | */ |
||
749 | |||
750 | /** |
||
751 | * @brief Transmit an amount of data in blocking mode |
||
752 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
753 | * the configuration information for I2S module |
||
754 | * @param pData a 16-bit pointer to data buffer. |
||
755 | * @param Size number of data sample to be sent: |
||
756 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
||
757 | * configuration phase, the Size parameter means the number of 16-bit data length |
||
758 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
||
759 | * the Size parameter means the number of 16-bit data length. |
||
760 | * @param Timeout Timeout duration |
||
761 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
||
762 | * between Master and Slave(example: audio streaming). |
||
763 | * @retval HAL status |
||
764 | */ |
||
765 | HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) |
||
766 | { |
||
767 | uint32_t tmpreg_cfgr; |
||
768 | |||
769 | if ((pData == NULL) || (Size == 0U)) |
||
770 | { |
||
771 | return HAL_ERROR; |
||
772 | } |
||
773 | |||
774 | /* Process Locked */ |
||
775 | __HAL_LOCK(hi2s); |
||
776 | |||
777 | if (hi2s->State != HAL_I2S_STATE_READY) |
||
778 | { |
||
779 | __HAL_UNLOCK(hi2s); |
||
780 | return HAL_BUSY; |
||
781 | } |
||
782 | |||
783 | /* Set state and reset error code */ |
||
784 | hi2s->State = HAL_I2S_STATE_BUSY_TX; |
||
785 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
||
786 | hi2s->pTxBuffPtr = pData; |
||
787 | |||
788 | tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
||
789 | |||
790 | if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) |
||
791 | { |
||
792 | hi2s->TxXferSize = (Size << 1U); |
||
793 | hi2s->TxXferCount = (Size << 1U); |
||
794 | } |
||
795 | else |
||
796 | { |
||
797 | hi2s->TxXferSize = Size; |
||
798 | hi2s->TxXferCount = Size; |
||
799 | } |
||
800 | |||
801 | tmpreg_cfgr = hi2s->Instance->I2SCFGR; |
||
802 | |||
803 | /* Check if the I2S is already enabled */ |
||
804 | if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
||
805 | { |
||
806 | /* Enable I2S peripheral */ |
||
807 | __HAL_I2S_ENABLE(hi2s); |
||
808 | } |
||
809 | |||
810 | /* Wait until TXE flag is set */ |
||
811 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) |
||
812 | { |
||
813 | /* Set the error code */ |
||
814 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); |
||
815 | hi2s->State = HAL_I2S_STATE_READY; |
||
816 | __HAL_UNLOCK(hi2s); |
||
817 | return HAL_ERROR; |
||
818 | } |
||
819 | |||
820 | while (hi2s->TxXferCount > 0U) |
||
821 | { |
||
822 | hi2s->Instance->DR = (*hi2s->pTxBuffPtr); |
||
823 | hi2s->pTxBuffPtr++; |
||
824 | hi2s->TxXferCount--; |
||
825 | |||
826 | /* Wait until TXE flag is set */ |
||
827 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) |
||
828 | { |
||
829 | /* Set the error code */ |
||
830 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); |
||
831 | hi2s->State = HAL_I2S_STATE_READY; |
||
832 | __HAL_UNLOCK(hi2s); |
||
833 | return HAL_ERROR; |
||
834 | } |
||
835 | |||
836 | /* Check if an underrun occurs */ |
||
837 | if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) |
||
838 | { |
||
839 | /* Clear underrun flag */ |
||
840 | __HAL_I2S_CLEAR_UDRFLAG(hi2s); |
||
841 | |||
842 | /* Set the error code */ |
||
843 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); |
||
844 | } |
||
845 | } |
||
846 | |||
847 | /* Check if Slave mode is selected */ |
||
848 | if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) |
||
849 | || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) |
||
850 | { |
||
851 | /* Wait until Busy flag is reset */ |
||
852 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) |
||
853 | { |
||
854 | /* Set the error code */ |
||
855 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); |
||
856 | hi2s->State = HAL_I2S_STATE_READY; |
||
857 | __HAL_UNLOCK(hi2s); |
||
858 | return HAL_ERROR; |
||
859 | } |
||
860 | } |
||
861 | |||
862 | hi2s->State = HAL_I2S_STATE_READY; |
||
863 | __HAL_UNLOCK(hi2s); |
||
864 | return HAL_OK; |
||
865 | } |
||
866 | |||
867 | /** |
||
868 | * @brief Receive an amount of data in blocking mode |
||
869 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
870 | * the configuration information for I2S module |
||
871 | * @param pData a 16-bit pointer to data buffer. |
||
872 | * @param Size number of data sample to be sent: |
||
873 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
||
874 | * configuration phase, the Size parameter means the number of 16-bit data length |
||
875 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
||
876 | * the Size parameter means the number of 16-bit data length. |
||
877 | * @param Timeout Timeout duration |
||
878 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
||
879 | * between Master and Slave(example: audio streaming). |
||
880 | * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate |
||
881 | * in continuous way and as the I2S is not disabled at the end of the I2S transaction. |
||
882 | * @retval HAL status |
||
883 | */ |
||
884 | HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) |
||
885 | { |
||
886 | uint32_t tmpreg_cfgr; |
||
887 | |||
888 | if ((pData == NULL) || (Size == 0U)) |
||
889 | { |
||
890 | return HAL_ERROR; |
||
891 | } |
||
892 | |||
893 | /* Process Locked */ |
||
894 | __HAL_LOCK(hi2s); |
||
895 | |||
896 | if (hi2s->State != HAL_I2S_STATE_READY) |
||
897 | { |
||
898 | __HAL_UNLOCK(hi2s); |
||
899 | return HAL_BUSY; |
||
900 | } |
||
901 | |||
902 | /* Set state and reset error code */ |
||
903 | hi2s->State = HAL_I2S_STATE_BUSY_RX; |
||
904 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
||
905 | hi2s->pRxBuffPtr = pData; |
||
906 | |||
907 | tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
||
908 | |||
909 | if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) |
||
910 | { |
||
911 | hi2s->RxXferSize = (Size << 1U); |
||
912 | hi2s->RxXferCount = (Size << 1U); |
||
913 | } |
||
914 | else |
||
915 | { |
||
916 | hi2s->RxXferSize = Size; |
||
917 | hi2s->RxXferCount = Size; |
||
918 | } |
||
919 | |||
920 | /* Check if the I2S is already enabled */ |
||
921 | if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
||
922 | { |
||
923 | /* Enable I2S peripheral */ |
||
924 | __HAL_I2S_ENABLE(hi2s); |
||
925 | } |
||
926 | |||
927 | /* Check if Master Receiver mode is selected */ |
||
928 | if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
||
929 | { |
||
930 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
||
931 | access to the SPI_SR register. */ |
||
932 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
||
933 | } |
||
934 | |||
935 | /* Receive data */ |
||
936 | while (hi2s->RxXferCount > 0U) |
||
937 | { |
||
938 | /* Wait until RXNE flag is set */ |
||
939 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) |
||
940 | { |
||
941 | /* Set the error code */ |
||
942 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); |
||
943 | hi2s->State = HAL_I2S_STATE_READY; |
||
944 | __HAL_UNLOCK(hi2s); |
||
945 | return HAL_ERROR; |
||
946 | } |
||
947 | |||
948 | (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; |
||
949 | hi2s->pRxBuffPtr++; |
||
950 | hi2s->RxXferCount--; |
||
951 | |||
952 | /* Check if an overrun occurs */ |
||
953 | if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) |
||
954 | { |
||
955 | /* Clear overrun flag */ |
||
956 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
||
957 | |||
958 | /* Set the error code */ |
||
959 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); |
||
960 | } |
||
961 | } |
||
962 | |||
963 | hi2s->State = HAL_I2S_STATE_READY; |
||
964 | __HAL_UNLOCK(hi2s); |
||
965 | return HAL_OK; |
||
966 | } |
||
967 | |||
968 | /** |
||
969 | * @brief Transmit an amount of data in non-blocking mode with Interrupt |
||
970 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
971 | * the configuration information for I2S module |
||
972 | * @param pData a 16-bit pointer to data buffer. |
||
973 | * @param Size number of data sample to be sent: |
||
974 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
||
975 | * configuration phase, the Size parameter means the number of 16-bit data length |
||
976 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
||
977 | * the Size parameter means the number of 16-bit data length. |
||
978 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
||
979 | * between Master and Slave(example: audio streaming). |
||
980 | * @retval HAL status |
||
981 | */ |
||
982 | HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
||
983 | { |
||
984 | uint32_t tmpreg_cfgr; |
||
985 | |||
986 | if ((pData == NULL) || (Size == 0U)) |
||
987 | { |
||
988 | return HAL_ERROR; |
||
989 | } |
||
990 | |||
991 | /* Process Locked */ |
||
992 | __HAL_LOCK(hi2s); |
||
993 | |||
994 | if (hi2s->State != HAL_I2S_STATE_READY) |
||
995 | { |
||
996 | __HAL_UNLOCK(hi2s); |
||
997 | return HAL_BUSY; |
||
998 | } |
||
999 | |||
1000 | /* Set state and reset error code */ |
||
1001 | hi2s->State = HAL_I2S_STATE_BUSY_TX; |
||
1002 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
||
1003 | hi2s->pTxBuffPtr = pData; |
||
1004 | |||
1005 | tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
||
1006 | |||
1007 | if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) |
||
1008 | { |
||
1009 | hi2s->TxXferSize = (Size << 1U); |
||
1010 | hi2s->TxXferCount = (Size << 1U); |
||
1011 | } |
||
1012 | else |
||
1013 | { |
||
1014 | hi2s->TxXferSize = Size; |
||
1015 | hi2s->TxXferCount = Size; |
||
1016 | } |
||
1017 | |||
1018 | /* Enable TXE and ERR interrupt */ |
||
1019 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
||
1020 | |||
1021 | /* Check if the I2S is already enabled */ |
||
1022 | if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
||
1023 | { |
||
1024 | /* Enable I2S peripheral */ |
||
1025 | __HAL_I2S_ENABLE(hi2s); |
||
1026 | } |
||
1027 | |||
1028 | __HAL_UNLOCK(hi2s); |
||
1029 | return HAL_OK; |
||
1030 | } |
||
1031 | |||
1032 | /** |
||
1033 | * @brief Receive an amount of data in non-blocking mode with Interrupt |
||
1034 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1035 | * the configuration information for I2S module |
||
1036 | * @param pData a 16-bit pointer to the Receive data buffer. |
||
1037 | * @param Size number of data sample to be sent: |
||
1038 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
||
1039 | * configuration phase, the Size parameter means the number of 16-bit data length |
||
1040 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
||
1041 | * the Size parameter means the number of 16-bit data length. |
||
1042 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
||
1043 | * between Master and Slave(example: audio streaming). |
||
1044 | * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization |
||
1045 | * between Master and Slave otherwise the I2S interrupt should be optimized. |
||
1046 | * @retval HAL status |
||
1047 | */ |
||
1048 | HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
||
1049 | { |
||
1050 | uint32_t tmpreg_cfgr; |
||
1051 | |||
1052 | if ((pData == NULL) || (Size == 0U)) |
||
1053 | { |
||
1054 | return HAL_ERROR; |
||
1055 | } |
||
1056 | |||
1057 | /* Process Locked */ |
||
1058 | __HAL_LOCK(hi2s); |
||
1059 | |||
1060 | if (hi2s->State != HAL_I2S_STATE_READY) |
||
1061 | { |
||
1062 | __HAL_UNLOCK(hi2s); |
||
1063 | return HAL_BUSY; |
||
1064 | } |
||
1065 | |||
1066 | /* Set state and reset error code */ |
||
1067 | hi2s->State = HAL_I2S_STATE_BUSY_RX; |
||
1068 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
||
1069 | hi2s->pRxBuffPtr = pData; |
||
1070 | |||
1071 | tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
||
1072 | |||
1073 | if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) |
||
1074 | { |
||
1075 | hi2s->RxXferSize = (Size << 1U); |
||
1076 | hi2s->RxXferCount = (Size << 1U); |
||
1077 | } |
||
1078 | else |
||
1079 | { |
||
1080 | hi2s->RxXferSize = Size; |
||
1081 | hi2s->RxXferCount = Size; |
||
1082 | } |
||
1083 | |||
1084 | /* Enable RXNE and ERR interrupt */ |
||
1085 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
||
1086 | |||
1087 | /* Check if the I2S is already enabled */ |
||
1088 | if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
||
1089 | { |
||
1090 | /* Enable I2S peripheral */ |
||
1091 | __HAL_I2S_ENABLE(hi2s); |
||
1092 | } |
||
1093 | |||
1094 | __HAL_UNLOCK(hi2s); |
||
1095 | return HAL_OK; |
||
1096 | } |
||
1097 | |||
1098 | /** |
||
1099 | * @brief Transmit an amount of data in non-blocking mode with DMA |
||
1100 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1101 | * the configuration information for I2S module |
||
1102 | * @param pData a 16-bit pointer to the Transmit data buffer. |
||
1103 | * @param Size number of data sample to be sent: |
||
1104 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
||
1105 | * configuration phase, the Size parameter means the number of 16-bit data length |
||
1106 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
||
1107 | * the Size parameter means the number of 16-bit data length. |
||
1108 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
||
1109 | * between Master and Slave(example: audio streaming). |
||
1110 | * @retval HAL status |
||
1111 | */ |
||
1112 | HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
||
1113 | { |
||
1114 | uint32_t tmpreg_cfgr; |
||
1115 | |||
1116 | if ((pData == NULL) || (Size == 0U)) |
||
1117 | { |
||
1118 | return HAL_ERROR; |
||
1119 | } |
||
1120 | |||
1121 | /* Process Locked */ |
||
1122 | __HAL_LOCK(hi2s); |
||
1123 | |||
1124 | if (hi2s->State != HAL_I2S_STATE_READY) |
||
1125 | { |
||
1126 | __HAL_UNLOCK(hi2s); |
||
1127 | return HAL_BUSY; |
||
1128 | } |
||
1129 | |||
1130 | /* Set state and reset error code */ |
||
1131 | hi2s->State = HAL_I2S_STATE_BUSY_TX; |
||
1132 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
||
1133 | hi2s->pTxBuffPtr = pData; |
||
1134 | |||
1135 | tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
||
1136 | |||
1137 | if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) |
||
1138 | { |
||
1139 | hi2s->TxXferSize = (Size << 1U); |
||
1140 | hi2s->TxXferCount = (Size << 1U); |
||
1141 | } |
||
1142 | else |
||
1143 | { |
||
1144 | hi2s->TxXferSize = Size; |
||
1145 | hi2s->TxXferCount = Size; |
||
1146 | } |
||
1147 | |||
1148 | /* Set the I2S Tx DMA Half transfer complete callback */ |
||
1149 | hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; |
||
1150 | |||
1151 | /* Set the I2S Tx DMA transfer complete callback */ |
||
1152 | hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; |
||
1153 | |||
1154 | /* Set the DMA error callback */ |
||
1155 | hi2s->hdmatx->XferErrorCallback = I2S_DMAError; |
||
1156 | |||
1157 | /* Enable the Tx DMA Stream/Channel */ |
||
1158 | if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, |
||
1159 | (uint32_t)hi2s->pTxBuffPtr, |
||
1160 | (uint32_t)&hi2s->Instance->DR, |
||
1161 | hi2s->TxXferSize)) |
||
1162 | { |
||
1163 | /* Update SPI error code */ |
||
1164 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); |
||
1165 | hi2s->State = HAL_I2S_STATE_READY; |
||
1166 | |||
1167 | __HAL_UNLOCK(hi2s); |
||
1168 | return HAL_ERROR; |
||
1169 | } |
||
1170 | |||
1171 | /* Check if the I2S is already enabled */ |
||
1172 | if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) |
||
1173 | { |
||
1174 | /* Enable I2S peripheral */ |
||
1175 | __HAL_I2S_ENABLE(hi2s); |
||
1176 | } |
||
1177 | |||
1178 | /* Check if the I2S Tx request is already enabled */ |
||
1179 | if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) |
||
1180 | { |
||
1181 | /* Enable Tx DMA Request */ |
||
1182 | SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); |
||
1183 | } |
||
1184 | |||
1185 | __HAL_UNLOCK(hi2s); |
||
1186 | return HAL_OK; |
||
1187 | } |
||
1188 | |||
1189 | /** |
||
1190 | * @brief Receive an amount of data in non-blocking mode with DMA |
||
1191 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1192 | * the configuration information for I2S module |
||
1193 | * @param pData a 16-bit pointer to the Receive data buffer. |
||
1194 | * @param Size number of data sample to be sent: |
||
1195 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
||
1196 | * configuration phase, the Size parameter means the number of 16-bit data length |
||
1197 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
||
1198 | * the Size parameter means the number of 16-bit data length. |
||
1199 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
||
1200 | * between Master and Slave(example: audio streaming). |
||
1201 | * @retval HAL status |
||
1202 | */ |
||
1203 | HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
||
1204 | { |
||
1205 | uint32_t tmpreg_cfgr; |
||
1206 | |||
1207 | if ((pData == NULL) || (Size == 0U)) |
||
1208 | { |
||
1209 | return HAL_ERROR; |
||
1210 | } |
||
1211 | |||
1212 | /* Process Locked */ |
||
1213 | __HAL_LOCK(hi2s); |
||
1214 | |||
1215 | if (hi2s->State != HAL_I2S_STATE_READY) |
||
1216 | { |
||
1217 | __HAL_UNLOCK(hi2s); |
||
1218 | return HAL_BUSY; |
||
1219 | } |
||
1220 | |||
1221 | /* Set state and reset error code */ |
||
1222 | hi2s->State = HAL_I2S_STATE_BUSY_RX; |
||
1223 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
||
1224 | hi2s->pRxBuffPtr = pData; |
||
1225 | |||
1226 | tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
||
1227 | |||
1228 | if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) |
||
1229 | { |
||
1230 | hi2s->RxXferSize = (Size << 1U); |
||
1231 | hi2s->RxXferCount = (Size << 1U); |
||
1232 | } |
||
1233 | else |
||
1234 | { |
||
1235 | hi2s->RxXferSize = Size; |
||
1236 | hi2s->RxXferCount = Size; |
||
1237 | } |
||
1238 | |||
1239 | /* Set the I2S Rx DMA Half transfer complete callback */ |
||
1240 | hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; |
||
1241 | |||
1242 | /* Set the I2S Rx DMA transfer complete callback */ |
||
1243 | hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; |
||
1244 | |||
1245 | /* Set the DMA error callback */ |
||
1246 | hi2s->hdmarx->XferErrorCallback = I2S_DMAError; |
||
1247 | |||
1248 | /* Check if Master Receiver mode is selected */ |
||
1249 | if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
||
1250 | { |
||
1251 | /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read |
||
1252 | access to the SPI_SR register. */ |
||
1253 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
||
1254 | } |
||
1255 | |||
1256 | /* Enable the Rx DMA Stream/Channel */ |
||
1257 | if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, |
||
1258 | hi2s->RxXferSize)) |
||
1259 | { |
||
1260 | /* Update SPI error code */ |
||
1261 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); |
||
1262 | hi2s->State = HAL_I2S_STATE_READY; |
||
1263 | |||
1264 | __HAL_UNLOCK(hi2s); |
||
1265 | return HAL_ERROR; |
||
1266 | } |
||
1267 | |||
1268 | /* Check if the I2S is already enabled */ |
||
1269 | if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) |
||
1270 | { |
||
1271 | /* Enable I2S peripheral */ |
||
1272 | __HAL_I2S_ENABLE(hi2s); |
||
1273 | } |
||
1274 | |||
1275 | /* Check if the I2S Rx request is already enabled */ |
||
1276 | if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) |
||
1277 | { |
||
1278 | /* Enable Rx DMA Request */ |
||
1279 | SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); |
||
1280 | } |
||
1281 | |||
1282 | __HAL_UNLOCK(hi2s); |
||
1283 | return HAL_OK; |
||
1284 | } |
||
1285 | |||
1286 | /** |
||
1287 | * @brief Pauses the audio DMA Stream/Channel playing from the Media. |
||
1288 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1289 | * the configuration information for I2S module |
||
1290 | * @retval HAL status |
||
1291 | */ |
||
1292 | HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) |
||
1293 | { |
||
1294 | /* Process Locked */ |
||
1295 | __HAL_LOCK(hi2s); |
||
1296 | |||
1297 | if (hi2s->State == HAL_I2S_STATE_BUSY_TX) |
||
1298 | { |
||
1299 | /* Disable the I2S DMA Tx request */ |
||
1300 | CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); |
||
1301 | } |
||
1302 | else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) |
||
1303 | { |
||
1304 | /* Disable the I2S DMA Rx request */ |
||
1305 | CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); |
||
1306 | } |
||
1307 | else |
||
1308 | { |
||
1309 | /* nothing to do */ |
||
1310 | } |
||
1311 | |||
1312 | /* Process Unlocked */ |
||
1313 | __HAL_UNLOCK(hi2s); |
||
1314 | |||
1315 | return HAL_OK; |
||
1316 | } |
||
1317 | |||
1318 | /** |
||
1319 | * @brief Resumes the audio DMA Stream/Channel playing from the Media. |
||
1320 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1321 | * the configuration information for I2S module |
||
1322 | * @retval HAL status |
||
1323 | */ |
||
1324 | HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) |
||
1325 | { |
||
1326 | /* Process Locked */ |
||
1327 | __HAL_LOCK(hi2s); |
||
1328 | |||
1329 | if (hi2s->State == HAL_I2S_STATE_BUSY_TX) |
||
1330 | { |
||
1331 | /* Enable the I2S DMA Tx request */ |
||
1332 | SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); |
||
1333 | } |
||
1334 | else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) |
||
1335 | { |
||
1336 | /* Enable the I2S DMA Rx request */ |
||
1337 | SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); |
||
1338 | } |
||
1339 | else |
||
1340 | { |
||
1341 | /* nothing to do */ |
||
1342 | } |
||
1343 | |||
1344 | /* If the I2S peripheral is still not enabled, enable it */ |
||
1345 | if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) |
||
1346 | { |
||
1347 | /* Enable I2S peripheral */ |
||
1348 | __HAL_I2S_ENABLE(hi2s); |
||
1349 | } |
||
1350 | |||
1351 | /* Process Unlocked */ |
||
1352 | __HAL_UNLOCK(hi2s); |
||
1353 | |||
1354 | return HAL_OK; |
||
1355 | } |
||
1356 | |||
1357 | /** |
||
1358 | * @brief Stops the audio DMA Stream/Channel playing from the Media. |
||
1359 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1360 | * the configuration information for I2S module |
||
1361 | * @retval HAL status |
||
1362 | */ |
||
1363 | HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) |
||
1364 | { |
||
1365 | HAL_StatusTypeDef errorcode = HAL_OK; |
||
1366 | /* The Lock is not implemented on this API to allow the user application |
||
1367 | to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() |
||
1368 | when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated |
||
1369 | and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() |
||
1370 | */ |
||
1371 | |||
1372 | /* Disable the I2S Tx/Rx DMA requests */ |
||
1373 | CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); |
||
1374 | CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); |
||
1375 | |||
1376 | /* Abort the I2S DMA tx Stream/Channel */ |
||
1377 | if (hi2s->hdmatx != NULL) |
||
1378 | { |
||
1379 | /* Disable the I2S DMA tx Stream/Channel */ |
||
1380 | if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) |
||
1381 | { |
||
1382 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); |
||
1383 | errorcode = HAL_ERROR; |
||
1384 | } |
||
1385 | } |
||
1386 | |||
1387 | /* Abort the I2S DMA rx Stream/Channel */ |
||
1388 | if (hi2s->hdmarx != NULL) |
||
1389 | { |
||
1390 | /* Disable the I2S DMA rx Stream/Channel */ |
||
1391 | if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) |
||
1392 | { |
||
1393 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); |
||
1394 | errorcode = HAL_ERROR; |
||
1395 | } |
||
1396 | } |
||
1397 | |||
1398 | /* Disable I2S peripheral */ |
||
1399 | __HAL_I2S_DISABLE(hi2s); |
||
1400 | |||
1401 | hi2s->State = HAL_I2S_STATE_READY; |
||
1402 | |||
1403 | return errorcode; |
||
1404 | } |
||
1405 | |||
1406 | /** |
||
1407 | * @brief This function handles I2S interrupt request. |
||
1408 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1409 | * the configuration information for I2S module |
||
1410 | * @retval None |
||
1411 | */ |
||
1412 | void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) |
||
1413 | { |
||
1414 | uint32_t itsource = hi2s->Instance->CR2; |
||
1415 | uint32_t itflag = hi2s->Instance->SR; |
||
1416 | |||
1417 | /* I2S in mode Receiver ------------------------------------------------*/ |
||
1418 | if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) && |
||
1419 | (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET)) |
||
1420 | { |
||
1421 | I2S_Receive_IT(hi2s); |
||
1422 | return; |
||
1423 | } |
||
1424 | |||
1425 | /* I2S in mode Tramitter -----------------------------------------------*/ |
||
1426 | if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET)) |
||
1427 | { |
||
1428 | I2S_Transmit_IT(hi2s); |
||
1429 | return; |
||
1430 | } |
||
1431 | |||
1432 | /* I2S interrupt error -------------------------------------------------*/ |
||
1433 | if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET) |
||
1434 | { |
||
1435 | /* I2S Overrun error interrupt occurred ---------------------------------*/ |
||
1436 | if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET) |
||
1437 | { |
||
1438 | /* Disable RXNE and ERR interrupt */ |
||
1439 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
||
1440 | |||
1441 | /* Set the error code and execute error callback*/ |
||
1442 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); |
||
1443 | } |
||
1444 | |||
1445 | /* I2S Underrun error interrupt occurred --------------------------------*/ |
||
1446 | if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET) |
||
1447 | { |
||
1448 | /* Disable TXE and ERR interrupt */ |
||
1449 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
||
1450 | |||
1451 | /* Set the error code and execute error callback*/ |
||
1452 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); |
||
1453 | } |
||
1454 | |||
1455 | /* Set the I2S State ready */ |
||
1456 | hi2s->State = HAL_I2S_STATE_READY; |
||
1457 | |||
1458 | /* Call user error callback */ |
||
1459 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
1460 | hi2s->ErrorCallback(hi2s); |
||
1461 | #else |
||
1462 | HAL_I2S_ErrorCallback(hi2s); |
||
1463 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
1464 | } |
||
1465 | } |
||
1466 | |||
1467 | /** |
||
1468 | * @brief Tx Transfer Half completed callbacks |
||
1469 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1470 | * the configuration information for I2S module |
||
1471 | * @retval None |
||
1472 | */ |
||
1473 | __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) |
||
1474 | { |
||
1475 | /* Prevent unused argument(s) compilation warning */ |
||
1476 | UNUSED(hi2s); |
||
1477 | |||
1478 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
1479 | the HAL_I2S_TxHalfCpltCallback could be implemented in the user file |
||
1480 | */ |
||
1481 | } |
||
1482 | |||
1483 | /** |
||
1484 | * @brief Tx Transfer completed callbacks |
||
1485 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1486 | * the configuration information for I2S module |
||
1487 | * @retval None |
||
1488 | */ |
||
1489 | __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) |
||
1490 | { |
||
1491 | /* Prevent unused argument(s) compilation warning */ |
||
1492 | UNUSED(hi2s); |
||
1493 | |||
1494 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
1495 | the HAL_I2S_TxCpltCallback could be implemented in the user file |
||
1496 | */ |
||
1497 | } |
||
1498 | |||
1499 | /** |
||
1500 | * @brief Rx Transfer half completed callbacks |
||
1501 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1502 | * the configuration information for I2S module |
||
1503 | * @retval None |
||
1504 | */ |
||
1505 | __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) |
||
1506 | { |
||
1507 | /* Prevent unused argument(s) compilation warning */ |
||
1508 | UNUSED(hi2s); |
||
1509 | |||
1510 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
1511 | the HAL_I2S_RxHalfCpltCallback could be implemented in the user file |
||
1512 | */ |
||
1513 | } |
||
1514 | |||
1515 | /** |
||
1516 | * @brief Rx Transfer completed callbacks |
||
1517 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1518 | * the configuration information for I2S module |
||
1519 | * @retval None |
||
1520 | */ |
||
1521 | __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) |
||
1522 | { |
||
1523 | /* Prevent unused argument(s) compilation warning */ |
||
1524 | UNUSED(hi2s); |
||
1525 | |||
1526 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
1527 | the HAL_I2S_RxCpltCallback could be implemented in the user file |
||
1528 | */ |
||
1529 | } |
||
1530 | |||
1531 | /** |
||
1532 | * @brief I2S error callbacks |
||
1533 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1534 | * the configuration information for I2S module |
||
1535 | * @retval None |
||
1536 | */ |
||
1537 | __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) |
||
1538 | { |
||
1539 | /* Prevent unused argument(s) compilation warning */ |
||
1540 | UNUSED(hi2s); |
||
1541 | |||
1542 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
1543 | the HAL_I2S_ErrorCallback could be implemented in the user file |
||
1544 | */ |
||
1545 | } |
||
1546 | |||
1547 | /** |
||
1548 | * @} |
||
1549 | */ |
||
1550 | |||
1551 | /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions |
||
1552 | * @brief Peripheral State functions |
||
1553 | * |
||
1554 | @verbatim |
||
1555 | =============================================================================== |
||
1556 | ##### Peripheral State and Errors functions ##### |
||
1557 | =============================================================================== |
||
1558 | [..] |
||
1559 | This subsection permits to get in run-time the status of the peripheral |
||
1560 | and the data flow. |
||
1561 | |||
1562 | @endverbatim |
||
1563 | * @{ |
||
1564 | */ |
||
1565 | |||
1566 | /** |
||
1567 | * @brief Return the I2S state |
||
1568 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1569 | * the configuration information for I2S module |
||
1570 | * @retval HAL state |
||
1571 | */ |
||
1572 | HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) |
||
1573 | { |
||
1574 | return hi2s->State; |
||
1575 | } |
||
1576 | |||
1577 | /** |
||
1578 | * @brief Return the I2S error code |
||
1579 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1580 | * the configuration information for I2S module |
||
1581 | * @retval I2S Error Code |
||
1582 | */ |
||
1583 | uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) |
||
1584 | { |
||
1585 | return hi2s->ErrorCode; |
||
1586 | } |
||
1587 | /** |
||
1588 | * @} |
||
1589 | */ |
||
1590 | |||
1591 | /** |
||
1592 | * @} |
||
1593 | */ |
||
1594 | |||
1595 | /** @addtogroup I2S_Private_Functions I2S Private Functions |
||
1596 | * @{ |
||
1597 | */ |
||
1598 | /** |
||
1599 | * @brief DMA I2S transmit process complete callback |
||
1600 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
1601 | * the configuration information for the specified DMA module. |
||
1602 | * @retval None |
||
1603 | */ |
||
1604 | static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) |
||
1605 | { |
||
1606 | I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
1607 | |||
1608 | /* if DMA is configured in DMA_NORMAL Mode */ |
||
1609 | if (hdma->Init.Mode == DMA_NORMAL) |
||
1610 | { |
||
1611 | /* Disable Tx DMA Request */ |
||
1612 | CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); |
||
1613 | |||
1614 | hi2s->TxXferCount = 0U; |
||
1615 | hi2s->State = HAL_I2S_STATE_READY; |
||
1616 | } |
||
1617 | /* Call user Tx complete callback */ |
||
1618 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
1619 | hi2s->TxCpltCallback(hi2s); |
||
1620 | #else |
||
1621 | HAL_I2S_TxCpltCallback(hi2s); |
||
1622 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
1623 | } |
||
1624 | |||
1625 | /** |
||
1626 | * @brief DMA I2S transmit process half complete callback |
||
1627 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
1628 | * the configuration information for the specified DMA module. |
||
1629 | * @retval None |
||
1630 | */ |
||
1631 | static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) |
||
1632 | { |
||
1633 | I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
1634 | |||
1635 | /* Call user Tx half complete callback */ |
||
1636 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
1637 | hi2s->TxHalfCpltCallback(hi2s); |
||
1638 | #else |
||
1639 | HAL_I2S_TxHalfCpltCallback(hi2s); |
||
1640 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
1641 | } |
||
1642 | |||
1643 | /** |
||
1644 | * @brief DMA I2S receive process complete callback |
||
1645 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
1646 | * the configuration information for the specified DMA module. |
||
1647 | * @retval None |
||
1648 | */ |
||
1649 | static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) |
||
1650 | { |
||
1651 | I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
1652 | |||
1653 | /* if DMA is configured in DMA_NORMAL Mode */ |
||
1654 | if (hdma->Init.Mode == DMA_NORMAL) |
||
1655 | { |
||
1656 | /* Disable Rx DMA Request */ |
||
1657 | CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); |
||
1658 | hi2s->RxXferCount = 0U; |
||
1659 | hi2s->State = HAL_I2S_STATE_READY; |
||
1660 | } |
||
1661 | /* Call user Rx complete callback */ |
||
1662 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
1663 | hi2s->RxCpltCallback(hi2s); |
||
1664 | #else |
||
1665 | HAL_I2S_RxCpltCallback(hi2s); |
||
1666 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
1667 | } |
||
1668 | |||
1669 | /** |
||
1670 | * @brief DMA I2S receive process half complete callback |
||
1671 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
1672 | * the configuration information for the specified DMA module. |
||
1673 | * @retval None |
||
1674 | */ |
||
1675 | static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) |
||
1676 | { |
||
1677 | I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
1678 | |||
1679 | /* Call user Rx half complete callback */ |
||
1680 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
1681 | hi2s->RxHalfCpltCallback(hi2s); |
||
1682 | #else |
||
1683 | HAL_I2S_RxHalfCpltCallback(hi2s); |
||
1684 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
1685 | } |
||
1686 | |||
1687 | /** |
||
1688 | * @brief DMA I2S communication error callback |
||
1689 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
1690 | * the configuration information for the specified DMA module. |
||
1691 | * @retval None |
||
1692 | */ |
||
1693 | static void I2S_DMAError(DMA_HandleTypeDef *hdma) |
||
1694 | { |
||
1695 | I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
1696 | |||
1697 | /* Disable Rx and Tx DMA Request */ |
||
1698 | CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); |
||
1699 | hi2s->TxXferCount = 0U; |
||
1700 | hi2s->RxXferCount = 0U; |
||
1701 | |||
1702 | hi2s->State = HAL_I2S_STATE_READY; |
||
1703 | |||
1704 | /* Set the error code and execute error callback*/ |
||
1705 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); |
||
1706 | /* Call user error callback */ |
||
1707 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
1708 | hi2s->ErrorCallback(hi2s); |
||
1709 | #else |
||
1710 | HAL_I2S_ErrorCallback(hi2s); |
||
1711 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
1712 | } |
||
1713 | |||
1714 | /** |
||
1715 | * @brief Transmit an amount of data in non-blocking mode with Interrupt |
||
1716 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1717 | * the configuration information for I2S module |
||
1718 | * @retval None |
||
1719 | */ |
||
1720 | static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) |
||
1721 | { |
||
1722 | /* Transmit data */ |
||
1723 | hi2s->Instance->DR = (*hi2s->pTxBuffPtr); |
||
1724 | hi2s->pTxBuffPtr++; |
||
1725 | hi2s->TxXferCount--; |
||
1726 | |||
1727 | if (hi2s->TxXferCount == 0U) |
||
1728 | { |
||
1729 | /* Disable TXE and ERR interrupt */ |
||
1730 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
||
1731 | |||
1732 | hi2s->State = HAL_I2S_STATE_READY; |
||
1733 | /* Call user Tx complete callback */ |
||
1734 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
1735 | hi2s->TxCpltCallback(hi2s); |
||
1736 | #else |
||
1737 | HAL_I2S_TxCpltCallback(hi2s); |
||
1738 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
1739 | } |
||
1740 | } |
||
1741 | |||
1742 | /** |
||
1743 | * @brief Receive an amount of data in non-blocking mode with Interrupt |
||
1744 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1745 | * the configuration information for I2S module |
||
1746 | * @retval None |
||
1747 | */ |
||
1748 | static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) |
||
1749 | { |
||
1750 | /* Receive data */ |
||
1751 | (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; |
||
1752 | hi2s->pRxBuffPtr++; |
||
1753 | hi2s->RxXferCount--; |
||
1754 | |||
1755 | if (hi2s->RxXferCount == 0U) |
||
1756 | { |
||
1757 | /* Disable RXNE and ERR interrupt */ |
||
1758 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
||
1759 | |||
1760 | hi2s->State = HAL_I2S_STATE_READY; |
||
1761 | /* Call user Rx complete callback */ |
||
1762 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
||
1763 | hi2s->RxCpltCallback(hi2s); |
||
1764 | #else |
||
1765 | HAL_I2S_RxCpltCallback(hi2s); |
||
1766 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
||
1767 | } |
||
1768 | } |
||
1769 | |||
1770 | /** |
||
1771 | * @brief This function handles I2S Communication Timeout. |
||
1772 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
||
1773 | * the configuration information for I2S module |
||
1774 | * @param Flag Flag checked |
||
1775 | * @param State Value of the flag expected |
||
1776 | * @param Timeout Duration of the timeout |
||
1777 | * @retval HAL status |
||
1778 | */ |
||
1779 | static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, |
||
1780 | uint32_t Timeout) |
||
1781 | { |
||
1782 | uint32_t tickstart; |
||
1783 | |||
1784 | /* Get tick */ |
||
1785 | tickstart = HAL_GetTick(); |
||
1786 | |||
1787 | /* Wait until flag is set to status*/ |
||
1788 | while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) |
||
1789 | { |
||
1790 | if (Timeout != HAL_MAX_DELAY) |
||
1791 | { |
||
1792 | if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) |
||
1793 | { |
||
1794 | /* Set the I2S State ready */ |
||
1795 | hi2s->State = HAL_I2S_STATE_READY; |
||
1796 | |||
1797 | /* Process Unlocked */ |
||
1798 | __HAL_UNLOCK(hi2s); |
||
1799 | |||
1800 | return HAL_TIMEOUT; |
||
1801 | } |
||
1802 | } |
||
1803 | } |
||
1804 | return HAL_OK; |
||
1805 | } |
||
1806 | |||
1807 | /** |
||
1808 | * @} |
||
1809 | */ |
||
1810 | |||
1811 | /** |
||
1812 | * @} |
||
1813 | */ |
||
1814 | |||
1815 | /** |
||
1816 | * @} |
||
1817 | */ |
||
1818 | #endif /* SPI_I2S_SUPPORT */ |
||
1819 | |||
1820 | #endif /* HAL_I2S_MODULE_ENABLED */ |
||
1821 | |||
1822 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |