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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f1xx_hal_i2c.c |
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4 | * @author MCD Application Team |
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5 | * @brief I2C HAL module driver. |
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6 | * This file provides firmware functions to manage the following |
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7 | * functionalities of the Inter Integrated Circuit (I2C) peripheral: |
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8 | * + Initialization and de-initialization functions |
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9 | * + IO operation functions |
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10 | * + Peripheral State, Mode and Error functions |
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11 | * |
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12 | @verbatim |
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13 | ============================================================================== |
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14 | ##### How to use this driver ##### |
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15 | ============================================================================== |
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16 | [..] |
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17 | The I2C HAL driver can be used as follows: |
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18 | |||
19 | (#) Declare a I2C_HandleTypeDef handle structure, for example: |
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20 | I2C_HandleTypeDef hi2c; |
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21 | |||
22 | (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: |
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23 | (##) Enable the I2Cx interface clock |
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24 | (##) I2C pins configuration |
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25 | (+++) Enable the clock for the I2C GPIOs |
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26 | (+++) Configure I2C pins as alternate function open-drain |
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27 | (##) NVIC configuration if you need to use interrupt process |
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28 | (+++) Configure the I2Cx interrupt priority |
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29 | (+++) Enable the NVIC I2C IRQ Channel |
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30 | (##) DMA Configuration if you need to use DMA process |
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31 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel |
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32 | (+++) Enable the DMAx interface clock using |
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33 | (+++) Configure the DMA handle parameters |
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34 | (+++) Configure the DMA Tx or Rx channel |
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35 | (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle |
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36 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on |
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37 | the DMA Tx or Rx channel |
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38 | |||
39 | (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, |
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40 | Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. |
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41 | |||
42 | (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware |
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43 | (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API. |
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44 | |||
45 | (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() |
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46 | |||
47 | (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : |
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48 | |||
49 | *** Polling mode IO operation *** |
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50 | ================================= |
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51 | [..] |
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52 | (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() |
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53 | (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() |
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54 | (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() |
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55 | (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() |
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56 | |||
57 | *** Polling mode IO MEM operation *** |
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58 | ===================================== |
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59 | [..] |
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60 | (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() |
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61 | (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() |
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62 | |||
63 | |||
64 | *** Interrupt mode IO operation *** |
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65 | =================================== |
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66 | [..] |
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67 | (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() |
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68 | (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can |
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69 | add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() |
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70 | (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() |
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71 | (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can |
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72 | add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() |
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73 | (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() |
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74 | (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can |
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75 | add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() |
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76 | (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() |
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77 | (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can |
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78 | add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() |
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79 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
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80 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
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81 | (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() |
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82 | (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can |
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83 | add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() |
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84 | |||
85 | *** Interrupt mode or DMA mode IO sequential operation *** |
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86 | ========================================================== |
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87 | [..] |
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88 | (@) These interfaces allow to manage a sequential transfer with a repeated start condition |
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89 | when a direction change during transfer |
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90 | [..] |
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91 | (+) A specific option field manage the different steps of a sequential transfer |
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92 | (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below: |
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93 | (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode |
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94 | (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address |
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95 | and data to transfer without a final stop condition |
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96 | (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address |
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97 | and data to transfer without a final stop condition, an then permit a call the same master sequential interface |
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98 | several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() |
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99 | or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) |
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100 | (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address |
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101 | and with new data to transfer if the direction change or manage only the new data to transfer |
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102 | if no direction change and without a final stop condition in both cases |
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103 | (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address |
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104 | and with new data to transfer if the direction change or manage only the new data to transfer |
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105 | if no direction change and with a final stop condition in both cases |
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106 | (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential |
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107 | interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). |
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108 | Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
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109 | or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
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110 | or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
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111 | or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). |
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112 | Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit |
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113 | without stopping the communication and so generate a restart condition. |
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114 | (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential |
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115 | interface. |
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116 | Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
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117 | or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
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118 | or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
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119 | or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). |
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120 | Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. |
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121 | |||
122 | (+) Different sequential I2C interfaces are listed below: |
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123 | (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() |
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124 | or using @ref HAL_I2C_Master_Seq_Transmit_DMA() |
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125 | (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can |
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126 | add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() |
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127 | (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() |
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128 | or using @ref HAL_I2C_Master_Seq_Receive_DMA() |
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129 | (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can |
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130 | add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() |
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131 | (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() |
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132 | (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can |
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133 | add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() |
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134 | (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() |
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135 | (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can |
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136 | add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). |
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137 | (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can |
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138 | add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() |
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139 | (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() |
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140 | or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() |
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141 | (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can |
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142 | add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() |
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143 | (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() |
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144 | or using @ref HAL_I2C_Slave_Seq_Receive_DMA() |
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145 | (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can |
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146 | add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() |
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147 | (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
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148 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
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149 | |||
150 | *** Interrupt mode IO MEM operation *** |
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151 | ======================================= |
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152 | [..] |
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153 | (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using |
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154 | @ref HAL_I2C_Mem_Write_IT() |
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155 | (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can |
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156 | add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() |
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157 | (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using |
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158 | @ref HAL_I2C_Mem_Read_IT() |
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159 | (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can |
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160 | add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() |
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161 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
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162 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
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163 | |||
164 | *** DMA mode IO operation *** |
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165 | ============================== |
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166 | [..] |
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167 | (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using |
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168 | @ref HAL_I2C_Master_Transmit_DMA() |
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169 | (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can |
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170 | add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() |
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171 | (+) Receive in master mode an amount of data in non-blocking mode (DMA) using |
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172 | @ref HAL_I2C_Master_Receive_DMA() |
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173 | (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can |
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174 | add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() |
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175 | (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using |
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176 | @ref HAL_I2C_Slave_Transmit_DMA() |
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177 | (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can |
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178 | add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() |
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179 | (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using |
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180 | @ref HAL_I2C_Slave_Receive_DMA() |
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181 | (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can |
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182 | add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() |
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183 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
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184 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
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185 | (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() |
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186 | (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can |
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187 | add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() |
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188 | |||
189 | *** DMA mode IO MEM operation *** |
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190 | ================================= |
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191 | [..] |
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192 | (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using |
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193 | @ref HAL_I2C_Mem_Write_DMA() |
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194 | (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can |
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195 | add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() |
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196 | (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using |
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197 | @ref HAL_I2C_Mem_Read_DMA() |
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198 | (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can |
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199 | add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() |
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200 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
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201 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
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202 | |||
203 | |||
204 | *** I2C HAL driver macros list *** |
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205 | ================================== |
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206 | [..] |
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207 | Below the list of most used macros in I2C HAL driver. |
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208 | |||
209 | (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral |
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210 | (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral |
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211 | (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not |
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212 | (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag |
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213 | (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt |
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214 | (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt |
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215 | |||
216 | *** Callback registration *** |
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217 | ============================================= |
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218 | [..] |
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219 | The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 |
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220 | allows the user to configure dynamically the driver callbacks. |
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221 | Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() |
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222 | to register an interrupt callback. |
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223 | [..] |
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224 | Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: |
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225 | (+) MasterTxCpltCallback : callback for Master transmission end of transfer. |
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226 | (+) MasterRxCpltCallback : callback for Master reception end of transfer. |
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227 | (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. |
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228 | (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. |
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229 | (+) ListenCpltCallback : callback for end of listen mode. |
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230 | (+) MemTxCpltCallback : callback for Memory transmission end of transfer. |
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231 | (+) MemRxCpltCallback : callback for Memory reception end of transfer. |
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232 | (+) ErrorCallback : callback for error detection. |
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233 | (+) AbortCpltCallback : callback for abort completion process. |
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234 | (+) MspInitCallback : callback for Msp Init. |
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235 | (+) MspDeInitCallback : callback for Msp DeInit. |
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236 | This function takes as parameters the HAL peripheral handle, the Callback ID |
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237 | and a pointer to the user callback function. |
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238 | [..] |
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239 | For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). |
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240 | [..] |
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241 | Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default |
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242 | weak function. |
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243 | @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, |
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244 | and the Callback ID. |
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245 | This function allows to reset following callbacks: |
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246 | (+) MasterTxCpltCallback : callback for Master transmission end of transfer. |
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247 | (+) MasterRxCpltCallback : callback for Master reception end of transfer. |
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248 | (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. |
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249 | (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. |
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250 | (+) ListenCpltCallback : callback for end of listen mode. |
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251 | (+) MemTxCpltCallback : callback for Memory transmission end of transfer. |
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252 | (+) MemRxCpltCallback : callback for Memory reception end of transfer. |
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253 | (+) ErrorCallback : callback for error detection. |
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254 | (+) AbortCpltCallback : callback for abort completion process. |
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255 | (+) MspInitCallback : callback for Msp Init. |
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256 | (+) MspDeInitCallback : callback for Msp DeInit. |
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257 | [..] |
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258 | For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). |
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259 | [..] |
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260 | By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET |
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261 | all callbacks are set to the corresponding weak functions: |
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262 | examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). |
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263 | Exception done for MspInit and MspDeInit functions that are |
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264 | reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when |
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265 | these callbacks are null (not registered beforehand). |
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266 | If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() |
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267 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
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268 | [..] |
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269 | Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. |
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270 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
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271 | in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, |
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272 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
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273 | Then, the user first registers the MspInit/MspDeInit user callbacks |
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274 | using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() |
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275 | or @ref HAL_I2C_Init() function. |
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276 | [..] |
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277 | When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or |
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278 | not defined, the callback registration feature is not available and all callbacks |
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279 | are set to the corresponding weak functions. |
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280 | |||
281 | |||
282 | *** I2C Workarounds linked to Silicon Limitation *** |
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283 | ==================================================== |
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284 | [..] |
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285 | Below the list of all silicon limitations implemented for HAL on STM32F1xx product. |
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286 | (@) See ErrataSheet to know full silicon limitation list of your product. |
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287 | |||
288 | (+) Workarounds Implemented inside I2C HAL Driver |
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289 | (++) Wrong data read into data register (Polling and Interrupt mode) |
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290 | (++) Start cannot be generated after a misplaced Stop |
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291 | (++) Some software events must be managed before the current byte is being transferred: |
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292 | Workaround: Use DMA in general, except when the Master is receiving a single byte. |
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293 | For Interupt mode, I2C should have the highest priority in the application. |
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294 | (++) Mismatch on the "Setup time for a repeated Start condition" timing parameter: |
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295 | Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if |
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296 | supported by the slave. |
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297 | (++) Data valid time (tVD;DAT) violated without the OVR flag being set: |
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298 | Workaround: If the slave device allows it, use the clock stretching mechanism |
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299 | by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in @ref HAL_I2C_Init. |
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300 | |||
301 | [..] |
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302 | (@) You can refer to the I2C HAL driver header file for more useful macros |
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303 | |||
304 | @endverbatim |
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305 | ****************************************************************************** |
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306 | * @attention |
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307 | * |
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308 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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309 | * All rights reserved.</center></h2> |
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310 | * |
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311 | * This software component is licensed by ST under BSD 3-Clause license, |
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312 | * the "License"; You may not use this file except in compliance with the |
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313 | * License. You may obtain a copy of the License at: |
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314 | * opensource.org/licenses/BSD-3-Clause |
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315 | * |
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316 | ****************************************************************************** |
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317 | */ |
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318 | |||
319 | /* Includes ------------------------------------------------------------------*/ |
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320 | #include "stm32f1xx_hal.h" |
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321 | |||
322 | /** @addtogroup STM32F1xx_HAL_Driver |
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323 | * @{ |
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324 | */ |
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325 | |||
326 | /** @defgroup I2C I2C |
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327 | * @brief I2C HAL module driver |
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328 | * @{ |
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329 | */ |
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330 | |||
331 | #ifdef HAL_I2C_MODULE_ENABLED |
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332 | |||
333 | /* Private typedef -----------------------------------------------------------*/ |
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334 | /* Private define ------------------------------------------------------------*/ |
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335 | /** @addtogroup I2C_Private_Define |
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336 | * @{ |
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337 | */ |
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338 | #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ |
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339 | #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ |
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340 | #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ |
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341 | #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ |
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342 | |||
343 | /* Private define for @ref PreviousState usage */ |
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344 | #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ |
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345 | #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ |
||
346 | #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ |
||
347 | #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ |
||
348 | #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ |
||
349 | #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ |
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350 | |||
351 | /** |
||
352 | * @} |
||
353 | */ |
||
354 | |||
355 | /* Private macro -------------------------------------------------------------*/ |
||
356 | /* Private variables ---------------------------------------------------------*/ |
||
357 | /* Private function prototypes -----------------------------------------------*/ |
||
358 | |||
359 | /** @defgroup I2C_Private_Functions I2C Private Functions |
||
360 | * @{ |
||
361 | */ |
||
362 | /* Private functions to handle DMA transfer */ |
||
363 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); |
||
364 | static void I2C_DMAError(DMA_HandleTypeDef *hdma); |
||
365 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); |
||
366 | |||
367 | static void I2C_ITError(I2C_HandleTypeDef *hi2c); |
||
368 | |||
369 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
||
370 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
||
371 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
||
372 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
||
373 | |||
374 | /* Private functions to handle flags during polling transfer */ |
||
375 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); |
||
376 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); |
||
377 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
||
378 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
||
379 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
||
380 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
||
381 | static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); |
||
382 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); |
||
383 | |||
384 | /* Private functions for I2C transfer IRQ handler */ |
||
385 | static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); |
||
386 | static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); |
||
387 | static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); |
||
388 | static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); |
||
389 | static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); |
||
390 | static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); |
||
391 | static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); |
||
392 | |||
393 | static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); |
||
394 | static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); |
||
395 | static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); |
||
396 | static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); |
||
397 | static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); |
||
398 | static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); |
||
399 | static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); |
||
400 | |||
401 | static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); |
||
402 | |||
403 | /* Private function to Convert Specific options */ |
||
404 | static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); |
||
405 | /** |
||
406 | * @} |
||
407 | */ |
||
408 | |||
409 | /* Exported functions --------------------------------------------------------*/ |
||
410 | |||
411 | /** @defgroup I2C_Exported_Functions I2C Exported Functions |
||
412 | * @{ |
||
413 | */ |
||
414 | |||
415 | /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions |
||
416 | * @brief Initialization and Configuration functions |
||
417 | * |
||
418 | @verbatim |
||
419 | =============================================================================== |
||
420 | ##### Initialization and de-initialization functions ##### |
||
421 | =============================================================================== |
||
422 | [..] This subsection provides a set of functions allowing to initialize and |
||
423 | deinitialize the I2Cx peripheral: |
||
424 | |||
425 | (+) User must Implement HAL_I2C_MspInit() function in which he configures |
||
426 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). |
||
427 | |||
428 | (+) Call the function HAL_I2C_Init() to configure the selected device with |
||
429 | the selected configuration: |
||
430 | (++) Communication Speed |
||
431 | (++) Duty cycle |
||
432 | (++) Addressing mode |
||
433 | (++) Own Address 1 |
||
434 | (++) Dual Addressing mode |
||
435 | (++) Own Address 2 |
||
436 | (++) General call mode |
||
437 | (++) Nostretch mode |
||
438 | |||
439 | (+) Call the function HAL_I2C_DeInit() to restore the default configuration |
||
440 | of the selected I2Cx peripheral. |
||
441 | |||
442 | @endverbatim |
||
443 | * @{ |
||
444 | */ |
||
445 | |||
446 | /** |
||
447 | * @brief Initializes the I2C according to the specified parameters |
||
448 | * in the I2C_InitTypeDef and initialize the associated handle. |
||
449 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
450 | * the configuration information for the specified I2C. |
||
451 | * @retval HAL status |
||
452 | */ |
||
453 | HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) |
||
454 | { |
||
455 | uint32_t freqrange; |
||
456 | uint32_t pclk1; |
||
457 | |||
458 | /* Check the I2C handle allocation */ |
||
459 | if (hi2c == NULL) |
||
460 | { |
||
461 | return HAL_ERROR; |
||
462 | } |
||
463 | |||
464 | /* Check the parameters */ |
||
465 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
||
466 | assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); |
||
467 | assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); |
||
468 | assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); |
||
469 | assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); |
||
470 | assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); |
||
471 | assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); |
||
472 | assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); |
||
473 | assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); |
||
474 | |||
475 | if (hi2c->State == HAL_I2C_STATE_RESET) |
||
476 | { |
||
477 | /* Allocate lock resource and initialize it */ |
||
478 | hi2c->Lock = HAL_UNLOCKED; |
||
479 | |||
480 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
481 | /* Init the I2C Callback settings */ |
||
482 | hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ |
||
483 | hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ |
||
484 | hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ |
||
485 | hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ |
||
486 | hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ |
||
487 | hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ |
||
488 | hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ |
||
489 | hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ |
||
490 | hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ |
||
491 | hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ |
||
492 | |||
493 | if (hi2c->MspInitCallback == NULL) |
||
494 | { |
||
495 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
||
496 | } |
||
497 | |||
498 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
||
499 | hi2c->MspInitCallback(hi2c); |
||
500 | #else |
||
501 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
||
502 | HAL_I2C_MspInit(hi2c); |
||
503 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
504 | } |
||
505 | |||
506 | hi2c->State = HAL_I2C_STATE_BUSY; |
||
507 | |||
508 | /* Disable the selected I2C peripheral */ |
||
509 | __HAL_I2C_DISABLE(hi2c); |
||
510 | |||
511 | /*Reset I2C*/ |
||
512 | hi2c->Instance->CR1 |= I2C_CR1_SWRST; |
||
513 | hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; |
||
514 | |||
515 | /* Get PCLK1 frequency */ |
||
516 | pclk1 = HAL_RCC_GetPCLK1Freq(); |
||
517 | |||
518 | /* Check the minimum allowed PCLK1 frequency */ |
||
519 | if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) |
||
520 | { |
||
521 | return HAL_ERROR; |
||
522 | } |
||
523 | |||
524 | /* Calculate frequency range */ |
||
525 | freqrange = I2C_FREQRANGE(pclk1); |
||
526 | |||
527 | /*---------------------------- I2Cx CR2 Configuration ----------------------*/ |
||
528 | /* Configure I2Cx: Frequency range */ |
||
529 | MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); |
||
530 | |||
531 | /*---------------------------- I2Cx TRISE Configuration --------------------*/ |
||
532 | /* Configure I2Cx: Rise Time */ |
||
533 | MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); |
||
534 | |||
535 | /*---------------------------- I2Cx CCR Configuration ----------------------*/ |
||
536 | /* Configure I2Cx: Speed */ |
||
537 | MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); |
||
538 | |||
539 | /*---------------------------- I2Cx CR1 Configuration ----------------------*/ |
||
540 | /* Configure I2Cx: Generalcall and NoStretch mode */ |
||
541 | MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); |
||
542 | |||
543 | /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ |
||
544 | /* Configure I2Cx: Own Address1 and addressing mode */ |
||
545 | MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); |
||
546 | |||
547 | /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ |
||
548 | /* Configure I2Cx: Dual mode and Own Address2 */ |
||
549 | MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); |
||
550 | |||
551 | /* Enable the selected I2C peripheral */ |
||
552 | __HAL_I2C_ENABLE(hi2c); |
||
553 | |||
554 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
555 | hi2c->State = HAL_I2C_STATE_READY; |
||
556 | hi2c->PreviousState = I2C_STATE_NONE; |
||
557 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
558 | |||
559 | return HAL_OK; |
||
560 | } |
||
561 | |||
562 | /** |
||
563 | * @brief DeInitialize the I2C peripheral. |
||
564 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
565 | * the configuration information for the specified I2C. |
||
566 | * @retval HAL status |
||
567 | */ |
||
568 | HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) |
||
569 | { |
||
570 | /* Check the I2C handle allocation */ |
||
571 | if (hi2c == NULL) |
||
572 | { |
||
573 | return HAL_ERROR; |
||
574 | } |
||
575 | |||
576 | /* Check the parameters */ |
||
577 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
||
578 | |||
579 | hi2c->State = HAL_I2C_STATE_BUSY; |
||
580 | |||
581 | /* Disable the I2C Peripheral Clock */ |
||
582 | __HAL_I2C_DISABLE(hi2c); |
||
583 | |||
584 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
585 | if (hi2c->MspDeInitCallback == NULL) |
||
586 | { |
||
587 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
||
588 | } |
||
589 | |||
590 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
||
591 | hi2c->MspDeInitCallback(hi2c); |
||
592 | #else |
||
593 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
||
594 | HAL_I2C_MspDeInit(hi2c); |
||
595 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
596 | |||
597 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
598 | hi2c->State = HAL_I2C_STATE_RESET; |
||
599 | hi2c->PreviousState = I2C_STATE_NONE; |
||
600 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
601 | |||
602 | /* Release Lock */ |
||
603 | __HAL_UNLOCK(hi2c); |
||
604 | |||
605 | return HAL_OK; |
||
606 | } |
||
607 | |||
608 | /** |
||
609 | * @brief Initialize the I2C MSP. |
||
610 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
611 | * the configuration information for the specified I2C. |
||
612 | * @retval None |
||
613 | */ |
||
614 | __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) |
||
615 | { |
||
616 | /* Prevent unused argument(s) compilation warning */ |
||
617 | UNUSED(hi2c); |
||
618 | |||
619 | /* NOTE : This function should not be modified, when the callback is needed, |
||
620 | the HAL_I2C_MspInit could be implemented in the user file |
||
621 | */ |
||
622 | } |
||
623 | |||
624 | /** |
||
625 | * @brief DeInitialize the I2C MSP. |
||
626 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
627 | * the configuration information for the specified I2C. |
||
628 | * @retval None |
||
629 | */ |
||
630 | __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) |
||
631 | { |
||
632 | /* Prevent unused argument(s) compilation warning */ |
||
633 | UNUSED(hi2c); |
||
634 | |||
635 | /* NOTE : This function should not be modified, when the callback is needed, |
||
636 | the HAL_I2C_MspDeInit could be implemented in the user file |
||
637 | */ |
||
638 | } |
||
639 | |||
640 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
641 | /** |
||
642 | * @brief Register a User I2C Callback |
||
643 | * To be used instead of the weak predefined callback |
||
644 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
645 | * the configuration information for the specified I2C. |
||
646 | * @param CallbackID ID of the callback to be registered |
||
647 | * This parameter can be one of the following values: |
||
648 | * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID |
||
649 | * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID |
||
650 | * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID |
||
651 | * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID |
||
652 | * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID |
||
653 | * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID |
||
654 | * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID |
||
655 | * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID |
||
656 | * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID |
||
657 | * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID |
||
658 | * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID |
||
659 | * @param pCallback pointer to the Callback function |
||
660 | * @retval HAL status |
||
661 | */ |
||
662 | HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) |
||
663 | { |
||
664 | HAL_StatusTypeDef status = HAL_OK; |
||
665 | |||
666 | if (pCallback == NULL) |
||
667 | { |
||
668 | /* Update the error code */ |
||
669 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
670 | |||
671 | return HAL_ERROR; |
||
672 | } |
||
673 | /* Process locked */ |
||
674 | __HAL_LOCK(hi2c); |
||
675 | |||
676 | if (HAL_I2C_STATE_READY == hi2c->State) |
||
677 | { |
||
678 | switch (CallbackID) |
||
679 | { |
||
680 | case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : |
||
681 | hi2c->MasterTxCpltCallback = pCallback; |
||
682 | break; |
||
683 | |||
684 | case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : |
||
685 | hi2c->MasterRxCpltCallback = pCallback; |
||
686 | break; |
||
687 | |||
688 | case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : |
||
689 | hi2c->SlaveTxCpltCallback = pCallback; |
||
690 | break; |
||
691 | |||
692 | case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : |
||
693 | hi2c->SlaveRxCpltCallback = pCallback; |
||
694 | break; |
||
695 | |||
696 | case HAL_I2C_LISTEN_COMPLETE_CB_ID : |
||
697 | hi2c->ListenCpltCallback = pCallback; |
||
698 | break; |
||
699 | |||
700 | case HAL_I2C_MEM_TX_COMPLETE_CB_ID : |
||
701 | hi2c->MemTxCpltCallback = pCallback; |
||
702 | break; |
||
703 | |||
704 | case HAL_I2C_MEM_RX_COMPLETE_CB_ID : |
||
705 | hi2c->MemRxCpltCallback = pCallback; |
||
706 | break; |
||
707 | |||
708 | case HAL_I2C_ERROR_CB_ID : |
||
709 | hi2c->ErrorCallback = pCallback; |
||
710 | break; |
||
711 | |||
712 | case HAL_I2C_ABORT_CB_ID : |
||
713 | hi2c->AbortCpltCallback = pCallback; |
||
714 | break; |
||
715 | |||
716 | case HAL_I2C_MSPINIT_CB_ID : |
||
717 | hi2c->MspInitCallback = pCallback; |
||
718 | break; |
||
719 | |||
720 | case HAL_I2C_MSPDEINIT_CB_ID : |
||
721 | hi2c->MspDeInitCallback = pCallback; |
||
722 | break; |
||
723 | |||
724 | default : |
||
725 | /* Update the error code */ |
||
726 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
727 | |||
728 | /* Return error status */ |
||
729 | status = HAL_ERROR; |
||
730 | break; |
||
731 | } |
||
732 | } |
||
733 | else if (HAL_I2C_STATE_RESET == hi2c->State) |
||
734 | { |
||
735 | switch (CallbackID) |
||
736 | { |
||
737 | case HAL_I2C_MSPINIT_CB_ID : |
||
738 | hi2c->MspInitCallback = pCallback; |
||
739 | break; |
||
740 | |||
741 | case HAL_I2C_MSPDEINIT_CB_ID : |
||
742 | hi2c->MspDeInitCallback = pCallback; |
||
743 | break; |
||
744 | |||
745 | default : |
||
746 | /* Update the error code */ |
||
747 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
748 | |||
749 | /* Return error status */ |
||
750 | status = HAL_ERROR; |
||
751 | break; |
||
752 | } |
||
753 | } |
||
754 | else |
||
755 | { |
||
756 | /* Update the error code */ |
||
757 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
758 | |||
759 | /* Return error status */ |
||
760 | status = HAL_ERROR; |
||
761 | } |
||
762 | |||
763 | /* Release Lock */ |
||
764 | __HAL_UNLOCK(hi2c); |
||
765 | return status; |
||
766 | } |
||
767 | |||
768 | /** |
||
769 | * @brief Unregister an I2C Callback |
||
770 | * I2C callback is redirected to the weak predefined callback |
||
771 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
772 | * the configuration information for the specified I2C. |
||
773 | * @param CallbackID ID of the callback to be unregistered |
||
774 | * This parameter can be one of the following values: |
||
775 | * This parameter can be one of the following values: |
||
776 | * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID |
||
777 | * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID |
||
778 | * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID |
||
779 | * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID |
||
780 | * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID |
||
781 | * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID |
||
782 | * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID |
||
783 | * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID |
||
784 | * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID |
||
785 | * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID |
||
786 | * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID |
||
787 | * @retval HAL status |
||
788 | */ |
||
789 | HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) |
||
790 | { |
||
791 | HAL_StatusTypeDef status = HAL_OK; |
||
792 | |||
793 | /* Process locked */ |
||
794 | __HAL_LOCK(hi2c); |
||
795 | |||
796 | if (HAL_I2C_STATE_READY == hi2c->State) |
||
797 | { |
||
798 | switch (CallbackID) |
||
799 | { |
||
800 | case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : |
||
801 | hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ |
||
802 | break; |
||
803 | |||
804 | case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : |
||
805 | hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ |
||
806 | break; |
||
807 | |||
808 | case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : |
||
809 | hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ |
||
810 | break; |
||
811 | |||
812 | case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : |
||
813 | hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ |
||
814 | break; |
||
815 | |||
816 | case HAL_I2C_LISTEN_COMPLETE_CB_ID : |
||
817 | hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ |
||
818 | break; |
||
819 | |||
820 | case HAL_I2C_MEM_TX_COMPLETE_CB_ID : |
||
821 | hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ |
||
822 | break; |
||
823 | |||
824 | case HAL_I2C_MEM_RX_COMPLETE_CB_ID : |
||
825 | hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ |
||
826 | break; |
||
827 | |||
828 | case HAL_I2C_ERROR_CB_ID : |
||
829 | hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ |
||
830 | break; |
||
831 | |||
832 | case HAL_I2C_ABORT_CB_ID : |
||
833 | hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ |
||
834 | break; |
||
835 | |||
836 | case HAL_I2C_MSPINIT_CB_ID : |
||
837 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
||
838 | break; |
||
839 | |||
840 | case HAL_I2C_MSPDEINIT_CB_ID : |
||
841 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
||
842 | break; |
||
843 | |||
844 | default : |
||
845 | /* Update the error code */ |
||
846 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
847 | |||
848 | /* Return error status */ |
||
849 | status = HAL_ERROR; |
||
850 | break; |
||
851 | } |
||
852 | } |
||
853 | else if (HAL_I2C_STATE_RESET == hi2c->State) |
||
854 | { |
||
855 | switch (CallbackID) |
||
856 | { |
||
857 | case HAL_I2C_MSPINIT_CB_ID : |
||
858 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
||
859 | break; |
||
860 | |||
861 | case HAL_I2C_MSPDEINIT_CB_ID : |
||
862 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
||
863 | break; |
||
864 | |||
865 | default : |
||
866 | /* Update the error code */ |
||
867 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
868 | |||
869 | /* Return error status */ |
||
870 | status = HAL_ERROR; |
||
871 | break; |
||
872 | } |
||
873 | } |
||
874 | else |
||
875 | { |
||
876 | /* Update the error code */ |
||
877 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
878 | |||
879 | /* Return error status */ |
||
880 | status = HAL_ERROR; |
||
881 | } |
||
882 | |||
883 | /* Release Lock */ |
||
884 | __HAL_UNLOCK(hi2c); |
||
885 | return status; |
||
886 | } |
||
887 | |||
888 | /** |
||
889 | * @brief Register the Slave Address Match I2C Callback |
||
890 | * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback |
||
891 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
892 | * the configuration information for the specified I2C. |
||
893 | * @param pCallback pointer to the Address Match Callback function |
||
894 | * @retval HAL status |
||
895 | */ |
||
896 | HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) |
||
897 | { |
||
898 | HAL_StatusTypeDef status = HAL_OK; |
||
899 | |||
900 | if (pCallback == NULL) |
||
901 | { |
||
902 | /* Update the error code */ |
||
903 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
904 | |||
905 | return HAL_ERROR; |
||
906 | } |
||
907 | /* Process locked */ |
||
908 | __HAL_LOCK(hi2c); |
||
909 | |||
910 | if (HAL_I2C_STATE_READY == hi2c->State) |
||
911 | { |
||
912 | hi2c->AddrCallback = pCallback; |
||
913 | } |
||
914 | else |
||
915 | { |
||
916 | /* Update the error code */ |
||
917 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
918 | |||
919 | /* Return error status */ |
||
920 | status = HAL_ERROR; |
||
921 | } |
||
922 | |||
923 | /* Release Lock */ |
||
924 | __HAL_UNLOCK(hi2c); |
||
925 | return status; |
||
926 | } |
||
927 | |||
928 | /** |
||
929 | * @brief UnRegister the Slave Address Match I2C Callback |
||
930 | * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback |
||
931 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
932 | * the configuration information for the specified I2C. |
||
933 | * @retval HAL status |
||
934 | */ |
||
935 | HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) |
||
936 | { |
||
937 | HAL_StatusTypeDef status = HAL_OK; |
||
938 | |||
939 | /* Process locked */ |
||
940 | __HAL_LOCK(hi2c); |
||
941 | |||
942 | if (HAL_I2C_STATE_READY == hi2c->State) |
||
943 | { |
||
944 | hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ |
||
945 | } |
||
946 | else |
||
947 | { |
||
948 | /* Update the error code */ |
||
949 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
950 | |||
951 | /* Return error status */ |
||
952 | status = HAL_ERROR; |
||
953 | } |
||
954 | |||
955 | /* Release Lock */ |
||
956 | __HAL_UNLOCK(hi2c); |
||
957 | return status; |
||
958 | } |
||
959 | |||
960 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
961 | |||
962 | /** |
||
963 | * @} |
||
964 | */ |
||
965 | |||
966 | /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions |
||
967 | * @brief Data transfers functions |
||
968 | * |
||
969 | @verbatim |
||
970 | =============================================================================== |
||
971 | ##### IO operation functions ##### |
||
972 | =============================================================================== |
||
973 | [..] |
||
974 | This subsection provides a set of functions allowing to manage the I2C data |
||
975 | transfers. |
||
976 | |||
977 | (#) There are two modes of transfer: |
||
978 | (++) Blocking mode : The communication is performed in the polling mode. |
||
979 | The status of all data processing is returned by the same function |
||
980 | after finishing transfer. |
||
981 | (++) No-Blocking mode : The communication is performed using Interrupts |
||
982 | or DMA. These functions return the status of the transfer startup. |
||
983 | The end of the data processing will be indicated through the |
||
984 | dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when |
||
985 | using DMA mode. |
||
986 | |||
987 | (#) Blocking mode functions are : |
||
988 | (++) HAL_I2C_Master_Transmit() |
||
989 | (++) HAL_I2C_Master_Receive() |
||
990 | (++) HAL_I2C_Slave_Transmit() |
||
991 | (++) HAL_I2C_Slave_Receive() |
||
992 | (++) HAL_I2C_Mem_Write() |
||
993 | (++) HAL_I2C_Mem_Read() |
||
994 | (++) HAL_I2C_IsDeviceReady() |
||
995 | |||
996 | (#) No-Blocking mode functions with Interrupt are : |
||
997 | (++) HAL_I2C_Master_Transmit_IT() |
||
998 | (++) HAL_I2C_Master_Receive_IT() |
||
999 | (++) HAL_I2C_Slave_Transmit_IT() |
||
1000 | (++) HAL_I2C_Slave_Receive_IT() |
||
1001 | (++) HAL_I2C_Mem_Write_IT() |
||
1002 | (++) HAL_I2C_Mem_Read_IT() |
||
1003 | (++) HAL_I2C_Master_Seq_Transmit_IT() |
||
1004 | (++) HAL_I2C_Master_Seq_Receive_IT() |
||
1005 | (++) HAL_I2C_Slave_Seq_Transmit_IT() |
||
1006 | (++) HAL_I2C_Slave_Seq_Receive_IT() |
||
1007 | (++) HAL_I2C_EnableListen_IT() |
||
1008 | (++) HAL_I2C_DisableListen_IT() |
||
1009 | (++) HAL_I2C_Master_Abort_IT() |
||
1010 | |||
1011 | (#) No-Blocking mode functions with DMA are : |
||
1012 | (++) HAL_I2C_Master_Transmit_DMA() |
||
1013 | (++) HAL_I2C_Master_Receive_DMA() |
||
1014 | (++) HAL_I2C_Slave_Transmit_DMA() |
||
1015 | (++) HAL_I2C_Slave_Receive_DMA() |
||
1016 | (++) HAL_I2C_Mem_Write_DMA() |
||
1017 | (++) HAL_I2C_Mem_Read_DMA() |
||
1018 | (++) HAL_I2C_Master_Seq_Transmit_DMA() |
||
1019 | (++) HAL_I2C_Master_Seq_Receive_DMA() |
||
1020 | (++) HAL_I2C_Slave_Seq_Transmit_DMA() |
||
1021 | (++) HAL_I2C_Slave_Seq_Receive_DMA() |
||
1022 | |||
1023 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
||
1024 | (++) HAL_I2C_MasterTxCpltCallback() |
||
1025 | (++) HAL_I2C_MasterRxCpltCallback() |
||
1026 | (++) HAL_I2C_SlaveTxCpltCallback() |
||
1027 | (++) HAL_I2C_SlaveRxCpltCallback() |
||
1028 | (++) HAL_I2C_MemTxCpltCallback() |
||
1029 | (++) HAL_I2C_MemRxCpltCallback() |
||
1030 | (++) HAL_I2C_AddrCallback() |
||
1031 | (++) HAL_I2C_ListenCpltCallback() |
||
1032 | (++) HAL_I2C_ErrorCallback() |
||
1033 | (++) HAL_I2C_AbortCpltCallback() |
||
1034 | |||
1035 | @endverbatim |
||
1036 | * @{ |
||
1037 | */ |
||
1038 | |||
1039 | /** |
||
1040 | * @brief Transmits in master mode an amount of data in blocking mode. |
||
1041 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1042 | * the configuration information for the specified I2C. |
||
1043 | * @param DevAddress Target device address: The device 7 bits address value |
||
1044 | * in datasheet must be shifted to the left before calling the interface |
||
1045 | * @param pData Pointer to data buffer |
||
1046 | * @param Size Amount of data to be sent |
||
1047 | * @param Timeout Timeout duration |
||
1048 | * @retval HAL status |
||
1049 | */ |
||
1050 | HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
1051 | { |
||
1052 | /* Init tickstart for timeout management*/ |
||
1053 | uint32_t tickstart = HAL_GetTick(); |
||
1054 | |||
1055 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1056 | { |
||
1057 | /* Wait until BUSY flag is reset */ |
||
1058 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
1059 | { |
||
1060 | return HAL_BUSY; |
||
1061 | } |
||
1062 | |||
1063 | /* Process Locked */ |
||
1064 | __HAL_LOCK(hi2c); |
||
1065 | |||
1066 | /* Check if the I2C is already enabled */ |
||
1067 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1068 | { |
||
1069 | /* Enable I2C peripheral */ |
||
1070 | __HAL_I2C_ENABLE(hi2c); |
||
1071 | } |
||
1072 | |||
1073 | /* Disable Pos */ |
||
1074 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1075 | |||
1076 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
1077 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
1078 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1079 | |||
1080 | /* Prepare transfer parameters */ |
||
1081 | hi2c->pBuffPtr = pData; |
||
1082 | hi2c->XferCount = Size; |
||
1083 | hi2c->XferSize = hi2c->XferCount; |
||
1084 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1085 | |||
1086 | /* Send Slave Address */ |
||
1087 | if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
||
1088 | { |
||
1089 | return HAL_ERROR; |
||
1090 | } |
||
1091 | |||
1092 | /* Clear ADDR flag */ |
||
1093 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1094 | |||
1095 | while (hi2c->XferSize > 0U) |
||
1096 | { |
||
1097 | /* Wait until TXE flag is set */ |
||
1098 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1099 | { |
||
1100 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
1101 | { |
||
1102 | /* Generate Stop */ |
||
1103 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1104 | } |
||
1105 | return HAL_ERROR; |
||
1106 | } |
||
1107 | |||
1108 | /* Write data to DR */ |
||
1109 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
1110 | |||
1111 | /* Increment Buffer pointer */ |
||
1112 | hi2c->pBuffPtr++; |
||
1113 | |||
1114 | /* Update counter */ |
||
1115 | hi2c->XferCount--; |
||
1116 | hi2c->XferSize--; |
||
1117 | |||
1118 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
1119 | { |
||
1120 | /* Write data to DR */ |
||
1121 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
1122 | |||
1123 | /* Increment Buffer pointer */ |
||
1124 | hi2c->pBuffPtr++; |
||
1125 | |||
1126 | /* Update counter */ |
||
1127 | hi2c->XferCount--; |
||
1128 | hi2c->XferSize--; |
||
1129 | } |
||
1130 | |||
1131 | /* Wait until BTF flag is set */ |
||
1132 | if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1133 | { |
||
1134 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
1135 | { |
||
1136 | /* Generate Stop */ |
||
1137 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1138 | } |
||
1139 | return HAL_ERROR; |
||
1140 | } |
||
1141 | } |
||
1142 | |||
1143 | /* Generate Stop */ |
||
1144 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1145 | |||
1146 | hi2c->State = HAL_I2C_STATE_READY; |
||
1147 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1148 | |||
1149 | /* Process Unlocked */ |
||
1150 | __HAL_UNLOCK(hi2c); |
||
1151 | |||
1152 | return HAL_OK; |
||
1153 | } |
||
1154 | else |
||
1155 | { |
||
1156 | return HAL_BUSY; |
||
1157 | } |
||
1158 | } |
||
1159 | |||
1160 | /** |
||
1161 | * @brief Receives in master mode an amount of data in blocking mode. |
||
1162 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1163 | * the configuration information for the specified I2C. |
||
1164 | * @param DevAddress Target device address: The device 7 bits address value |
||
1165 | * in datasheet must be shifted to the left before calling the interface |
||
1166 | * @param pData Pointer to data buffer |
||
1167 | * @param Size Amount of data to be sent |
||
1168 | * @param Timeout Timeout duration |
||
1169 | * @retval HAL status |
||
1170 | */ |
||
1171 | HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
1172 | { |
||
1173 | __IO uint32_t count = 0U; |
||
1174 | |||
1175 | /* Init tickstart for timeout management*/ |
||
1176 | uint32_t tickstart = HAL_GetTick(); |
||
1177 | |||
1178 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1179 | { |
||
1180 | /* Wait until BUSY flag is reset */ |
||
1181 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
1182 | { |
||
1183 | return HAL_BUSY; |
||
1184 | } |
||
1185 | |||
1186 | /* Process Locked */ |
||
1187 | __HAL_LOCK(hi2c); |
||
1188 | |||
1189 | /* Check if the I2C is already enabled */ |
||
1190 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1191 | { |
||
1192 | /* Enable I2C peripheral */ |
||
1193 | __HAL_I2C_ENABLE(hi2c); |
||
1194 | } |
||
1195 | |||
1196 | /* Disable Pos */ |
||
1197 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1198 | |||
1199 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
1200 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
1201 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1202 | |||
1203 | /* Prepare transfer parameters */ |
||
1204 | hi2c->pBuffPtr = pData; |
||
1205 | hi2c->XferCount = Size; |
||
1206 | hi2c->XferSize = hi2c->XferCount; |
||
1207 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1208 | |||
1209 | /* Send Slave Address */ |
||
1210 | if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
||
1211 | { |
||
1212 | return HAL_ERROR; |
||
1213 | } |
||
1214 | |||
1215 | if (hi2c->XferSize == 0U) |
||
1216 | { |
||
1217 | /* Clear ADDR flag */ |
||
1218 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1219 | |||
1220 | /* Generate Stop */ |
||
1221 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1222 | } |
||
1223 | else if (hi2c->XferSize == 1U) |
||
1224 | { |
||
1225 | /* Disable Acknowledge */ |
||
1226 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1227 | |||
1228 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
1229 | software sequence must complete before the current byte end of transfer */ |
||
1230 | __disable_irq(); |
||
1231 | |||
1232 | /* Clear ADDR flag */ |
||
1233 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1234 | |||
1235 | /* Generate Stop */ |
||
1236 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1237 | |||
1238 | /* Re-enable IRQs */ |
||
1239 | __enable_irq(); |
||
1240 | } |
||
1241 | else if (hi2c->XferSize == 2U) |
||
1242 | { |
||
1243 | /* Enable Pos */ |
||
1244 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1245 | |||
1246 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
1247 | software sequence must complete before the current byte end of transfer */ |
||
1248 | __disable_irq(); |
||
1249 | |||
1250 | /* Clear ADDR flag */ |
||
1251 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1252 | |||
1253 | /* Disable Acknowledge */ |
||
1254 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1255 | |||
1256 | /* Re-enable IRQs */ |
||
1257 | __enable_irq(); |
||
1258 | } |
||
1259 | else |
||
1260 | { |
||
1261 | /* Enable Acknowledge */ |
||
1262 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1263 | |||
1264 | /* Clear ADDR flag */ |
||
1265 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1266 | } |
||
1267 | |||
1268 | while (hi2c->XferSize > 0U) |
||
1269 | { |
||
1270 | if (hi2c->XferSize <= 3U) |
||
1271 | { |
||
1272 | /* One byte */ |
||
1273 | if (hi2c->XferSize == 1U) |
||
1274 | { |
||
1275 | /* Wait until RXNE flag is set */ |
||
1276 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1277 | { |
||
1278 | return HAL_ERROR; |
||
1279 | } |
||
1280 | |||
1281 | /* Read data from DR */ |
||
1282 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1283 | |||
1284 | /* Increment Buffer pointer */ |
||
1285 | hi2c->pBuffPtr++; |
||
1286 | |||
1287 | /* Update counter */ |
||
1288 | hi2c->XferSize--; |
||
1289 | hi2c->XferCount--; |
||
1290 | } |
||
1291 | /* Two bytes */ |
||
1292 | else if (hi2c->XferSize == 2U) |
||
1293 | { |
||
1294 | /* Wait until BTF flag is set */ |
||
1295 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
1296 | { |
||
1297 | return HAL_ERROR; |
||
1298 | } |
||
1299 | |||
1300 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
1301 | software sequence must complete before the current byte end of transfer */ |
||
1302 | __disable_irq(); |
||
1303 | |||
1304 | /* Generate Stop */ |
||
1305 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1306 | |||
1307 | /* Read data from DR */ |
||
1308 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1309 | |||
1310 | /* Increment Buffer pointer */ |
||
1311 | hi2c->pBuffPtr++; |
||
1312 | |||
1313 | /* Update counter */ |
||
1314 | hi2c->XferSize--; |
||
1315 | hi2c->XferCount--; |
||
1316 | |||
1317 | /* Re-enable IRQs */ |
||
1318 | __enable_irq(); |
||
1319 | |||
1320 | /* Read data from DR */ |
||
1321 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1322 | |||
1323 | /* Increment Buffer pointer */ |
||
1324 | hi2c->pBuffPtr++; |
||
1325 | |||
1326 | /* Update counter */ |
||
1327 | hi2c->XferSize--; |
||
1328 | hi2c->XferCount--; |
||
1329 | } |
||
1330 | /* 3 Last bytes */ |
||
1331 | else |
||
1332 | { |
||
1333 | /* Wait until BTF flag is set */ |
||
1334 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
1335 | { |
||
1336 | return HAL_ERROR; |
||
1337 | } |
||
1338 | |||
1339 | /* Disable Acknowledge */ |
||
1340 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1341 | |||
1342 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
1343 | software sequence must complete before the current byte end of transfer */ |
||
1344 | __disable_irq(); |
||
1345 | |||
1346 | /* Read data from DR */ |
||
1347 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1348 | |||
1349 | /* Increment Buffer pointer */ |
||
1350 | hi2c->pBuffPtr++; |
||
1351 | |||
1352 | /* Update counter */ |
||
1353 | hi2c->XferSize--; |
||
1354 | hi2c->XferCount--; |
||
1355 | |||
1356 | /* Wait until BTF flag is set */ |
||
1357 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
||
1358 | do |
||
1359 | { |
||
1360 | count--; |
||
1361 | if (count == 0U) |
||
1362 | { |
||
1363 | hi2c->PreviousState = I2C_STATE_NONE; |
||
1364 | hi2c->State = HAL_I2C_STATE_READY; |
||
1365 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1366 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
1367 | |||
1368 | /* Re-enable IRQs */ |
||
1369 | __enable_irq(); |
||
1370 | |||
1371 | /* Process Unlocked */ |
||
1372 | __HAL_UNLOCK(hi2c); |
||
1373 | |||
1374 | return HAL_ERROR; |
||
1375 | } |
||
1376 | } |
||
1377 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); |
||
1378 | |||
1379 | /* Generate Stop */ |
||
1380 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1381 | |||
1382 | /* Read data from DR */ |
||
1383 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1384 | |||
1385 | /* Increment Buffer pointer */ |
||
1386 | hi2c->pBuffPtr++; |
||
1387 | |||
1388 | /* Update counter */ |
||
1389 | hi2c->XferSize--; |
||
1390 | hi2c->XferCount--; |
||
1391 | |||
1392 | /* Re-enable IRQs */ |
||
1393 | __enable_irq(); |
||
1394 | |||
1395 | /* Read data from DR */ |
||
1396 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1397 | |||
1398 | /* Increment Buffer pointer */ |
||
1399 | hi2c->pBuffPtr++; |
||
1400 | |||
1401 | /* Update counter */ |
||
1402 | hi2c->XferSize--; |
||
1403 | hi2c->XferCount--; |
||
1404 | } |
||
1405 | } |
||
1406 | else |
||
1407 | { |
||
1408 | /* Wait until RXNE flag is set */ |
||
1409 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1410 | { |
||
1411 | return HAL_ERROR; |
||
1412 | } |
||
1413 | |||
1414 | /* Read data from DR */ |
||
1415 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1416 | |||
1417 | /* Increment Buffer pointer */ |
||
1418 | hi2c->pBuffPtr++; |
||
1419 | |||
1420 | /* Update counter */ |
||
1421 | hi2c->XferSize--; |
||
1422 | hi2c->XferCount--; |
||
1423 | |||
1424 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
||
1425 | { |
||
1426 | /* Read data from DR */ |
||
1427 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1428 | |||
1429 | /* Increment Buffer pointer */ |
||
1430 | hi2c->pBuffPtr++; |
||
1431 | |||
1432 | /* Update counter */ |
||
1433 | hi2c->XferSize--; |
||
1434 | hi2c->XferCount--; |
||
1435 | } |
||
1436 | } |
||
1437 | } |
||
1438 | |||
1439 | hi2c->State = HAL_I2C_STATE_READY; |
||
1440 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1441 | |||
1442 | /* Process Unlocked */ |
||
1443 | __HAL_UNLOCK(hi2c); |
||
1444 | |||
1445 | return HAL_OK; |
||
1446 | } |
||
1447 | else |
||
1448 | { |
||
1449 | return HAL_BUSY; |
||
1450 | } |
||
1451 | } |
||
1452 | |||
1453 | /** |
||
1454 | * @brief Transmits in slave mode an amount of data in blocking mode. |
||
1455 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1456 | * the configuration information for the specified I2C. |
||
1457 | * @param pData Pointer to data buffer |
||
1458 | * @param Size Amount of data to be sent |
||
1459 | * @param Timeout Timeout duration |
||
1460 | * @retval HAL status |
||
1461 | */ |
||
1462 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
1463 | { |
||
1464 | /* Init tickstart for timeout management*/ |
||
1465 | uint32_t tickstart = HAL_GetTick(); |
||
1466 | |||
1467 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1468 | { |
||
1469 | if ((pData == NULL) || (Size == 0U)) |
||
1470 | { |
||
1471 | return HAL_ERROR; |
||
1472 | } |
||
1473 | |||
1474 | /* Process Locked */ |
||
1475 | __HAL_LOCK(hi2c); |
||
1476 | |||
1477 | /* Check if the I2C is already enabled */ |
||
1478 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1479 | { |
||
1480 | /* Enable I2C peripheral */ |
||
1481 | __HAL_I2C_ENABLE(hi2c); |
||
1482 | } |
||
1483 | |||
1484 | /* Disable Pos */ |
||
1485 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1486 | |||
1487 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
1488 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
1489 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1490 | |||
1491 | /* Prepare transfer parameters */ |
||
1492 | hi2c->pBuffPtr = pData; |
||
1493 | hi2c->XferCount = Size; |
||
1494 | hi2c->XferSize = hi2c->XferCount; |
||
1495 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1496 | |||
1497 | /* Enable Address Acknowledge */ |
||
1498 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1499 | |||
1500 | /* Wait until ADDR flag is set */ |
||
1501 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
||
1502 | { |
||
1503 | return HAL_ERROR; |
||
1504 | } |
||
1505 | |||
1506 | /* Clear ADDR flag */ |
||
1507 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1508 | |||
1509 | /* If 10bit addressing mode is selected */ |
||
1510 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) |
||
1511 | { |
||
1512 | /* Wait until ADDR flag is set */ |
||
1513 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
||
1514 | { |
||
1515 | return HAL_ERROR; |
||
1516 | } |
||
1517 | |||
1518 | /* Clear ADDR flag */ |
||
1519 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1520 | } |
||
1521 | |||
1522 | while (hi2c->XferSize > 0U) |
||
1523 | { |
||
1524 | /* Wait until TXE flag is set */ |
||
1525 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1526 | { |
||
1527 | /* Disable Address Acknowledge */ |
||
1528 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1529 | |||
1530 | return HAL_ERROR; |
||
1531 | } |
||
1532 | |||
1533 | /* Write data to DR */ |
||
1534 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
1535 | |||
1536 | /* Increment Buffer pointer */ |
||
1537 | hi2c->pBuffPtr++; |
||
1538 | |||
1539 | /* Update counter */ |
||
1540 | hi2c->XferCount--; |
||
1541 | hi2c->XferSize--; |
||
1542 | |||
1543 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
1544 | { |
||
1545 | /* Write data to DR */ |
||
1546 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
1547 | |||
1548 | /* Increment Buffer pointer */ |
||
1549 | hi2c->pBuffPtr++; |
||
1550 | |||
1551 | /* Update counter */ |
||
1552 | hi2c->XferCount--; |
||
1553 | hi2c->XferSize--; |
||
1554 | } |
||
1555 | } |
||
1556 | |||
1557 | /* Wait until AF flag is set */ |
||
1558 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) |
||
1559 | { |
||
1560 | return HAL_ERROR; |
||
1561 | } |
||
1562 | |||
1563 | /* Clear AF flag */ |
||
1564 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
1565 | |||
1566 | /* Disable Address Acknowledge */ |
||
1567 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1568 | |||
1569 | hi2c->State = HAL_I2C_STATE_READY; |
||
1570 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1571 | |||
1572 | /* Process Unlocked */ |
||
1573 | __HAL_UNLOCK(hi2c); |
||
1574 | |||
1575 | return HAL_OK; |
||
1576 | } |
||
1577 | else |
||
1578 | { |
||
1579 | return HAL_BUSY; |
||
1580 | } |
||
1581 | } |
||
1582 | |||
1583 | /** |
||
1584 | * @brief Receive in slave mode an amount of data in blocking mode |
||
1585 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1586 | * the configuration information for the specified I2C. |
||
1587 | * @param pData Pointer to data buffer |
||
1588 | * @param Size Amount of data to be sent |
||
1589 | * @param Timeout Timeout duration |
||
1590 | * @retval HAL status |
||
1591 | */ |
||
1592 | HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
1593 | { |
||
1594 | /* Init tickstart for timeout management*/ |
||
1595 | uint32_t tickstart = HAL_GetTick(); |
||
1596 | |||
1597 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1598 | { |
||
1599 | if ((pData == NULL) || (Size == (uint16_t)0)) |
||
1600 | { |
||
1601 | return HAL_ERROR; |
||
1602 | } |
||
1603 | |||
1604 | /* Process Locked */ |
||
1605 | __HAL_LOCK(hi2c); |
||
1606 | |||
1607 | /* Check if the I2C is already enabled */ |
||
1608 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1609 | { |
||
1610 | /* Enable I2C peripheral */ |
||
1611 | __HAL_I2C_ENABLE(hi2c); |
||
1612 | } |
||
1613 | |||
1614 | /* Disable Pos */ |
||
1615 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1616 | |||
1617 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
1618 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
1619 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1620 | |||
1621 | /* Prepare transfer parameters */ |
||
1622 | hi2c->pBuffPtr = pData; |
||
1623 | hi2c->XferCount = Size; |
||
1624 | hi2c->XferSize = hi2c->XferCount; |
||
1625 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1626 | |||
1627 | /* Enable Address Acknowledge */ |
||
1628 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1629 | |||
1630 | /* Wait until ADDR flag is set */ |
||
1631 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
||
1632 | { |
||
1633 | return HAL_ERROR; |
||
1634 | } |
||
1635 | |||
1636 | /* Clear ADDR flag */ |
||
1637 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1638 | |||
1639 | while (hi2c->XferSize > 0U) |
||
1640 | { |
||
1641 | /* Wait until RXNE flag is set */ |
||
1642 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1643 | { |
||
1644 | /* Disable Address Acknowledge */ |
||
1645 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1646 | |||
1647 | return HAL_ERROR; |
||
1648 | } |
||
1649 | |||
1650 | /* Read data from DR */ |
||
1651 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1652 | |||
1653 | /* Increment Buffer pointer */ |
||
1654 | hi2c->pBuffPtr++; |
||
1655 | |||
1656 | /* Update counter */ |
||
1657 | hi2c->XferSize--; |
||
1658 | hi2c->XferCount--; |
||
1659 | |||
1660 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
1661 | { |
||
1662 | /* Read data from DR */ |
||
1663 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1664 | |||
1665 | /* Increment Buffer pointer */ |
||
1666 | hi2c->pBuffPtr++; |
||
1667 | |||
1668 | /* Update counter */ |
||
1669 | hi2c->XferSize--; |
||
1670 | hi2c->XferCount--; |
||
1671 | } |
||
1672 | } |
||
1673 | |||
1674 | /* Wait until STOP flag is set */ |
||
1675 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1676 | { |
||
1677 | /* Disable Address Acknowledge */ |
||
1678 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1679 | |||
1680 | return HAL_ERROR; |
||
1681 | } |
||
1682 | |||
1683 | /* Clear STOP flag */ |
||
1684 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
||
1685 | |||
1686 | /* Disable Address Acknowledge */ |
||
1687 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1688 | |||
1689 | hi2c->State = HAL_I2C_STATE_READY; |
||
1690 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1691 | |||
1692 | /* Process Unlocked */ |
||
1693 | __HAL_UNLOCK(hi2c); |
||
1694 | |||
1695 | return HAL_OK; |
||
1696 | } |
||
1697 | else |
||
1698 | { |
||
1699 | return HAL_BUSY; |
||
1700 | } |
||
1701 | } |
||
1702 | |||
1703 | /** |
||
1704 | * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt |
||
1705 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1706 | * the configuration information for the specified I2C. |
||
1707 | * @param DevAddress Target device address: The device 7 bits address value |
||
1708 | * in datasheet must be shifted to the left before calling the interface |
||
1709 | * @param pData Pointer to data buffer |
||
1710 | * @param Size Amount of data to be sent |
||
1711 | * @retval HAL status |
||
1712 | */ |
||
1713 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
1714 | { |
||
1715 | __IO uint32_t count = 0U; |
||
1716 | |||
1717 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1718 | { |
||
1719 | /* Wait until BUSY flag is reset */ |
||
1720 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
1721 | do |
||
1722 | { |
||
1723 | count--; |
||
1724 | if (count == 0U) |
||
1725 | { |
||
1726 | hi2c->PreviousState = I2C_STATE_NONE; |
||
1727 | hi2c->State = HAL_I2C_STATE_READY; |
||
1728 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1729 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
1730 | |||
1731 | /* Process Unlocked */ |
||
1732 | __HAL_UNLOCK(hi2c); |
||
1733 | |||
1734 | return HAL_ERROR; |
||
1735 | } |
||
1736 | } |
||
1737 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
1738 | |||
1739 | /* Process Locked */ |
||
1740 | __HAL_LOCK(hi2c); |
||
1741 | |||
1742 | /* Check if the I2C is already enabled */ |
||
1743 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1744 | { |
||
1745 | /* Enable I2C peripheral */ |
||
1746 | __HAL_I2C_ENABLE(hi2c); |
||
1747 | } |
||
1748 | |||
1749 | /* Disable Pos */ |
||
1750 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1751 | |||
1752 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
1753 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
1754 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1755 | |||
1756 | /* Prepare transfer parameters */ |
||
1757 | hi2c->pBuffPtr = pData; |
||
1758 | hi2c->XferCount = Size; |
||
1759 | hi2c->XferSize = hi2c->XferCount; |
||
1760 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1761 | hi2c->Devaddress = DevAddress; |
||
1762 | |||
1763 | /* Process Unlocked */ |
||
1764 | __HAL_UNLOCK(hi2c); |
||
1765 | |||
1766 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
1767 | to avoid the risk of I2C interrupt handle execution before current |
||
1768 | process unlock */ |
||
1769 | /* Enable EVT, BUF and ERR interrupt */ |
||
1770 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
1771 | |||
1772 | /* Generate Start */ |
||
1773 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
1774 | |||
1775 | return HAL_OK; |
||
1776 | } |
||
1777 | else |
||
1778 | { |
||
1779 | return HAL_BUSY; |
||
1780 | } |
||
1781 | } |
||
1782 | |||
1783 | /** |
||
1784 | * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt |
||
1785 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1786 | * the configuration information for the specified I2C. |
||
1787 | * @param DevAddress Target device address: The device 7 bits address value |
||
1788 | * in datasheet must be shifted to the left before calling the interface |
||
1789 | * @param pData Pointer to data buffer |
||
1790 | * @param Size Amount of data to be sent |
||
1791 | * @retval HAL status |
||
1792 | */ |
||
1793 | HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
1794 | { |
||
1795 | __IO uint32_t count = 0U; |
||
1796 | |||
1797 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1798 | { |
||
1799 | /* Wait until BUSY flag is reset */ |
||
1800 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
1801 | do |
||
1802 | { |
||
1803 | count--; |
||
1804 | if (count == 0U) |
||
1805 | { |
||
1806 | hi2c->PreviousState = I2C_STATE_NONE; |
||
1807 | hi2c->State = HAL_I2C_STATE_READY; |
||
1808 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1809 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
1810 | |||
1811 | /* Process Unlocked */ |
||
1812 | __HAL_UNLOCK(hi2c); |
||
1813 | |||
1814 | return HAL_ERROR; |
||
1815 | } |
||
1816 | } |
||
1817 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
1818 | |||
1819 | /* Process Locked */ |
||
1820 | __HAL_LOCK(hi2c); |
||
1821 | |||
1822 | /* Check if the I2C is already enabled */ |
||
1823 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1824 | { |
||
1825 | /* Enable I2C peripheral */ |
||
1826 | __HAL_I2C_ENABLE(hi2c); |
||
1827 | } |
||
1828 | |||
1829 | /* Disable Pos */ |
||
1830 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1831 | |||
1832 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
1833 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
1834 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1835 | |||
1836 | /* Prepare transfer parameters */ |
||
1837 | hi2c->pBuffPtr = pData; |
||
1838 | hi2c->XferCount = Size; |
||
1839 | hi2c->XferSize = hi2c->XferCount; |
||
1840 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1841 | hi2c->Devaddress = DevAddress; |
||
1842 | |||
1843 | |||
1844 | /* Process Unlocked */ |
||
1845 | __HAL_UNLOCK(hi2c); |
||
1846 | |||
1847 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
1848 | to avoid the risk of I2C interrupt handle execution before current |
||
1849 | process unlock */ |
||
1850 | |||
1851 | /* Enable EVT, BUF and ERR interrupt */ |
||
1852 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
1853 | |||
1854 | /* Enable Acknowledge */ |
||
1855 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1856 | |||
1857 | /* Generate Start */ |
||
1858 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
1859 | |||
1860 | return HAL_OK; |
||
1861 | } |
||
1862 | else |
||
1863 | { |
||
1864 | return HAL_BUSY; |
||
1865 | } |
||
1866 | } |
||
1867 | |||
1868 | /** |
||
1869 | * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt |
||
1870 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1871 | * the configuration information for the specified I2C. |
||
1872 | * @param pData Pointer to data buffer |
||
1873 | * @param Size Amount of data to be sent |
||
1874 | * @retval HAL status |
||
1875 | */ |
||
1876 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
1877 | { |
||
1878 | |||
1879 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1880 | { |
||
1881 | if ((pData == NULL) || (Size == 0U)) |
||
1882 | { |
||
1883 | return HAL_ERROR; |
||
1884 | } |
||
1885 | |||
1886 | /* Process Locked */ |
||
1887 | __HAL_LOCK(hi2c); |
||
1888 | |||
1889 | /* Check if the I2C is already enabled */ |
||
1890 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1891 | { |
||
1892 | /* Enable I2C peripheral */ |
||
1893 | __HAL_I2C_ENABLE(hi2c); |
||
1894 | } |
||
1895 | |||
1896 | /* Disable Pos */ |
||
1897 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1898 | |||
1899 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
1900 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
1901 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1902 | |||
1903 | /* Prepare transfer parameters */ |
||
1904 | hi2c->pBuffPtr = pData; |
||
1905 | hi2c->XferCount = Size; |
||
1906 | hi2c->XferSize = hi2c->XferCount; |
||
1907 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1908 | |||
1909 | /* Enable Address Acknowledge */ |
||
1910 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1911 | |||
1912 | /* Process Unlocked */ |
||
1913 | __HAL_UNLOCK(hi2c); |
||
1914 | |||
1915 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
1916 | to avoid the risk of I2C interrupt handle execution before current |
||
1917 | process unlock */ |
||
1918 | |||
1919 | /* Enable EVT, BUF and ERR interrupt */ |
||
1920 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
1921 | |||
1922 | return HAL_OK; |
||
1923 | } |
||
1924 | else |
||
1925 | { |
||
1926 | return HAL_BUSY; |
||
1927 | } |
||
1928 | } |
||
1929 | |||
1930 | /** |
||
1931 | * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt |
||
1932 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1933 | * the configuration information for the specified I2C. |
||
1934 | * @param pData Pointer to data buffer |
||
1935 | * @param Size Amount of data to be sent |
||
1936 | * @retval HAL status |
||
1937 | */ |
||
1938 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
1939 | { |
||
1940 | |||
1941 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1942 | { |
||
1943 | if ((pData == NULL) || (Size == 0U)) |
||
1944 | { |
||
1945 | return HAL_ERROR; |
||
1946 | } |
||
1947 | |||
1948 | /* Process Locked */ |
||
1949 | __HAL_LOCK(hi2c); |
||
1950 | |||
1951 | /* Check if the I2C is already enabled */ |
||
1952 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1953 | { |
||
1954 | /* Enable I2C peripheral */ |
||
1955 | __HAL_I2C_ENABLE(hi2c); |
||
1956 | } |
||
1957 | |||
1958 | /* Disable Pos */ |
||
1959 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1960 | |||
1961 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
1962 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
1963 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1964 | |||
1965 | /* Prepare transfer parameters */ |
||
1966 | hi2c->pBuffPtr = pData; |
||
1967 | hi2c->XferCount = Size; |
||
1968 | hi2c->XferSize = hi2c->XferCount; |
||
1969 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1970 | |||
1971 | /* Enable Address Acknowledge */ |
||
1972 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1973 | |||
1974 | /* Process Unlocked */ |
||
1975 | __HAL_UNLOCK(hi2c); |
||
1976 | |||
1977 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
1978 | to avoid the risk of I2C interrupt handle execution before current |
||
1979 | process unlock */ |
||
1980 | |||
1981 | /* Enable EVT, BUF and ERR interrupt */ |
||
1982 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
1983 | |||
1984 | return HAL_OK; |
||
1985 | } |
||
1986 | else |
||
1987 | { |
||
1988 | return HAL_BUSY; |
||
1989 | } |
||
1990 | } |
||
1991 | |||
1992 | /** |
||
1993 | * @brief Transmit in master mode an amount of data in non-blocking mode with DMA |
||
1994 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1995 | * the configuration information for the specified I2C. |
||
1996 | * @param DevAddress Target device address: The device 7 bits address value |
||
1997 | * in datasheet must be shifted to the left before calling the interface |
||
1998 | * @param pData Pointer to data buffer |
||
1999 | * @param Size Amount of data to be sent |
||
2000 | * @retval HAL status |
||
2001 | */ |
||
2002 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
2003 | { |
||
2004 | __IO uint32_t count = 0U; |
||
2005 | HAL_StatusTypeDef dmaxferstatus; |
||
2006 | |||
2007 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2008 | { |
||
2009 | /* Wait until BUSY flag is reset */ |
||
2010 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
2011 | do |
||
2012 | { |
||
2013 | count--; |
||
2014 | if (count == 0U) |
||
2015 | { |
||
2016 | hi2c->PreviousState = I2C_STATE_NONE; |
||
2017 | hi2c->State = HAL_I2C_STATE_READY; |
||
2018 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2019 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
2020 | |||
2021 | /* Process Unlocked */ |
||
2022 | __HAL_UNLOCK(hi2c); |
||
2023 | |||
2024 | return HAL_ERROR; |
||
2025 | } |
||
2026 | } |
||
2027 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
2028 | |||
2029 | /* Process Locked */ |
||
2030 | __HAL_LOCK(hi2c); |
||
2031 | |||
2032 | /* Check if the I2C is already enabled */ |
||
2033 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2034 | { |
||
2035 | /* Enable I2C peripheral */ |
||
2036 | __HAL_I2C_ENABLE(hi2c); |
||
2037 | } |
||
2038 | |||
2039 | /* Disable Pos */ |
||
2040 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2041 | |||
2042 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
2043 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
2044 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2045 | |||
2046 | /* Prepare transfer parameters */ |
||
2047 | hi2c->pBuffPtr = pData; |
||
2048 | hi2c->XferCount = Size; |
||
2049 | hi2c->XferSize = hi2c->XferCount; |
||
2050 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2051 | hi2c->Devaddress = DevAddress; |
||
2052 | |||
2053 | if (hi2c->XferSize > 0U) |
||
2054 | { |
||
2055 | if (hi2c->hdmatx != NULL) |
||
2056 | { |
||
2057 | /* Set the I2C DMA transfer complete callback */ |
||
2058 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
2059 | |||
2060 | /* Set the DMA error callback */ |
||
2061 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
2062 | |||
2063 | /* Set the unused DMA callbacks to NULL */ |
||
2064 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
2065 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
2066 | |||
2067 | /* Enable the DMA channel */ |
||
2068 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
2069 | } |
||
2070 | else |
||
2071 | { |
||
2072 | /* Update I2C state */ |
||
2073 | hi2c->State = HAL_I2C_STATE_READY; |
||
2074 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2075 | |||
2076 | /* Update I2C error code */ |
||
2077 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
2078 | |||
2079 | /* Process Unlocked */ |
||
2080 | __HAL_UNLOCK(hi2c); |
||
2081 | |||
2082 | return HAL_ERROR; |
||
2083 | } |
||
2084 | |||
2085 | if (dmaxferstatus == HAL_OK) |
||
2086 | { |
||
2087 | /* Process Unlocked */ |
||
2088 | __HAL_UNLOCK(hi2c); |
||
2089 | |||
2090 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2091 | to avoid the risk of I2C interrupt handle execution before current |
||
2092 | process unlock */ |
||
2093 | |||
2094 | /* Enable EVT and ERR interrupt */ |
||
2095 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
2096 | |||
2097 | /* Enable DMA Request */ |
||
2098 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
2099 | |||
2100 | /* Enable Acknowledge */ |
||
2101 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2102 | |||
2103 | /* Generate Start */ |
||
2104 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2105 | } |
||
2106 | else |
||
2107 | { |
||
2108 | /* Update I2C state */ |
||
2109 | hi2c->State = HAL_I2C_STATE_READY; |
||
2110 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2111 | |||
2112 | /* Update I2C error code */ |
||
2113 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
2114 | |||
2115 | /* Process Unlocked */ |
||
2116 | __HAL_UNLOCK(hi2c); |
||
2117 | |||
2118 | return HAL_ERROR; |
||
2119 | } |
||
2120 | } |
||
2121 | else |
||
2122 | { |
||
2123 | /* Enable Acknowledge */ |
||
2124 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2125 | |||
2126 | /* Generate Start */ |
||
2127 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2128 | |||
2129 | /* Process Unlocked */ |
||
2130 | __HAL_UNLOCK(hi2c); |
||
2131 | |||
2132 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2133 | to avoid the risk of I2C interrupt handle execution before current |
||
2134 | process unlock */ |
||
2135 | |||
2136 | /* Enable EVT, BUF and ERR interrupt */ |
||
2137 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
2138 | } |
||
2139 | |||
2140 | return HAL_OK; |
||
2141 | } |
||
2142 | else |
||
2143 | { |
||
2144 | return HAL_BUSY; |
||
2145 | } |
||
2146 | } |
||
2147 | |||
2148 | /** |
||
2149 | * @brief Receive in master mode an amount of data in non-blocking mode with DMA |
||
2150 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2151 | * the configuration information for the specified I2C. |
||
2152 | * @param DevAddress Target device address: The device 7 bits address value |
||
2153 | * in datasheet must be shifted to the left before calling the interface |
||
2154 | * @param pData Pointer to data buffer |
||
2155 | * @param Size Amount of data to be sent |
||
2156 | * @retval HAL status |
||
2157 | */ |
||
2158 | HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
2159 | { |
||
2160 | __IO uint32_t count = 0U; |
||
2161 | HAL_StatusTypeDef dmaxferstatus; |
||
2162 | |||
2163 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2164 | { |
||
2165 | /* Wait until BUSY flag is reset */ |
||
2166 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
2167 | do |
||
2168 | { |
||
2169 | count--; |
||
2170 | if (count == 0U) |
||
2171 | { |
||
2172 | hi2c->PreviousState = I2C_STATE_NONE; |
||
2173 | hi2c->State = HAL_I2C_STATE_READY; |
||
2174 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2175 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
2176 | |||
2177 | /* Process Unlocked */ |
||
2178 | __HAL_UNLOCK(hi2c); |
||
2179 | |||
2180 | return HAL_ERROR; |
||
2181 | } |
||
2182 | } |
||
2183 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
2184 | |||
2185 | /* Process Locked */ |
||
2186 | __HAL_LOCK(hi2c); |
||
2187 | |||
2188 | /* Check if the I2C is already enabled */ |
||
2189 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2190 | { |
||
2191 | /* Enable I2C peripheral */ |
||
2192 | __HAL_I2C_ENABLE(hi2c); |
||
2193 | } |
||
2194 | |||
2195 | /* Disable Pos */ |
||
2196 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2197 | |||
2198 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
2199 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
2200 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2201 | |||
2202 | /* Prepare transfer parameters */ |
||
2203 | hi2c->pBuffPtr = pData; |
||
2204 | hi2c->XferCount = Size; |
||
2205 | hi2c->XferSize = hi2c->XferCount; |
||
2206 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2207 | hi2c->Devaddress = DevAddress; |
||
2208 | |||
2209 | if (hi2c->XferSize > 0U) |
||
2210 | { |
||
2211 | if (hi2c->hdmarx != NULL) |
||
2212 | { |
||
2213 | /* Set the I2C DMA transfer complete callback */ |
||
2214 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
2215 | |||
2216 | /* Set the DMA error callback */ |
||
2217 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
2218 | |||
2219 | /* Set the unused DMA callbacks to NULL */ |
||
2220 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
2221 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
2222 | |||
2223 | /* Enable the DMA channel */ |
||
2224 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
2225 | } |
||
2226 | else |
||
2227 | { |
||
2228 | /* Update I2C state */ |
||
2229 | hi2c->State = HAL_I2C_STATE_READY; |
||
2230 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2231 | |||
2232 | /* Update I2C error code */ |
||
2233 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
2234 | |||
2235 | /* Process Unlocked */ |
||
2236 | __HAL_UNLOCK(hi2c); |
||
2237 | |||
2238 | return HAL_ERROR; |
||
2239 | } |
||
2240 | |||
2241 | if (dmaxferstatus == HAL_OK) |
||
2242 | { |
||
2243 | /* Enable Acknowledge */ |
||
2244 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2245 | |||
2246 | /* Generate Start */ |
||
2247 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2248 | |||
2249 | /* Process Unlocked */ |
||
2250 | __HAL_UNLOCK(hi2c); |
||
2251 | |||
2252 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2253 | to avoid the risk of I2C interrupt handle execution before current |
||
2254 | process unlock */ |
||
2255 | |||
2256 | /* Enable EVT and ERR interrupt */ |
||
2257 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
2258 | |||
2259 | /* Enable DMA Request */ |
||
2260 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
2261 | } |
||
2262 | else |
||
2263 | { |
||
2264 | /* Update I2C state */ |
||
2265 | hi2c->State = HAL_I2C_STATE_READY; |
||
2266 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2267 | |||
2268 | /* Update I2C error code */ |
||
2269 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
2270 | |||
2271 | /* Process Unlocked */ |
||
2272 | __HAL_UNLOCK(hi2c); |
||
2273 | |||
2274 | return HAL_ERROR; |
||
2275 | } |
||
2276 | } |
||
2277 | else |
||
2278 | { |
||
2279 | /* Process Unlocked */ |
||
2280 | __HAL_UNLOCK(hi2c); |
||
2281 | |||
2282 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2283 | to avoid the risk of I2C interrupt handle execution before current |
||
2284 | process unlock */ |
||
2285 | |||
2286 | /* Enable EVT, BUF and ERR interrupt */ |
||
2287 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
2288 | |||
2289 | /* Enable Acknowledge */ |
||
2290 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2291 | |||
2292 | /* Generate Start */ |
||
2293 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2294 | } |
||
2295 | |||
2296 | return HAL_OK; |
||
2297 | } |
||
2298 | else |
||
2299 | { |
||
2300 | return HAL_BUSY; |
||
2301 | } |
||
2302 | } |
||
2303 | |||
2304 | /** |
||
2305 | * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA |
||
2306 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2307 | * the configuration information for the specified I2C. |
||
2308 | * @param pData Pointer to data buffer |
||
2309 | * @param Size Amount of data to be sent |
||
2310 | * @retval HAL status |
||
2311 | */ |
||
2312 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
2313 | { |
||
2314 | HAL_StatusTypeDef dmaxferstatus; |
||
2315 | |||
2316 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2317 | { |
||
2318 | if ((pData == NULL) || (Size == 0U)) |
||
2319 | { |
||
2320 | return HAL_ERROR; |
||
2321 | } |
||
2322 | |||
2323 | /* Process Locked */ |
||
2324 | __HAL_LOCK(hi2c); |
||
2325 | |||
2326 | /* Check if the I2C is already enabled */ |
||
2327 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2328 | { |
||
2329 | /* Enable I2C peripheral */ |
||
2330 | __HAL_I2C_ENABLE(hi2c); |
||
2331 | } |
||
2332 | |||
2333 | /* Disable Pos */ |
||
2334 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2335 | |||
2336 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
2337 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
2338 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2339 | |||
2340 | /* Prepare transfer parameters */ |
||
2341 | hi2c->pBuffPtr = pData; |
||
2342 | hi2c->XferCount = Size; |
||
2343 | hi2c->XferSize = hi2c->XferCount; |
||
2344 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2345 | |||
2346 | if (hi2c->hdmatx != NULL) |
||
2347 | { |
||
2348 | /* Set the I2C DMA transfer complete callback */ |
||
2349 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
2350 | |||
2351 | /* Set the DMA error callback */ |
||
2352 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
2353 | |||
2354 | /* Set the unused DMA callbacks to NULL */ |
||
2355 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
2356 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
2357 | |||
2358 | /* Enable the DMA channel */ |
||
2359 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
2360 | } |
||
2361 | else |
||
2362 | { |
||
2363 | /* Update I2C state */ |
||
2364 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
2365 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2366 | |||
2367 | /* Update I2C error code */ |
||
2368 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
2369 | |||
2370 | /* Process Unlocked */ |
||
2371 | __HAL_UNLOCK(hi2c); |
||
2372 | |||
2373 | return HAL_ERROR; |
||
2374 | } |
||
2375 | |||
2376 | if (dmaxferstatus == HAL_OK) |
||
2377 | { |
||
2378 | /* Enable Address Acknowledge */ |
||
2379 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2380 | |||
2381 | /* Process Unlocked */ |
||
2382 | __HAL_UNLOCK(hi2c); |
||
2383 | |||
2384 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2385 | to avoid the risk of I2C interrupt handle execution before current |
||
2386 | process unlock */ |
||
2387 | /* Enable EVT and ERR interrupt */ |
||
2388 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
2389 | |||
2390 | /* Enable DMA Request */ |
||
2391 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
2392 | |||
2393 | return HAL_OK; |
||
2394 | } |
||
2395 | else |
||
2396 | { |
||
2397 | /* Update I2C state */ |
||
2398 | hi2c->State = HAL_I2C_STATE_READY; |
||
2399 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2400 | |||
2401 | /* Update I2C error code */ |
||
2402 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
2403 | |||
2404 | /* Process Unlocked */ |
||
2405 | __HAL_UNLOCK(hi2c); |
||
2406 | |||
2407 | return HAL_ERROR; |
||
2408 | } |
||
2409 | } |
||
2410 | else |
||
2411 | { |
||
2412 | return HAL_BUSY; |
||
2413 | } |
||
2414 | } |
||
2415 | |||
2416 | /** |
||
2417 | * @brief Receive in slave mode an amount of data in non-blocking mode with DMA |
||
2418 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2419 | * the configuration information for the specified I2C. |
||
2420 | * @param pData Pointer to data buffer |
||
2421 | * @param Size Amount of data to be sent |
||
2422 | * @retval HAL status |
||
2423 | */ |
||
2424 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
2425 | { |
||
2426 | HAL_StatusTypeDef dmaxferstatus; |
||
2427 | |||
2428 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2429 | { |
||
2430 | if ((pData == NULL) || (Size == 0U)) |
||
2431 | { |
||
2432 | return HAL_ERROR; |
||
2433 | } |
||
2434 | |||
2435 | /* Process Locked */ |
||
2436 | __HAL_LOCK(hi2c); |
||
2437 | |||
2438 | /* Check if the I2C is already enabled */ |
||
2439 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2440 | { |
||
2441 | /* Enable I2C peripheral */ |
||
2442 | __HAL_I2C_ENABLE(hi2c); |
||
2443 | } |
||
2444 | |||
2445 | /* Disable Pos */ |
||
2446 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2447 | |||
2448 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
2449 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
2450 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2451 | |||
2452 | /* Prepare transfer parameters */ |
||
2453 | hi2c->pBuffPtr = pData; |
||
2454 | hi2c->XferCount = Size; |
||
2455 | hi2c->XferSize = hi2c->XferCount; |
||
2456 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2457 | |||
2458 | if (hi2c->hdmarx != NULL) |
||
2459 | { |
||
2460 | /* Set the I2C DMA transfer complete callback */ |
||
2461 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
2462 | |||
2463 | /* Set the DMA error callback */ |
||
2464 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
2465 | |||
2466 | /* Set the unused DMA callbacks to NULL */ |
||
2467 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
2468 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
2469 | |||
2470 | /* Enable the DMA channel */ |
||
2471 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
2472 | } |
||
2473 | else |
||
2474 | { |
||
2475 | /* Update I2C state */ |
||
2476 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
2477 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2478 | |||
2479 | /* Update I2C error code */ |
||
2480 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
2481 | |||
2482 | /* Process Unlocked */ |
||
2483 | __HAL_UNLOCK(hi2c); |
||
2484 | |||
2485 | return HAL_ERROR; |
||
2486 | } |
||
2487 | |||
2488 | if (dmaxferstatus == HAL_OK) |
||
2489 | { |
||
2490 | /* Enable Address Acknowledge */ |
||
2491 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2492 | |||
2493 | /* Process Unlocked */ |
||
2494 | __HAL_UNLOCK(hi2c); |
||
2495 | |||
2496 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2497 | to avoid the risk of I2C interrupt handle execution before current |
||
2498 | process unlock */ |
||
2499 | /* Enable EVT and ERR interrupt */ |
||
2500 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
2501 | |||
2502 | /* Enable DMA Request */ |
||
2503 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
2504 | |||
2505 | return HAL_OK; |
||
2506 | } |
||
2507 | else |
||
2508 | { |
||
2509 | /* Update I2C state */ |
||
2510 | hi2c->State = HAL_I2C_STATE_READY; |
||
2511 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2512 | |||
2513 | /* Update I2C error code */ |
||
2514 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
2515 | |||
2516 | /* Process Unlocked */ |
||
2517 | __HAL_UNLOCK(hi2c); |
||
2518 | |||
2519 | return HAL_ERROR; |
||
2520 | } |
||
2521 | } |
||
2522 | else |
||
2523 | { |
||
2524 | return HAL_BUSY; |
||
2525 | } |
||
2526 | } |
||
2527 | |||
2528 | /** |
||
2529 | * @brief Write an amount of data in blocking mode to a specific memory address |
||
2530 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2531 | * the configuration information for the specified I2C. |
||
2532 | * @param DevAddress Target device address: The device 7 bits address value |
||
2533 | * in datasheet must be shifted to the left before calling the interface |
||
2534 | * @param MemAddress Internal memory address |
||
2535 | * @param MemAddSize Size of internal memory address |
||
2536 | * @param pData Pointer to data buffer |
||
2537 | * @param Size Amount of data to be sent |
||
2538 | * @param Timeout Timeout duration |
||
2539 | * @retval HAL status |
||
2540 | */ |
||
2541 | HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
2542 | { |
||
2543 | /* Init tickstart for timeout management*/ |
||
2544 | uint32_t tickstart = HAL_GetTick(); |
||
2545 | |||
2546 | /* Check the parameters */ |
||
2547 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
2548 | |||
2549 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2550 | { |
||
2551 | /* Wait until BUSY flag is reset */ |
||
2552 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
2553 | { |
||
2554 | return HAL_BUSY; |
||
2555 | } |
||
2556 | |||
2557 | /* Process Locked */ |
||
2558 | __HAL_LOCK(hi2c); |
||
2559 | |||
2560 | /* Check if the I2C is already enabled */ |
||
2561 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2562 | { |
||
2563 | /* Enable I2C peripheral */ |
||
2564 | __HAL_I2C_ENABLE(hi2c); |
||
2565 | } |
||
2566 | |||
2567 | /* Disable Pos */ |
||
2568 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2569 | |||
2570 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
2571 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
2572 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2573 | |||
2574 | /* Prepare transfer parameters */ |
||
2575 | hi2c->pBuffPtr = pData; |
||
2576 | hi2c->XferCount = Size; |
||
2577 | hi2c->XferSize = hi2c->XferCount; |
||
2578 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2579 | |||
2580 | /* Send Slave Address and Memory Address */ |
||
2581 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
||
2582 | { |
||
2583 | return HAL_ERROR; |
||
2584 | } |
||
2585 | |||
2586 | while (hi2c->XferSize > 0U) |
||
2587 | { |
||
2588 | /* Wait until TXE flag is set */ |
||
2589 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
2590 | { |
||
2591 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
2592 | { |
||
2593 | /* Generate Stop */ |
||
2594 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2595 | } |
||
2596 | return HAL_ERROR; |
||
2597 | } |
||
2598 | |||
2599 | /* Write data to DR */ |
||
2600 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
2601 | |||
2602 | /* Increment Buffer pointer */ |
||
2603 | hi2c->pBuffPtr++; |
||
2604 | |||
2605 | /* Update counter */ |
||
2606 | hi2c->XferSize--; |
||
2607 | hi2c->XferCount--; |
||
2608 | |||
2609 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
2610 | { |
||
2611 | /* Write data to DR */ |
||
2612 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
2613 | |||
2614 | /* Increment Buffer pointer */ |
||
2615 | hi2c->pBuffPtr++; |
||
2616 | |||
2617 | /* Update counter */ |
||
2618 | hi2c->XferSize--; |
||
2619 | hi2c->XferCount--; |
||
2620 | } |
||
2621 | } |
||
2622 | |||
2623 | /* Wait until BTF flag is set */ |
||
2624 | if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
2625 | { |
||
2626 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
2627 | { |
||
2628 | /* Generate Stop */ |
||
2629 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2630 | } |
||
2631 | return HAL_ERROR; |
||
2632 | } |
||
2633 | |||
2634 | /* Generate Stop */ |
||
2635 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2636 | |||
2637 | hi2c->State = HAL_I2C_STATE_READY; |
||
2638 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2639 | |||
2640 | /* Process Unlocked */ |
||
2641 | __HAL_UNLOCK(hi2c); |
||
2642 | |||
2643 | return HAL_OK; |
||
2644 | } |
||
2645 | else |
||
2646 | { |
||
2647 | return HAL_BUSY; |
||
2648 | } |
||
2649 | } |
||
2650 | |||
2651 | /** |
||
2652 | * @brief Read an amount of data in blocking mode from a specific memory address |
||
2653 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2654 | * the configuration information for the specified I2C. |
||
2655 | * @param DevAddress Target device address: The device 7 bits address value |
||
2656 | * in datasheet must be shifted to the left before calling the interface |
||
2657 | * @param MemAddress Internal memory address |
||
2658 | * @param MemAddSize Size of internal memory address |
||
2659 | * @param pData Pointer to data buffer |
||
2660 | * @param Size Amount of data to be sent |
||
2661 | * @param Timeout Timeout duration |
||
2662 | * @retval HAL status |
||
2663 | */ |
||
2664 | HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
2665 | { |
||
2666 | __IO uint32_t count = 0U; |
||
2667 | |||
2668 | /* Init tickstart for timeout management*/ |
||
2669 | uint32_t tickstart = HAL_GetTick(); |
||
2670 | |||
2671 | /* Check the parameters */ |
||
2672 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
2673 | |||
2674 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2675 | { |
||
2676 | /* Wait until BUSY flag is reset */ |
||
2677 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
2678 | { |
||
2679 | return HAL_BUSY; |
||
2680 | } |
||
2681 | |||
2682 | /* Process Locked */ |
||
2683 | __HAL_LOCK(hi2c); |
||
2684 | |||
2685 | /* Check if the I2C is already enabled */ |
||
2686 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2687 | { |
||
2688 | /* Enable I2C peripheral */ |
||
2689 | __HAL_I2C_ENABLE(hi2c); |
||
2690 | } |
||
2691 | |||
2692 | /* Disable Pos */ |
||
2693 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2694 | |||
2695 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
2696 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
2697 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2698 | |||
2699 | /* Prepare transfer parameters */ |
||
2700 | hi2c->pBuffPtr = pData; |
||
2701 | hi2c->XferCount = Size; |
||
2702 | hi2c->XferSize = hi2c->XferCount; |
||
2703 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2704 | |||
2705 | /* Send Slave Address and Memory Address */ |
||
2706 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
||
2707 | { |
||
2708 | return HAL_ERROR; |
||
2709 | } |
||
2710 | |||
2711 | if (hi2c->XferSize == 0U) |
||
2712 | { |
||
2713 | /* Clear ADDR flag */ |
||
2714 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
2715 | |||
2716 | /* Generate Stop */ |
||
2717 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2718 | } |
||
2719 | else if (hi2c->XferSize == 1U) |
||
2720 | { |
||
2721 | /* Disable Acknowledge */ |
||
2722 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2723 | |||
2724 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
2725 | software sequence must complete before the current byte end of transfer */ |
||
2726 | __disable_irq(); |
||
2727 | |||
2728 | /* Clear ADDR flag */ |
||
2729 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
2730 | |||
2731 | /* Generate Stop */ |
||
2732 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2733 | |||
2734 | /* Re-enable IRQs */ |
||
2735 | __enable_irq(); |
||
2736 | } |
||
2737 | else if (hi2c->XferSize == 2U) |
||
2738 | { |
||
2739 | /* Enable Pos */ |
||
2740 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2741 | |||
2742 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
2743 | software sequence must complete before the current byte end of transfer */ |
||
2744 | __disable_irq(); |
||
2745 | |||
2746 | /* Clear ADDR flag */ |
||
2747 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
2748 | |||
2749 | /* Disable Acknowledge */ |
||
2750 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2751 | |||
2752 | /* Re-enable IRQs */ |
||
2753 | __enable_irq(); |
||
2754 | } |
||
2755 | else |
||
2756 | { |
||
2757 | /* Enable Acknowledge */ |
||
2758 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2759 | /* Clear ADDR flag */ |
||
2760 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
2761 | } |
||
2762 | |||
2763 | while (hi2c->XferSize > 0U) |
||
2764 | { |
||
2765 | if (hi2c->XferSize <= 3U) |
||
2766 | { |
||
2767 | /* One byte */ |
||
2768 | if (hi2c->XferSize == 1U) |
||
2769 | { |
||
2770 | /* Wait until RXNE flag is set */ |
||
2771 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
2772 | { |
||
2773 | return HAL_ERROR; |
||
2774 | } |
||
2775 | |||
2776 | /* Read data from DR */ |
||
2777 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2778 | |||
2779 | /* Increment Buffer pointer */ |
||
2780 | hi2c->pBuffPtr++; |
||
2781 | |||
2782 | /* Update counter */ |
||
2783 | hi2c->XferSize--; |
||
2784 | hi2c->XferCount--; |
||
2785 | } |
||
2786 | /* Two bytes */ |
||
2787 | else if (hi2c->XferSize == 2U) |
||
2788 | { |
||
2789 | /* Wait until BTF flag is set */ |
||
2790 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
2791 | { |
||
2792 | return HAL_ERROR; |
||
2793 | } |
||
2794 | |||
2795 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
2796 | software sequence must complete before the current byte end of transfer */ |
||
2797 | __disable_irq(); |
||
2798 | |||
2799 | /* Generate Stop */ |
||
2800 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2801 | |||
2802 | /* Read data from DR */ |
||
2803 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2804 | |||
2805 | /* Increment Buffer pointer */ |
||
2806 | hi2c->pBuffPtr++; |
||
2807 | |||
2808 | /* Update counter */ |
||
2809 | hi2c->XferSize--; |
||
2810 | hi2c->XferCount--; |
||
2811 | |||
2812 | /* Re-enable IRQs */ |
||
2813 | __enable_irq(); |
||
2814 | |||
2815 | /* Read data from DR */ |
||
2816 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2817 | |||
2818 | /* Increment Buffer pointer */ |
||
2819 | hi2c->pBuffPtr++; |
||
2820 | |||
2821 | /* Update counter */ |
||
2822 | hi2c->XferSize--; |
||
2823 | hi2c->XferCount--; |
||
2824 | } |
||
2825 | /* 3 Last bytes */ |
||
2826 | else |
||
2827 | { |
||
2828 | /* Wait until BTF flag is set */ |
||
2829 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
2830 | { |
||
2831 | return HAL_ERROR; |
||
2832 | } |
||
2833 | |||
2834 | /* Disable Acknowledge */ |
||
2835 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2836 | |||
2837 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
2838 | software sequence must complete before the current byte end of transfer */ |
||
2839 | __disable_irq(); |
||
2840 | |||
2841 | /* Read data from DR */ |
||
2842 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2843 | |||
2844 | /* Increment Buffer pointer */ |
||
2845 | hi2c->pBuffPtr++; |
||
2846 | |||
2847 | /* Update counter */ |
||
2848 | hi2c->XferSize--; |
||
2849 | hi2c->XferCount--; |
||
2850 | |||
2851 | /* Wait until BTF flag is set */ |
||
2852 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
||
2853 | do |
||
2854 | { |
||
2855 | count--; |
||
2856 | if (count == 0U) |
||
2857 | { |
||
2858 | hi2c->PreviousState = I2C_STATE_NONE; |
||
2859 | hi2c->State = HAL_I2C_STATE_READY; |
||
2860 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2861 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
2862 | |||
2863 | /* Re-enable IRQs */ |
||
2864 | __enable_irq(); |
||
2865 | |||
2866 | /* Process Unlocked */ |
||
2867 | __HAL_UNLOCK(hi2c); |
||
2868 | |||
2869 | return HAL_ERROR; |
||
2870 | } |
||
2871 | } |
||
2872 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); |
||
2873 | |||
2874 | /* Generate Stop */ |
||
2875 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2876 | |||
2877 | /* Read data from DR */ |
||
2878 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2879 | |||
2880 | /* Increment Buffer pointer */ |
||
2881 | hi2c->pBuffPtr++; |
||
2882 | |||
2883 | /* Update counter */ |
||
2884 | hi2c->XferSize--; |
||
2885 | hi2c->XferCount--; |
||
2886 | |||
2887 | /* Re-enable IRQs */ |
||
2888 | __enable_irq(); |
||
2889 | |||
2890 | /* Read data from DR */ |
||
2891 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2892 | |||
2893 | /* Increment Buffer pointer */ |
||
2894 | hi2c->pBuffPtr++; |
||
2895 | |||
2896 | /* Update counter */ |
||
2897 | hi2c->XferSize--; |
||
2898 | hi2c->XferCount--; |
||
2899 | } |
||
2900 | } |
||
2901 | else |
||
2902 | { |
||
2903 | /* Wait until RXNE flag is set */ |
||
2904 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
2905 | { |
||
2906 | return HAL_ERROR; |
||
2907 | } |
||
2908 | |||
2909 | /* Read data from DR */ |
||
2910 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2911 | |||
2912 | /* Increment Buffer pointer */ |
||
2913 | hi2c->pBuffPtr++; |
||
2914 | |||
2915 | /* Update counter */ |
||
2916 | hi2c->XferSize--; |
||
2917 | hi2c->XferCount--; |
||
2918 | |||
2919 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
||
2920 | { |
||
2921 | /* Read data from DR */ |
||
2922 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2923 | |||
2924 | /* Increment Buffer pointer */ |
||
2925 | hi2c->pBuffPtr++; |
||
2926 | |||
2927 | /* Update counter */ |
||
2928 | hi2c->XferSize--; |
||
2929 | hi2c->XferCount--; |
||
2930 | } |
||
2931 | } |
||
2932 | } |
||
2933 | |||
2934 | hi2c->State = HAL_I2C_STATE_READY; |
||
2935 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2936 | |||
2937 | /* Process Unlocked */ |
||
2938 | __HAL_UNLOCK(hi2c); |
||
2939 | |||
2940 | return HAL_OK; |
||
2941 | } |
||
2942 | else |
||
2943 | { |
||
2944 | return HAL_BUSY; |
||
2945 | } |
||
2946 | } |
||
2947 | |||
2948 | /** |
||
2949 | * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address |
||
2950 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2951 | * the configuration information for the specified I2C. |
||
2952 | * @param DevAddress Target device address: The device 7 bits address value |
||
2953 | * in datasheet must be shifted to the left before calling the interface |
||
2954 | * @param MemAddress Internal memory address |
||
2955 | * @param MemAddSize Size of internal memory address |
||
2956 | * @param pData Pointer to data buffer |
||
2957 | * @param Size Amount of data to be sent |
||
2958 | * @retval HAL status |
||
2959 | */ |
||
2960 | HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
2961 | { |
||
2962 | __IO uint32_t count = 0U; |
||
2963 | |||
2964 | /* Check the parameters */ |
||
2965 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
2966 | |||
2967 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2968 | { |
||
2969 | /* Wait until BUSY flag is reset */ |
||
2970 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
2971 | do |
||
2972 | { |
||
2973 | count--; |
||
2974 | if (count == 0U) |
||
2975 | { |
||
2976 | hi2c->PreviousState = I2C_STATE_NONE; |
||
2977 | hi2c->State = HAL_I2C_STATE_READY; |
||
2978 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2979 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
2980 | |||
2981 | /* Process Unlocked */ |
||
2982 | __HAL_UNLOCK(hi2c); |
||
2983 | |||
2984 | return HAL_ERROR; |
||
2985 | } |
||
2986 | } |
||
2987 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
2988 | |||
2989 | /* Process Locked */ |
||
2990 | __HAL_LOCK(hi2c); |
||
2991 | |||
2992 | /* Check if the I2C is already enabled */ |
||
2993 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2994 | { |
||
2995 | /* Enable I2C peripheral */ |
||
2996 | __HAL_I2C_ENABLE(hi2c); |
||
2997 | } |
||
2998 | |||
2999 | /* Disable Pos */ |
||
3000 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3001 | |||
3002 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
3003 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
3004 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3005 | |||
3006 | /* Prepare transfer parameters */ |
||
3007 | hi2c->pBuffPtr = pData; |
||
3008 | hi2c->XferCount = Size; |
||
3009 | hi2c->XferSize = hi2c->XferCount; |
||
3010 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
3011 | hi2c->Devaddress = DevAddress; |
||
3012 | hi2c->Memaddress = MemAddress; |
||
3013 | hi2c->MemaddSize = MemAddSize; |
||
3014 | hi2c->EventCount = 0U; |
||
3015 | |||
3016 | /* Generate Start */ |
||
3017 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3018 | |||
3019 | /* Process Unlocked */ |
||
3020 | __HAL_UNLOCK(hi2c); |
||
3021 | |||
3022 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3023 | to avoid the risk of I2C interrupt handle execution before current |
||
3024 | process unlock */ |
||
3025 | |||
3026 | /* Enable EVT, BUF and ERR interrupt */ |
||
3027 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
3028 | |||
3029 | return HAL_OK; |
||
3030 | } |
||
3031 | else |
||
3032 | { |
||
3033 | return HAL_BUSY; |
||
3034 | } |
||
3035 | } |
||
3036 | |||
3037 | /** |
||
3038 | * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address |
||
3039 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3040 | * the configuration information for the specified I2C. |
||
3041 | * @param DevAddress Target device address |
||
3042 | * @param MemAddress Internal memory address |
||
3043 | * @param MemAddSize Size of internal memory address |
||
3044 | * @param pData Pointer to data buffer |
||
3045 | * @param Size Amount of data to be sent |
||
3046 | * @retval HAL status |
||
3047 | */ |
||
3048 | HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
3049 | { |
||
3050 | __IO uint32_t count = 0U; |
||
3051 | |||
3052 | /* Check the parameters */ |
||
3053 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
3054 | |||
3055 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3056 | { |
||
3057 | /* Wait until BUSY flag is reset */ |
||
3058 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3059 | do |
||
3060 | { |
||
3061 | count--; |
||
3062 | if (count == 0U) |
||
3063 | { |
||
3064 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3065 | hi2c->State = HAL_I2C_STATE_READY; |
||
3066 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3067 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3068 | |||
3069 | /* Process Unlocked */ |
||
3070 | __HAL_UNLOCK(hi2c); |
||
3071 | |||
3072 | return HAL_ERROR; |
||
3073 | } |
||
3074 | } |
||
3075 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3076 | |||
3077 | /* Process Locked */ |
||
3078 | __HAL_LOCK(hi2c); |
||
3079 | |||
3080 | /* Check if the I2C is already enabled */ |
||
3081 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3082 | { |
||
3083 | /* Enable I2C peripheral */ |
||
3084 | __HAL_I2C_ENABLE(hi2c); |
||
3085 | } |
||
3086 | |||
3087 | /* Disable Pos */ |
||
3088 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3089 | |||
3090 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
3091 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
3092 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3093 | |||
3094 | /* Prepare transfer parameters */ |
||
3095 | hi2c->pBuffPtr = pData; |
||
3096 | hi2c->XferCount = Size; |
||
3097 | hi2c->XferSize = hi2c->XferCount; |
||
3098 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
3099 | hi2c->Devaddress = DevAddress; |
||
3100 | hi2c->Memaddress = MemAddress; |
||
3101 | hi2c->MemaddSize = MemAddSize; |
||
3102 | hi2c->EventCount = 0U; |
||
3103 | |||
3104 | /* Enable Acknowledge */ |
||
3105 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3106 | |||
3107 | /* Generate Start */ |
||
3108 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3109 | |||
3110 | /* Process Unlocked */ |
||
3111 | __HAL_UNLOCK(hi2c); |
||
3112 | |||
3113 | if (hi2c->XferSize > 0U) |
||
3114 | { |
||
3115 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3116 | to avoid the risk of I2C interrupt handle execution before current |
||
3117 | process unlock */ |
||
3118 | |||
3119 | /* Enable EVT, BUF and ERR interrupt */ |
||
3120 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
3121 | } |
||
3122 | return HAL_OK; |
||
3123 | } |
||
3124 | else |
||
3125 | { |
||
3126 | return HAL_BUSY; |
||
3127 | } |
||
3128 | } |
||
3129 | |||
3130 | /** |
||
3131 | * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address |
||
3132 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3133 | * the configuration information for the specified I2C. |
||
3134 | * @param DevAddress Target device address: The device 7 bits address value |
||
3135 | * in datasheet must be shifted to the left before calling the interface |
||
3136 | * @param MemAddress Internal memory address |
||
3137 | * @param MemAddSize Size of internal memory address |
||
3138 | * @param pData Pointer to data buffer |
||
3139 | * @param Size Amount of data to be sent |
||
3140 | * @retval HAL status |
||
3141 | */ |
||
3142 | HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
3143 | { |
||
3144 | __IO uint32_t count = 0U; |
||
3145 | HAL_StatusTypeDef dmaxferstatus; |
||
3146 | |||
3147 | /* Init tickstart for timeout management*/ |
||
3148 | uint32_t tickstart = HAL_GetTick(); |
||
3149 | |||
3150 | /* Check the parameters */ |
||
3151 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
3152 | |||
3153 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3154 | { |
||
3155 | /* Wait until BUSY flag is reset */ |
||
3156 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3157 | do |
||
3158 | { |
||
3159 | count--; |
||
3160 | if (count == 0U) |
||
3161 | { |
||
3162 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3163 | hi2c->State = HAL_I2C_STATE_READY; |
||
3164 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3165 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3166 | |||
3167 | /* Process Unlocked */ |
||
3168 | __HAL_UNLOCK(hi2c); |
||
3169 | |||
3170 | return HAL_ERROR; |
||
3171 | } |
||
3172 | } |
||
3173 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3174 | |||
3175 | /* Process Locked */ |
||
3176 | __HAL_LOCK(hi2c); |
||
3177 | |||
3178 | /* Check if the I2C is already enabled */ |
||
3179 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3180 | { |
||
3181 | /* Enable I2C peripheral */ |
||
3182 | __HAL_I2C_ENABLE(hi2c); |
||
3183 | } |
||
3184 | |||
3185 | /* Disable Pos */ |
||
3186 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3187 | |||
3188 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
3189 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
3190 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3191 | |||
3192 | /* Prepare transfer parameters */ |
||
3193 | hi2c->pBuffPtr = pData; |
||
3194 | hi2c->XferCount = Size; |
||
3195 | hi2c->XferSize = hi2c->XferCount; |
||
3196 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
3197 | |||
3198 | if (hi2c->XferSize > 0U) |
||
3199 | { |
||
3200 | if (hi2c->hdmatx != NULL) |
||
3201 | { |
||
3202 | /* Set the I2C DMA transfer complete callback */ |
||
3203 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
3204 | |||
3205 | /* Set the DMA error callback */ |
||
3206 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
3207 | |||
3208 | /* Set the unused DMA callbacks to NULL */ |
||
3209 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
3210 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
3211 | |||
3212 | /* Enable the DMA channel */ |
||
3213 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
3214 | } |
||
3215 | else |
||
3216 | { |
||
3217 | /* Update I2C state */ |
||
3218 | hi2c->State = HAL_I2C_STATE_READY; |
||
3219 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3220 | |||
3221 | /* Update I2C error code */ |
||
3222 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
3223 | |||
3224 | /* Process Unlocked */ |
||
3225 | __HAL_UNLOCK(hi2c); |
||
3226 | |||
3227 | return HAL_ERROR; |
||
3228 | } |
||
3229 | |||
3230 | if (dmaxferstatus == HAL_OK) |
||
3231 | { |
||
3232 | /* Send Slave Address and Memory Address */ |
||
3233 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
||
3234 | { |
||
3235 | /* Abort the ongoing DMA */ |
||
3236 | dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); |
||
3237 | |||
3238 | /* Prevent unused argument(s) compilation and MISRA warning */ |
||
3239 | UNUSED(dmaxferstatus); |
||
3240 | |||
3241 | /* Set the unused I2C DMA transfer complete callback to NULL */ |
||
3242 | hi2c->hdmatx->XferCpltCallback = NULL; |
||
3243 | |||
3244 | /* Disable Acknowledge */ |
||
3245 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3246 | |||
3247 | hi2c->XferSize = 0U; |
||
3248 | hi2c->XferCount = 0U; |
||
3249 | |||
3250 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
3251 | __HAL_I2C_DISABLE(hi2c); |
||
3252 | |||
3253 | return HAL_ERROR; |
||
3254 | } |
||
3255 | |||
3256 | /* Clear ADDR flag */ |
||
3257 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
3258 | |||
3259 | /* Process Unlocked */ |
||
3260 | __HAL_UNLOCK(hi2c); |
||
3261 | |||
3262 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3263 | to avoid the risk of I2C interrupt handle execution before current |
||
3264 | process unlock */ |
||
3265 | /* Enable ERR interrupt */ |
||
3266 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
||
3267 | |||
3268 | /* Enable DMA Request */ |
||
3269 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
3270 | |||
3271 | return HAL_OK; |
||
3272 | } |
||
3273 | else |
||
3274 | { |
||
3275 | /* Update I2C state */ |
||
3276 | hi2c->State = HAL_I2C_STATE_READY; |
||
3277 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3278 | |||
3279 | /* Update I2C error code */ |
||
3280 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
3281 | |||
3282 | /* Process Unlocked */ |
||
3283 | __HAL_UNLOCK(hi2c); |
||
3284 | |||
3285 | return HAL_ERROR; |
||
3286 | } |
||
3287 | } |
||
3288 | else |
||
3289 | { |
||
3290 | /* Update I2C state */ |
||
3291 | hi2c->State = HAL_I2C_STATE_READY; |
||
3292 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3293 | |||
3294 | /* Update I2C error code */ |
||
3295 | hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; |
||
3296 | |||
3297 | /* Process Unlocked */ |
||
3298 | __HAL_UNLOCK(hi2c); |
||
3299 | |||
3300 | return HAL_ERROR; |
||
3301 | } |
||
3302 | } |
||
3303 | else |
||
3304 | { |
||
3305 | return HAL_BUSY; |
||
3306 | } |
||
3307 | } |
||
3308 | |||
3309 | /** |
||
3310 | * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. |
||
3311 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3312 | * the configuration information for the specified I2C. |
||
3313 | * @param DevAddress Target device address: The device 7 bits address value |
||
3314 | * in datasheet must be shifted to the left before calling the interface |
||
3315 | * @param MemAddress Internal memory address |
||
3316 | * @param MemAddSize Size of internal memory address |
||
3317 | * @param pData Pointer to data buffer |
||
3318 | * @param Size Amount of data to be read |
||
3319 | * @retval HAL status |
||
3320 | */ |
||
3321 | HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
3322 | { |
||
3323 | /* Init tickstart for timeout management*/ |
||
3324 | uint32_t tickstart = HAL_GetTick(); |
||
3325 | __IO uint32_t count = 0U; |
||
3326 | HAL_StatusTypeDef dmaxferstatus; |
||
3327 | |||
3328 | /* Check the parameters */ |
||
3329 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
3330 | |||
3331 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3332 | { |
||
3333 | /* Wait until BUSY flag is reset */ |
||
3334 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3335 | do |
||
3336 | { |
||
3337 | count--; |
||
3338 | if (count == 0U) |
||
3339 | { |
||
3340 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3341 | hi2c->State = HAL_I2C_STATE_READY; |
||
3342 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3343 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3344 | |||
3345 | /* Process Unlocked */ |
||
3346 | __HAL_UNLOCK(hi2c); |
||
3347 | |||
3348 | return HAL_ERROR; |
||
3349 | } |
||
3350 | } |
||
3351 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3352 | |||
3353 | /* Process Locked */ |
||
3354 | __HAL_LOCK(hi2c); |
||
3355 | |||
3356 | /* Check if the I2C is already enabled */ |
||
3357 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3358 | { |
||
3359 | /* Enable I2C peripheral */ |
||
3360 | __HAL_I2C_ENABLE(hi2c); |
||
3361 | } |
||
3362 | |||
3363 | /* Disable Pos */ |
||
3364 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3365 | |||
3366 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
3367 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
3368 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3369 | |||
3370 | /* Prepare transfer parameters */ |
||
3371 | hi2c->pBuffPtr = pData; |
||
3372 | hi2c->XferCount = Size; |
||
3373 | hi2c->XferSize = hi2c->XferCount; |
||
3374 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
3375 | |||
3376 | if (hi2c->XferSize > 0U) |
||
3377 | { |
||
3378 | if (hi2c->hdmarx != NULL) |
||
3379 | { |
||
3380 | /* Set the I2C DMA transfer complete callback */ |
||
3381 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
3382 | |||
3383 | /* Set the DMA error callback */ |
||
3384 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
3385 | |||
3386 | /* Set the unused DMA callbacks to NULL */ |
||
3387 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
3388 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
3389 | |||
3390 | /* Enable the DMA channel */ |
||
3391 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
3392 | } |
||
3393 | else |
||
3394 | { |
||
3395 | /* Update I2C state */ |
||
3396 | hi2c->State = HAL_I2C_STATE_READY; |
||
3397 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3398 | |||
3399 | /* Update I2C error code */ |
||
3400 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
3401 | |||
3402 | /* Process Unlocked */ |
||
3403 | __HAL_UNLOCK(hi2c); |
||
3404 | |||
3405 | return HAL_ERROR; |
||
3406 | } |
||
3407 | |||
3408 | if (dmaxferstatus == HAL_OK) |
||
3409 | { |
||
3410 | /* Send Slave Address and Memory Address */ |
||
3411 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
||
3412 | { |
||
3413 | /* Abort the ongoing DMA */ |
||
3414 | dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); |
||
3415 | |||
3416 | /* Prevent unused argument(s) compilation and MISRA warning */ |
||
3417 | UNUSED(dmaxferstatus); |
||
3418 | |||
3419 | /* Set the unused I2C DMA transfer complete callback to NULL */ |
||
3420 | hi2c->hdmarx->XferCpltCallback = NULL; |
||
3421 | |||
3422 | /* Disable Acknowledge */ |
||
3423 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3424 | |||
3425 | hi2c->XferSize = 0U; |
||
3426 | hi2c->XferCount = 0U; |
||
3427 | |||
3428 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
3429 | __HAL_I2C_DISABLE(hi2c); |
||
3430 | |||
3431 | return HAL_ERROR; |
||
3432 | } |
||
3433 | |||
3434 | if (hi2c->XferSize == 1U) |
||
3435 | { |
||
3436 | /* Disable Acknowledge */ |
||
3437 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3438 | } |
||
3439 | else |
||
3440 | { |
||
3441 | /* Enable Last DMA bit */ |
||
3442 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
3443 | } |
||
3444 | |||
3445 | /* Clear ADDR flag */ |
||
3446 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
3447 | |||
3448 | /* Process Unlocked */ |
||
3449 | __HAL_UNLOCK(hi2c); |
||
3450 | |||
3451 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3452 | to avoid the risk of I2C interrupt handle execution before current |
||
3453 | process unlock */ |
||
3454 | /* Enable ERR interrupt */ |
||
3455 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
||
3456 | |||
3457 | /* Enable DMA Request */ |
||
3458 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
3459 | } |
||
3460 | else |
||
3461 | { |
||
3462 | /* Update I2C state */ |
||
3463 | hi2c->State = HAL_I2C_STATE_READY; |
||
3464 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3465 | |||
3466 | /* Update I2C error code */ |
||
3467 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
3468 | |||
3469 | /* Process Unlocked */ |
||
3470 | __HAL_UNLOCK(hi2c); |
||
3471 | |||
3472 | return HAL_ERROR; |
||
3473 | } |
||
3474 | } |
||
3475 | else |
||
3476 | { |
||
3477 | /* Send Slave Address and Memory Address */ |
||
3478 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
||
3479 | { |
||
3480 | return HAL_ERROR; |
||
3481 | } |
||
3482 | |||
3483 | /* Clear ADDR flag */ |
||
3484 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
3485 | |||
3486 | /* Generate Stop */ |
||
3487 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
3488 | |||
3489 | hi2c->State = HAL_I2C_STATE_READY; |
||
3490 | |||
3491 | /* Process Unlocked */ |
||
3492 | __HAL_UNLOCK(hi2c); |
||
3493 | } |
||
3494 | |||
3495 | return HAL_OK; |
||
3496 | } |
||
3497 | else |
||
3498 | { |
||
3499 | return HAL_BUSY; |
||
3500 | } |
||
3501 | } |
||
3502 | |||
3503 | /** |
||
3504 | * @brief Checks if target device is ready for communication. |
||
3505 | * @note This function is used with Memory devices |
||
3506 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3507 | * the configuration information for the specified I2C. |
||
3508 | * @param DevAddress Target device address: The device 7 bits address value |
||
3509 | * in datasheet must be shifted to the left before calling the interface |
||
3510 | * @param Trials Number of trials |
||
3511 | * @param Timeout Timeout duration |
||
3512 | * @retval HAL status |
||
3513 | */ |
||
3514 | HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) |
||
3515 | { |
||
3516 | /* Get tick */ |
||
3517 | uint32_t tickstart = HAL_GetTick(); |
||
3518 | uint32_t I2C_Trials = 1U; |
||
3519 | FlagStatus tmp1; |
||
3520 | FlagStatus tmp2; |
||
3521 | |||
3522 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3523 | { |
||
3524 | /* Wait until BUSY flag is reset */ |
||
3525 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
3526 | { |
||
3527 | return HAL_BUSY; |
||
3528 | } |
||
3529 | |||
3530 | /* Process Locked */ |
||
3531 | __HAL_LOCK(hi2c); |
||
3532 | |||
3533 | /* Check if the I2C is already enabled */ |
||
3534 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3535 | { |
||
3536 | /* Enable I2C peripheral */ |
||
3537 | __HAL_I2C_ENABLE(hi2c); |
||
3538 | } |
||
3539 | |||
3540 | /* Disable Pos */ |
||
3541 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3542 | |||
3543 | hi2c->State = HAL_I2C_STATE_BUSY; |
||
3544 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3545 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
3546 | |||
3547 | do |
||
3548 | { |
||
3549 | /* Generate Start */ |
||
3550 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3551 | |||
3552 | /* Wait until SB flag is set */ |
||
3553 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) |
||
3554 | { |
||
3555 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
3556 | { |
||
3557 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
3558 | } |
||
3559 | return HAL_TIMEOUT; |
||
3560 | } |
||
3561 | |||
3562 | /* Send slave address */ |
||
3563 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
3564 | |||
3565 | /* Wait until ADDR or AF flag are set */ |
||
3566 | /* Get tick */ |
||
3567 | tickstart = HAL_GetTick(); |
||
3568 | |||
3569 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
||
3570 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
||
3571 | while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) |
||
3572 | { |
||
3573 | if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) |
||
3574 | { |
||
3575 | hi2c->State = HAL_I2C_STATE_TIMEOUT; |
||
3576 | } |
||
3577 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
||
3578 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
||
3579 | } |
||
3580 | |||
3581 | hi2c->State = HAL_I2C_STATE_READY; |
||
3582 | |||
3583 | /* Check if the ADDR flag has been set */ |
||
3584 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) |
||
3585 | { |
||
3586 | /* Generate Stop */ |
||
3587 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
3588 | |||
3589 | /* Clear ADDR Flag */ |
||
3590 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
3591 | |||
3592 | /* Wait until BUSY flag is reset */ |
||
3593 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
3594 | { |
||
3595 | return HAL_ERROR; |
||
3596 | } |
||
3597 | |||
3598 | hi2c->State = HAL_I2C_STATE_READY; |
||
3599 | |||
3600 | /* Process Unlocked */ |
||
3601 | __HAL_UNLOCK(hi2c); |
||
3602 | |||
3603 | return HAL_OK; |
||
3604 | } |
||
3605 | else |
||
3606 | { |
||
3607 | /* Generate Stop */ |
||
3608 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
3609 | |||
3610 | /* Clear AF Flag */ |
||
3611 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
3612 | |||
3613 | /* Wait until BUSY flag is reset */ |
||
3614 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
3615 | { |
||
3616 | return HAL_ERROR; |
||
3617 | } |
||
3618 | } |
||
3619 | |||
3620 | /* Increment Trials */ |
||
3621 | I2C_Trials++; |
||
3622 | } |
||
3623 | while (I2C_Trials < Trials); |
||
3624 | |||
3625 | hi2c->State = HAL_I2C_STATE_READY; |
||
3626 | |||
3627 | /* Process Unlocked */ |
||
3628 | __HAL_UNLOCK(hi2c); |
||
3629 | |||
3630 | return HAL_ERROR; |
||
3631 | } |
||
3632 | else |
||
3633 | { |
||
3634 | return HAL_BUSY; |
||
3635 | } |
||
3636 | } |
||
3637 | |||
3638 | /** |
||
3639 | * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. |
||
3640 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
3641 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3642 | * the configuration information for the specified I2C. |
||
3643 | * @param DevAddress Target device address: The device 7 bits address value |
||
3644 | * in datasheet must be shifted to the left before calling the interface |
||
3645 | * @param pData Pointer to data buffer |
||
3646 | * @param Size Amount of data to be sent |
||
3647 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
3648 | * @retval HAL status |
||
3649 | */ |
||
3650 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
3651 | { |
||
3652 | __IO uint32_t Prev_State = 0x00U; |
||
3653 | __IO uint32_t count = 0x00U; |
||
3654 | |||
3655 | /* Check the parameters */ |
||
3656 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
3657 | |||
3658 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3659 | { |
||
3660 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
3661 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
3662 | { |
||
3663 | /* Wait until BUSY flag is reset */ |
||
3664 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3665 | do |
||
3666 | { |
||
3667 | count--; |
||
3668 | if (count == 0U) |
||
3669 | { |
||
3670 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3671 | hi2c->State = HAL_I2C_STATE_READY; |
||
3672 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3673 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3674 | |||
3675 | /* Process Unlocked */ |
||
3676 | __HAL_UNLOCK(hi2c); |
||
3677 | |||
3678 | return HAL_ERROR; |
||
3679 | } |
||
3680 | } |
||
3681 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3682 | } |
||
3683 | |||
3684 | /* Process Locked */ |
||
3685 | __HAL_LOCK(hi2c); |
||
3686 | |||
3687 | /* Check if the I2C is already enabled */ |
||
3688 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3689 | { |
||
3690 | /* Enable I2C peripheral */ |
||
3691 | __HAL_I2C_ENABLE(hi2c); |
||
3692 | } |
||
3693 | |||
3694 | /* Disable Pos */ |
||
3695 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3696 | |||
3697 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
3698 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
3699 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3700 | |||
3701 | /* Prepare transfer parameters */ |
||
3702 | hi2c->pBuffPtr = pData; |
||
3703 | hi2c->XferCount = Size; |
||
3704 | hi2c->XferSize = hi2c->XferCount; |
||
3705 | hi2c->XferOptions = XferOptions; |
||
3706 | hi2c->Devaddress = DevAddress; |
||
3707 | |||
3708 | Prev_State = hi2c->PreviousState; |
||
3709 | |||
3710 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
3711 | /* Mean Previous state is same as current state */ |
||
3712 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
3713 | { |
||
3714 | /* Generate Start */ |
||
3715 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3716 | } |
||
3717 | |||
3718 | /* Process Unlocked */ |
||
3719 | __HAL_UNLOCK(hi2c); |
||
3720 | |||
3721 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3722 | to avoid the risk of I2C interrupt handle execution before current |
||
3723 | process unlock */ |
||
3724 | |||
3725 | /* Enable EVT, BUF and ERR interrupt */ |
||
3726 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
3727 | |||
3728 | return HAL_OK; |
||
3729 | } |
||
3730 | else |
||
3731 | { |
||
3732 | return HAL_BUSY; |
||
3733 | } |
||
3734 | } |
||
3735 | |||
3736 | /** |
||
3737 | * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. |
||
3738 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
3739 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3740 | * the configuration information for the specified I2C. |
||
3741 | * @param DevAddress Target device address: The device 7 bits address value |
||
3742 | * in datasheet must be shifted to the left before calling the interface |
||
3743 | * @param pData Pointer to data buffer |
||
3744 | * @param Size Amount of data to be sent |
||
3745 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
3746 | * @retval HAL status |
||
3747 | */ |
||
3748 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
3749 | { |
||
3750 | __IO uint32_t Prev_State = 0x00U; |
||
3751 | __IO uint32_t count = 0x00U; |
||
3752 | HAL_StatusTypeDef dmaxferstatus; |
||
3753 | |||
3754 | /* Check the parameters */ |
||
3755 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
3756 | |||
3757 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3758 | { |
||
3759 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
3760 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
3761 | { |
||
3762 | /* Wait until BUSY flag is reset */ |
||
3763 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3764 | do |
||
3765 | { |
||
3766 | count--; |
||
3767 | if (count == 0U) |
||
3768 | { |
||
3769 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3770 | hi2c->State = HAL_I2C_STATE_READY; |
||
3771 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3772 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3773 | |||
3774 | /* Process Unlocked */ |
||
3775 | __HAL_UNLOCK(hi2c); |
||
3776 | |||
3777 | return HAL_ERROR; |
||
3778 | } |
||
3779 | } |
||
3780 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3781 | } |
||
3782 | |||
3783 | /* Process Locked */ |
||
3784 | __HAL_LOCK(hi2c); |
||
3785 | |||
3786 | /* Check if the I2C is already enabled */ |
||
3787 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3788 | { |
||
3789 | /* Enable I2C peripheral */ |
||
3790 | __HAL_I2C_ENABLE(hi2c); |
||
3791 | } |
||
3792 | |||
3793 | /* Disable Pos */ |
||
3794 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3795 | |||
3796 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
3797 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
3798 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3799 | |||
3800 | /* Prepare transfer parameters */ |
||
3801 | hi2c->pBuffPtr = pData; |
||
3802 | hi2c->XferCount = Size; |
||
3803 | hi2c->XferSize = hi2c->XferCount; |
||
3804 | hi2c->XferOptions = XferOptions; |
||
3805 | hi2c->Devaddress = DevAddress; |
||
3806 | |||
3807 | Prev_State = hi2c->PreviousState; |
||
3808 | |||
3809 | if (hi2c->XferSize > 0U) |
||
3810 | { |
||
3811 | if (hi2c->hdmatx != NULL) |
||
3812 | { |
||
3813 | /* Set the I2C DMA transfer complete callback */ |
||
3814 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
3815 | |||
3816 | /* Set the DMA error callback */ |
||
3817 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
3818 | |||
3819 | /* Set the unused DMA callbacks to NULL */ |
||
3820 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
3821 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
3822 | |||
3823 | /* Enable the DMA channel */ |
||
3824 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
3825 | } |
||
3826 | else |
||
3827 | { |
||
3828 | /* Update I2C state */ |
||
3829 | hi2c->State = HAL_I2C_STATE_READY; |
||
3830 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3831 | |||
3832 | /* Update I2C error code */ |
||
3833 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
3834 | |||
3835 | /* Process Unlocked */ |
||
3836 | __HAL_UNLOCK(hi2c); |
||
3837 | |||
3838 | return HAL_ERROR; |
||
3839 | } |
||
3840 | |||
3841 | if (dmaxferstatus == HAL_OK) |
||
3842 | { |
||
3843 | /* Enable Acknowledge */ |
||
3844 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3845 | |||
3846 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
3847 | /* Mean Previous state is same as current state */ |
||
3848 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
3849 | { |
||
3850 | /* Generate Start */ |
||
3851 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3852 | } |
||
3853 | |||
3854 | /* Process Unlocked */ |
||
3855 | __HAL_UNLOCK(hi2c); |
||
3856 | |||
3857 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3858 | to avoid the risk of I2C interrupt handle execution before current |
||
3859 | process unlock */ |
||
3860 | |||
3861 | /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ |
||
3862 | /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ |
||
3863 | if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
||
3864 | { |
||
3865 | /* Enable DMA Request */ |
||
3866 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
3867 | } |
||
3868 | |||
3869 | /* Enable EVT and ERR interrupt */ |
||
3870 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
3871 | } |
||
3872 | else |
||
3873 | { |
||
3874 | /* Update I2C state */ |
||
3875 | hi2c->State = HAL_I2C_STATE_READY; |
||
3876 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3877 | |||
3878 | /* Update I2C error code */ |
||
3879 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
3880 | |||
3881 | /* Process Unlocked */ |
||
3882 | __HAL_UNLOCK(hi2c); |
||
3883 | |||
3884 | return HAL_ERROR; |
||
3885 | } |
||
3886 | } |
||
3887 | else |
||
3888 | { |
||
3889 | /* Enable Acknowledge */ |
||
3890 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3891 | |||
3892 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
3893 | /* Mean Previous state is same as current state */ |
||
3894 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
3895 | { |
||
3896 | /* Generate Start */ |
||
3897 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3898 | } |
||
3899 | |||
3900 | /* Process Unlocked */ |
||
3901 | __HAL_UNLOCK(hi2c); |
||
3902 | |||
3903 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3904 | to avoid the risk of I2C interrupt handle execution before current |
||
3905 | process unlock */ |
||
3906 | |||
3907 | /* Enable EVT, BUF and ERR interrupt */ |
||
3908 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
3909 | } |
||
3910 | |||
3911 | return HAL_OK; |
||
3912 | } |
||
3913 | else |
||
3914 | { |
||
3915 | return HAL_BUSY; |
||
3916 | } |
||
3917 | } |
||
3918 | |||
3919 | /** |
||
3920 | * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt |
||
3921 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
3922 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3923 | * the configuration information for the specified I2C. |
||
3924 | * @param DevAddress Target device address: The device 7 bits address value |
||
3925 | * in datasheet must be shifted to the left before calling the interface |
||
3926 | * @param pData Pointer to data buffer |
||
3927 | * @param Size Amount of data to be sent |
||
3928 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
3929 | * @retval HAL status |
||
3930 | */ |
||
3931 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
3932 | { |
||
3933 | __IO uint32_t Prev_State = 0x00U; |
||
3934 | __IO uint32_t count = 0U; |
||
3935 | uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
3936 | |||
3937 | /* Check the parameters */ |
||
3938 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
3939 | |||
3940 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3941 | { |
||
3942 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
3943 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
3944 | { |
||
3945 | /* Wait until BUSY flag is reset */ |
||
3946 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3947 | do |
||
3948 | { |
||
3949 | count--; |
||
3950 | if (count == 0U) |
||
3951 | { |
||
3952 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3953 | hi2c->State = HAL_I2C_STATE_READY; |
||
3954 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3955 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3956 | |||
3957 | /* Process Unlocked */ |
||
3958 | __HAL_UNLOCK(hi2c); |
||
3959 | |||
3960 | return HAL_ERROR; |
||
3961 | } |
||
3962 | } |
||
3963 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3964 | } |
||
3965 | |||
3966 | /* Process Locked */ |
||
3967 | __HAL_LOCK(hi2c); |
||
3968 | |||
3969 | /* Check if the I2C is already enabled */ |
||
3970 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3971 | { |
||
3972 | /* Enable I2C peripheral */ |
||
3973 | __HAL_I2C_ENABLE(hi2c); |
||
3974 | } |
||
3975 | |||
3976 | /* Disable Pos */ |
||
3977 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3978 | |||
3979 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
3980 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
3981 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3982 | |||
3983 | /* Prepare transfer parameters */ |
||
3984 | hi2c->pBuffPtr = pData; |
||
3985 | hi2c->XferCount = Size; |
||
3986 | hi2c->XferSize = hi2c->XferCount; |
||
3987 | hi2c->XferOptions = XferOptions; |
||
3988 | hi2c->Devaddress = DevAddress; |
||
3989 | |||
3990 | Prev_State = hi2c->PreviousState; |
||
3991 | |||
3992 | if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) |
||
3993 | { |
||
3994 | if (Prev_State == I2C_STATE_MASTER_BUSY_RX) |
||
3995 | { |
||
3996 | /* Disable Acknowledge */ |
||
3997 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3998 | |||
3999 | /* Enable Pos */ |
||
4000 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4001 | |||
4002 | /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ |
||
4003 | enableIT &= ~I2C_IT_BUF; |
||
4004 | } |
||
4005 | else |
||
4006 | { |
||
4007 | /* Enable Acknowledge */ |
||
4008 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4009 | } |
||
4010 | } |
||
4011 | else |
||
4012 | { |
||
4013 | /* Enable Acknowledge */ |
||
4014 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4015 | } |
||
4016 | |||
4017 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
4018 | /* Mean Previous state is same as current state */ |
||
4019 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
4020 | { |
||
4021 | /* Generate Start */ |
||
4022 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
4023 | } |
||
4024 | |||
4025 | /* Process Unlocked */ |
||
4026 | __HAL_UNLOCK(hi2c); |
||
4027 | |||
4028 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4029 | to avoid the risk of I2C interrupt handle execution before current |
||
4030 | process unlock */ |
||
4031 | |||
4032 | /* Enable interrupts */ |
||
4033 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
||
4034 | |||
4035 | return HAL_OK; |
||
4036 | } |
||
4037 | else |
||
4038 | { |
||
4039 | return HAL_BUSY; |
||
4040 | } |
||
4041 | } |
||
4042 | |||
4043 | /** |
||
4044 | * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA |
||
4045 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
4046 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4047 | * the configuration information for the specified I2C. |
||
4048 | * @param DevAddress Target device address: The device 7 bits address value |
||
4049 | * in datasheet must be shifted to the left before calling the interface |
||
4050 | * @param pData Pointer to data buffer |
||
4051 | * @param Size Amount of data to be sent |
||
4052 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
4053 | * @retval HAL status |
||
4054 | */ |
||
4055 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
4056 | { |
||
4057 | __IO uint32_t Prev_State = 0x00U; |
||
4058 | __IO uint32_t count = 0U; |
||
4059 | uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
4060 | HAL_StatusTypeDef dmaxferstatus; |
||
4061 | |||
4062 | /* Check the parameters */ |
||
4063 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
4064 | |||
4065 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
4066 | { |
||
4067 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
4068 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
4069 | { |
||
4070 | /* Wait until BUSY flag is reset */ |
||
4071 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
4072 | do |
||
4073 | { |
||
4074 | count--; |
||
4075 | if (count == 0U) |
||
4076 | { |
||
4077 | hi2c->PreviousState = I2C_STATE_NONE; |
||
4078 | hi2c->State = HAL_I2C_STATE_READY; |
||
4079 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4080 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
4081 | |||
4082 | /* Process Unlocked */ |
||
4083 | __HAL_UNLOCK(hi2c); |
||
4084 | |||
4085 | return HAL_ERROR; |
||
4086 | } |
||
4087 | } |
||
4088 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
4089 | } |
||
4090 | |||
4091 | /* Process Locked */ |
||
4092 | __HAL_LOCK(hi2c); |
||
4093 | |||
4094 | /* Check if the I2C is already enabled */ |
||
4095 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4096 | { |
||
4097 | /* Enable I2C peripheral */ |
||
4098 | __HAL_I2C_ENABLE(hi2c); |
||
4099 | } |
||
4100 | |||
4101 | /* Disable Pos */ |
||
4102 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4103 | |||
4104 | /* Clear Last DMA bit */ |
||
4105 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
4106 | |||
4107 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
4108 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
4109 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
4110 | |||
4111 | /* Prepare transfer parameters */ |
||
4112 | hi2c->pBuffPtr = pData; |
||
4113 | hi2c->XferCount = Size; |
||
4114 | hi2c->XferSize = hi2c->XferCount; |
||
4115 | hi2c->XferOptions = XferOptions; |
||
4116 | hi2c->Devaddress = DevAddress; |
||
4117 | |||
4118 | Prev_State = hi2c->PreviousState; |
||
4119 | |||
4120 | if (hi2c->XferSize > 0U) |
||
4121 | { |
||
4122 | if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) |
||
4123 | { |
||
4124 | if (Prev_State == I2C_STATE_MASTER_BUSY_RX) |
||
4125 | { |
||
4126 | /* Disable Acknowledge */ |
||
4127 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4128 | |||
4129 | /* Enable Pos */ |
||
4130 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4131 | |||
4132 | /* Enable Last DMA bit */ |
||
4133 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
4134 | } |
||
4135 | else |
||
4136 | { |
||
4137 | /* Enable Acknowledge */ |
||
4138 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4139 | } |
||
4140 | } |
||
4141 | else |
||
4142 | { |
||
4143 | /* Enable Acknowledge */ |
||
4144 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4145 | |||
4146 | if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
||
4147 | { |
||
4148 | /* Enable Last DMA bit */ |
||
4149 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
4150 | } |
||
4151 | } |
||
4152 | if (hi2c->hdmarx != NULL) |
||
4153 | { |
||
4154 | /* Set the I2C DMA transfer complete callback */ |
||
4155 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
4156 | |||
4157 | /* Set the DMA error callback */ |
||
4158 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
4159 | |||
4160 | /* Set the unused DMA callbacks to NULL */ |
||
4161 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
4162 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
4163 | |||
4164 | /* Enable the DMA channel */ |
||
4165 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
4166 | } |
||
4167 | else |
||
4168 | { |
||
4169 | /* Update I2C state */ |
||
4170 | hi2c->State = HAL_I2C_STATE_READY; |
||
4171 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4172 | |||
4173 | /* Update I2C error code */ |
||
4174 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
4175 | |||
4176 | /* Process Unlocked */ |
||
4177 | __HAL_UNLOCK(hi2c); |
||
4178 | |||
4179 | return HAL_ERROR; |
||
4180 | } |
||
4181 | if (dmaxferstatus == HAL_OK) |
||
4182 | { |
||
4183 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
4184 | /* Mean Previous state is same as current state */ |
||
4185 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
4186 | { |
||
4187 | /* Generate Start */ |
||
4188 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
4189 | |||
4190 | /* Update interrupt for only EVT and ERR */ |
||
4191 | enableIT = (I2C_IT_EVT | I2C_IT_ERR); |
||
4192 | } |
||
4193 | else |
||
4194 | { |
||
4195 | /* Update interrupt for only ERR */ |
||
4196 | enableIT = I2C_IT_ERR; |
||
4197 | } |
||
4198 | |||
4199 | /* Process Unlocked */ |
||
4200 | __HAL_UNLOCK(hi2c); |
||
4201 | |||
4202 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4203 | to avoid the risk of I2C interrupt handle execution before current |
||
4204 | process unlock */ |
||
4205 | |||
4206 | /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ |
||
4207 | /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ |
||
4208 | if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
||
4209 | { |
||
4210 | /* Enable DMA Request */ |
||
4211 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4212 | } |
||
4213 | |||
4214 | /* Enable EVT and ERR interrupt */ |
||
4215 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
||
4216 | } |
||
4217 | else |
||
4218 | { |
||
4219 | /* Update I2C state */ |
||
4220 | hi2c->State = HAL_I2C_STATE_READY; |
||
4221 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4222 | |||
4223 | /* Update I2C error code */ |
||
4224 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
4225 | |||
4226 | /* Process Unlocked */ |
||
4227 | __HAL_UNLOCK(hi2c); |
||
4228 | |||
4229 | return HAL_ERROR; |
||
4230 | } |
||
4231 | } |
||
4232 | else |
||
4233 | { |
||
4234 | /* Enable Acknowledge */ |
||
4235 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4236 | |||
4237 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
4238 | /* Mean Previous state is same as current state */ |
||
4239 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
4240 | { |
||
4241 | /* Generate Start */ |
||
4242 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
4243 | } |
||
4244 | |||
4245 | /* Process Unlocked */ |
||
4246 | __HAL_UNLOCK(hi2c); |
||
4247 | |||
4248 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4249 | to avoid the risk of I2C interrupt handle execution before current |
||
4250 | process unlock */ |
||
4251 | |||
4252 | /* Enable interrupts */ |
||
4253 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
||
4254 | } |
||
4255 | return HAL_OK; |
||
4256 | } |
||
4257 | else |
||
4258 | { |
||
4259 | return HAL_BUSY; |
||
4260 | } |
||
4261 | } |
||
4262 | |||
4263 | /** |
||
4264 | * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt |
||
4265 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
4266 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4267 | * the configuration information for the specified I2C. |
||
4268 | * @param pData Pointer to data buffer |
||
4269 | * @param Size Amount of data to be sent |
||
4270 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
4271 | * @retval HAL status |
||
4272 | */ |
||
4273 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
4274 | { |
||
4275 | /* Check the parameters */ |
||
4276 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
4277 | |||
4278 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
4279 | { |
||
4280 | if ((pData == NULL) || (Size == 0U)) |
||
4281 | { |
||
4282 | return HAL_ERROR; |
||
4283 | } |
||
4284 | |||
4285 | /* Process Locked */ |
||
4286 | __HAL_LOCK(hi2c); |
||
4287 | |||
4288 | /* Check if the I2C is already enabled */ |
||
4289 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4290 | { |
||
4291 | /* Enable I2C peripheral */ |
||
4292 | __HAL_I2C_ENABLE(hi2c); |
||
4293 | } |
||
4294 | |||
4295 | /* Disable Pos */ |
||
4296 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4297 | |||
4298 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
||
4299 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
4300 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
4301 | |||
4302 | /* Prepare transfer parameters */ |
||
4303 | hi2c->pBuffPtr = pData; |
||
4304 | hi2c->XferCount = Size; |
||
4305 | hi2c->XferSize = hi2c->XferCount; |
||
4306 | hi2c->XferOptions = XferOptions; |
||
4307 | |||
4308 | /* Clear ADDR flag */ |
||
4309 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
4310 | |||
4311 | /* Process Unlocked */ |
||
4312 | __HAL_UNLOCK(hi2c); |
||
4313 | |||
4314 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4315 | to avoid the risk of I2C interrupt handle execution before current |
||
4316 | process unlock */ |
||
4317 | |||
4318 | /* Enable EVT, BUF and ERR interrupt */ |
||
4319 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
4320 | |||
4321 | return HAL_OK; |
||
4322 | } |
||
4323 | else |
||
4324 | { |
||
4325 | return HAL_BUSY; |
||
4326 | } |
||
4327 | } |
||
4328 | |||
4329 | /** |
||
4330 | * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA |
||
4331 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
4332 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4333 | * the configuration information for the specified I2C. |
||
4334 | * @param pData Pointer to data buffer |
||
4335 | * @param Size Amount of data to be sent |
||
4336 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
4337 | * @retval HAL status |
||
4338 | */ |
||
4339 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
4340 | { |
||
4341 | HAL_StatusTypeDef dmaxferstatus; |
||
4342 | |||
4343 | /* Check the parameters */ |
||
4344 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
4345 | |||
4346 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
4347 | { |
||
4348 | if ((pData == NULL) || (Size == 0U)) |
||
4349 | { |
||
4350 | return HAL_ERROR; |
||
4351 | } |
||
4352 | |||
4353 | /* Process Locked */ |
||
4354 | __HAL_LOCK(hi2c); |
||
4355 | |||
4356 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
||
4357 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4358 | |||
4359 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
||
4360 | /* and then toggle the HAL slave RX state to TX state */ |
||
4361 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
||
4362 | { |
||
4363 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
4364 | { |
||
4365 | /* Abort DMA Xfer if any */ |
||
4366 | if (hi2c->hdmarx != NULL) |
||
4367 | { |
||
4368 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4369 | |||
4370 | /* Set the I2C DMA Abort callback : |
||
4371 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
4372 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
||
4373 | |||
4374 | /* Abort DMA RX */ |
||
4375 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
||
4376 | { |
||
4377 | /* Call Directly XferAbortCallback function in case of error */ |
||
4378 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
||
4379 | } |
||
4380 | } |
||
4381 | } |
||
4382 | } |
||
4383 | else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
||
4384 | { |
||
4385 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
4386 | { |
||
4387 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4388 | |||
4389 | /* Abort DMA Xfer if any */ |
||
4390 | if (hi2c->hdmatx != NULL) |
||
4391 | { |
||
4392 | /* Set the I2C DMA Abort callback : |
||
4393 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
4394 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
||
4395 | |||
4396 | /* Abort DMA TX */ |
||
4397 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
||
4398 | { |
||
4399 | /* Call Directly XferAbortCallback function in case of error */ |
||
4400 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
||
4401 | } |
||
4402 | } |
||
4403 | } |
||
4404 | } |
||
4405 | else |
||
4406 | { |
||
4407 | /* Nothing to do */ |
||
4408 | } |
||
4409 | |||
4410 | /* Check if the I2C is already enabled */ |
||
4411 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4412 | { |
||
4413 | /* Enable I2C peripheral */ |
||
4414 | __HAL_I2C_ENABLE(hi2c); |
||
4415 | } |
||
4416 | |||
4417 | /* Disable Pos */ |
||
4418 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4419 | |||
4420 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
||
4421 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
4422 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
4423 | |||
4424 | /* Prepare transfer parameters */ |
||
4425 | hi2c->pBuffPtr = pData; |
||
4426 | hi2c->XferCount = Size; |
||
4427 | hi2c->XferSize = hi2c->XferCount; |
||
4428 | hi2c->XferOptions = XferOptions; |
||
4429 | |||
4430 | if (hi2c->hdmatx != NULL) |
||
4431 | { |
||
4432 | /* Set the I2C DMA transfer complete callback */ |
||
4433 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
4434 | |||
4435 | /* Set the DMA error callback */ |
||
4436 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
4437 | |||
4438 | /* Set the unused DMA callbacks to NULL */ |
||
4439 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
4440 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
4441 | |||
4442 | /* Enable the DMA channel */ |
||
4443 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
4444 | } |
||
4445 | else |
||
4446 | { |
||
4447 | /* Update I2C state */ |
||
4448 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
4449 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4450 | |||
4451 | /* Update I2C error code */ |
||
4452 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
4453 | |||
4454 | /* Process Unlocked */ |
||
4455 | __HAL_UNLOCK(hi2c); |
||
4456 | |||
4457 | return HAL_ERROR; |
||
4458 | } |
||
4459 | |||
4460 | if (dmaxferstatus == HAL_OK) |
||
4461 | { |
||
4462 | /* Enable Address Acknowledge */ |
||
4463 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4464 | |||
4465 | /* Clear ADDR flag */ |
||
4466 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
4467 | |||
4468 | /* Process Unlocked */ |
||
4469 | __HAL_UNLOCK(hi2c); |
||
4470 | |||
4471 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4472 | to avoid the risk of I2C interrupt handle execution before current |
||
4473 | process unlock */ |
||
4474 | /* Enable EVT and ERR interrupt */ |
||
4475 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4476 | |||
4477 | /* Enable DMA Request */ |
||
4478 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
4479 | |||
4480 | return HAL_OK; |
||
4481 | } |
||
4482 | else |
||
4483 | { |
||
4484 | /* Update I2C state */ |
||
4485 | hi2c->State = HAL_I2C_STATE_READY; |
||
4486 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4487 | |||
4488 | /* Update I2C error code */ |
||
4489 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
4490 | |||
4491 | /* Process Unlocked */ |
||
4492 | __HAL_UNLOCK(hi2c); |
||
4493 | |||
4494 | return HAL_ERROR; |
||
4495 | } |
||
4496 | } |
||
4497 | else |
||
4498 | { |
||
4499 | return HAL_BUSY; |
||
4500 | } |
||
4501 | } |
||
4502 | |||
4503 | /** |
||
4504 | * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt |
||
4505 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
4506 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4507 | * the configuration information for the specified I2C. |
||
4508 | * @param pData Pointer to data buffer |
||
4509 | * @param Size Amount of data to be sent |
||
4510 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
4511 | * @retval HAL status |
||
4512 | */ |
||
4513 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
4514 | { |
||
4515 | /* Check the parameters */ |
||
4516 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
4517 | |||
4518 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
4519 | { |
||
4520 | if ((pData == NULL) || (Size == 0U)) |
||
4521 | { |
||
4522 | return HAL_ERROR; |
||
4523 | } |
||
4524 | |||
4525 | /* Process Locked */ |
||
4526 | __HAL_LOCK(hi2c); |
||
4527 | |||
4528 | /* Check if the I2C is already enabled */ |
||
4529 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4530 | { |
||
4531 | /* Enable I2C peripheral */ |
||
4532 | __HAL_I2C_ENABLE(hi2c); |
||
4533 | } |
||
4534 | |||
4535 | /* Disable Pos */ |
||
4536 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4537 | |||
4538 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
||
4539 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
4540 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
4541 | |||
4542 | /* Prepare transfer parameters */ |
||
4543 | hi2c->pBuffPtr = pData; |
||
4544 | hi2c->XferCount = Size; |
||
4545 | hi2c->XferSize = hi2c->XferCount; |
||
4546 | hi2c->XferOptions = XferOptions; |
||
4547 | |||
4548 | /* Clear ADDR flag */ |
||
4549 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
4550 | |||
4551 | /* Process Unlocked */ |
||
4552 | __HAL_UNLOCK(hi2c); |
||
4553 | |||
4554 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4555 | to avoid the risk of I2C interrupt handle execution before current |
||
4556 | process unlock */ |
||
4557 | |||
4558 | /* Enable EVT, BUF and ERR interrupt */ |
||
4559 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
4560 | |||
4561 | return HAL_OK; |
||
4562 | } |
||
4563 | else |
||
4564 | { |
||
4565 | return HAL_BUSY; |
||
4566 | } |
||
4567 | } |
||
4568 | |||
4569 | /** |
||
4570 | * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA |
||
4571 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
4572 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4573 | * the configuration information for the specified I2C. |
||
4574 | * @param pData Pointer to data buffer |
||
4575 | * @param Size Amount of data to be sent |
||
4576 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
4577 | * @retval HAL status |
||
4578 | */ |
||
4579 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
4580 | { |
||
4581 | HAL_StatusTypeDef dmaxferstatus; |
||
4582 | |||
4583 | /* Check the parameters */ |
||
4584 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
4585 | |||
4586 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
4587 | { |
||
4588 | if ((pData == NULL) || (Size == 0U)) |
||
4589 | { |
||
4590 | return HAL_ERROR; |
||
4591 | } |
||
4592 | |||
4593 | /* Process Locked */ |
||
4594 | __HAL_LOCK(hi2c); |
||
4595 | |||
4596 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
||
4597 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4598 | |||
4599 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
||
4600 | /* and then toggle the HAL slave RX state to TX state */ |
||
4601 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
||
4602 | { |
||
4603 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
4604 | { |
||
4605 | /* Abort DMA Xfer if any */ |
||
4606 | if (hi2c->hdmarx != NULL) |
||
4607 | { |
||
4608 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4609 | |||
4610 | /* Set the I2C DMA Abort callback : |
||
4611 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
4612 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
||
4613 | |||
4614 | /* Abort DMA RX */ |
||
4615 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
||
4616 | { |
||
4617 | /* Call Directly XferAbortCallback function in case of error */ |
||
4618 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
||
4619 | } |
||
4620 | } |
||
4621 | } |
||
4622 | } |
||
4623 | else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
||
4624 | { |
||
4625 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
4626 | { |
||
4627 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4628 | |||
4629 | /* Abort DMA Xfer if any */ |
||
4630 | if (hi2c->hdmatx != NULL) |
||
4631 | { |
||
4632 | /* Set the I2C DMA Abort callback : |
||
4633 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
4634 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
||
4635 | |||
4636 | /* Abort DMA TX */ |
||
4637 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
||
4638 | { |
||
4639 | /* Call Directly XferAbortCallback function in case of error */ |
||
4640 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
||
4641 | } |
||
4642 | } |
||
4643 | } |
||
4644 | } |
||
4645 | else |
||
4646 | { |
||
4647 | /* Nothing to do */ |
||
4648 | } |
||
4649 | |||
4650 | /* Check if the I2C is already enabled */ |
||
4651 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4652 | { |
||
4653 | /* Enable I2C peripheral */ |
||
4654 | __HAL_I2C_ENABLE(hi2c); |
||
4655 | } |
||
4656 | |||
4657 | /* Disable Pos */ |
||
4658 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4659 | |||
4660 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
||
4661 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
4662 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
4663 | |||
4664 | /* Prepare transfer parameters */ |
||
4665 | hi2c->pBuffPtr = pData; |
||
4666 | hi2c->XferCount = Size; |
||
4667 | hi2c->XferSize = hi2c->XferCount; |
||
4668 | hi2c->XferOptions = XferOptions; |
||
4669 | |||
4670 | if (hi2c->hdmarx != NULL) |
||
4671 | { |
||
4672 | /* Set the I2C DMA transfer complete callback */ |
||
4673 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
4674 | |||
4675 | /* Set the DMA error callback */ |
||
4676 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
4677 | |||
4678 | /* Set the unused DMA callbacks to NULL */ |
||
4679 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
4680 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
4681 | |||
4682 | /* Enable the DMA channel */ |
||
4683 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
4684 | } |
||
4685 | else |
||
4686 | { |
||
4687 | /* Update I2C state */ |
||
4688 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
4689 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4690 | |||
4691 | /* Update I2C error code */ |
||
4692 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
||
4693 | |||
4694 | /* Process Unlocked */ |
||
4695 | __HAL_UNLOCK(hi2c); |
||
4696 | |||
4697 | return HAL_ERROR; |
||
4698 | } |
||
4699 | |||
4700 | if (dmaxferstatus == HAL_OK) |
||
4701 | { |
||
4702 | /* Enable Address Acknowledge */ |
||
4703 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4704 | |||
4705 | /* Clear ADDR flag */ |
||
4706 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
4707 | |||
4708 | /* Process Unlocked */ |
||
4709 | __HAL_UNLOCK(hi2c); |
||
4710 | |||
4711 | /* Enable DMA Request */ |
||
4712 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4713 | |||
4714 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4715 | to avoid the risk of I2C interrupt handle execution before current |
||
4716 | process unlock */ |
||
4717 | /* Enable EVT and ERR interrupt */ |
||
4718 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4719 | |||
4720 | return HAL_OK; |
||
4721 | } |
||
4722 | else |
||
4723 | { |
||
4724 | /* Update I2C state */ |
||
4725 | hi2c->State = HAL_I2C_STATE_READY; |
||
4726 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4727 | |||
4728 | /* Update I2C error code */ |
||
4729 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
4730 | |||
4731 | /* Process Unlocked */ |
||
4732 | __HAL_UNLOCK(hi2c); |
||
4733 | |||
4734 | return HAL_ERROR; |
||
4735 | } |
||
4736 | } |
||
4737 | else |
||
4738 | { |
||
4739 | return HAL_BUSY; |
||
4740 | } |
||
4741 | } |
||
4742 | |||
4743 | /** |
||
4744 | * @brief Enable the Address listen mode with Interrupt. |
||
4745 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4746 | * the configuration information for the specified I2C. |
||
4747 | * @retval HAL status |
||
4748 | */ |
||
4749 | HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) |
||
4750 | { |
||
4751 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
4752 | { |
||
4753 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
4754 | |||
4755 | /* Check if the I2C is already enabled */ |
||
4756 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4757 | { |
||
4758 | /* Enable I2C peripheral */ |
||
4759 | __HAL_I2C_ENABLE(hi2c); |
||
4760 | } |
||
4761 | |||
4762 | /* Enable Address Acknowledge */ |
||
4763 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4764 | |||
4765 | /* Enable EVT and ERR interrupt */ |
||
4766 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4767 | |||
4768 | return HAL_OK; |
||
4769 | } |
||
4770 | else |
||
4771 | { |
||
4772 | return HAL_BUSY; |
||
4773 | } |
||
4774 | } |
||
4775 | |||
4776 | /** |
||
4777 | * @brief Disable the Address listen mode with Interrupt. |
||
4778 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4779 | * the configuration information for the specified I2C. |
||
4780 | * @retval HAL status |
||
4781 | */ |
||
4782 | HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) |
||
4783 | { |
||
4784 | /* Declaration of tmp to prevent undefined behavior of volatile usage */ |
||
4785 | uint32_t tmp; |
||
4786 | |||
4787 | /* Disable Address listen mode only if a transfer is not ongoing */ |
||
4788 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
||
4789 | { |
||
4790 | tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; |
||
4791 | hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); |
||
4792 | hi2c->State = HAL_I2C_STATE_READY; |
||
4793 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4794 | |||
4795 | /* Disable Address Acknowledge */ |
||
4796 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4797 | |||
4798 | /* Disable EVT and ERR interrupt */ |
||
4799 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4800 | |||
4801 | return HAL_OK; |
||
4802 | } |
||
4803 | else |
||
4804 | { |
||
4805 | return HAL_BUSY; |
||
4806 | } |
||
4807 | } |
||
4808 | |||
4809 | /** |
||
4810 | * @brief Abort a master I2C IT or DMA process communication with Interrupt. |
||
4811 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4812 | * the configuration information for the specified I2C. |
||
4813 | * @param DevAddress Target device address: The device 7 bits address value |
||
4814 | * in datasheet must be shifted to the left before calling the interface |
||
4815 | * @retval HAL status |
||
4816 | */ |
||
4817 | HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) |
||
4818 | { |
||
4819 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
4820 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
4821 | |||
4822 | /* Prevent unused argument(s) compilation warning */ |
||
4823 | UNUSED(DevAddress); |
||
4824 | |||
4825 | /* Abort Master transfer during Receive or Transmit process */ |
||
4826 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER)) |
||
4827 | { |
||
4828 | /* Process Locked */ |
||
4829 | __HAL_LOCK(hi2c); |
||
4830 | |||
4831 | hi2c->PreviousState = I2C_STATE_NONE; |
||
4832 | hi2c->State = HAL_I2C_STATE_ABORT; |
||
4833 | |||
4834 | /* Disable Acknowledge */ |
||
4835 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4836 | |||
4837 | /* Generate Stop */ |
||
4838 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
4839 | |||
4840 | hi2c->XferCount = 0U; |
||
4841 | |||
4842 | /* Disable EVT, BUF and ERR interrupt */ |
||
4843 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
4844 | |||
4845 | /* Process Unlocked */ |
||
4846 | __HAL_UNLOCK(hi2c); |
||
4847 | |||
4848 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
4849 | I2C_ITError(hi2c); |
||
4850 | |||
4851 | return HAL_OK; |
||
4852 | } |
||
4853 | else |
||
4854 | { |
||
4855 | /* Wrong usage of abort function */ |
||
4856 | /* This function should be used only in case of abort monitored by master device */ |
||
4857 | /* Or periphal is not in busy state, mean there is no active sequence to be abort */ |
||
4858 | return HAL_ERROR; |
||
4859 | } |
||
4860 | } |
||
4861 | |||
4862 | /** |
||
4863 | * @} |
||
4864 | */ |
||
4865 | |||
4866 | /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
||
4867 | * @{ |
||
4868 | */ |
||
4869 | |||
4870 | /** |
||
4871 | * @brief This function handles I2C event interrupt request. |
||
4872 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4873 | * the configuration information for the specified I2C. |
||
4874 | * @retval None |
||
4875 | */ |
||
4876 | void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) |
||
4877 | { |
||
4878 | uint32_t sr1itflags; |
||
4879 | uint32_t sr2itflags = 0U; |
||
4880 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
||
4881 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
4882 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
4883 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
4884 | |||
4885 | /* Master or Memory mode selected */ |
||
4886 | if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) |
||
4887 | { |
||
4888 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
||
4889 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
4890 | |||
4891 | /* Exit IRQ event until Start Bit detected in case of Other frame requested */ |
||
4892 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) |
||
4893 | { |
||
4894 | return; |
||
4895 | } |
||
4896 | |||
4897 | /* SB Set ----------------------------------------------------------------*/ |
||
4898 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4899 | { |
||
4900 | /* Convert OTHER_xxx XferOptions if any */ |
||
4901 | I2C_ConvertOtherXferOptions(hi2c); |
||
4902 | |||
4903 | I2C_Master_SB(hi2c); |
||
4904 | } |
||
4905 | /* ADD10 Set -------------------------------------------------------------*/ |
||
4906 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4907 | { |
||
4908 | I2C_Master_ADD10(hi2c); |
||
4909 | } |
||
4910 | /* ADDR Set --------------------------------------------------------------*/ |
||
4911 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4912 | { |
||
4913 | I2C_Master_ADDR(hi2c); |
||
4914 | } |
||
4915 | /* I2C in mode Transmitter -----------------------------------------------*/ |
||
4916 | else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) |
||
4917 | { |
||
4918 | /* Do not check buffer and BTF flag if a Xfer DMA is on going */ |
||
4919 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) |
||
4920 | { |
||
4921 | /* TXE set and BTF reset -----------------------------------------------*/ |
||
4922 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
||
4923 | { |
||
4924 | I2C_MasterTransmit_TXE(hi2c); |
||
4925 | } |
||
4926 | /* BTF set -------------------------------------------------------------*/ |
||
4927 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4928 | { |
||
4929 | if (CurrentState == HAL_I2C_STATE_BUSY_TX) |
||
4930 | { |
||
4931 | I2C_MasterTransmit_BTF(hi2c); |
||
4932 | } |
||
4933 | else /* HAL_I2C_MODE_MEM */ |
||
4934 | { |
||
4935 | if (CurrentMode == HAL_I2C_MODE_MEM) |
||
4936 | { |
||
4937 | I2C_MemoryTransmit_TXE_BTF(hi2c); |
||
4938 | } |
||
4939 | } |
||
4940 | } |
||
4941 | else |
||
4942 | { |
||
4943 | /* Do nothing */ |
||
4944 | } |
||
4945 | } |
||
4946 | } |
||
4947 | /* I2C in mode Receiver --------------------------------------------------*/ |
||
4948 | else |
||
4949 | { |
||
4950 | /* Do not check buffer and BTF flag if a Xfer DMA is on going */ |
||
4951 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) |
||
4952 | { |
||
4953 | /* RXNE set and BTF reset -----------------------------------------------*/ |
||
4954 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
||
4955 | { |
||
4956 | I2C_MasterReceive_RXNE(hi2c); |
||
4957 | } |
||
4958 | /* BTF set -------------------------------------------------------------*/ |
||
4959 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4960 | { |
||
4961 | I2C_MasterReceive_BTF(hi2c); |
||
4962 | } |
||
4963 | else |
||
4964 | { |
||
4965 | /* Do nothing */ |
||
4966 | } |
||
4967 | } |
||
4968 | } |
||
4969 | } |
||
4970 | /* Slave mode selected */ |
||
4971 | else |
||
4972 | { |
||
4973 | /* If an error is detected, read only SR1 register to prevent */ |
||
4974 | /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ |
||
4975 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
4976 | { |
||
4977 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
4978 | } |
||
4979 | else |
||
4980 | { |
||
4981 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
||
4982 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
4983 | } |
||
4984 | |||
4985 | /* ADDR set --------------------------------------------------------------*/ |
||
4986 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4987 | { |
||
4988 | /* Now time to read SR2, this will clear ADDR flag automatically */ |
||
4989 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
4990 | { |
||
4991 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
||
4992 | } |
||
4993 | I2C_Slave_ADDR(hi2c, sr2itflags); |
||
4994 | } |
||
4995 | /* STOPF set --------------------------------------------------------------*/ |
||
4996 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4997 | { |
||
4998 | I2C_Slave_STOPF(hi2c); |
||
4999 | } |
||
5000 | /* I2C in mode Transmitter -----------------------------------------------*/ |
||
5001 | else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
||
5002 | { |
||
5003 | /* TXE set and BTF reset -----------------------------------------------*/ |
||
5004 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
||
5005 | { |
||
5006 | I2C_SlaveTransmit_TXE(hi2c); |
||
5007 | } |
||
5008 | /* BTF set -------------------------------------------------------------*/ |
||
5009 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
5010 | { |
||
5011 | I2C_SlaveTransmit_BTF(hi2c); |
||
5012 | } |
||
5013 | else |
||
5014 | { |
||
5015 | /* Do nothing */ |
||
5016 | } |
||
5017 | } |
||
5018 | /* I2C in mode Receiver --------------------------------------------------*/ |
||
5019 | else |
||
5020 | { |
||
5021 | /* RXNE set and BTF reset ----------------------------------------------*/ |
||
5022 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
||
5023 | { |
||
5024 | I2C_SlaveReceive_RXNE(hi2c); |
||
5025 | } |
||
5026 | /* BTF set -------------------------------------------------------------*/ |
||
5027 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
5028 | { |
||
5029 | I2C_SlaveReceive_BTF(hi2c); |
||
5030 | } |
||
5031 | else |
||
5032 | { |
||
5033 | /* Do nothing */ |
||
5034 | } |
||
5035 | } |
||
5036 | } |
||
5037 | } |
||
5038 | |||
5039 | /** |
||
5040 | * @brief This function handles I2C error interrupt request. |
||
5041 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5042 | * the configuration information for the specified I2C. |
||
5043 | * @retval None |
||
5044 | */ |
||
5045 | void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) |
||
5046 | { |
||
5047 | HAL_I2C_ModeTypeDef tmp1; |
||
5048 | uint32_t tmp2; |
||
5049 | HAL_I2C_StateTypeDef tmp3; |
||
5050 | uint32_t tmp4; |
||
5051 | uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
5052 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
||
5053 | uint32_t error = HAL_I2C_ERROR_NONE; |
||
5054 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
5055 | |||
5056 | /* I2C Bus error interrupt occurred ----------------------------------------*/ |
||
5057 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
||
5058 | { |
||
5059 | error |= HAL_I2C_ERROR_BERR; |
||
5060 | |||
5061 | /* Clear BERR flag */ |
||
5062 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); |
||
5063 | |||
5064 | /* Workaround: Start cannot be generated after a misplaced Stop */ |
||
5065 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST); |
||
5066 | } |
||
5067 | |||
5068 | /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ |
||
5069 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
||
5070 | { |
||
5071 | error |= HAL_I2C_ERROR_ARLO; |
||
5072 | |||
5073 | /* Clear ARLO flag */ |
||
5074 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); |
||
5075 | } |
||
5076 | |||
5077 | /* I2C Acknowledge failure error interrupt occurred ------------------------*/ |
||
5078 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
||
5079 | { |
||
5080 | tmp1 = CurrentMode; |
||
5081 | tmp2 = hi2c->XferCount; |
||
5082 | tmp3 = hi2c->State; |
||
5083 | tmp4 = hi2c->PreviousState; |
||
5084 | if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ |
||
5085 | ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ |
||
5086 | ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) |
||
5087 | { |
||
5088 | I2C_Slave_AF(hi2c); |
||
5089 | } |
||
5090 | else |
||
5091 | { |
||
5092 | /* Clear AF flag */ |
||
5093 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
5094 | |||
5095 | error |= HAL_I2C_ERROR_AF; |
||
5096 | |||
5097 | /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ |
||
5098 | if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) |
||
5099 | { |
||
5100 | /* Generate Stop */ |
||
5101 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5102 | } |
||
5103 | } |
||
5104 | } |
||
5105 | |||
5106 | /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ |
||
5107 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
||
5108 | { |
||
5109 | error |= HAL_I2C_ERROR_OVR; |
||
5110 | /* Clear OVR flag */ |
||
5111 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); |
||
5112 | } |
||
5113 | |||
5114 | /* Call the Error Callback in case of Error detected -----------------------*/ |
||
5115 | if (error != HAL_I2C_ERROR_NONE) |
||
5116 | { |
||
5117 | hi2c->ErrorCode |= error; |
||
5118 | I2C_ITError(hi2c); |
||
5119 | } |
||
5120 | } |
||
5121 | |||
5122 | /** |
||
5123 | * @brief Master Tx Transfer completed callback. |
||
5124 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5125 | * the configuration information for the specified I2C. |
||
5126 | * @retval None |
||
5127 | */ |
||
5128 | __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
5129 | { |
||
5130 | /* Prevent unused argument(s) compilation warning */ |
||
5131 | UNUSED(hi2c); |
||
5132 | |||
5133 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5134 | the HAL_I2C_MasterTxCpltCallback could be implemented in the user file |
||
5135 | */ |
||
5136 | } |
||
5137 | |||
5138 | /** |
||
5139 | * @brief Master Rx Transfer completed callback. |
||
5140 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5141 | * the configuration information for the specified I2C. |
||
5142 | * @retval None |
||
5143 | */ |
||
5144 | __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
5145 | { |
||
5146 | /* Prevent unused argument(s) compilation warning */ |
||
5147 | UNUSED(hi2c); |
||
5148 | |||
5149 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5150 | the HAL_I2C_MasterRxCpltCallback could be implemented in the user file |
||
5151 | */ |
||
5152 | } |
||
5153 | |||
5154 | /** @brief Slave Tx Transfer completed callback. |
||
5155 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5156 | * the configuration information for the specified I2C. |
||
5157 | * @retval None |
||
5158 | */ |
||
5159 | __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
5160 | { |
||
5161 | /* Prevent unused argument(s) compilation warning */ |
||
5162 | UNUSED(hi2c); |
||
5163 | |||
5164 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5165 | the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file |
||
5166 | */ |
||
5167 | } |
||
5168 | |||
5169 | /** |
||
5170 | * @brief Slave Rx Transfer completed callback. |
||
5171 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5172 | * the configuration information for the specified I2C. |
||
5173 | * @retval None |
||
5174 | */ |
||
5175 | __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
5176 | { |
||
5177 | /* Prevent unused argument(s) compilation warning */ |
||
5178 | UNUSED(hi2c); |
||
5179 | |||
5180 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5181 | the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file |
||
5182 | */ |
||
5183 | } |
||
5184 | |||
5185 | /** |
||
5186 | * @brief Slave Address Match callback. |
||
5187 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5188 | * the configuration information for the specified I2C. |
||
5189 | * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition |
||
5190 | * @param AddrMatchCode Address Match Code |
||
5191 | * @retval None |
||
5192 | */ |
||
5193 | __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) |
||
5194 | { |
||
5195 | /* Prevent unused argument(s) compilation warning */ |
||
5196 | UNUSED(hi2c); |
||
5197 | UNUSED(TransferDirection); |
||
5198 | UNUSED(AddrMatchCode); |
||
5199 | |||
5200 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5201 | the HAL_I2C_AddrCallback() could be implemented in the user file |
||
5202 | */ |
||
5203 | } |
||
5204 | |||
5205 | /** |
||
5206 | * @brief Listen Complete callback. |
||
5207 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5208 | * the configuration information for the specified I2C. |
||
5209 | * @retval None |
||
5210 | */ |
||
5211 | __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) |
||
5212 | { |
||
5213 | /* Prevent unused argument(s) compilation warning */ |
||
5214 | UNUSED(hi2c); |
||
5215 | |||
5216 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5217 | the HAL_I2C_ListenCpltCallback() could be implemented in the user file |
||
5218 | */ |
||
5219 | } |
||
5220 | |||
5221 | /** |
||
5222 | * @brief Memory Tx Transfer completed callback. |
||
5223 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5224 | * the configuration information for the specified I2C. |
||
5225 | * @retval None |
||
5226 | */ |
||
5227 | __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
5228 | { |
||
5229 | /* Prevent unused argument(s) compilation warning */ |
||
5230 | UNUSED(hi2c); |
||
5231 | |||
5232 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5233 | the HAL_I2C_MemTxCpltCallback could be implemented in the user file |
||
5234 | */ |
||
5235 | } |
||
5236 | |||
5237 | /** |
||
5238 | * @brief Memory Rx Transfer completed callback. |
||
5239 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5240 | * the configuration information for the specified I2C. |
||
5241 | * @retval None |
||
5242 | */ |
||
5243 | __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
5244 | { |
||
5245 | /* Prevent unused argument(s) compilation warning */ |
||
5246 | UNUSED(hi2c); |
||
5247 | |||
5248 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5249 | the HAL_I2C_MemRxCpltCallback could be implemented in the user file |
||
5250 | */ |
||
5251 | } |
||
5252 | |||
5253 | /** |
||
5254 | * @brief I2C error callback. |
||
5255 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5256 | * the configuration information for the specified I2C. |
||
5257 | * @retval None |
||
5258 | */ |
||
5259 | __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) |
||
5260 | { |
||
5261 | /* Prevent unused argument(s) compilation warning */ |
||
5262 | UNUSED(hi2c); |
||
5263 | |||
5264 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5265 | the HAL_I2C_ErrorCallback could be implemented in the user file |
||
5266 | */ |
||
5267 | } |
||
5268 | |||
5269 | /** |
||
5270 | * @brief I2C abort callback. |
||
5271 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5272 | * the configuration information for the specified I2C. |
||
5273 | * @retval None |
||
5274 | */ |
||
5275 | __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) |
||
5276 | { |
||
5277 | /* Prevent unused argument(s) compilation warning */ |
||
5278 | UNUSED(hi2c); |
||
5279 | |||
5280 | /* NOTE : This function should not be modified, when the callback is needed, |
||
5281 | the HAL_I2C_AbortCpltCallback could be implemented in the user file |
||
5282 | */ |
||
5283 | } |
||
5284 | |||
5285 | /** |
||
5286 | * @} |
||
5287 | */ |
||
5288 | |||
5289 | /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions |
||
5290 | * @brief Peripheral State, Mode and Error functions |
||
5291 | * |
||
5292 | @verbatim |
||
5293 | =============================================================================== |
||
5294 | ##### Peripheral State, Mode and Error functions ##### |
||
5295 | =============================================================================== |
||
5296 | [..] |
||
5297 | This subsection permit to get in run-time the status of the peripheral |
||
5298 | and the data flow. |
||
5299 | |||
5300 | @endverbatim |
||
5301 | * @{ |
||
5302 | */ |
||
5303 | |||
5304 | /** |
||
5305 | * @brief Return the I2C handle state. |
||
5306 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5307 | * the configuration information for the specified I2C. |
||
5308 | * @retval HAL state |
||
5309 | */ |
||
5310 | HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) |
||
5311 | { |
||
5312 | /* Return I2C handle state */ |
||
5313 | return hi2c->State; |
||
5314 | } |
||
5315 | |||
5316 | /** |
||
5317 | * @brief Returns the I2C Master, Slave, Memory or no mode. |
||
5318 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5319 | * the configuration information for I2C module |
||
5320 | * @retval HAL mode |
||
5321 | */ |
||
5322 | HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) |
||
5323 | { |
||
5324 | return hi2c->Mode; |
||
5325 | } |
||
5326 | |||
5327 | /** |
||
5328 | * @brief Return the I2C error code. |
||
5329 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5330 | * the configuration information for the specified I2C. |
||
5331 | * @retval I2C Error Code |
||
5332 | */ |
||
5333 | uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) |
||
5334 | { |
||
5335 | return hi2c->ErrorCode; |
||
5336 | } |
||
5337 | |||
5338 | /** |
||
5339 | * @} |
||
5340 | */ |
||
5341 | |||
5342 | /** |
||
5343 | * @} |
||
5344 | */ |
||
5345 | |||
5346 | /** @addtogroup I2C_Private_Functions |
||
5347 | * @{ |
||
5348 | */ |
||
5349 | |||
5350 | /** |
||
5351 | * @brief Handle TXE flag for Master |
||
5352 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5353 | * the configuration information for I2C module |
||
5354 | * @retval None |
||
5355 | */ |
||
5356 | static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) |
||
5357 | { |
||
5358 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5359 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
5360 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
5361 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
5362 | |||
5363 | if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
||
5364 | { |
||
5365 | /* Call TxCpltCallback() directly if no stop mode is set */ |
||
5366 | if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
||
5367 | { |
||
5368 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5369 | |||
5370 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
||
5371 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5372 | hi2c->State = HAL_I2C_STATE_READY; |
||
5373 | |||
5374 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5375 | hi2c->MasterTxCpltCallback(hi2c); |
||
5376 | #else |
||
5377 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
5378 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5379 | } |
||
5380 | else /* Generate Stop condition then Call TxCpltCallback() */ |
||
5381 | { |
||
5382 | /* Disable EVT, BUF and ERR interrupt */ |
||
5383 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5384 | |||
5385 | /* Generate Stop */ |
||
5386 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5387 | |||
5388 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5389 | hi2c->State = HAL_I2C_STATE_READY; |
||
5390 | |||
5391 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5392 | { |
||
5393 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5394 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5395 | hi2c->MemTxCpltCallback(hi2c); |
||
5396 | #else |
||
5397 | HAL_I2C_MemTxCpltCallback(hi2c); |
||
5398 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5399 | } |
||
5400 | else |
||
5401 | { |
||
5402 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5403 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5404 | hi2c->MasterTxCpltCallback(hi2c); |
||
5405 | #else |
||
5406 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
5407 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5408 | } |
||
5409 | } |
||
5410 | } |
||
5411 | else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ |
||
5412 | ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) |
||
5413 | { |
||
5414 | if (hi2c->XferCount == 0U) |
||
5415 | { |
||
5416 | /* Disable BUF interrupt */ |
||
5417 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5418 | } |
||
5419 | else |
||
5420 | { |
||
5421 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5422 | { |
||
5423 | I2C_MemoryTransmit_TXE_BTF(hi2c); |
||
5424 | } |
||
5425 | else |
||
5426 | { |
||
5427 | /* Write data to DR */ |
||
5428 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
5429 | |||
5430 | /* Increment Buffer pointer */ |
||
5431 | hi2c->pBuffPtr++; |
||
5432 | |||
5433 | /* Update counter */ |
||
5434 | hi2c->XferCount--; |
||
5435 | } |
||
5436 | } |
||
5437 | } |
||
5438 | else |
||
5439 | { |
||
5440 | /* Do nothing */ |
||
5441 | } |
||
5442 | } |
||
5443 | |||
5444 | /** |
||
5445 | * @brief Handle BTF flag for Master transmitter |
||
5446 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5447 | * the configuration information for I2C module |
||
5448 | * @retval None |
||
5449 | */ |
||
5450 | static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) |
||
5451 | { |
||
5452 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5453 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
5454 | |||
5455 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
||
5456 | { |
||
5457 | if (hi2c->XferCount != 0U) |
||
5458 | { |
||
5459 | /* Write data to DR */ |
||
5460 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
5461 | |||
5462 | /* Increment Buffer pointer */ |
||
5463 | hi2c->pBuffPtr++; |
||
5464 | |||
5465 | /* Update counter */ |
||
5466 | hi2c->XferCount--; |
||
5467 | } |
||
5468 | else |
||
5469 | { |
||
5470 | /* Call TxCpltCallback() directly if no stop mode is set */ |
||
5471 | if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
||
5472 | { |
||
5473 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5474 | |||
5475 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
||
5476 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5477 | hi2c->State = HAL_I2C_STATE_READY; |
||
5478 | |||
5479 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5480 | hi2c->MasterTxCpltCallback(hi2c); |
||
5481 | #else |
||
5482 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
5483 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5484 | } |
||
5485 | else /* Generate Stop condition then Call TxCpltCallback() */ |
||
5486 | { |
||
5487 | /* Disable EVT, BUF and ERR interrupt */ |
||
5488 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5489 | |||
5490 | /* Generate Stop */ |
||
5491 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5492 | |||
5493 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5494 | hi2c->State = HAL_I2C_STATE_READY; |
||
5495 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5496 | { |
||
5497 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5498 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5499 | hi2c->MemTxCpltCallback(hi2c); |
||
5500 | #else |
||
5501 | HAL_I2C_MemTxCpltCallback(hi2c); |
||
5502 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5503 | } |
||
5504 | else |
||
5505 | { |
||
5506 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5507 | |||
5508 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5509 | hi2c->MasterTxCpltCallback(hi2c); |
||
5510 | #else |
||
5511 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
5512 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5513 | } |
||
5514 | } |
||
5515 | } |
||
5516 | } |
||
5517 | else |
||
5518 | { |
||
5519 | /* Do nothing */ |
||
5520 | } |
||
5521 | } |
||
5522 | |||
5523 | /** |
||
5524 | * @brief Handle TXE and BTF flag for Memory transmitter |
||
5525 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5526 | * the configuration information for I2C module |
||
5527 | * @retval None |
||
5528 | */ |
||
5529 | static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) |
||
5530 | { |
||
5531 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5532 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
5533 | |||
5534 | if (hi2c->EventCount == 0U) |
||
5535 | { |
||
5536 | /* If Memory address size is 8Bit */ |
||
5537 | if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) |
||
5538 | { |
||
5539 | /* Send Memory Address */ |
||
5540 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
||
5541 | |||
5542 | hi2c->EventCount += 2U; |
||
5543 | } |
||
5544 | /* If Memory address size is 16Bit */ |
||
5545 | else |
||
5546 | { |
||
5547 | /* Send MSB of Memory Address */ |
||
5548 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); |
||
5549 | |||
5550 | hi2c->EventCount++; |
||
5551 | } |
||
5552 | } |
||
5553 | else if (hi2c->EventCount == 1U) |
||
5554 | { |
||
5555 | /* Send LSB of Memory Address */ |
||
5556 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
||
5557 | |||
5558 | hi2c->EventCount++; |
||
5559 | } |
||
5560 | else if (hi2c->EventCount == 2U) |
||
5561 | { |
||
5562 | if (CurrentState == HAL_I2C_STATE_BUSY_RX) |
||
5563 | { |
||
5564 | /* Generate Restart */ |
||
5565 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
5566 | |||
5567 | hi2c->EventCount++; |
||
5568 | } |
||
5569 | else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
||
5570 | { |
||
5571 | /* Write data to DR */ |
||
5572 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
5573 | |||
5574 | /* Increment Buffer pointer */ |
||
5575 | hi2c->pBuffPtr++; |
||
5576 | |||
5577 | /* Update counter */ |
||
5578 | hi2c->XferCount--; |
||
5579 | } |
||
5580 | else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
||
5581 | { |
||
5582 | /* Generate Stop condition then Call TxCpltCallback() */ |
||
5583 | /* Disable EVT, BUF and ERR interrupt */ |
||
5584 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5585 | |||
5586 | /* Generate Stop */ |
||
5587 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5588 | |||
5589 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5590 | hi2c->State = HAL_I2C_STATE_READY; |
||
5591 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5592 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5593 | hi2c->MemTxCpltCallback(hi2c); |
||
5594 | #else |
||
5595 | HAL_I2C_MemTxCpltCallback(hi2c); |
||
5596 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5597 | } |
||
5598 | else |
||
5599 | { |
||
5600 | /* Do nothing */ |
||
5601 | } |
||
5602 | } |
||
5603 | else |
||
5604 | { |
||
5605 | /* Do nothing */ |
||
5606 | } |
||
5607 | } |
||
5608 | |||
5609 | /** |
||
5610 | * @brief Handle RXNE flag for Master |
||
5611 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5612 | * the configuration information for I2C module |
||
5613 | * @retval None |
||
5614 | */ |
||
5615 | static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) |
||
5616 | { |
||
5617 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
||
5618 | { |
||
5619 | uint32_t tmp; |
||
5620 | |||
5621 | tmp = hi2c->XferCount; |
||
5622 | if (tmp > 3U) |
||
5623 | { |
||
5624 | /* Read data from DR */ |
||
5625 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5626 | |||
5627 | /* Increment Buffer pointer */ |
||
5628 | hi2c->pBuffPtr++; |
||
5629 | |||
5630 | /* Update counter */ |
||
5631 | hi2c->XferCount--; |
||
5632 | |||
5633 | if (hi2c->XferCount == (uint16_t)3) |
||
5634 | { |
||
5635 | /* Disable BUF interrupt, this help to treat correctly the last 4 bytes |
||
5636 | on BTF subroutine */ |
||
5637 | /* Disable BUF interrupt */ |
||
5638 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5639 | } |
||
5640 | } |
||
5641 | else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) |
||
5642 | { |
||
5643 | if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) |
||
5644 | { |
||
5645 | /* Disable Acknowledge */ |
||
5646 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5647 | |||
5648 | /* Disable EVT, BUF and ERR interrupt */ |
||
5649 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5650 | |||
5651 | /* Read data from DR */ |
||
5652 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5653 | |||
5654 | /* Increment Buffer pointer */ |
||
5655 | hi2c->pBuffPtr++; |
||
5656 | |||
5657 | /* Update counter */ |
||
5658 | hi2c->XferCount--; |
||
5659 | |||
5660 | hi2c->State = HAL_I2C_STATE_READY; |
||
5661 | |||
5662 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5663 | { |
||
5664 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5665 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5666 | |||
5667 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5668 | hi2c->MemRxCpltCallback(hi2c); |
||
5669 | #else |
||
5670 | HAL_I2C_MemRxCpltCallback(hi2c); |
||
5671 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5672 | } |
||
5673 | else |
||
5674 | { |
||
5675 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5676 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
||
5677 | |||
5678 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5679 | hi2c->MasterRxCpltCallback(hi2c); |
||
5680 | #else |
||
5681 | HAL_I2C_MasterRxCpltCallback(hi2c); |
||
5682 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5683 | } |
||
5684 | } |
||
5685 | else |
||
5686 | { |
||
5687 | /* Disable EVT, BUF and ERR interrupt */ |
||
5688 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5689 | |||
5690 | /* Read data from DR */ |
||
5691 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5692 | |||
5693 | /* Increment Buffer pointer */ |
||
5694 | hi2c->pBuffPtr++; |
||
5695 | |||
5696 | /* Update counter */ |
||
5697 | hi2c->XferCount--; |
||
5698 | |||
5699 | hi2c->State = HAL_I2C_STATE_READY; |
||
5700 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5701 | |||
5702 | /* Call user error callback */ |
||
5703 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5704 | hi2c->ErrorCallback(hi2c); |
||
5705 | #else |
||
5706 | HAL_I2C_ErrorCallback(hi2c); |
||
5707 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5708 | } |
||
5709 | } |
||
5710 | else |
||
5711 | { |
||
5712 | /* Do nothing */ |
||
5713 | } |
||
5714 | } |
||
5715 | } |
||
5716 | |||
5717 | /** |
||
5718 | * @brief Handle BTF flag for Master receiver |
||
5719 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5720 | * the configuration information for I2C module |
||
5721 | * @retval None |
||
5722 | */ |
||
5723 | static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) |
||
5724 | { |
||
5725 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5726 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
5727 | |||
5728 | if (hi2c->XferCount == 4U) |
||
5729 | { |
||
5730 | /* Disable BUF interrupt, this help to treat correctly the last 2 bytes |
||
5731 | on BTF subroutine if there is a reception delay between N-1 and N byte */ |
||
5732 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5733 | |||
5734 | /* Read data from DR */ |
||
5735 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5736 | |||
5737 | /* Increment Buffer pointer */ |
||
5738 | hi2c->pBuffPtr++; |
||
5739 | |||
5740 | /* Update counter */ |
||
5741 | hi2c->XferCount--; |
||
5742 | } |
||
5743 | else if (hi2c->XferCount == 3U) |
||
5744 | { |
||
5745 | /* Disable BUF interrupt, this help to treat correctly the last 2 bytes |
||
5746 | on BTF subroutine if there is a reception delay between N-1 and N byte */ |
||
5747 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5748 | |||
5749 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) |
||
5750 | { |
||
5751 | /* Disable Acknowledge */ |
||
5752 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5753 | } |
||
5754 | |||
5755 | /* Read data from DR */ |
||
5756 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5757 | |||
5758 | /* Increment Buffer pointer */ |
||
5759 | hi2c->pBuffPtr++; |
||
5760 | |||
5761 | /* Update counter */ |
||
5762 | hi2c->XferCount--; |
||
5763 | } |
||
5764 | else if (hi2c->XferCount == 2U) |
||
5765 | { |
||
5766 | /* Prepare next transfer or stop current transfer */ |
||
5767 | if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) |
||
5768 | { |
||
5769 | /* Disable Acknowledge */ |
||
5770 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5771 | } |
||
5772 | else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) |
||
5773 | { |
||
5774 | /* Enable Acknowledge */ |
||
5775 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5776 | } |
||
5777 | else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP) |
||
5778 | { |
||
5779 | /* Generate Stop */ |
||
5780 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5781 | } |
||
5782 | else |
||
5783 | { |
||
5784 | /* Do nothing */ |
||
5785 | } |
||
5786 | |||
5787 | /* Read data from DR */ |
||
5788 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5789 | |||
5790 | /* Increment Buffer pointer */ |
||
5791 | hi2c->pBuffPtr++; |
||
5792 | |||
5793 | /* Update counter */ |
||
5794 | hi2c->XferCount--; |
||
5795 | |||
5796 | /* Read data from DR */ |
||
5797 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5798 | |||
5799 | /* Increment Buffer pointer */ |
||
5800 | hi2c->pBuffPtr++; |
||
5801 | |||
5802 | /* Update counter */ |
||
5803 | hi2c->XferCount--; |
||
5804 | |||
5805 | /* Disable EVT and ERR interrupt */ |
||
5806 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
5807 | |||
5808 | hi2c->State = HAL_I2C_STATE_READY; |
||
5809 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5810 | { |
||
5811 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5812 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5813 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5814 | hi2c->MemRxCpltCallback(hi2c); |
||
5815 | #else |
||
5816 | HAL_I2C_MemRxCpltCallback(hi2c); |
||
5817 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5818 | } |
||
5819 | else |
||
5820 | { |
||
5821 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5822 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
||
5823 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5824 | hi2c->MasterRxCpltCallback(hi2c); |
||
5825 | #else |
||
5826 | HAL_I2C_MasterRxCpltCallback(hi2c); |
||
5827 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5828 | } |
||
5829 | } |
||
5830 | else |
||
5831 | { |
||
5832 | /* Read data from DR */ |
||
5833 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5834 | |||
5835 | /* Increment Buffer pointer */ |
||
5836 | hi2c->pBuffPtr++; |
||
5837 | |||
5838 | /* Update counter */ |
||
5839 | hi2c->XferCount--; |
||
5840 | } |
||
5841 | } |
||
5842 | |||
5843 | /** |
||
5844 | * @brief Handle SB flag for Master |
||
5845 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5846 | * the configuration information for I2C module |
||
5847 | * @retval None |
||
5848 | */ |
||
5849 | static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) |
||
5850 | { |
||
5851 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5852 | { |
||
5853 | if (hi2c->EventCount == 0U) |
||
5854 | { |
||
5855 | /* Send slave address */ |
||
5856 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
||
5857 | } |
||
5858 | else |
||
5859 | { |
||
5860 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
||
5861 | } |
||
5862 | } |
||
5863 | else |
||
5864 | { |
||
5865 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
||
5866 | { |
||
5867 | /* Send slave 7 Bits address */ |
||
5868 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
||
5869 | { |
||
5870 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
||
5871 | } |
||
5872 | else |
||
5873 | { |
||
5874 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
||
5875 | } |
||
5876 | |||
5877 | if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) |
||
5878 | || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) |
||
5879 | { |
||
5880 | /* Enable DMA Request */ |
||
5881 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
5882 | } |
||
5883 | } |
||
5884 | else |
||
5885 | { |
||
5886 | if (hi2c->EventCount == 0U) |
||
5887 | { |
||
5888 | /* Send header of slave address */ |
||
5889 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); |
||
5890 | } |
||
5891 | else if (hi2c->EventCount == 1U) |
||
5892 | { |
||
5893 | /* Send header of slave address */ |
||
5894 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); |
||
5895 | } |
||
5896 | else |
||
5897 | { |
||
5898 | /* Do nothing */ |
||
5899 | } |
||
5900 | } |
||
5901 | } |
||
5902 | } |
||
5903 | |||
5904 | /** |
||
5905 | * @brief Handle ADD10 flag for Master |
||
5906 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5907 | * the configuration information for I2C module |
||
5908 | * @retval None |
||
5909 | */ |
||
5910 | static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) |
||
5911 | { |
||
5912 | /* Send slave address */ |
||
5913 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); |
||
5914 | |||
5915 | if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) |
||
5916 | || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) |
||
5917 | { |
||
5918 | /* Enable DMA Request */ |
||
5919 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
5920 | } |
||
5921 | } |
||
5922 | |||
5923 | /** |
||
5924 | * @brief Handle ADDR flag for Master |
||
5925 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5926 | * the configuration information for I2C module |
||
5927 | * @retval None |
||
5928 | */ |
||
5929 | static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) |
||
5930 | { |
||
5931 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
5932 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
5933 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
5934 | uint32_t Prev_State = hi2c->PreviousState; |
||
5935 | |||
5936 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
||
5937 | { |
||
5938 | if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) |
||
5939 | { |
||
5940 | /* Clear ADDR flag */ |
||
5941 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5942 | } |
||
5943 | else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) |
||
5944 | { |
||
5945 | /* Clear ADDR flag */ |
||
5946 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5947 | |||
5948 | /* Generate Restart */ |
||
5949 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
5950 | |||
5951 | hi2c->EventCount++; |
||
5952 | } |
||
5953 | else |
||
5954 | { |
||
5955 | if (hi2c->XferCount == 0U) |
||
5956 | { |
||
5957 | /* Clear ADDR flag */ |
||
5958 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5959 | |||
5960 | /* Generate Stop */ |
||
5961 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5962 | } |
||
5963 | else if (hi2c->XferCount == 1U) |
||
5964 | { |
||
5965 | if (CurrentXferOptions == I2C_NO_OPTION_FRAME) |
||
5966 | { |
||
5967 | /* Disable Acknowledge */ |
||
5968 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5969 | |||
5970 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
5971 | { |
||
5972 | /* Disable Acknowledge */ |
||
5973 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5974 | |||
5975 | /* Clear ADDR flag */ |
||
5976 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5977 | } |
||
5978 | else |
||
5979 | { |
||
5980 | /* Clear ADDR flag */ |
||
5981 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5982 | |||
5983 | /* Generate Stop */ |
||
5984 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5985 | } |
||
5986 | } |
||
5987 | /* Prepare next transfer or stop current transfer */ |
||
5988 | else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ |
||
5989 | && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) |
||
5990 | { |
||
5991 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) |
||
5992 | { |
||
5993 | /* Disable Acknowledge */ |
||
5994 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5995 | } |
||
5996 | else |
||
5997 | { |
||
5998 | /* Enable Acknowledge */ |
||
5999 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6000 | } |
||
6001 | |||
6002 | /* Clear ADDR flag */ |
||
6003 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6004 | } |
||
6005 | else |
||
6006 | { |
||
6007 | /* Disable Acknowledge */ |
||
6008 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6009 | |||
6010 | /* Clear ADDR flag */ |
||
6011 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6012 | |||
6013 | /* Generate Stop */ |
||
6014 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6015 | } |
||
6016 | } |
||
6017 | else if (hi2c->XferCount == 2U) |
||
6018 | { |
||
6019 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) |
||
6020 | { |
||
6021 | /* Enable Pos */ |
||
6022 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
6023 | |||
6024 | /* Clear ADDR flag */ |
||
6025 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6026 | |||
6027 | /* Disable Acknowledge */ |
||
6028 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6029 | } |
||
6030 | else |
||
6031 | { |
||
6032 | /* Enable Acknowledge */ |
||
6033 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6034 | |||
6035 | /* Clear ADDR flag */ |
||
6036 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6037 | } |
||
6038 | |||
6039 | if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) |
||
6040 | { |
||
6041 | /* Enable Last DMA bit */ |
||
6042 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
6043 | } |
||
6044 | } |
||
6045 | else |
||
6046 | { |
||
6047 | /* Enable Acknowledge */ |
||
6048 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6049 | |||
6050 | if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) |
||
6051 | { |
||
6052 | /* Enable Last DMA bit */ |
||
6053 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
6054 | } |
||
6055 | |||
6056 | /* Clear ADDR flag */ |
||
6057 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6058 | } |
||
6059 | |||
6060 | /* Reset Event counter */ |
||
6061 | hi2c->EventCount = 0U; |
||
6062 | } |
||
6063 | } |
||
6064 | else |
||
6065 | { |
||
6066 | /* Clear ADDR flag */ |
||
6067 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6068 | } |
||
6069 | } |
||
6070 | |||
6071 | /** |
||
6072 | * @brief Handle TXE flag for Slave |
||
6073 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6074 | * the configuration information for I2C module |
||
6075 | * @retval None |
||
6076 | */ |
||
6077 | static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) |
||
6078 | { |
||
6079 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
6080 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
6081 | |||
6082 | if (hi2c->XferCount != 0U) |
||
6083 | { |
||
6084 | /* Write data to DR */ |
||
6085 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
6086 | |||
6087 | /* Increment Buffer pointer */ |
||
6088 | hi2c->pBuffPtr++; |
||
6089 | |||
6090 | /* Update counter */ |
||
6091 | hi2c->XferCount--; |
||
6092 | |||
6093 | if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
||
6094 | { |
||
6095 | /* Last Byte is received, disable Interrupt */ |
||
6096 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
6097 | |||
6098 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
6099 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
||
6100 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
6101 | |||
6102 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6103 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6104 | hi2c->SlaveTxCpltCallback(hi2c); |
||
6105 | #else |
||
6106 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
||
6107 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6108 | } |
||
6109 | } |
||
6110 | } |
||
6111 | |||
6112 | /** |
||
6113 | * @brief Handle BTF flag for Slave transmitter |
||
6114 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6115 | * the configuration information for I2C module |
||
6116 | * @retval None |
||
6117 | */ |
||
6118 | static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) |
||
6119 | { |
||
6120 | if (hi2c->XferCount != 0U) |
||
6121 | { |
||
6122 | /* Write data to DR */ |
||
6123 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
6124 | |||
6125 | /* Increment Buffer pointer */ |
||
6126 | hi2c->pBuffPtr++; |
||
6127 | |||
6128 | /* Update counter */ |
||
6129 | hi2c->XferCount--; |
||
6130 | } |
||
6131 | } |
||
6132 | |||
6133 | /** |
||
6134 | * @brief Handle RXNE flag for Slave |
||
6135 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6136 | * the configuration information for I2C module |
||
6137 | * @retval None |
||
6138 | */ |
||
6139 | static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) |
||
6140 | { |
||
6141 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
6142 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
6143 | |||
6144 | if (hi2c->XferCount != 0U) |
||
6145 | { |
||
6146 | /* Read data from DR */ |
||
6147 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6148 | |||
6149 | /* Increment Buffer pointer */ |
||
6150 | hi2c->pBuffPtr++; |
||
6151 | |||
6152 | /* Update counter */ |
||
6153 | hi2c->XferCount--; |
||
6154 | |||
6155 | if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
||
6156 | { |
||
6157 | /* Last Byte is received, disable Interrupt */ |
||
6158 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
6159 | |||
6160 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
6161 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
||
6162 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
6163 | |||
6164 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6165 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6166 | hi2c->SlaveRxCpltCallback(hi2c); |
||
6167 | #else |
||
6168 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
6169 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6170 | } |
||
6171 | } |
||
6172 | } |
||
6173 | |||
6174 | /** |
||
6175 | * @brief Handle BTF flag for Slave receiver |
||
6176 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6177 | * the configuration information for I2C module |
||
6178 | * @retval None |
||
6179 | */ |
||
6180 | static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) |
||
6181 | { |
||
6182 | if (hi2c->XferCount != 0U) |
||
6183 | { |
||
6184 | /* Read data from DR */ |
||
6185 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6186 | |||
6187 | /* Increment Buffer pointer */ |
||
6188 | hi2c->pBuffPtr++; |
||
6189 | |||
6190 | /* Update counter */ |
||
6191 | hi2c->XferCount--; |
||
6192 | } |
||
6193 | } |
||
6194 | |||
6195 | /** |
||
6196 | * @brief Handle ADD flag for Slave |
||
6197 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6198 | * the configuration information for I2C module |
||
6199 | * @param IT2Flags Interrupt2 flags to handle. |
||
6200 | * @retval None |
||
6201 | */ |
||
6202 | static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) |
||
6203 | { |
||
6204 | uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; |
||
6205 | uint16_t SlaveAddrCode; |
||
6206 | |||
6207 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
6208 | { |
||
6209 | /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ |
||
6210 | __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); |
||
6211 | |||
6212 | /* Transfer Direction requested by Master */ |
||
6213 | if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) |
||
6214 | { |
||
6215 | TransferDirection = I2C_DIRECTION_TRANSMIT; |
||
6216 | } |
||
6217 | |||
6218 | if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) |
||
6219 | { |
||
6220 | SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; |
||
6221 | } |
||
6222 | else |
||
6223 | { |
||
6224 | SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; |
||
6225 | } |
||
6226 | |||
6227 | /* Process Unlocked */ |
||
6228 | __HAL_UNLOCK(hi2c); |
||
6229 | |||
6230 | /* Call Slave Addr callback */ |
||
6231 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6232 | hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); |
||
6233 | #else |
||
6234 | HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); |
||
6235 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6236 | } |
||
6237 | else |
||
6238 | { |
||
6239 | /* Clear ADDR flag */ |
||
6240 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6241 | |||
6242 | /* Process Unlocked */ |
||
6243 | __HAL_UNLOCK(hi2c); |
||
6244 | } |
||
6245 | } |
||
6246 | |||
6247 | /** |
||
6248 | * @brief Handle STOPF flag for Slave |
||
6249 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6250 | * the configuration information for I2C module |
||
6251 | * @retval None |
||
6252 | */ |
||
6253 | static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) |
||
6254 | { |
||
6255 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
6256 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
6257 | |||
6258 | /* Disable EVT, BUF and ERR interrupt */ |
||
6259 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
6260 | |||
6261 | /* Clear STOPF flag */ |
||
6262 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
||
6263 | |||
6264 | /* Disable Acknowledge */ |
||
6265 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6266 | |||
6267 | /* If a DMA is ongoing, Update handle size context */ |
||
6268 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
6269 | { |
||
6270 | if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
||
6271 | { |
||
6272 | hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx)); |
||
6273 | |||
6274 | if (hi2c->XferCount != 0U) |
||
6275 | { |
||
6276 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
||
6277 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
6278 | } |
||
6279 | |||
6280 | /* Disable, stop the current DMA */ |
||
6281 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
6282 | |||
6283 | /* Abort DMA Xfer if any */ |
||
6284 | if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) |
||
6285 | { |
||
6286 | /* Set the I2C DMA Abort callback : |
||
6287 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
6288 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
||
6289 | |||
6290 | /* Abort DMA RX */ |
||
6291 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
||
6292 | { |
||
6293 | /* Call Directly XferAbortCallback function in case of error */ |
||
6294 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
||
6295 | } |
||
6296 | } |
||
6297 | } |
||
6298 | else |
||
6299 | { |
||
6300 | hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx)); |
||
6301 | |||
6302 | if (hi2c->XferCount != 0U) |
||
6303 | { |
||
6304 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
||
6305 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
6306 | } |
||
6307 | |||
6308 | /* Disable, stop the current DMA */ |
||
6309 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
6310 | |||
6311 | /* Abort DMA Xfer if any */ |
||
6312 | if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) |
||
6313 | { |
||
6314 | /* Set the I2C DMA Abort callback : |
||
6315 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
6316 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
||
6317 | |||
6318 | /* Abort DMA TX */ |
||
6319 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
||
6320 | { |
||
6321 | /* Call Directly XferAbortCallback function in case of error */ |
||
6322 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
||
6323 | } |
||
6324 | } |
||
6325 | } |
||
6326 | } |
||
6327 | |||
6328 | /* All data are not transferred, so set error code accordingly */ |
||
6329 | if (hi2c->XferCount != 0U) |
||
6330 | { |
||
6331 | /* Store Last receive data if any */ |
||
6332 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
||
6333 | { |
||
6334 | /* Read data from DR */ |
||
6335 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6336 | |||
6337 | /* Increment Buffer pointer */ |
||
6338 | hi2c->pBuffPtr++; |
||
6339 | |||
6340 | /* Update counter */ |
||
6341 | hi2c->XferCount--; |
||
6342 | } |
||
6343 | |||
6344 | /* Store Last receive data if any */ |
||
6345 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
6346 | { |
||
6347 | /* Read data from DR */ |
||
6348 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6349 | |||
6350 | /* Increment Buffer pointer */ |
||
6351 | hi2c->pBuffPtr++; |
||
6352 | |||
6353 | /* Update counter */ |
||
6354 | hi2c->XferCount--; |
||
6355 | } |
||
6356 | |||
6357 | if (hi2c->XferCount != 0U) |
||
6358 | { |
||
6359 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
||
6360 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
6361 | } |
||
6362 | } |
||
6363 | |||
6364 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
6365 | { |
||
6366 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6367 | I2C_ITError(hi2c); |
||
6368 | } |
||
6369 | else |
||
6370 | { |
||
6371 | if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) |
||
6372 | { |
||
6373 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
6374 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6375 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
6376 | |||
6377 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6378 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6379 | hi2c->SlaveRxCpltCallback(hi2c); |
||
6380 | #else |
||
6381 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
6382 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6383 | } |
||
6384 | |||
6385 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
||
6386 | { |
||
6387 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
6388 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6389 | hi2c->State = HAL_I2C_STATE_READY; |
||
6390 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6391 | |||
6392 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
||
6393 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6394 | hi2c->ListenCpltCallback(hi2c); |
||
6395 | #else |
||
6396 | HAL_I2C_ListenCpltCallback(hi2c); |
||
6397 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6398 | } |
||
6399 | else |
||
6400 | { |
||
6401 | if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) |
||
6402 | { |
||
6403 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6404 | hi2c->State = HAL_I2C_STATE_READY; |
||
6405 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6406 | |||
6407 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6408 | hi2c->SlaveRxCpltCallback(hi2c); |
||
6409 | #else |
||
6410 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
6411 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6412 | } |
||
6413 | } |
||
6414 | } |
||
6415 | } |
||
6416 | |||
6417 | /** |
||
6418 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6419 | * the configuration information for I2C module |
||
6420 | * @retval None |
||
6421 | */ |
||
6422 | static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) |
||
6423 | { |
||
6424 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
6425 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
6426 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
6427 | |||
6428 | if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ |
||
6429 | (CurrentState == HAL_I2C_STATE_LISTEN)) |
||
6430 | { |
||
6431 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
6432 | |||
6433 | /* Disable EVT, BUF and ERR interrupt */ |
||
6434 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
6435 | |||
6436 | /* Clear AF flag */ |
||
6437 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
6438 | |||
6439 | /* Disable Acknowledge */ |
||
6440 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6441 | |||
6442 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6443 | hi2c->State = HAL_I2C_STATE_READY; |
||
6444 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6445 | |||
6446 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
||
6447 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6448 | hi2c->ListenCpltCallback(hi2c); |
||
6449 | #else |
||
6450 | HAL_I2C_ListenCpltCallback(hi2c); |
||
6451 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6452 | } |
||
6453 | else if (CurrentState == HAL_I2C_STATE_BUSY_TX) |
||
6454 | { |
||
6455 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
6456 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
||
6457 | hi2c->State = HAL_I2C_STATE_READY; |
||
6458 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6459 | |||
6460 | /* Disable EVT, BUF and ERR interrupt */ |
||
6461 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
6462 | |||
6463 | /* Clear AF flag */ |
||
6464 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
6465 | |||
6466 | /* Disable Acknowledge */ |
||
6467 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6468 | |||
6469 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6470 | hi2c->SlaveTxCpltCallback(hi2c); |
||
6471 | #else |
||
6472 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
||
6473 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6474 | } |
||
6475 | else |
||
6476 | { |
||
6477 | /* Clear AF flag only */ |
||
6478 | /* State Listen, but XferOptions == FIRST or NEXT */ |
||
6479 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
6480 | } |
||
6481 | } |
||
6482 | |||
6483 | /** |
||
6484 | * @brief I2C interrupts error process |
||
6485 | * @param hi2c I2C handle. |
||
6486 | * @retval None |
||
6487 | */ |
||
6488 | static void I2C_ITError(I2C_HandleTypeDef *hi2c) |
||
6489 | { |
||
6490 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
6491 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
6492 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
6493 | uint32_t CurrentError; |
||
6494 | |||
6495 | if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) |
||
6496 | { |
||
6497 | /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ |
||
6498 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
6499 | } |
||
6500 | |||
6501 | if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
6502 | { |
||
6503 | /* keep HAL_I2C_STATE_LISTEN */ |
||
6504 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6505 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
6506 | } |
||
6507 | else |
||
6508 | { |
||
6509 | /* If state is an abort treatment on going, don't change state */ |
||
6510 | /* This change will be do later */ |
||
6511 | if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) |
||
6512 | { |
||
6513 | hi2c->State = HAL_I2C_STATE_READY; |
||
6514 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6515 | } |
||
6516 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6517 | } |
||
6518 | |||
6519 | /* Abort DMA transfer */ |
||
6520 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
6521 | { |
||
6522 | hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; |
||
6523 | |||
6524 | if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) |
||
6525 | { |
||
6526 | /* Set the DMA Abort callback : |
||
6527 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
6528 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
||
6529 | |||
6530 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
||
6531 | { |
||
6532 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
6533 | __HAL_I2C_DISABLE(hi2c); |
||
6534 | |||
6535 | hi2c->State = HAL_I2C_STATE_READY; |
||
6536 | |||
6537 | /* Call Directly XferAbortCallback function in case of error */ |
||
6538 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
||
6539 | } |
||
6540 | } |
||
6541 | else |
||
6542 | { |
||
6543 | /* Set the DMA Abort callback : |
||
6544 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
6545 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
||
6546 | |||
6547 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
||
6548 | { |
||
6549 | /* Store Last receive data if any */ |
||
6550 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
6551 | { |
||
6552 | /* Read data from DR */ |
||
6553 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6554 | |||
6555 | /* Increment Buffer pointer */ |
||
6556 | hi2c->pBuffPtr++; |
||
6557 | } |
||
6558 | |||
6559 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
6560 | __HAL_I2C_DISABLE(hi2c); |
||
6561 | |||
6562 | hi2c->State = HAL_I2C_STATE_READY; |
||
6563 | |||
6564 | /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ |
||
6565 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
||
6566 | } |
||
6567 | } |
||
6568 | } |
||
6569 | else if (hi2c->State == HAL_I2C_STATE_ABORT) |
||
6570 | { |
||
6571 | hi2c->State = HAL_I2C_STATE_READY; |
||
6572 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
6573 | |||
6574 | /* Store Last receive data if any */ |
||
6575 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
6576 | { |
||
6577 | /* Read data from DR */ |
||
6578 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6579 | |||
6580 | /* Increment Buffer pointer */ |
||
6581 | hi2c->pBuffPtr++; |
||
6582 | } |
||
6583 | |||
6584 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
6585 | __HAL_I2C_DISABLE(hi2c); |
||
6586 | |||
6587 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6588 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6589 | hi2c->AbortCpltCallback(hi2c); |
||
6590 | #else |
||
6591 | HAL_I2C_AbortCpltCallback(hi2c); |
||
6592 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6593 | } |
||
6594 | else |
||
6595 | { |
||
6596 | /* Store Last receive data if any */ |
||
6597 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
6598 | { |
||
6599 | /* Read data from DR */ |
||
6600 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6601 | |||
6602 | /* Increment Buffer pointer */ |
||
6603 | hi2c->pBuffPtr++; |
||
6604 | } |
||
6605 | |||
6606 | /* Call user error callback */ |
||
6607 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6608 | hi2c->ErrorCallback(hi2c); |
||
6609 | #else |
||
6610 | HAL_I2C_ErrorCallback(hi2c); |
||
6611 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6612 | } |
||
6613 | |||
6614 | /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ |
||
6615 | CurrentError = hi2c->ErrorCode; |
||
6616 | |||
6617 | if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ |
||
6618 | ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ |
||
6619 | ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ |
||
6620 | ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) |
||
6621 | { |
||
6622 | /* Disable EVT, BUF and ERR interrupt */ |
||
6623 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
6624 | } |
||
6625 | |||
6626 | /* So may inform upper layer that listen phase is stopped */ |
||
6627 | /* during NACK error treatment */ |
||
6628 | CurrentState = hi2c->State; |
||
6629 | if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) |
||
6630 | { |
||
6631 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
6632 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6633 | hi2c->State = HAL_I2C_STATE_READY; |
||
6634 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6635 | |||
6636 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
||
6637 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6638 | hi2c->ListenCpltCallback(hi2c); |
||
6639 | #else |
||
6640 | HAL_I2C_ListenCpltCallback(hi2c); |
||
6641 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6642 | } |
||
6643 | } |
||
6644 | |||
6645 | /** |
||
6646 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6647 | * the configuration information for I2C module |
||
6648 | * @param DevAddress Target device address: The device 7 bits address value |
||
6649 | * in datasheet must be shifted to the left before calling the interface |
||
6650 | * @param Timeout Timeout duration |
||
6651 | * @param Tickstart Tick start value |
||
6652 | * @retval HAL status |
||
6653 | */ |
||
6654 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
||
6655 | { |
||
6656 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
6657 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
6658 | |||
6659 | /* Generate Start condition if first transfer */ |
||
6660 | if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
||
6661 | { |
||
6662 | /* Generate Start */ |
||
6663 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6664 | } |
||
6665 | else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) |
||
6666 | { |
||
6667 | /* Generate ReStart */ |
||
6668 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6669 | } |
||
6670 | else |
||
6671 | { |
||
6672 | /* Do nothing */ |
||
6673 | } |
||
6674 | |||
6675 | /* Wait until SB flag is set */ |
||
6676 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6677 | { |
||
6678 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6679 | { |
||
6680 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6681 | } |
||
6682 | return HAL_TIMEOUT; |
||
6683 | } |
||
6684 | |||
6685 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
||
6686 | { |
||
6687 | /* Send slave address */ |
||
6688 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
6689 | } |
||
6690 | else |
||
6691 | { |
||
6692 | /* Send header of slave address */ |
||
6693 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
||
6694 | |||
6695 | /* Wait until ADD10 flag is set */ |
||
6696 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
||
6697 | { |
||
6698 | return HAL_ERROR; |
||
6699 | } |
||
6700 | |||
6701 | /* Send slave address */ |
||
6702 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
||
6703 | } |
||
6704 | |||
6705 | /* Wait until ADDR flag is set */ |
||
6706 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6707 | { |
||
6708 | return HAL_ERROR; |
||
6709 | } |
||
6710 | |||
6711 | return HAL_OK; |
||
6712 | } |
||
6713 | |||
6714 | /** |
||
6715 | * @brief Master sends target device address for read request. |
||
6716 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6717 | * the configuration information for I2C module |
||
6718 | * @param DevAddress Target device address: The device 7 bits address value |
||
6719 | * in datasheet must be shifted to the left before calling the interface |
||
6720 | * @param Timeout Timeout duration |
||
6721 | * @param Tickstart Tick start value |
||
6722 | * @retval HAL status |
||
6723 | */ |
||
6724 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
||
6725 | { |
||
6726 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
6727 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
6728 | |||
6729 | /* Enable Acknowledge */ |
||
6730 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6731 | |||
6732 | /* Generate Start condition if first transfer */ |
||
6733 | if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
||
6734 | { |
||
6735 | /* Generate Start */ |
||
6736 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6737 | } |
||
6738 | else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) |
||
6739 | { |
||
6740 | /* Generate ReStart */ |
||
6741 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6742 | } |
||
6743 | else |
||
6744 | { |
||
6745 | /* Do nothing */ |
||
6746 | } |
||
6747 | |||
6748 | /* Wait until SB flag is set */ |
||
6749 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6750 | { |
||
6751 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6752 | { |
||
6753 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6754 | } |
||
6755 | return HAL_TIMEOUT; |
||
6756 | } |
||
6757 | |||
6758 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
||
6759 | { |
||
6760 | /* Send slave address */ |
||
6761 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
||
6762 | } |
||
6763 | else |
||
6764 | { |
||
6765 | /* Send header of slave address */ |
||
6766 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
||
6767 | |||
6768 | /* Wait until ADD10 flag is set */ |
||
6769 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
||
6770 | { |
||
6771 | return HAL_ERROR; |
||
6772 | } |
||
6773 | |||
6774 | /* Send slave address */ |
||
6775 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
||
6776 | |||
6777 | /* Wait until ADDR flag is set */ |
||
6778 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6779 | { |
||
6780 | return HAL_ERROR; |
||
6781 | } |
||
6782 | |||
6783 | /* Clear ADDR flag */ |
||
6784 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6785 | |||
6786 | /* Generate Restart */ |
||
6787 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6788 | |||
6789 | /* Wait until SB flag is set */ |
||
6790 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6791 | { |
||
6792 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6793 | { |
||
6794 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6795 | } |
||
6796 | return HAL_TIMEOUT; |
||
6797 | } |
||
6798 | |||
6799 | /* Send header of slave address */ |
||
6800 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); |
||
6801 | } |
||
6802 | |||
6803 | /* Wait until ADDR flag is set */ |
||
6804 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6805 | { |
||
6806 | return HAL_ERROR; |
||
6807 | } |
||
6808 | |||
6809 | return HAL_OK; |
||
6810 | } |
||
6811 | |||
6812 | /** |
||
6813 | * @brief Master sends target device address followed by internal memory address for write request. |
||
6814 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6815 | * the configuration information for I2C module |
||
6816 | * @param DevAddress Target device address: The device 7 bits address value |
||
6817 | * in datasheet must be shifted to the left before calling the interface |
||
6818 | * @param MemAddress Internal memory address |
||
6819 | * @param MemAddSize Size of internal memory address |
||
6820 | * @param Timeout Timeout duration |
||
6821 | * @param Tickstart Tick start value |
||
6822 | * @retval HAL status |
||
6823 | */ |
||
6824 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
||
6825 | { |
||
6826 | /* Generate Start */ |
||
6827 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6828 | |||
6829 | /* Wait until SB flag is set */ |
||
6830 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6831 | { |
||
6832 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6833 | { |
||
6834 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6835 | } |
||
6836 | return HAL_TIMEOUT; |
||
6837 | } |
||
6838 | |||
6839 | /* Send slave address */ |
||
6840 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
6841 | |||
6842 | /* Wait until ADDR flag is set */ |
||
6843 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6844 | { |
||
6845 | return HAL_ERROR; |
||
6846 | } |
||
6847 | |||
6848 | /* Clear ADDR flag */ |
||
6849 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6850 | |||
6851 | /* Wait until TXE flag is set */ |
||
6852 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6853 | { |
||
6854 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6855 | { |
||
6856 | /* Generate Stop */ |
||
6857 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6858 | } |
||
6859 | return HAL_ERROR; |
||
6860 | } |
||
6861 | |||
6862 | /* If Memory address size is 8Bit */ |
||
6863 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
||
6864 | { |
||
6865 | /* Send Memory Address */ |
||
6866 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
6867 | } |
||
6868 | /* If Memory address size is 16Bit */ |
||
6869 | else |
||
6870 | { |
||
6871 | /* Send MSB of Memory Address */ |
||
6872 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
||
6873 | |||
6874 | /* Wait until TXE flag is set */ |
||
6875 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6876 | { |
||
6877 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6878 | { |
||
6879 | /* Generate Stop */ |
||
6880 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6881 | } |
||
6882 | return HAL_ERROR; |
||
6883 | } |
||
6884 | |||
6885 | /* Send LSB of Memory Address */ |
||
6886 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
6887 | } |
||
6888 | |||
6889 | return HAL_OK; |
||
6890 | } |
||
6891 | |||
6892 | /** |
||
6893 | * @brief Master sends target device address followed by internal memory address for read request. |
||
6894 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6895 | * the configuration information for I2C module |
||
6896 | * @param DevAddress Target device address: The device 7 bits address value |
||
6897 | * in datasheet must be shifted to the left before calling the interface |
||
6898 | * @param MemAddress Internal memory address |
||
6899 | * @param MemAddSize Size of internal memory address |
||
6900 | * @param Timeout Timeout duration |
||
6901 | * @param Tickstart Tick start value |
||
6902 | * @retval HAL status |
||
6903 | */ |
||
6904 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
||
6905 | { |
||
6906 | /* Enable Acknowledge */ |
||
6907 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6908 | |||
6909 | /* Generate Start */ |
||
6910 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6911 | |||
6912 | /* Wait until SB flag is set */ |
||
6913 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6914 | { |
||
6915 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6916 | { |
||
6917 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6918 | } |
||
6919 | return HAL_TIMEOUT; |
||
6920 | } |
||
6921 | |||
6922 | /* Send slave address */ |
||
6923 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
6924 | |||
6925 | /* Wait until ADDR flag is set */ |
||
6926 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6927 | { |
||
6928 | return HAL_ERROR; |
||
6929 | } |
||
6930 | |||
6931 | /* Clear ADDR flag */ |
||
6932 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6933 | |||
6934 | /* Wait until TXE flag is set */ |
||
6935 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6936 | { |
||
6937 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6938 | { |
||
6939 | /* Generate Stop */ |
||
6940 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6941 | } |
||
6942 | return HAL_ERROR; |
||
6943 | } |
||
6944 | |||
6945 | /* If Memory address size is 8Bit */ |
||
6946 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
||
6947 | { |
||
6948 | /* Send Memory Address */ |
||
6949 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
6950 | } |
||
6951 | /* If Memory address size is 16Bit */ |
||
6952 | else |
||
6953 | { |
||
6954 | /* Send MSB of Memory Address */ |
||
6955 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
||
6956 | |||
6957 | /* Wait until TXE flag is set */ |
||
6958 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6959 | { |
||
6960 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6961 | { |
||
6962 | /* Generate Stop */ |
||
6963 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6964 | } |
||
6965 | return HAL_ERROR; |
||
6966 | } |
||
6967 | |||
6968 | /* Send LSB of Memory Address */ |
||
6969 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
6970 | } |
||
6971 | |||
6972 | /* Wait until TXE flag is set */ |
||
6973 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6974 | { |
||
6975 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6976 | { |
||
6977 | /* Generate Stop */ |
||
6978 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6979 | } |
||
6980 | return HAL_ERROR; |
||
6981 | } |
||
6982 | |||
6983 | /* Generate Restart */ |
||
6984 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6985 | |||
6986 | /* Wait until SB flag is set */ |
||
6987 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6988 | { |
||
6989 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6990 | { |
||
6991 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6992 | } |
||
6993 | return HAL_TIMEOUT; |
||
6994 | } |
||
6995 | |||
6996 | /* Send slave address */ |
||
6997 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
||
6998 | |||
6999 | /* Wait until ADDR flag is set */ |
||
7000 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
7001 | { |
||
7002 | return HAL_ERROR; |
||
7003 | } |
||
7004 | |||
7005 | return HAL_OK; |
||
7006 | } |
||
7007 | |||
7008 | /** |
||
7009 | * @brief DMA I2C process complete callback. |
||
7010 | * @param hdma DMA handle |
||
7011 | * @retval None |
||
7012 | */ |
||
7013 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) |
||
7014 | { |
||
7015 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
7016 | |||
7017 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
7018 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
7019 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
7020 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
7021 | |||
7022 | /* Disable EVT and ERR interrupt */ |
||
7023 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
7024 | |||
7025 | /* Clear Complete callback */ |
||
7026 | if (hi2c->hdmatx != NULL) |
||
7027 | { |
||
7028 | hi2c->hdmatx->XferCpltCallback = NULL; |
||
7029 | } |
||
7030 | if (hi2c->hdmarx != NULL) |
||
7031 | { |
||
7032 | hi2c->hdmarx->XferCpltCallback = NULL; |
||
7033 | } |
||
7034 | |||
7035 | if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) |
||
7036 | { |
||
7037 | /* Disable DMA Request */ |
||
7038 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
7039 | |||
7040 | hi2c->XferCount = 0U; |
||
7041 | |||
7042 | if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) |
||
7043 | { |
||
7044 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
7045 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
||
7046 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
7047 | |||
7048 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
7049 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
7050 | hi2c->SlaveTxCpltCallback(hi2c); |
||
7051 | #else |
||
7052 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
||
7053 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
7054 | } |
||
7055 | else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) |
||
7056 | { |
||
7057 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
7058 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
||
7059 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
7060 | |||
7061 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
7062 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
7063 | hi2c->SlaveRxCpltCallback(hi2c); |
||
7064 | #else |
||
7065 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
7066 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
7067 | } |
||
7068 | else |
||
7069 | { |
||
7070 | /* Do nothing */ |
||
7071 | } |
||
7072 | |||
7073 | /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ |
||
7074 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
7075 | } |
||
7076 | /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ |
||
7077 | else if (hi2c->Mode != HAL_I2C_MODE_NONE) |
||
7078 | { |
||
7079 | if (hi2c->XferCount == (uint16_t)1) |
||
7080 | { |
||
7081 | /* Disable Acknowledge */ |
||
7082 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
7083 | } |
||
7084 | |||
7085 | /* Disable EVT and ERR interrupt */ |
||
7086 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
7087 | |||
7088 | /* Prepare next transfer or stop current transfer */ |
||
7089 | if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) |
||
7090 | { |
||
7091 | /* Generate Stop */ |
||
7092 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
7093 | } |
||
7094 | |||
7095 | /* Disable Last DMA */ |
||
7096 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
7097 | |||
7098 | /* Disable DMA Request */ |
||
7099 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
7100 | |||
7101 | hi2c->XferCount = 0U; |
||
7102 | |||
7103 | /* Check if Errors has been detected during transfer */ |
||
7104 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
7105 | { |
||
7106 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
7107 | hi2c->ErrorCallback(hi2c); |
||
7108 | #else |
||
7109 | HAL_I2C_ErrorCallback(hi2c); |
||
7110 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
7111 | } |
||
7112 | else |
||
7113 | { |
||
7114 | hi2c->State = HAL_I2C_STATE_READY; |
||
7115 | |||
7116 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
7117 | { |
||
7118 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7119 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7120 | |||
7121 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
7122 | hi2c->MemRxCpltCallback(hi2c); |
||
7123 | #else |
||
7124 | HAL_I2C_MemRxCpltCallback(hi2c); |
||
7125 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
7126 | } |
||
7127 | else |
||
7128 | { |
||
7129 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7130 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
||
7131 | |||
7132 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
7133 | hi2c->MasterRxCpltCallback(hi2c); |
||
7134 | #else |
||
7135 | HAL_I2C_MasterRxCpltCallback(hi2c); |
||
7136 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
7137 | } |
||
7138 | } |
||
7139 | } |
||
7140 | else |
||
7141 | { |
||
7142 | /* Do nothing */ |
||
7143 | } |
||
7144 | } |
||
7145 | |||
7146 | /** |
||
7147 | * @brief DMA I2C communication error callback. |
||
7148 | * @param hdma DMA handle |
||
7149 | * @retval None |
||
7150 | */ |
||
7151 | static void I2C_DMAError(DMA_HandleTypeDef *hdma) |
||
7152 | { |
||
7153 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
7154 | |||
7155 | /* Clear Complete callback */ |
||
7156 | if (hi2c->hdmatx != NULL) |
||
7157 | { |
||
7158 | hi2c->hdmatx->XferCpltCallback = NULL; |
||
7159 | } |
||
7160 | if (hi2c->hdmarx != NULL) |
||
7161 | { |
||
7162 | hi2c->hdmarx->XferCpltCallback = NULL; |
||
7163 | } |
||
7164 | |||
7165 | /* Disable Acknowledge */ |
||
7166 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
7167 | |||
7168 | hi2c->XferCount = 0U; |
||
7169 | hi2c->State = HAL_I2C_STATE_READY; |
||
7170 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7171 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
7172 | |||
7173 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
7174 | hi2c->ErrorCallback(hi2c); |
||
7175 | #else |
||
7176 | HAL_I2C_ErrorCallback(hi2c); |
||
7177 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
7178 | } |
||
7179 | |||
7180 | /** |
||
7181 | * @brief DMA I2C communication abort callback |
||
7182 | * (To be called at end of DMA Abort procedure). |
||
7183 | * @param hdma DMA handle. |
||
7184 | * @retval None |
||
7185 | */ |
||
7186 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) |
||
7187 | { |
||
7188 | __IO uint32_t count = 0U; |
||
7189 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
7190 | |||
7191 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
7192 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
7193 | |||
7194 | /* During abort treatment, check that there is no pending STOP request */ |
||
7195 | /* Wait until STOP flag is reset */ |
||
7196 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
||
7197 | do |
||
7198 | { |
||
7199 | if (count == 0U) |
||
7200 | { |
||
7201 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7202 | break; |
||
7203 | } |
||
7204 | count--; |
||
7205 | } |
||
7206 | while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); |
||
7207 | |||
7208 | /* Clear Complete callback */ |
||
7209 | if (hi2c->hdmatx != NULL) |
||
7210 | { |
||
7211 | hi2c->hdmatx->XferCpltCallback = NULL; |
||
7212 | } |
||
7213 | if (hi2c->hdmarx != NULL) |
||
7214 | { |
||
7215 | hi2c->hdmarx->XferCpltCallback = NULL; |
||
7216 | } |
||
7217 | |||
7218 | /* Disable Acknowledge */ |
||
7219 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
7220 | |||
7221 | hi2c->XferCount = 0U; |
||
7222 | |||
7223 | /* Reset XferAbortCallback */ |
||
7224 | if (hi2c->hdmatx != NULL) |
||
7225 | { |
||
7226 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
7227 | } |
||
7228 | if (hi2c->hdmarx != NULL) |
||
7229 | { |
||
7230 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
7231 | } |
||
7232 | |||
7233 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
7234 | __HAL_I2C_DISABLE(hi2c); |
||
7235 | |||
7236 | /* Check if come from abort from user */ |
||
7237 | if (hi2c->State == HAL_I2C_STATE_ABORT) |
||
7238 | { |
||
7239 | hi2c->State = HAL_I2C_STATE_READY; |
||
7240 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7241 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
7242 | |||
7243 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
7244 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
7245 | hi2c->AbortCpltCallback(hi2c); |
||
7246 | #else |
||
7247 | HAL_I2C_AbortCpltCallback(hi2c); |
||
7248 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
7249 | } |
||
7250 | else |
||
7251 | { |
||
7252 | if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
7253 | { |
||
7254 | /* Renable I2C peripheral */ |
||
7255 | __HAL_I2C_ENABLE(hi2c); |
||
7256 | |||
7257 | /* Enable Acknowledge */ |
||
7258 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
7259 | |||
7260 | /* keep HAL_I2C_STATE_LISTEN */ |
||
7261 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7262 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
7263 | } |
||
7264 | else |
||
7265 | { |
||
7266 | hi2c->State = HAL_I2C_STATE_READY; |
||
7267 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7268 | } |
||
7269 | |||
7270 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
7271 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
7272 | hi2c->ErrorCallback(hi2c); |
||
7273 | #else |
||
7274 | HAL_I2C_ErrorCallback(hi2c); |
||
7275 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
7276 | } |
||
7277 | } |
||
7278 | |||
7279 | /** |
||
7280 | * @brief This function handles I2C Communication Timeout. |
||
7281 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7282 | * the configuration information for I2C module |
||
7283 | * @param Flag specifies the I2C flag to check. |
||
7284 | * @param Status The new Flag status (SET or RESET). |
||
7285 | * @param Timeout Timeout duration |
||
7286 | * @param Tickstart Tick start value |
||
7287 | * @retval HAL status |
||
7288 | */ |
||
7289 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) |
||
7290 | { |
||
7291 | /* Wait until flag is set */ |
||
7292 | while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) |
||
7293 | { |
||
7294 | /* Check for the Timeout */ |
||
7295 | if (Timeout != HAL_MAX_DELAY) |
||
7296 | { |
||
7297 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7298 | { |
||
7299 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7300 | hi2c->State = HAL_I2C_STATE_READY; |
||
7301 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7302 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7303 | |||
7304 | /* Process Unlocked */ |
||
7305 | __HAL_UNLOCK(hi2c); |
||
7306 | |||
7307 | return HAL_ERROR; |
||
7308 | } |
||
7309 | } |
||
7310 | } |
||
7311 | return HAL_OK; |
||
7312 | } |
||
7313 | |||
7314 | /** |
||
7315 | * @brief This function handles I2C Communication Timeout for Master addressing phase. |
||
7316 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7317 | * the configuration information for I2C module |
||
7318 | * @param Flag specifies the I2C flag to check. |
||
7319 | * @param Timeout Timeout duration |
||
7320 | * @param Tickstart Tick start value |
||
7321 | * @retval HAL status |
||
7322 | */ |
||
7323 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) |
||
7324 | { |
||
7325 | while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) |
||
7326 | { |
||
7327 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
||
7328 | { |
||
7329 | /* Generate Stop */ |
||
7330 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
7331 | |||
7332 | /* Clear AF Flag */ |
||
7333 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
7334 | |||
7335 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7336 | hi2c->State = HAL_I2C_STATE_READY; |
||
7337 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7338 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
7339 | |||
7340 | /* Process Unlocked */ |
||
7341 | __HAL_UNLOCK(hi2c); |
||
7342 | |||
7343 | return HAL_ERROR; |
||
7344 | } |
||
7345 | |||
7346 | /* Check for the Timeout */ |
||
7347 | if (Timeout != HAL_MAX_DELAY) |
||
7348 | { |
||
7349 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7350 | { |
||
7351 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7352 | hi2c->State = HAL_I2C_STATE_READY; |
||
7353 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7354 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7355 | |||
7356 | /* Process Unlocked */ |
||
7357 | __HAL_UNLOCK(hi2c); |
||
7358 | |||
7359 | return HAL_ERROR; |
||
7360 | } |
||
7361 | } |
||
7362 | } |
||
7363 | return HAL_OK; |
||
7364 | } |
||
7365 | |||
7366 | /** |
||
7367 | * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. |
||
7368 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7369 | * the configuration information for the specified I2C. |
||
7370 | * @param Timeout Timeout duration |
||
7371 | * @param Tickstart Tick start value |
||
7372 | * @retval HAL status |
||
7373 | */ |
||
7374 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
7375 | { |
||
7376 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) |
||
7377 | { |
||
7378 | /* Check if a NACK is detected */ |
||
7379 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
||
7380 | { |
||
7381 | return HAL_ERROR; |
||
7382 | } |
||
7383 | |||
7384 | /* Check for the Timeout */ |
||
7385 | if (Timeout != HAL_MAX_DELAY) |
||
7386 | { |
||
7387 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7388 | { |
||
7389 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7390 | hi2c->State = HAL_I2C_STATE_READY; |
||
7391 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7392 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7393 | |||
7394 | /* Process Unlocked */ |
||
7395 | __HAL_UNLOCK(hi2c); |
||
7396 | |||
7397 | return HAL_ERROR; |
||
7398 | } |
||
7399 | } |
||
7400 | } |
||
7401 | return HAL_OK; |
||
7402 | } |
||
7403 | |||
7404 | /** |
||
7405 | * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. |
||
7406 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7407 | * the configuration information for the specified I2C. |
||
7408 | * @param Timeout Timeout duration |
||
7409 | * @param Tickstart Tick start value |
||
7410 | * @retval HAL status |
||
7411 | */ |
||
7412 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
7413 | { |
||
7414 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) |
||
7415 | { |
||
7416 | /* Check if a NACK is detected */ |
||
7417 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
||
7418 | { |
||
7419 | return HAL_ERROR; |
||
7420 | } |
||
7421 | |||
7422 | /* Check for the Timeout */ |
||
7423 | if (Timeout != HAL_MAX_DELAY) |
||
7424 | { |
||
7425 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7426 | { |
||
7427 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7428 | hi2c->State = HAL_I2C_STATE_READY; |
||
7429 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7430 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7431 | |||
7432 | /* Process Unlocked */ |
||
7433 | __HAL_UNLOCK(hi2c); |
||
7434 | |||
7435 | return HAL_ERROR; |
||
7436 | } |
||
7437 | } |
||
7438 | } |
||
7439 | return HAL_OK; |
||
7440 | } |
||
7441 | |||
7442 | /** |
||
7443 | * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. |
||
7444 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7445 | * the configuration information for the specified I2C. |
||
7446 | * @param Timeout Timeout duration |
||
7447 | * @param Tickstart Tick start value |
||
7448 | * @retval HAL status |
||
7449 | */ |
||
7450 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
7451 | { |
||
7452 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) |
||
7453 | { |
||
7454 | /* Check if a NACK is detected */ |
||
7455 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
||
7456 | { |
||
7457 | return HAL_ERROR; |
||
7458 | } |
||
7459 | |||
7460 | /* Check for the Timeout */ |
||
7461 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7462 | { |
||
7463 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7464 | hi2c->State = HAL_I2C_STATE_READY; |
||
7465 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7466 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7467 | |||
7468 | /* Process Unlocked */ |
||
7469 | __HAL_UNLOCK(hi2c); |
||
7470 | |||
7471 | return HAL_ERROR; |
||
7472 | } |
||
7473 | } |
||
7474 | return HAL_OK; |
||
7475 | } |
||
7476 | |||
7477 | /** |
||
7478 | * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. |
||
7479 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7480 | * the configuration information for the specified I2C. |
||
7481 | * @retval HAL status |
||
7482 | */ |
||
7483 | static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) |
||
7484 | { |
||
7485 | __IO uint32_t count = 0U; |
||
7486 | |||
7487 | /* Wait until STOP flag is reset */ |
||
7488 | count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); |
||
7489 | do |
||
7490 | { |
||
7491 | count--; |
||
7492 | if (count == 0U) |
||
7493 | { |
||
7494 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7495 | |||
7496 | return HAL_ERROR; |
||
7497 | } |
||
7498 | } |
||
7499 | while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); |
||
7500 | |||
7501 | return HAL_OK; |
||
7502 | } |
||
7503 | |||
7504 | /** |
||
7505 | * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. |
||
7506 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7507 | * the configuration information for the specified I2C. |
||
7508 | * @param Timeout Timeout duration |
||
7509 | * @param Tickstart Tick start value |
||
7510 | * @retval HAL status |
||
7511 | */ |
||
7512 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
7513 | { |
||
7514 | |||
7515 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) |
||
7516 | { |
||
7517 | /* Check if a STOPF is detected */ |
||
7518 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) |
||
7519 | { |
||
7520 | /* Clear STOP Flag */ |
||
7521 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
||
7522 | |||
7523 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7524 | hi2c->State = HAL_I2C_STATE_READY; |
||
7525 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7526 | hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; |
||
7527 | |||
7528 | /* Process Unlocked */ |
||
7529 | __HAL_UNLOCK(hi2c); |
||
7530 | |||
7531 | return HAL_ERROR; |
||
7532 | } |
||
7533 | |||
7534 | /* Check for the Timeout */ |
||
7535 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7536 | { |
||
7537 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7538 | hi2c->State = HAL_I2C_STATE_READY; |
||
7539 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7540 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7541 | |||
7542 | /* Process Unlocked */ |
||
7543 | __HAL_UNLOCK(hi2c); |
||
7544 | |||
7545 | return HAL_ERROR; |
||
7546 | } |
||
7547 | } |
||
7548 | return HAL_OK; |
||
7549 | } |
||
7550 | |||
7551 | /** |
||
7552 | * @brief This function handles Acknowledge failed detection during an I2C Communication. |
||
7553 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7554 | * the configuration information for the specified I2C. |
||
7555 | * @retval HAL status |
||
7556 | */ |
||
7557 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) |
||
7558 | { |
||
7559 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
||
7560 | { |
||
7561 | /* Clear NACKF Flag */ |
||
7562 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
7563 | |||
7564 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7565 | hi2c->State = HAL_I2C_STATE_READY; |
||
7566 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7567 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
7568 | |||
7569 | /* Process Unlocked */ |
||
7570 | __HAL_UNLOCK(hi2c); |
||
7571 | |||
7572 | return HAL_ERROR; |
||
7573 | } |
||
7574 | return HAL_OK; |
||
7575 | } |
||
7576 | |||
7577 | /** |
||
7578 | * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. |
||
7579 | * @param hi2c I2C handle. |
||
7580 | * @retval None |
||
7581 | */ |
||
7582 | static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) |
||
7583 | { |
||
7584 | /* if user set XferOptions to I2C_OTHER_FRAME */ |
||
7585 | /* it request implicitly to generate a restart condition */ |
||
7586 | /* set XferOptions to I2C_FIRST_FRAME */ |
||
7587 | if (hi2c->XferOptions == I2C_OTHER_FRAME) |
||
7588 | { |
||
7589 | hi2c->XferOptions = I2C_FIRST_FRAME; |
||
7590 | } |
||
7591 | /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ |
||
7592 | /* it request implicitly to generate a restart condition */ |
||
7593 | /* then generate a stop condition at the end of transfer */ |
||
7594 | /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ |
||
7595 | else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) |
||
7596 | { |
||
7597 | hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; |
||
7598 | } |
||
7599 | else |
||
7600 | { |
||
7601 | /* Nothing to do */ |
||
7602 | } |
||
7603 | } |
||
7604 | |||
7605 | /** |
||
7606 | * @} |
||
7607 | */ |
||
7608 | |||
7609 | #endif /* HAL_I2C_MODULE_ENABLED */ |
||
7610 | /** |
||
7611 | * @} |
||
7612 | */ |
||
7613 | |||
7614 | /** |
||
7615 | * @} |
||
7616 | */ |
||
7617 | |||
7618 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |