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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_i2c.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief I2C HAL module driver. |
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| 6 | * This file provides firmware functions to manage the following |
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| 7 | * functionalities of the Inter Integrated Circuit (I2C) peripheral: |
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| 8 | * + Initialization and de-initialization functions |
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| 9 | * + IO operation functions |
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| 10 | * + Peripheral State, Mode and Error functions |
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| 11 | * |
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| 12 | @verbatim |
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| 13 | ============================================================================== |
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| 14 | ##### How to use this driver ##### |
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| 15 | ============================================================================== |
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| 16 | [..] |
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| 17 | The I2C HAL driver can be used as follows: |
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| 18 | |||
| 19 | (#) Declare a I2C_HandleTypeDef handle structure, for example: |
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| 20 | I2C_HandleTypeDef hi2c; |
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| 21 | |||
| 22 | (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: |
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| 23 | (##) Enable the I2Cx interface clock |
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| 24 | (##) I2C pins configuration |
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| 25 | (+++) Enable the clock for the I2C GPIOs |
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| 26 | (+++) Configure I2C pins as alternate function open-drain |
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| 27 | (##) NVIC configuration if you need to use interrupt process |
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| 28 | (+++) Configure the I2Cx interrupt priority |
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| 29 | (+++) Enable the NVIC I2C IRQ Channel |
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| 30 | (##) DMA Configuration if you need to use DMA process |
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| 31 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel |
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| 32 | (+++) Enable the DMAx interface clock using |
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| 33 | (+++) Configure the DMA handle parameters |
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| 34 | (+++) Configure the DMA Tx or Rx channel |
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| 35 | (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle |
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| 36 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on |
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| 37 | the DMA Tx or Rx channel |
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| 38 | |||
| 39 | (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, |
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| 40 | Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. |
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| 41 | |||
| 42 | (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware |
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| 43 | (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. |
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| 44 | |||
| 45 | (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() |
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| 46 | |||
| 47 | (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : |
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| 48 | |||
| 49 | *** Polling mode IO operation *** |
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| 50 | ================================= |
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| 51 | [..] |
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| 52 | (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() |
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| 53 | (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() |
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| 54 | (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() |
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| 55 | (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() |
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| 56 | |||
| 57 | *** Polling mode IO MEM operation *** |
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| 58 | ===================================== |
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| 59 | [..] |
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| 60 | (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() |
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| 61 | (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() |
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| 62 | |||
| 63 | |||
| 64 | *** Interrupt mode IO operation *** |
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| 65 | =================================== |
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| 66 | [..] |
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| 67 | (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() |
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| 68 | (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can |
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| 69 | add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback |
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| 70 | (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() |
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| 71 | (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can |
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| 72 | add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback |
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| 73 | (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() |
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| 74 | (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can |
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| 75 | add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback |
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| 76 | (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() |
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| 77 | (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can |
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| 78 | add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback |
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| 79 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
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| 80 | add his own code by customization of function pointer HAL_I2C_ErrorCallback |
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| 81 | (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
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| 82 | (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
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| 83 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
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| 84 | |||
| 85 | *** Interrupt mode IO sequential operation *** |
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| 86 | ============================================== |
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| 87 | [..] |
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| 88 | (@) These interfaces allow to manage a sequential transfer with a repeated start condition |
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| 89 | when a direction change during transfer |
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| 90 | [..] |
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| 91 | (+) A specific option field manage the different steps of a sequential transfer |
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| 92 | (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: |
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| 93 | (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode |
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| 94 | (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address |
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| 95 | and data to transfer without a final stop condition |
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| 96 | (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address |
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| 97 | and with new data to transfer if the direction change or manage only the new data to transfer |
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| 98 | if no direction change and without a final stop condition in both cases |
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| 99 | (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address |
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| 100 | and with new data to transfer if the direction change or manage only the new data to transfer |
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| 101 | if no direction change and with a final stop condition in both cases |
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| 102 | |||
| 103 | (+) Differents sequential I2C interfaces are listed below: |
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| 104 | (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() |
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| 105 | (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can |
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| 106 | add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() |
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| 107 | (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() |
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| 108 | (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can |
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| 109 | add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() |
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| 110 | (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
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| 111 | (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
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| 112 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
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| 113 | (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() |
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| 114 | (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can |
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| 115 | add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). |
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| 116 | (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can |
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| 117 | add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() |
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| 118 | (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() |
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| 119 | (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can |
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| 120 | add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() |
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| 121 | (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() |
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| 122 | (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can |
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| 123 | add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() |
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| 124 | (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
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| 125 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
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| 126 | |||
| 127 | *** Interrupt mode IO MEM operation *** |
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| 128 | ======================================= |
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| 129 | [..] |
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| 130 | (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using |
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| 131 | HAL_I2C_Mem_Write_IT() |
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| 132 | (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can |
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| 133 | add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback |
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| 134 | (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using |
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| 135 | HAL_I2C_Mem_Read_IT() |
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| 136 | (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can |
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| 137 | add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback |
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| 138 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
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| 139 | add his own code by customization of function pointer HAL_I2C_ErrorCallback |
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| 140 | |||
| 141 | *** DMA mode IO operation *** |
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| 142 | ============================== |
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| 143 | [..] |
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| 144 | (+) Transmit in master mode an amount of data in non blocking mode (DMA) using |
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| 145 | HAL_I2C_Master_Transmit_DMA() |
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| 146 | (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can |
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| 147 | add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback |
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| 148 | (+) Receive in master mode an amount of data in non blocking mode (DMA) using |
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| 149 | HAL_I2C_Master_Receive_DMA() |
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| 150 | (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can |
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| 151 | add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback |
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| 152 | (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using |
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| 153 | HAL_I2C_Slave_Transmit_DMA() |
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| 154 | (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can |
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| 155 | add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback |
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| 156 | (+) Receive in slave mode an amount of data in non blocking mode (DMA) using |
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| 157 | HAL_I2C_Slave_Receive_DMA() |
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| 158 | (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can |
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| 159 | add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback |
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| 160 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
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| 161 | add his own code by customization of function pointer HAL_I2C_ErrorCallback |
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| 162 | (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
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| 163 | (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
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| 164 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
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| 165 | |||
| 166 | *** DMA mode IO MEM operation *** |
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| 167 | ================================= |
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| 168 | [..] |
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| 169 | (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using |
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| 170 | HAL_I2C_Mem_Write_DMA() |
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| 171 | (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can |
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| 172 | add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback |
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| 173 | (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using |
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| 174 | HAL_I2C_Mem_Read_DMA() |
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| 175 | (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can |
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| 176 | add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback |
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| 177 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
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| 178 | add his own code by customization of function pointer HAL_I2C_ErrorCallback |
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| 179 | |||
| 180 | |||
| 181 | *** I2C HAL driver macros list *** |
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| 182 | ================================== |
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| 183 | [..] |
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| 184 | Below the list of most used macros in I2C HAL driver. |
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| 185 | |||
| 186 | (+) __HAL_I2C_ENABLE: Enable the I2C peripheral |
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| 187 | (+) __HAL_I2C_DISABLE: Disable the I2C peripheral |
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| 188 | (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not |
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| 189 | (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag |
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| 190 | (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt |
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| 191 | (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt |
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| 192 | |||
| 193 | [..] |
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| 194 | (@) You can refer to the I2C HAL driver header file for more useful macros |
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| 195 | |||
| 196 | *** I2C Workarounds linked to Silicon Limitation *** |
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| 197 | ==================================================== |
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| 198 | [..] |
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| 199 | Below the list of all silicon limitations implemented for HAL on STM32F1xx product. |
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| 200 | (@) See ErrataSheet to know full silicon limitation list of your product. |
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| 201 | |||
| 202 | (#) Workarounds Implemented inside I2C HAL Driver |
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| 203 | (##) Wrong data read into data register (Polling and Interrupt mode) |
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| 204 | (##) Start cannot be generated after a misplaced Stop |
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| 205 | (##) Some software events must be managed before the current byte is being transferred: |
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| 206 | Workaround: Use DMA in general, except when the Master is receiving a single byte. |
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| 207 | For Interupt mode, I2C should have the highest priority in the application. |
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| 208 | (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter: |
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| 209 | Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if |
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| 210 | supported by the slave. |
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| 211 | (##) Data valid time (tVD;DAT) violated without the OVR flag being set: |
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| 212 | Workaround: If the slave device allows it, use the clock stretching mechanism |
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| 213 | by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init. |
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| 214 | |||
| 215 | @endverbatim |
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| 216 | ****************************************************************************** |
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| 217 | * @attention |
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| 218 | * |
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| 219 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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| 220 | * |
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| 221 | * Redistribution and use in source and binary forms, with or without modification, |
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| 222 | * are permitted provided that the following conditions are met: |
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| 223 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 224 | * this list of conditions and the following disclaimer. |
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| 225 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 226 | * this list of conditions and the following disclaimer in the documentation |
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| 227 | * and/or other materials provided with the distribution. |
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| 228 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 229 | * may be used to endorse or promote products derived from this software |
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| 230 | * without specific prior written permission. |
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| 231 | * |
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| 232 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 233 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 234 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 235 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 236 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 237 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 238 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 239 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 240 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 241 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 242 | * |
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| 243 | ****************************************************************************** |
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| 244 | */ |
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| 245 | |||
| 246 | /* Includes ------------------------------------------------------------------*/ |
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| 247 | #include "stm32f1xx_hal.h" |
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| 248 | |||
| 249 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 250 | * @{ |
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| 251 | */ |
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| 252 | |||
| 253 | /** @defgroup I2C I2C |
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| 254 | * @brief I2C HAL module driver |
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| 255 | * @{ |
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| 256 | */ |
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| 257 | |||
| 258 | #ifdef HAL_I2C_MODULE_ENABLED |
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| 259 | |||
| 260 | /* Private typedef -----------------------------------------------------------*/ |
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| 261 | /* Private define ------------------------------------------------------------*/ |
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| 262 | /** @addtogroup I2C_Private_Define |
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| 263 | * @{ |
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| 264 | */ |
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| 265 | #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ |
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| 266 | #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ |
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| 267 | #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ |
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| 268 | |||
| 269 | /* Private define for @ref PreviousState usage */ |
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| 270 | #define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ |
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| 271 | #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ |
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| 272 | #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ |
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| 273 | #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ |
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| 274 | #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ |
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| 275 | #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ |
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| 276 | |||
| 277 | /** |
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| 278 | * @} |
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| 279 | */ |
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| 280 | |||
| 281 | /* Private macro -------------------------------------------------------------*/ |
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| 282 | /* Private variables ---------------------------------------------------------*/ |
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| 283 | /* Private function prototypes -----------------------------------------------*/ |
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| 284 | /** @addtogroup I2C_Private_Functions |
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| 285 | * @{ |
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| 286 | */ |
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| 287 | /* Private functions to handle DMA transfer */ |
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| 288 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); |
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| 289 | static void I2C_DMAError(DMA_HandleTypeDef *hdma); |
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| 290 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); |
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| 291 | |||
| 292 | static void I2C_ITError(I2C_HandleTypeDef *hi2c); |
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| 293 | |||
| 294 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
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| 295 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
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| 296 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
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| 297 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
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| 298 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); |
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| 299 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); |
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| 300 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
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| 301 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
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| 302 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
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| 303 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
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| 304 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); |
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| 305 | |||
| 306 | /* Private functions for I2C transfer IRQ handler */ |
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| 307 | static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); |
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| 308 | static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); |
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| 309 | static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); |
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| 310 | static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); |
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| 311 | static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c); |
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| 312 | static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); |
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| 313 | static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); |
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| 314 | |||
| 315 | static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); |
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| 316 | static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); |
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| 317 | static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); |
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| 318 | static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); |
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| 319 | static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); |
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| 320 | static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); |
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| 321 | static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); |
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| 322 | /** |
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| 323 | * @} |
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| 324 | */ |
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| 325 | |||
| 326 | /* Exported functions --------------------------------------------------------*/ |
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| 327 | /** @defgroup I2C_Exported_Functions I2C Exported Functions |
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| 328 | * @{ |
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| 329 | */ |
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| 330 | |||
| 331 | /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 332 | * @brief Initialization and Configuration functions |
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| 333 | * |
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| 334 | @verbatim |
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| 335 | =============================================================================== |
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| 336 | ##### Initialization and de-initialization functions ##### |
||
| 337 | =============================================================================== |
||
| 338 | [..] This subsection provides a set of functions allowing to initialize and |
||
| 339 | de-initialize the I2Cx peripheral: |
||
| 340 | |||
| 341 | (+) User must Implement HAL_I2C_MspInit() function in which he configures |
||
| 342 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). |
||
| 343 | |||
| 344 | (+) Call the function HAL_I2C_Init() to configure the selected device with |
||
| 345 | the selected configuration: |
||
| 346 | (++) Communication Speed |
||
| 347 | (++) Duty cycle |
||
| 348 | (++) Addressing mode |
||
| 349 | (++) Own Address 1 |
||
| 350 | (++) Dual Addressing mode |
||
| 351 | (++) Own Address 2 |
||
| 352 | (++) General call mode |
||
| 353 | (++) Nostretch mode |
||
| 354 | |||
| 355 | (+) Call the function HAL_I2C_DeInit() to restore the default configuration |
||
| 356 | of the selected I2Cx peripheral. |
||
| 357 | |||
| 358 | @endverbatim |
||
| 359 | * @{ |
||
| 360 | */ |
||
| 361 | |||
| 362 | /** |
||
| 363 | * @brief Initializes the I2C according to the specified parameters |
||
| 364 | * in the I2C_InitTypeDef and create the associated handle. |
||
| 365 | * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains |
||
| 366 | * the configuration information for I2C module |
||
| 367 | * @retval HAL status |
||
| 368 | */ |
||
| 369 | HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) |
||
| 370 | { |
||
| 371 | uint32_t freqrange = 0U; |
||
| 372 | uint32_t pclk1 = 0U; |
||
| 373 | |||
| 374 | /* Check the I2C handle allocation */ |
||
| 375 | if(hi2c == NULL) |
||
| 376 | { |
||
| 377 | return HAL_ERROR; |
||
| 378 | } |
||
| 379 | |||
| 380 | /* Check the parameters */ |
||
| 381 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
||
| 382 | assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); |
||
| 383 | assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); |
||
| 384 | assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); |
||
| 385 | assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); |
||
| 386 | assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); |
||
| 387 | assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); |
||
| 388 | assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); |
||
| 389 | assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); |
||
| 390 | |||
| 391 | if(hi2c->State == HAL_I2C_STATE_RESET) |
||
| 392 | { |
||
| 393 | /* Allocate lock resource and initialize it */ |
||
| 394 | hi2c->Lock = HAL_UNLOCKED; |
||
| 395 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
||
| 396 | HAL_I2C_MspInit(hi2c); |
||
| 397 | } |
||
| 398 | |||
| 399 | hi2c->State = HAL_I2C_STATE_BUSY; |
||
| 400 | |||
| 401 | /* Disable the selected I2C peripheral */ |
||
| 402 | __HAL_I2C_DISABLE(hi2c); |
||
| 403 | |||
| 404 | /* Get PCLK1 frequency */ |
||
| 405 | pclk1 = HAL_RCC_GetPCLK1Freq(); |
||
| 406 | |||
| 407 | /* Check the minimum allowed PCLK1 frequency */ |
||
| 408 | if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) |
||
| 409 | { |
||
| 410 | return HAL_ERROR; |
||
| 411 | } |
||
| 412 | |||
| 413 | /* Calculate frequency range */ |
||
| 414 | freqrange = I2C_FREQRANGE(pclk1); |
||
| 415 | |||
| 416 | /*---------------------------- I2Cx CR2 Configuration ----------------------*/ |
||
| 417 | /* Configure I2Cx: Frequency range */ |
||
| 418 | hi2c->Instance->CR2 = freqrange; |
||
| 419 | |||
| 420 | /*---------------------------- I2Cx TRISE Configuration --------------------*/ |
||
| 421 | /* Configure I2Cx: Rise Time */ |
||
| 422 | hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); |
||
| 423 | |||
| 424 | /*---------------------------- I2Cx CCR Configuration ----------------------*/ |
||
| 425 | /* Configure I2Cx: Speed */ |
||
| 426 | hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); |
||
| 427 | |||
| 428 | /*---------------------------- I2Cx CR1 Configuration ----------------------*/ |
||
| 429 | /* Configure I2Cx: Generalcall and NoStretch mode */ |
||
| 430 | hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); |
||
| 431 | |||
| 432 | /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ |
||
| 433 | /* Configure I2Cx: Own Address1 and addressing mode */ |
||
| 434 | hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1); |
||
| 435 | |||
| 436 | /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ |
||
| 437 | /* Configure I2Cx: Dual mode and Own Address2 */ |
||
| 438 | hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2); |
||
| 439 | |||
| 440 | /* Enable the selected I2C peripheral */ |
||
| 441 | __HAL_I2C_ENABLE(hi2c); |
||
| 442 | |||
| 443 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 444 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 445 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 446 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 447 | |||
| 448 | return HAL_OK; |
||
| 449 | } |
||
| 450 | |||
| 451 | /** |
||
| 452 | * @brief DeInitializes the I2C peripheral. |
||
| 453 | * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains |
||
| 454 | * the configuration information for I2C module |
||
| 455 | * @retval HAL status |
||
| 456 | */ |
||
| 457 | HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) |
||
| 458 | { |
||
| 459 | /* Check the I2C handle allocation */ |
||
| 460 | if(hi2c == NULL) |
||
| 461 | { |
||
| 462 | return HAL_ERROR; |
||
| 463 | } |
||
| 464 | |||
| 465 | /* Check the parameters */ |
||
| 466 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
||
| 467 | |||
| 468 | hi2c->State = HAL_I2C_STATE_BUSY; |
||
| 469 | |||
| 470 | /* Disable the I2C Peripheral Clock */ |
||
| 471 | __HAL_I2C_DISABLE(hi2c); |
||
| 472 | |||
| 473 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
||
| 474 | HAL_I2C_MspDeInit(hi2c); |
||
| 475 | |||
| 476 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 477 | hi2c->State = HAL_I2C_STATE_RESET; |
||
| 478 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 479 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 480 | |||
| 481 | /* Release Lock */ |
||
| 482 | __HAL_UNLOCK(hi2c); |
||
| 483 | |||
| 484 | return HAL_OK; |
||
| 485 | } |
||
| 486 | |||
| 487 | /** |
||
| 488 | * @brief I2C MSP Init. |
||
| 489 | * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains |
||
| 490 | * the configuration information for I2C module |
||
| 491 | * @retval None |
||
| 492 | */ |
||
| 493 | __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) |
||
| 494 | { |
||
| 495 | /* Prevent unused argument(s) compilation warning */ |
||
| 496 | UNUSED(hi2c); |
||
| 497 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
| 498 | the HAL_I2C_MspInit could be implemented in the user file |
||
| 499 | */ |
||
| 500 | } |
||
| 501 | |||
| 502 | /** |
||
| 503 | * @brief I2C MSP DeInit |
||
| 504 | * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains |
||
| 505 | * the configuration information for I2C module |
||
| 506 | * @retval None |
||
| 507 | */ |
||
| 508 | __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) |
||
| 509 | { |
||
| 510 | /* Prevent unused argument(s) compilation warning */ |
||
| 511 | UNUSED(hi2c); |
||
| 512 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
| 513 | the HAL_I2C_MspDeInit could be implemented in the user file |
||
| 514 | */ |
||
| 515 | } |
||
| 516 | |||
| 517 | /** |
||
| 518 | * @} |
||
| 519 | */ |
||
| 520 | |||
| 521 | /** @defgroup I2C_Exported_Functions_Group2 IO operation functions |
||
| 522 | * @brief Data transfers functions |
||
| 523 | * |
||
| 524 | @verbatim |
||
| 525 | =============================================================================== |
||
| 526 | ##### IO operation functions ##### |
||
| 527 | =============================================================================== |
||
| 528 | [..] |
||
| 529 | This subsection provides a set of functions allowing to manage the I2C data |
||
| 530 | transfers. |
||
| 531 | |||
| 532 | (#) There are two modes of transfer: |
||
| 533 | (++) Blocking mode : The communication is performed in the polling mode. |
||
| 534 | The status of all data processing is returned by the same function |
||
| 535 | after finishing transfer. |
||
| 536 | (++) No-Blocking mode : The communication is performed using Interrupts |
||
| 537 | or DMA. These functions return the status of the transfer startup. |
||
| 538 | The end of the data processing will be indicated through the |
||
| 539 | dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when |
||
| 540 | using DMA mode. |
||
| 541 | |||
| 542 | (#) Blocking mode functions are : |
||
| 543 | (++) HAL_I2C_Master_Transmit() |
||
| 544 | (++) HAL_I2C_Master_Receive() |
||
| 545 | (++) HAL_I2C_Slave_Transmit() |
||
| 546 | (++) HAL_I2C_Slave_Receive() |
||
| 547 | (++) HAL_I2C_Mem_Write() |
||
| 548 | (++) HAL_I2C_Mem_Read() |
||
| 549 | (++) HAL_I2C_IsDeviceReady() |
||
| 550 | |||
| 551 | (#) No-Blocking mode functions with Interrupt are : |
||
| 552 | (++) HAL_I2C_Master_Transmit_IT() |
||
| 553 | (++) HAL_I2C_Master_Receive_IT() |
||
| 554 | (++) HAL_I2C_Slave_Transmit_IT() |
||
| 555 | (++) HAL_I2C_Slave_Receive_IT() |
||
| 556 | (++) HAL_I2C_Master_Sequential_Transmit_IT() |
||
| 557 | (++) HAL_I2C_Master_Sequential_Receive_IT() |
||
| 558 | (++) HAL_I2C_Slave_Sequential_Transmit_IT() |
||
| 559 | (++) HAL_I2C_Slave_Sequential_Receive_IT() |
||
| 560 | (++) HAL_I2C_Mem_Write_IT() |
||
| 561 | (++) HAL_I2C_Mem_Read_IT() |
||
| 562 | |||
| 563 | (#) No-Blocking mode functions with DMA are : |
||
| 564 | (++) HAL_I2C_Master_Transmit_DMA() |
||
| 565 | (++) HAL_I2C_Master_Receive_DMA() |
||
| 566 | (++) HAL_I2C_Slave_Transmit_DMA() |
||
| 567 | (++) HAL_I2C_Slave_Receive_DMA() |
||
| 568 | (++) HAL_I2C_Mem_Write_DMA() |
||
| 569 | (++) HAL_I2C_Mem_Read_DMA() |
||
| 570 | |||
| 571 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
||
| 572 | (++) HAL_I2C_MemTxCpltCallback() |
||
| 573 | (++) HAL_I2C_MemRxCpltCallback() |
||
| 574 | (++) HAL_I2C_MasterTxCpltCallback() |
||
| 575 | (++) HAL_I2C_MasterRxCpltCallback() |
||
| 576 | (++) HAL_I2C_SlaveTxCpltCallback() |
||
| 577 | (++) HAL_I2C_SlaveRxCpltCallback() |
||
| 578 | (++) HAL_I2C_ErrorCallback() |
||
| 579 | (++) HAL_I2C_AbortCpltCallback() |
||
| 580 | |||
| 581 | @endverbatim |
||
| 582 | * @{ |
||
| 583 | */ |
||
| 584 | |||
| 585 | /** |
||
| 586 | * @brief Transmits in master mode an amount of data in blocking mode. |
||
| 587 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 588 | * the configuration information for the specified I2C. |
||
| 589 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 590 | * in datasheet must be shifted to the left before calling the interface |
||
| 591 | * @param pData Pointer to data buffer |
||
| 592 | * @param Size Amount of data to be sent |
||
| 593 | * @param Timeout Timeout duration |
||
| 594 | * @retval HAL status |
||
| 595 | */ |
||
| 596 | HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
| 597 | { |
||
| 598 | uint32_t tickstart = 0x00U; |
||
| 599 | |||
| 600 | /* Init tickstart for timeout management*/ |
||
| 601 | tickstart = HAL_GetTick(); |
||
| 602 | |||
| 603 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 604 | { |
||
| 605 | /* Wait until BUSY flag is reset */ |
||
| 606 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
| 607 | { |
||
| 608 | return HAL_BUSY; |
||
| 609 | } |
||
| 610 | |||
| 611 | /* Process Locked */ |
||
| 612 | __HAL_LOCK(hi2c); |
||
| 613 | |||
| 614 | /* Check if the I2C is already enabled */ |
||
| 615 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 616 | { |
||
| 617 | /* Enable I2C peripheral */ |
||
| 618 | __HAL_I2C_ENABLE(hi2c); |
||
| 619 | } |
||
| 620 | |||
| 621 | /* Disable Pos */ |
||
| 622 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 623 | |||
| 624 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 625 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
| 626 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 627 | |||
| 628 | /* Prepare transfer parameters */ |
||
| 629 | hi2c->pBuffPtr = pData; |
||
| 630 | hi2c->XferCount = Size; |
||
| 631 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 632 | hi2c->XferSize = hi2c->XferCount; |
||
| 633 | |||
| 634 | /* Send Slave Address */ |
||
| 635 | if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
||
| 636 | { |
||
| 637 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 638 | { |
||
| 639 | /* Process Unlocked */ |
||
| 640 | __HAL_UNLOCK(hi2c); |
||
| 641 | return HAL_ERROR; |
||
| 642 | } |
||
| 643 | else |
||
| 644 | { |
||
| 645 | /* Process Unlocked */ |
||
| 646 | __HAL_UNLOCK(hi2c); |
||
| 647 | return HAL_TIMEOUT; |
||
| 648 | } |
||
| 649 | } |
||
| 650 | |||
| 651 | /* Clear ADDR flag */ |
||
| 652 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 653 | |||
| 654 | while(hi2c->XferSize > 0U) |
||
| 655 | { |
||
| 656 | /* Wait until TXE flag is set */ |
||
| 657 | if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 658 | { |
||
| 659 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 660 | { |
||
| 661 | /* Generate Stop */ |
||
| 662 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 663 | return HAL_ERROR; |
||
| 664 | } |
||
| 665 | else |
||
| 666 | { |
||
| 667 | return HAL_TIMEOUT; |
||
| 668 | } |
||
| 669 | } |
||
| 670 | |||
| 671 | /* Write data to DR */ |
||
| 672 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 673 | hi2c->XferCount--; |
||
| 674 | hi2c->XferSize--; |
||
| 675 | |||
| 676 | if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
| 677 | { |
||
| 678 | /* Write data to DR */ |
||
| 679 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 680 | hi2c->XferCount--; |
||
| 681 | hi2c->XferSize--; |
||
| 682 | } |
||
| 683 | |||
| 684 | /* Wait until BTF flag is set */ |
||
| 685 | if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 686 | { |
||
| 687 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 688 | { |
||
| 689 | /* Generate Stop */ |
||
| 690 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 691 | return HAL_ERROR; |
||
| 692 | } |
||
| 693 | else |
||
| 694 | { |
||
| 695 | return HAL_TIMEOUT; |
||
| 696 | } |
||
| 697 | } |
||
| 698 | } |
||
| 699 | |||
| 700 | /* Generate Stop */ |
||
| 701 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 702 | |||
| 703 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 704 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 705 | |||
| 706 | /* Process Unlocked */ |
||
| 707 | __HAL_UNLOCK(hi2c); |
||
| 708 | |||
| 709 | return HAL_OK; |
||
| 710 | } |
||
| 711 | else |
||
| 712 | { |
||
| 713 | return HAL_BUSY; |
||
| 714 | } |
||
| 715 | } |
||
| 716 | |||
| 717 | /** |
||
| 718 | * @brief Receives in master mode an amount of data in blocking mode. |
||
| 719 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 720 | * the configuration information for the specified I2C. |
||
| 721 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 722 | * in datasheet must be shifted to the left before calling the interface |
||
| 723 | * @param pData Pointer to data buffer |
||
| 724 | * @param Size Amount of data to be sent |
||
| 725 | * @param Timeout Timeout duration |
||
| 726 | * @retval HAL status |
||
| 727 | */ |
||
| 728 | HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
| 729 | { |
||
| 730 | uint32_t tickstart = 0x00U; |
||
| 731 | |||
| 732 | /* Init tickstart for timeout management*/ |
||
| 733 | tickstart = HAL_GetTick(); |
||
| 734 | |||
| 735 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 736 | { |
||
| 737 | /* Wait until BUSY flag is reset */ |
||
| 738 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
| 739 | { |
||
| 740 | return HAL_BUSY; |
||
| 741 | } |
||
| 742 | |||
| 743 | /* Process Locked */ |
||
| 744 | __HAL_LOCK(hi2c); |
||
| 745 | |||
| 746 | /* Check if the I2C is already enabled */ |
||
| 747 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 748 | { |
||
| 749 | /* Enable I2C peripheral */ |
||
| 750 | __HAL_I2C_ENABLE(hi2c); |
||
| 751 | } |
||
| 752 | |||
| 753 | /* Disable Pos */ |
||
| 754 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 755 | |||
| 756 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 757 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
| 758 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 759 | |||
| 760 | /* Prepare transfer parameters */ |
||
| 761 | hi2c->pBuffPtr = pData; |
||
| 762 | hi2c->XferCount = Size; |
||
| 763 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 764 | hi2c->XferSize = hi2c->XferCount; |
||
| 765 | |||
| 766 | /* Send Slave Address */ |
||
| 767 | if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
||
| 768 | { |
||
| 769 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 770 | { |
||
| 771 | /* Process Unlocked */ |
||
| 772 | __HAL_UNLOCK(hi2c); |
||
| 773 | return HAL_ERROR; |
||
| 774 | } |
||
| 775 | else |
||
| 776 | { |
||
| 777 | /* Process Unlocked */ |
||
| 778 | __HAL_UNLOCK(hi2c); |
||
| 779 | return HAL_TIMEOUT; |
||
| 780 | } |
||
| 781 | } |
||
| 782 | |||
| 783 | if(hi2c->XferSize == 0U) |
||
| 784 | { |
||
| 785 | /* Clear ADDR flag */ |
||
| 786 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 787 | |||
| 788 | /* Generate Stop */ |
||
| 789 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 790 | } |
||
| 791 | else if(hi2c->XferSize == 1U) |
||
| 792 | { |
||
| 793 | /* Disable Acknowledge */ |
||
| 794 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 795 | |||
| 796 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
| 797 | software sequence must complete before the current byte end of transfer */ |
||
| 798 | __disable_irq(); |
||
| 799 | |||
| 800 | /* Clear ADDR flag */ |
||
| 801 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 802 | |||
| 803 | /* Generate Stop */ |
||
| 804 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 805 | |||
| 806 | /* Re-enable IRQs */ |
||
| 807 | __enable_irq(); |
||
| 808 | } |
||
| 809 | else if(hi2c->XferSize == 2U) |
||
| 810 | { |
||
| 811 | /* Enable Pos */ |
||
| 812 | hi2c->Instance->CR1 |= I2C_CR1_POS; |
||
| 813 | |||
| 814 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
| 815 | software sequence must complete before the current byte end of transfer */ |
||
| 816 | __disable_irq(); |
||
| 817 | |||
| 818 | /* Clear ADDR flag */ |
||
| 819 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 820 | |||
| 821 | /* Disable Acknowledge */ |
||
| 822 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 823 | |||
| 824 | /* Re-enable IRQs */ |
||
| 825 | __enable_irq(); |
||
| 826 | } |
||
| 827 | else |
||
| 828 | { |
||
| 829 | /* Enable Acknowledge */ |
||
| 830 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 831 | |||
| 832 | /* Clear ADDR flag */ |
||
| 833 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 834 | } |
||
| 835 | |||
| 836 | while(hi2c->XferSize > 0U) |
||
| 837 | { |
||
| 838 | if(hi2c->XferSize <= 3U) |
||
| 839 | { |
||
| 840 | /* One byte */ |
||
| 841 | if(hi2c->XferSize == 1U) |
||
| 842 | { |
||
| 843 | /* Wait until RXNE flag is set */ |
||
| 844 | if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 845 | { |
||
| 846 | if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) |
||
| 847 | { |
||
| 848 | return HAL_TIMEOUT; |
||
| 849 | } |
||
| 850 | else |
||
| 851 | { |
||
| 852 | return HAL_ERROR; |
||
| 853 | } |
||
| 854 | } |
||
| 855 | |||
| 856 | /* Read data from DR */ |
||
| 857 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 858 | hi2c->XferSize--; |
||
| 859 | hi2c->XferCount--; |
||
| 860 | } |
||
| 861 | /* Two bytes */ |
||
| 862 | else if(hi2c->XferSize == 2U) |
||
| 863 | { |
||
| 864 | /* Wait until BTF flag is set */ |
||
| 865 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
| 866 | { |
||
| 867 | return HAL_TIMEOUT; |
||
| 868 | } |
||
| 869 | |||
| 870 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
| 871 | software sequence must complete before the current byte end of transfer */ |
||
| 872 | __disable_irq(); |
||
| 873 | |||
| 874 | /* Generate Stop */ |
||
| 875 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 876 | |||
| 877 | /* Read data from DR */ |
||
| 878 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 879 | hi2c->XferSize--; |
||
| 880 | hi2c->XferCount--; |
||
| 881 | |||
| 882 | /* Re-enable IRQs */ |
||
| 883 | __enable_irq(); |
||
| 884 | |||
| 885 | /* Read data from DR */ |
||
| 886 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 887 | hi2c->XferSize--; |
||
| 888 | hi2c->XferCount--; |
||
| 889 | } |
||
| 890 | /* 3 Last bytes */ |
||
| 891 | else |
||
| 892 | { |
||
| 893 | /* Wait until BTF flag is set */ |
||
| 894 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
| 895 | { |
||
| 896 | return HAL_TIMEOUT; |
||
| 897 | } |
||
| 898 | |||
| 899 | /* Disable Acknowledge */ |
||
| 900 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 901 | |||
| 902 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
| 903 | software sequence must complete before the current byte end of transfer */ |
||
| 904 | __disable_irq(); |
||
| 905 | |||
| 906 | /* Read data from DR */ |
||
| 907 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 908 | hi2c->XferSize--; |
||
| 909 | hi2c->XferCount--; |
||
| 910 | |||
| 911 | /* Wait until BTF flag is set */ |
||
| 912 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
| 913 | { |
||
| 914 | return HAL_TIMEOUT; |
||
| 915 | } |
||
| 916 | |||
| 917 | /* Generate Stop */ |
||
| 918 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 919 | |||
| 920 | /* Read data from DR */ |
||
| 921 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 922 | hi2c->XferSize--; |
||
| 923 | hi2c->XferCount--; |
||
| 924 | |||
| 925 | /* Re-enable IRQs */ |
||
| 926 | __enable_irq(); |
||
| 927 | |||
| 928 | /* Read data from DR */ |
||
| 929 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 930 | hi2c->XferSize--; |
||
| 931 | hi2c->XferCount--; |
||
| 932 | } |
||
| 933 | } |
||
| 934 | else |
||
| 935 | { |
||
| 936 | /* Wait until RXNE flag is set */ |
||
| 937 | if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 938 | { |
||
| 939 | if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) |
||
| 940 | { |
||
| 941 | return HAL_TIMEOUT; |
||
| 942 | } |
||
| 943 | else |
||
| 944 | { |
||
| 945 | return HAL_ERROR; |
||
| 946 | } |
||
| 947 | } |
||
| 948 | |||
| 949 | /* Read data from DR */ |
||
| 950 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 951 | hi2c->XferSize--; |
||
| 952 | hi2c->XferCount--; |
||
| 953 | |||
| 954 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
||
| 955 | { |
||
| 956 | /* Read data from DR */ |
||
| 957 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 958 | hi2c->XferSize--; |
||
| 959 | hi2c->XferCount--; |
||
| 960 | } |
||
| 961 | } |
||
| 962 | } |
||
| 963 | |||
| 964 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 965 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 966 | |||
| 967 | /* Process Unlocked */ |
||
| 968 | __HAL_UNLOCK(hi2c); |
||
| 969 | |||
| 970 | return HAL_OK; |
||
| 971 | } |
||
| 972 | else |
||
| 973 | { |
||
| 974 | return HAL_BUSY; |
||
| 975 | } |
||
| 976 | } |
||
| 977 | |||
| 978 | /** |
||
| 979 | * @brief Transmits in slave mode an amount of data in blocking mode. |
||
| 980 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 981 | * the configuration information for the specified I2C. |
||
| 982 | * @param pData Pointer to data buffer |
||
| 983 | * @param Size Amount of data to be sent |
||
| 984 | * @param Timeout Timeout duration |
||
| 985 | * @retval HAL status |
||
| 986 | */ |
||
| 987 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
| 988 | { |
||
| 989 | uint32_t tickstart = 0x00U; |
||
| 990 | |||
| 991 | /* Init tickstart for timeout management*/ |
||
| 992 | tickstart = HAL_GetTick(); |
||
| 993 | |||
| 994 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 995 | { |
||
| 996 | if((pData == NULL) || (Size == 0U)) |
||
| 997 | { |
||
| 998 | return HAL_ERROR; |
||
| 999 | } |
||
| 1000 | |||
| 1001 | /* Process Locked */ |
||
| 1002 | __HAL_LOCK(hi2c); |
||
| 1003 | |||
| 1004 | /* Check if the I2C is already enabled */ |
||
| 1005 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1006 | { |
||
| 1007 | /* Enable I2C peripheral */ |
||
| 1008 | __HAL_I2C_ENABLE(hi2c); |
||
| 1009 | } |
||
| 1010 | |||
| 1011 | /* Disable Pos */ |
||
| 1012 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1013 | |||
| 1014 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 1015 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
| 1016 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1017 | |||
| 1018 | /* Prepare transfer parameters */ |
||
| 1019 | hi2c->pBuffPtr = pData; |
||
| 1020 | hi2c->XferCount = Size; |
||
| 1021 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 1022 | hi2c->XferSize = hi2c->XferCount; |
||
| 1023 | |||
| 1024 | /* Enable Address Acknowledge */ |
||
| 1025 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 1026 | |||
| 1027 | /* Wait until ADDR flag is set */ |
||
| 1028 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
||
| 1029 | { |
||
| 1030 | return HAL_TIMEOUT; |
||
| 1031 | } |
||
| 1032 | |||
| 1033 | /* Clear ADDR flag */ |
||
| 1034 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 1035 | |||
| 1036 | /* If 10bit addressing mode is selected */ |
||
| 1037 | if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) |
||
| 1038 | { |
||
| 1039 | /* Wait until ADDR flag is set */ |
||
| 1040 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
||
| 1041 | { |
||
| 1042 | return HAL_TIMEOUT; |
||
| 1043 | } |
||
| 1044 | |||
| 1045 | /* Clear ADDR flag */ |
||
| 1046 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 1047 | } |
||
| 1048 | |||
| 1049 | while(hi2c->XferSize > 0U) |
||
| 1050 | { |
||
| 1051 | /* Wait until TXE flag is set */ |
||
| 1052 | if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 1053 | { |
||
| 1054 | /* Disable Address Acknowledge */ |
||
| 1055 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 1056 | |||
| 1057 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 1058 | { |
||
| 1059 | return HAL_ERROR; |
||
| 1060 | } |
||
| 1061 | else |
||
| 1062 | { |
||
| 1063 | return HAL_TIMEOUT; |
||
| 1064 | } |
||
| 1065 | } |
||
| 1066 | |||
| 1067 | /* Write data to DR */ |
||
| 1068 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 1069 | hi2c->XferCount--; |
||
| 1070 | hi2c->XferSize--; |
||
| 1071 | |||
| 1072 | if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
| 1073 | { |
||
| 1074 | /* Write data to DR */ |
||
| 1075 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 1076 | hi2c->XferCount--; |
||
| 1077 | hi2c->XferSize--; |
||
| 1078 | } |
||
| 1079 | } |
||
| 1080 | |||
| 1081 | /* Wait until AF flag is set */ |
||
| 1082 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) |
||
| 1083 | { |
||
| 1084 | return HAL_TIMEOUT; |
||
| 1085 | } |
||
| 1086 | |||
| 1087 | /* Clear AF flag */ |
||
| 1088 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
| 1089 | |||
| 1090 | /* Disable Address Acknowledge */ |
||
| 1091 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 1092 | |||
| 1093 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 1094 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 1095 | |||
| 1096 | /* Process Unlocked */ |
||
| 1097 | __HAL_UNLOCK(hi2c); |
||
| 1098 | |||
| 1099 | return HAL_OK; |
||
| 1100 | } |
||
| 1101 | else |
||
| 1102 | { |
||
| 1103 | return HAL_BUSY; |
||
| 1104 | } |
||
| 1105 | } |
||
| 1106 | |||
| 1107 | /** |
||
| 1108 | * @brief Receive in slave mode an amount of data in blocking mode |
||
| 1109 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1110 | * the configuration information for the specified I2C. |
||
| 1111 | * @param pData Pointer to data buffer |
||
| 1112 | * @param Size Amount of data to be sent |
||
| 1113 | * @param Timeout Timeout duration |
||
| 1114 | * @retval HAL status |
||
| 1115 | */ |
||
| 1116 | HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
| 1117 | { |
||
| 1118 | uint32_t tickstart = 0x00U; |
||
| 1119 | |||
| 1120 | /* Init tickstart for timeout management*/ |
||
| 1121 | tickstart = HAL_GetTick(); |
||
| 1122 | |||
| 1123 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 1124 | { |
||
| 1125 | if((pData == NULL) || (Size == 0U)) |
||
| 1126 | { |
||
| 1127 | return HAL_ERROR; |
||
| 1128 | } |
||
| 1129 | |||
| 1130 | /* Process Locked */ |
||
| 1131 | __HAL_LOCK(hi2c); |
||
| 1132 | |||
| 1133 | /* Check if the I2C is already enabled */ |
||
| 1134 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1135 | { |
||
| 1136 | /* Enable I2C peripheral */ |
||
| 1137 | __HAL_I2C_ENABLE(hi2c); |
||
| 1138 | } |
||
| 1139 | |||
| 1140 | /* Disable Pos */ |
||
| 1141 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1142 | |||
| 1143 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 1144 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
| 1145 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1146 | |||
| 1147 | /* Prepare transfer parameters */ |
||
| 1148 | hi2c->pBuffPtr = pData; |
||
| 1149 | hi2c->XferCount = Size; |
||
| 1150 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 1151 | hi2c->XferSize = hi2c->XferCount; |
||
| 1152 | |||
| 1153 | /* Enable Address Acknowledge */ |
||
| 1154 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 1155 | |||
| 1156 | /* Wait until ADDR flag is set */ |
||
| 1157 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
||
| 1158 | { |
||
| 1159 | return HAL_TIMEOUT; |
||
| 1160 | } |
||
| 1161 | |||
| 1162 | /* Clear ADDR flag */ |
||
| 1163 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 1164 | |||
| 1165 | while(hi2c->XferSize > 0U) |
||
| 1166 | { |
||
| 1167 | /* Wait until RXNE flag is set */ |
||
| 1168 | if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 1169 | { |
||
| 1170 | /* Disable Address Acknowledge */ |
||
| 1171 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 1172 | |||
| 1173 | if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) |
||
| 1174 | { |
||
| 1175 | return HAL_TIMEOUT; |
||
| 1176 | } |
||
| 1177 | else |
||
| 1178 | { |
||
| 1179 | return HAL_ERROR; |
||
| 1180 | } |
||
| 1181 | } |
||
| 1182 | |||
| 1183 | /* Read data from DR */ |
||
| 1184 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 1185 | hi2c->XferSize--; |
||
| 1186 | hi2c->XferCount--; |
||
| 1187 | |||
| 1188 | if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
| 1189 | { |
||
| 1190 | /* Read data from DR */ |
||
| 1191 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 1192 | hi2c->XferSize--; |
||
| 1193 | hi2c->XferCount--; |
||
| 1194 | } |
||
| 1195 | } |
||
| 1196 | |||
| 1197 | /* Wait until STOP flag is set */ |
||
| 1198 | if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 1199 | { |
||
| 1200 | /* Disable Address Acknowledge */ |
||
| 1201 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 1202 | |||
| 1203 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 1204 | { |
||
| 1205 | return HAL_ERROR; |
||
| 1206 | } |
||
| 1207 | else |
||
| 1208 | { |
||
| 1209 | return HAL_TIMEOUT; |
||
| 1210 | } |
||
| 1211 | } |
||
| 1212 | |||
| 1213 | /* Clear STOP flag */ |
||
| 1214 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
||
| 1215 | |||
| 1216 | /* Disable Address Acknowledge */ |
||
| 1217 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 1218 | |||
| 1219 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 1220 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 1221 | |||
| 1222 | /* Process Unlocked */ |
||
| 1223 | __HAL_UNLOCK(hi2c); |
||
| 1224 | |||
| 1225 | return HAL_OK; |
||
| 1226 | } |
||
| 1227 | else |
||
| 1228 | { |
||
| 1229 | return HAL_BUSY; |
||
| 1230 | } |
||
| 1231 | } |
||
| 1232 | |||
| 1233 | /** |
||
| 1234 | * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt |
||
| 1235 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1236 | * the configuration information for the specified I2C. |
||
| 1237 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 1238 | * in datasheet must be shifted to the left before calling the interface |
||
| 1239 | * @param pData Pointer to data buffer |
||
| 1240 | * @param Size Amount of data to be sent |
||
| 1241 | * @retval HAL status |
||
| 1242 | */ |
||
| 1243 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
| 1244 | { |
||
| 1245 | __IO uint32_t count = 0U; |
||
| 1246 | |||
| 1247 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 1248 | { |
||
| 1249 | /* Wait until BUSY flag is reset */ |
||
| 1250 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 1251 | do |
||
| 1252 | { |
||
| 1253 | if(count-- == 0U) |
||
| 1254 | { |
||
| 1255 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 1256 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 1257 | |||
| 1258 | /* Process Unlocked */ |
||
| 1259 | __HAL_UNLOCK(hi2c); |
||
| 1260 | |||
| 1261 | return HAL_TIMEOUT; |
||
| 1262 | } |
||
| 1263 | } |
||
| 1264 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 1265 | |||
| 1266 | /* Process Locked */ |
||
| 1267 | __HAL_LOCK(hi2c); |
||
| 1268 | |||
| 1269 | /* Check if the I2C is already enabled */ |
||
| 1270 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1271 | { |
||
| 1272 | /* Enable I2C peripheral */ |
||
| 1273 | __HAL_I2C_ENABLE(hi2c); |
||
| 1274 | } |
||
| 1275 | |||
| 1276 | /* Disable Pos */ |
||
| 1277 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1278 | |||
| 1279 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 1280 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
| 1281 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1282 | |||
| 1283 | /* Prepare transfer parameters */ |
||
| 1284 | hi2c->pBuffPtr = pData; |
||
| 1285 | hi2c->XferCount = Size; |
||
| 1286 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 1287 | hi2c->XferSize = hi2c->XferCount; |
||
| 1288 | hi2c->Devaddress = DevAddress; |
||
| 1289 | |||
| 1290 | /* Generate Start */ |
||
| 1291 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 1292 | |||
| 1293 | /* Process Unlocked */ |
||
| 1294 | __HAL_UNLOCK(hi2c); |
||
| 1295 | |||
| 1296 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 1297 | to avoid the risk of I2C interrupt handle execution before current |
||
| 1298 | process unlock */ |
||
| 1299 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 1300 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 1301 | |||
| 1302 | return HAL_OK; |
||
| 1303 | } |
||
| 1304 | else |
||
| 1305 | { |
||
| 1306 | return HAL_BUSY; |
||
| 1307 | } |
||
| 1308 | } |
||
| 1309 | |||
| 1310 | /** |
||
| 1311 | * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt |
||
| 1312 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1313 | * the configuration information for the specified I2C. |
||
| 1314 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 1315 | * in datasheet must be shifted to the left before calling the interface |
||
| 1316 | * @param pData Pointer to data buffer |
||
| 1317 | * @param Size Amount of data to be sent |
||
| 1318 | * @retval HAL status |
||
| 1319 | */ |
||
| 1320 | HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
| 1321 | { |
||
| 1322 | __IO uint32_t count = 0U; |
||
| 1323 | |||
| 1324 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 1325 | { |
||
| 1326 | /* Wait until BUSY flag is reset */ |
||
| 1327 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 1328 | do |
||
| 1329 | { |
||
| 1330 | if(count-- == 0U) |
||
| 1331 | { |
||
| 1332 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 1333 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 1334 | |||
| 1335 | /* Process Unlocked */ |
||
| 1336 | __HAL_UNLOCK(hi2c); |
||
| 1337 | |||
| 1338 | return HAL_TIMEOUT; |
||
| 1339 | } |
||
| 1340 | } |
||
| 1341 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 1342 | |||
| 1343 | /* Process Locked */ |
||
| 1344 | __HAL_LOCK(hi2c); |
||
| 1345 | |||
| 1346 | /* Check if the I2C is already enabled */ |
||
| 1347 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1348 | { |
||
| 1349 | /* Enable I2C peripheral */ |
||
| 1350 | __HAL_I2C_ENABLE(hi2c); |
||
| 1351 | } |
||
| 1352 | |||
| 1353 | /* Disable Pos */ |
||
| 1354 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1355 | |||
| 1356 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 1357 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
| 1358 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1359 | |||
| 1360 | /* Prepare transfer parameters */ |
||
| 1361 | hi2c->pBuffPtr = pData; |
||
| 1362 | hi2c->XferCount = Size; |
||
| 1363 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 1364 | hi2c->XferSize = hi2c->XferCount; |
||
| 1365 | hi2c->Devaddress = DevAddress; |
||
| 1366 | |||
| 1367 | /* Enable Acknowledge */ |
||
| 1368 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 1369 | |||
| 1370 | /* Generate Start */ |
||
| 1371 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 1372 | |||
| 1373 | /* Process Unlocked */ |
||
| 1374 | __HAL_UNLOCK(hi2c); |
||
| 1375 | |||
| 1376 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 1377 | to avoid the risk of I2C interrupt handle execution before current |
||
| 1378 | process unlock */ |
||
| 1379 | |||
| 1380 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 1381 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 1382 | |||
| 1383 | return HAL_OK; |
||
| 1384 | } |
||
| 1385 | else |
||
| 1386 | { |
||
| 1387 | return HAL_BUSY; |
||
| 1388 | } |
||
| 1389 | } |
||
| 1390 | |||
| 1391 | /** |
||
| 1392 | * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt |
||
| 1393 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
| 1394 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1395 | * the configuration information for the specified I2C. |
||
| 1396 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 1397 | * in datasheet must be shifted to the left before calling the interface |
||
| 1398 | * @param pData Pointer to data buffer |
||
| 1399 | * @param Size Amount of data to be sent |
||
| 1400 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
| 1401 | * @retval HAL status |
||
| 1402 | */ |
||
| 1403 | HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
| 1404 | { |
||
| 1405 | __IO uint32_t Prev_State = 0x00U; |
||
| 1406 | __IO uint32_t count = 0x00U; |
||
| 1407 | |||
| 1408 | /* Check the parameters */ |
||
| 1409 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
| 1410 | |||
| 1411 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 1412 | { |
||
| 1413 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
| 1414 | if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
| 1415 | { |
||
| 1416 | /* Wait until BUSY flag is reset */ |
||
| 1417 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 1418 | do |
||
| 1419 | { |
||
| 1420 | if(count-- == 0U) |
||
| 1421 | { |
||
| 1422 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 1423 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 1424 | |||
| 1425 | /* Process Unlocked */ |
||
| 1426 | __HAL_UNLOCK(hi2c); |
||
| 1427 | |||
| 1428 | return HAL_TIMEOUT; |
||
| 1429 | } |
||
| 1430 | } |
||
| 1431 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 1432 | } |
||
| 1433 | |||
| 1434 | /* Process Locked */ |
||
| 1435 | __HAL_LOCK(hi2c); |
||
| 1436 | |||
| 1437 | /* Check if the I2C is already enabled */ |
||
| 1438 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1439 | { |
||
| 1440 | /* Enable I2C peripheral */ |
||
| 1441 | __HAL_I2C_ENABLE(hi2c); |
||
| 1442 | } |
||
| 1443 | |||
| 1444 | /* Disable Pos */ |
||
| 1445 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1446 | |||
| 1447 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 1448 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
| 1449 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1450 | |||
| 1451 | /* Prepare transfer parameters */ |
||
| 1452 | hi2c->pBuffPtr = pData; |
||
| 1453 | hi2c->XferCount = Size; |
||
| 1454 | hi2c->XferOptions = XferOptions; |
||
| 1455 | hi2c->XferSize = hi2c->XferCount; |
||
| 1456 | hi2c->Devaddress = DevAddress; |
||
| 1457 | |||
| 1458 | Prev_State = hi2c->PreviousState; |
||
| 1459 | |||
| 1460 | /* Generate Start */ |
||
| 1461 | if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) |
||
| 1462 | { |
||
| 1463 | /* Generate Start condition if first transfer */ |
||
| 1464 | if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
| 1465 | { |
||
| 1466 | /* Generate Start */ |
||
| 1467 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 1468 | } |
||
| 1469 | else |
||
| 1470 | { |
||
| 1471 | /* Generate ReStart */ |
||
| 1472 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 1473 | } |
||
| 1474 | } |
||
| 1475 | |||
| 1476 | /* Process Unlocked */ |
||
| 1477 | __HAL_UNLOCK(hi2c); |
||
| 1478 | |||
| 1479 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 1480 | to avoid the risk of I2C interrupt handle execution before current |
||
| 1481 | process unlock */ |
||
| 1482 | |||
| 1483 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 1484 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 1485 | |||
| 1486 | return HAL_OK; |
||
| 1487 | } |
||
| 1488 | else |
||
| 1489 | { |
||
| 1490 | return HAL_BUSY; |
||
| 1491 | } |
||
| 1492 | } |
||
| 1493 | |||
| 1494 | /** |
||
| 1495 | * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt |
||
| 1496 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
| 1497 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1498 | * the configuration information for the specified I2C. |
||
| 1499 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 1500 | * in datasheet must be shifted to the left before calling the interface |
||
| 1501 | * @param pData Pointer to data buffer |
||
| 1502 | * @param Size Amount of data to be sent |
||
| 1503 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
| 1504 | * @retval HAL status |
||
| 1505 | */ |
||
| 1506 | HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
| 1507 | { |
||
| 1508 | __IO uint32_t count = 0U; |
||
| 1509 | |||
| 1510 | /* Check the parameters */ |
||
| 1511 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
| 1512 | |||
| 1513 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 1514 | { |
||
| 1515 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
| 1516 | if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
| 1517 | { |
||
| 1518 | /* Wait until BUSY flag is reset */ |
||
| 1519 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 1520 | do |
||
| 1521 | { |
||
| 1522 | if(count-- == 0U) |
||
| 1523 | { |
||
| 1524 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 1525 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 1526 | |||
| 1527 | /* Process Unlocked */ |
||
| 1528 | __HAL_UNLOCK(hi2c); |
||
| 1529 | |||
| 1530 | return HAL_TIMEOUT; |
||
| 1531 | } |
||
| 1532 | } |
||
| 1533 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 1534 | } |
||
| 1535 | |||
| 1536 | /* Process Locked */ |
||
| 1537 | __HAL_LOCK(hi2c); |
||
| 1538 | |||
| 1539 | /* Check if the I2C is already enabled */ |
||
| 1540 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1541 | { |
||
| 1542 | /* Enable I2C peripheral */ |
||
| 1543 | __HAL_I2C_ENABLE(hi2c); |
||
| 1544 | } |
||
| 1545 | |||
| 1546 | /* Disable Pos */ |
||
| 1547 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1548 | |||
| 1549 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 1550 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
| 1551 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1552 | |||
| 1553 | /* Prepare transfer parameters */ |
||
| 1554 | hi2c->pBuffPtr = pData; |
||
| 1555 | hi2c->XferCount = Size; |
||
| 1556 | hi2c->XferOptions = XferOptions; |
||
| 1557 | hi2c->XferSize = hi2c->XferCount; |
||
| 1558 | hi2c->Devaddress = DevAddress; |
||
| 1559 | |||
| 1560 | if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) |
||
| 1561 | { |
||
| 1562 | /* Generate Start condition if first transfer */ |
||
| 1563 | if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) |
||
| 1564 | { |
||
| 1565 | /* Enable Acknowledge */ |
||
| 1566 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 1567 | |||
| 1568 | /* Generate Start */ |
||
| 1569 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 1570 | } |
||
| 1571 | else |
||
| 1572 | { |
||
| 1573 | /* Enable Acknowledge */ |
||
| 1574 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 1575 | |||
| 1576 | /* Generate ReStart */ |
||
| 1577 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 1578 | } |
||
| 1579 | } |
||
| 1580 | |||
| 1581 | /* Process Unlocked */ |
||
| 1582 | __HAL_UNLOCK(hi2c); |
||
| 1583 | |||
| 1584 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 1585 | to avoid the risk of I2C interrupt handle execution before current |
||
| 1586 | process unlock */ |
||
| 1587 | |||
| 1588 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 1589 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 1590 | |||
| 1591 | return HAL_OK; |
||
| 1592 | } |
||
| 1593 | else |
||
| 1594 | { |
||
| 1595 | return HAL_BUSY; |
||
| 1596 | } |
||
| 1597 | } |
||
| 1598 | |||
| 1599 | /** |
||
| 1600 | * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt |
||
| 1601 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1602 | * the configuration information for the specified I2C. |
||
| 1603 | * @param pData Pointer to data buffer |
||
| 1604 | * @param Size Amount of data to be sent |
||
| 1605 | * @retval HAL status |
||
| 1606 | */ |
||
| 1607 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
| 1608 | { |
||
| 1609 | __IO uint32_t count = 0U; |
||
| 1610 | |||
| 1611 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 1612 | { |
||
| 1613 | if((pData == NULL) || (Size == 0U)) |
||
| 1614 | { |
||
| 1615 | return HAL_ERROR; |
||
| 1616 | } |
||
| 1617 | |||
| 1618 | /* Wait until BUSY flag is reset */ |
||
| 1619 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 1620 | do |
||
| 1621 | { |
||
| 1622 | if(count-- == 0U) |
||
| 1623 | { |
||
| 1624 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 1625 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 1626 | |||
| 1627 | /* Process Unlocked */ |
||
| 1628 | __HAL_UNLOCK(hi2c); |
||
| 1629 | |||
| 1630 | return HAL_TIMEOUT; |
||
| 1631 | } |
||
| 1632 | } |
||
| 1633 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 1634 | |||
| 1635 | /* Process Locked */ |
||
| 1636 | __HAL_LOCK(hi2c); |
||
| 1637 | |||
| 1638 | /* Check if the I2C is already enabled */ |
||
| 1639 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1640 | { |
||
| 1641 | /* Enable I2C peripheral */ |
||
| 1642 | __HAL_I2C_ENABLE(hi2c); |
||
| 1643 | } |
||
| 1644 | |||
| 1645 | /* Disable Pos */ |
||
| 1646 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1647 | |||
| 1648 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 1649 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
| 1650 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1651 | |||
| 1652 | /* Prepare transfer parameters */ |
||
| 1653 | hi2c->pBuffPtr = pData; |
||
| 1654 | hi2c->XferCount = Size; |
||
| 1655 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 1656 | hi2c->XferSize = hi2c->XferCount; |
||
| 1657 | |||
| 1658 | /* Enable Address Acknowledge */ |
||
| 1659 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 1660 | |||
| 1661 | /* Process Unlocked */ |
||
| 1662 | __HAL_UNLOCK(hi2c); |
||
| 1663 | |||
| 1664 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 1665 | to avoid the risk of I2C interrupt handle execution before current |
||
| 1666 | process unlock */ |
||
| 1667 | |||
| 1668 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 1669 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 1670 | |||
| 1671 | return HAL_OK; |
||
| 1672 | } |
||
| 1673 | else |
||
| 1674 | { |
||
| 1675 | return HAL_BUSY; |
||
| 1676 | } |
||
| 1677 | } |
||
| 1678 | |||
| 1679 | /** |
||
| 1680 | * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt |
||
| 1681 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1682 | * the configuration information for the specified I2C. |
||
| 1683 | * @param pData Pointer to data buffer |
||
| 1684 | * @param Size Amount of data to be sent |
||
| 1685 | * @retval HAL status |
||
| 1686 | */ |
||
| 1687 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
| 1688 | { |
||
| 1689 | __IO uint32_t count = 0U; |
||
| 1690 | |||
| 1691 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 1692 | { |
||
| 1693 | if((pData == NULL) || (Size == 0U)) |
||
| 1694 | { |
||
| 1695 | return HAL_ERROR; |
||
| 1696 | } |
||
| 1697 | |||
| 1698 | /* Wait until BUSY flag is reset */ |
||
| 1699 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 1700 | do |
||
| 1701 | { |
||
| 1702 | if(count-- == 0U) |
||
| 1703 | { |
||
| 1704 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 1705 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 1706 | |||
| 1707 | /* Process Unlocked */ |
||
| 1708 | __HAL_UNLOCK(hi2c); |
||
| 1709 | |||
| 1710 | return HAL_TIMEOUT; |
||
| 1711 | } |
||
| 1712 | } |
||
| 1713 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 1714 | |||
| 1715 | /* Process Locked */ |
||
| 1716 | __HAL_LOCK(hi2c); |
||
| 1717 | |||
| 1718 | /* Check if the I2C is already enabled */ |
||
| 1719 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1720 | { |
||
| 1721 | /* Enable I2C peripheral */ |
||
| 1722 | __HAL_I2C_ENABLE(hi2c); |
||
| 1723 | } |
||
| 1724 | |||
| 1725 | /* Disable Pos */ |
||
| 1726 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1727 | |||
| 1728 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 1729 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
| 1730 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1731 | |||
| 1732 | /* Prepare transfer parameters */ |
||
| 1733 | hi2c->pBuffPtr = pData; |
||
| 1734 | hi2c->XferSize = Size; |
||
| 1735 | hi2c->XferCount = Size; |
||
| 1736 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 1737 | |||
| 1738 | /* Enable Address Acknowledge */ |
||
| 1739 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 1740 | |||
| 1741 | /* Process Unlocked */ |
||
| 1742 | __HAL_UNLOCK(hi2c); |
||
| 1743 | |||
| 1744 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 1745 | to avoid the risk of I2C interrupt handle execution before current |
||
| 1746 | process unlock */ |
||
| 1747 | |||
| 1748 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 1749 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 1750 | |||
| 1751 | return HAL_OK; |
||
| 1752 | } |
||
| 1753 | else |
||
| 1754 | { |
||
| 1755 | return HAL_BUSY; |
||
| 1756 | } |
||
| 1757 | } |
||
| 1758 | |||
| 1759 | /** |
||
| 1760 | * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt |
||
| 1761 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
| 1762 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1763 | * the configuration information for I2C module |
||
| 1764 | * @param pData Pointer to data buffer |
||
| 1765 | * @param Size Amount of data to be sent |
||
| 1766 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
| 1767 | * @retval HAL status |
||
| 1768 | */ |
||
| 1769 | HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
| 1770 | { |
||
| 1771 | /* Check the parameters */ |
||
| 1772 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
| 1773 | |||
| 1774 | if(hi2c->State == HAL_I2C_STATE_LISTEN) |
||
| 1775 | { |
||
| 1776 | if((pData == NULL) || (Size == 0U)) |
||
| 1777 | { |
||
| 1778 | return HAL_ERROR; |
||
| 1779 | } |
||
| 1780 | |||
| 1781 | /* Process Locked */ |
||
| 1782 | __HAL_LOCK(hi2c); |
||
| 1783 | |||
| 1784 | /* Check if the I2C is already enabled */ |
||
| 1785 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1786 | { |
||
| 1787 | /* Enable I2C peripheral */ |
||
| 1788 | __HAL_I2C_ENABLE(hi2c); |
||
| 1789 | } |
||
| 1790 | |||
| 1791 | /* Disable Pos */ |
||
| 1792 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1793 | |||
| 1794 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
||
| 1795 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
| 1796 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1797 | |||
| 1798 | /* Prepare transfer parameters */ |
||
| 1799 | hi2c->pBuffPtr = pData; |
||
| 1800 | hi2c->XferCount = Size; |
||
| 1801 | hi2c->XferOptions = XferOptions; |
||
| 1802 | hi2c->XferSize = hi2c->XferCount; |
||
| 1803 | |||
| 1804 | /* Clear ADDR flag */ |
||
| 1805 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 1806 | |||
| 1807 | /* Process Unlocked */ |
||
| 1808 | __HAL_UNLOCK(hi2c); |
||
| 1809 | |||
| 1810 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 1811 | to avoid the risk of I2C interrupt handle execution before current |
||
| 1812 | process unlock */ |
||
| 1813 | |||
| 1814 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 1815 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 1816 | |||
| 1817 | return HAL_OK; |
||
| 1818 | } |
||
| 1819 | else |
||
| 1820 | { |
||
| 1821 | return HAL_BUSY; |
||
| 1822 | } |
||
| 1823 | } |
||
| 1824 | |||
| 1825 | /** |
||
| 1826 | * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt |
||
| 1827 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
| 1828 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1829 | * the configuration information for the specified I2C. |
||
| 1830 | * @param pData Pointer to data buffer |
||
| 1831 | * @param Size Amount of data to be sent |
||
| 1832 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
| 1833 | * @retval HAL status |
||
| 1834 | */ |
||
| 1835 | HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
| 1836 | { |
||
| 1837 | /* Check the parameters */ |
||
| 1838 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
| 1839 | |||
| 1840 | if(hi2c->State == HAL_I2C_STATE_LISTEN) |
||
| 1841 | { |
||
| 1842 | if((pData == NULL) || (Size == 0U)) |
||
| 1843 | { |
||
| 1844 | return HAL_ERROR; |
||
| 1845 | } |
||
| 1846 | |||
| 1847 | /* Process Locked */ |
||
| 1848 | __HAL_LOCK(hi2c); |
||
| 1849 | |||
| 1850 | /* Check if the I2C is already enabled */ |
||
| 1851 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1852 | { |
||
| 1853 | /* Enable I2C peripheral */ |
||
| 1854 | __HAL_I2C_ENABLE(hi2c); |
||
| 1855 | } |
||
| 1856 | |||
| 1857 | /* Disable Pos */ |
||
| 1858 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 1859 | |||
| 1860 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
||
| 1861 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
| 1862 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 1863 | |||
| 1864 | /* Prepare transfer parameters */ |
||
| 1865 | hi2c->pBuffPtr = pData; |
||
| 1866 | hi2c->XferCount = Size; |
||
| 1867 | hi2c->XferOptions = XferOptions; |
||
| 1868 | hi2c->XferSize = hi2c->XferCount; |
||
| 1869 | |||
| 1870 | /* Clear ADDR flag */ |
||
| 1871 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 1872 | |||
| 1873 | /* Process Unlocked */ |
||
| 1874 | __HAL_UNLOCK(hi2c); |
||
| 1875 | |||
| 1876 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 1877 | to avoid the risk of I2C interrupt handle execution before current |
||
| 1878 | process unlock */ |
||
| 1879 | |||
| 1880 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 1881 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 1882 | |||
| 1883 | return HAL_OK; |
||
| 1884 | } |
||
| 1885 | else |
||
| 1886 | { |
||
| 1887 | return HAL_BUSY; |
||
| 1888 | } |
||
| 1889 | } |
||
| 1890 | |||
| 1891 | /** |
||
| 1892 | * @brief Enable the Address listen mode with Interrupt. |
||
| 1893 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1894 | * the configuration information for the specified I2C. |
||
| 1895 | * @retval HAL status |
||
| 1896 | */ |
||
| 1897 | HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) |
||
| 1898 | { |
||
| 1899 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 1900 | { |
||
| 1901 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
| 1902 | |||
| 1903 | /* Check if the I2C is already enabled */ |
||
| 1904 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1905 | { |
||
| 1906 | /* Enable I2C peripheral */ |
||
| 1907 | __HAL_I2C_ENABLE(hi2c); |
||
| 1908 | } |
||
| 1909 | |||
| 1910 | /* Enable Address Acknowledge */ |
||
| 1911 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 1912 | |||
| 1913 | /* Enable EVT and ERR interrupt */ |
||
| 1914 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
| 1915 | |||
| 1916 | return HAL_OK; |
||
| 1917 | } |
||
| 1918 | else |
||
| 1919 | { |
||
| 1920 | return HAL_BUSY; |
||
| 1921 | } |
||
| 1922 | } |
||
| 1923 | |||
| 1924 | /** |
||
| 1925 | * @brief Disable the Address listen mode with Interrupt. |
||
| 1926 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1927 | * the configuration information for the specified I2C. |
||
| 1928 | * @retval HAL status |
||
| 1929 | */ |
||
| 1930 | HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) |
||
| 1931 | { |
||
| 1932 | /* Declaration of tmp to prevent undefined behavior of volatile usage */ |
||
| 1933 | uint32_t tmp; |
||
| 1934 | |||
| 1935 | /* Disable Address listen mode only if a transfer is not ongoing */ |
||
| 1936 | if(hi2c->State == HAL_I2C_STATE_LISTEN) |
||
| 1937 | { |
||
| 1938 | tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; |
||
| 1939 | hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); |
||
| 1940 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 1941 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 1942 | |||
| 1943 | /* Disable Address Acknowledge */ |
||
| 1944 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 1945 | |||
| 1946 | /* Disable EVT and ERR interrupt */ |
||
| 1947 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
| 1948 | |||
| 1949 | return HAL_OK; |
||
| 1950 | } |
||
| 1951 | else |
||
| 1952 | { |
||
| 1953 | return HAL_BUSY; |
||
| 1954 | } |
||
| 1955 | } |
||
| 1956 | |||
| 1957 | /** |
||
| 1958 | * @brief Transmit in master mode an amount of data in non-blocking mode with DMA |
||
| 1959 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 1960 | * the configuration information for the specified I2C. |
||
| 1961 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 1962 | * in datasheet must be shifted to the left before calling the interface |
||
| 1963 | * @param pData Pointer to data buffer |
||
| 1964 | * @param Size Amount of data to be sent |
||
| 1965 | * @retval HAL status |
||
| 1966 | */ |
||
| 1967 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
| 1968 | { |
||
| 1969 | __IO uint32_t count = 0U; |
||
| 1970 | |||
| 1971 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 1972 | { |
||
| 1973 | /* Wait until BUSY flag is reset */ |
||
| 1974 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 1975 | do |
||
| 1976 | { |
||
| 1977 | if(count-- == 0U) |
||
| 1978 | { |
||
| 1979 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 1980 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 1981 | |||
| 1982 | /* Process Unlocked */ |
||
| 1983 | __HAL_UNLOCK(hi2c); |
||
| 1984 | |||
| 1985 | return HAL_TIMEOUT; |
||
| 1986 | } |
||
| 1987 | } |
||
| 1988 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 1989 | |||
| 1990 | /* Process Locked */ |
||
| 1991 | __HAL_LOCK(hi2c); |
||
| 1992 | |||
| 1993 | /* Check if the I2C is already enabled */ |
||
| 1994 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 1995 | { |
||
| 1996 | /* Enable I2C peripheral */ |
||
| 1997 | __HAL_I2C_ENABLE(hi2c); |
||
| 1998 | } |
||
| 1999 | |||
| 2000 | /* Disable Pos */ |
||
| 2001 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 2002 | |||
| 2003 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 2004 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
| 2005 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 2006 | |||
| 2007 | /* Prepare transfer parameters */ |
||
| 2008 | hi2c->pBuffPtr = pData; |
||
| 2009 | hi2c->XferCount = Size; |
||
| 2010 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 2011 | hi2c->XferSize = hi2c->XferCount; |
||
| 2012 | hi2c->Devaddress = DevAddress; |
||
| 2013 | |||
| 2014 | if(hi2c->XferSize > 0U) |
||
| 2015 | { |
||
| 2016 | /* Set the I2C DMA transfer complete callback */ |
||
| 2017 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
| 2018 | |||
| 2019 | /* Set the DMA error callback */ |
||
| 2020 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
| 2021 | |||
| 2022 | /* Set the unused DMA callbacks to NULL */ |
||
| 2023 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
| 2024 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
| 2025 | |||
| 2026 | /* Enable the DMA channel */ |
||
| 2027 | HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
| 2028 | |||
| 2029 | /* Enable Acknowledge */ |
||
| 2030 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 2031 | |||
| 2032 | /* Generate Start */ |
||
| 2033 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 2034 | |||
| 2035 | /* Process Unlocked */ |
||
| 2036 | __HAL_UNLOCK(hi2c); |
||
| 2037 | |||
| 2038 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 2039 | to avoid the risk of I2C interrupt handle execution before current |
||
| 2040 | process unlock */ |
||
| 2041 | |||
| 2042 | /* Enable EVT and ERR interrupt */ |
||
| 2043 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
| 2044 | |||
| 2045 | /* Enable DMA Request */ |
||
| 2046 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
| 2047 | } |
||
| 2048 | else |
||
| 2049 | { |
||
| 2050 | /* Enable Acknowledge */ |
||
| 2051 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 2052 | |||
| 2053 | /* Generate Start */ |
||
| 2054 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 2055 | |||
| 2056 | /* Process Unlocked */ |
||
| 2057 | __HAL_UNLOCK(hi2c); |
||
| 2058 | |||
| 2059 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 2060 | to avoid the risk of I2C interrupt handle execution before current |
||
| 2061 | process unlock */ |
||
| 2062 | |||
| 2063 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 2064 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 2065 | } |
||
| 2066 | |||
| 2067 | return HAL_OK; |
||
| 2068 | } |
||
| 2069 | else |
||
| 2070 | { |
||
| 2071 | return HAL_BUSY; |
||
| 2072 | } |
||
| 2073 | } |
||
| 2074 | |||
| 2075 | /** |
||
| 2076 | * @brief Receive in master mode an amount of data in non-blocking mode with DMA |
||
| 2077 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 2078 | * the configuration information for the specified I2C. |
||
| 2079 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 2080 | * in datasheet must be shifted to the left before calling the interface |
||
| 2081 | * @param pData Pointer to data buffer |
||
| 2082 | * @param Size Amount of data to be sent |
||
| 2083 | * @retval HAL status |
||
| 2084 | */ |
||
| 2085 | HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
| 2086 | { |
||
| 2087 | __IO uint32_t count = 0U; |
||
| 2088 | |||
| 2089 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 2090 | { |
||
| 2091 | /* Wait until BUSY flag is reset */ |
||
| 2092 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 2093 | do |
||
| 2094 | { |
||
| 2095 | if(count-- == 0U) |
||
| 2096 | { |
||
| 2097 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 2098 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 2099 | |||
| 2100 | /* Process Unlocked */ |
||
| 2101 | __HAL_UNLOCK(hi2c); |
||
| 2102 | |||
| 2103 | return HAL_TIMEOUT; |
||
| 2104 | } |
||
| 2105 | } |
||
| 2106 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 2107 | |||
| 2108 | /* Process Locked */ |
||
| 2109 | __HAL_LOCK(hi2c); |
||
| 2110 | |||
| 2111 | /* Check if the I2C is already enabled */ |
||
| 2112 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 2113 | { |
||
| 2114 | /* Enable I2C peripheral */ |
||
| 2115 | __HAL_I2C_ENABLE(hi2c); |
||
| 2116 | } |
||
| 2117 | |||
| 2118 | /* Disable Pos */ |
||
| 2119 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 2120 | |||
| 2121 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 2122 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
| 2123 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 2124 | |||
| 2125 | /* Prepare transfer parameters */ |
||
| 2126 | hi2c->pBuffPtr = pData; |
||
| 2127 | hi2c->XferCount = Size; |
||
| 2128 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 2129 | hi2c->XferSize = hi2c->XferCount; |
||
| 2130 | hi2c->Devaddress = DevAddress; |
||
| 2131 | |||
| 2132 | if(hi2c->XferSize > 0U) |
||
| 2133 | { |
||
| 2134 | /* Set the I2C DMA transfer complete callback */ |
||
| 2135 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
| 2136 | |||
| 2137 | /* Set the DMA error callback */ |
||
| 2138 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
| 2139 | |||
| 2140 | /* Set the unused DMA callbacks to NULL */ |
||
| 2141 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
| 2142 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
| 2143 | |||
| 2144 | /* Enable the DMA channel */ |
||
| 2145 | HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
| 2146 | |||
| 2147 | /* Enable Acknowledge */ |
||
| 2148 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 2149 | |||
| 2150 | /* Generate Start */ |
||
| 2151 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 2152 | |||
| 2153 | /* Process Unlocked */ |
||
| 2154 | __HAL_UNLOCK(hi2c); |
||
| 2155 | |||
| 2156 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 2157 | to avoid the risk of I2C interrupt handle execution before current |
||
| 2158 | process unlock */ |
||
| 2159 | |||
| 2160 | /* Enable EVT and ERR interrupt */ |
||
| 2161 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
| 2162 | |||
| 2163 | /* Enable DMA Request */ |
||
| 2164 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
| 2165 | } |
||
| 2166 | else |
||
| 2167 | { |
||
| 2168 | /* Enable Acknowledge */ |
||
| 2169 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 2170 | |||
| 2171 | /* Generate Start */ |
||
| 2172 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 2173 | |||
| 2174 | /* Process Unlocked */ |
||
| 2175 | __HAL_UNLOCK(hi2c); |
||
| 2176 | |||
| 2177 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 2178 | to avoid the risk of I2C interrupt handle execution before current |
||
| 2179 | process unlock */ |
||
| 2180 | |||
| 2181 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 2182 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 2183 | } |
||
| 2184 | |||
| 2185 | return HAL_OK; |
||
| 2186 | } |
||
| 2187 | else |
||
| 2188 | { |
||
| 2189 | return HAL_BUSY; |
||
| 2190 | } |
||
| 2191 | } |
||
| 2192 | |||
| 2193 | /** |
||
| 2194 | * @brief Abort a master I2C process communication with Interrupt. |
||
| 2195 | * @note This abort can be called only if state is ready |
||
| 2196 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 2197 | * the configuration information for the specified I2C. |
||
| 2198 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 2199 | * in datasheet must be shifted to the left before calling the interface |
||
| 2200 | * @retval HAL status |
||
| 2201 | */ |
||
| 2202 | HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) |
||
| 2203 | { |
||
| 2204 | /* Prevent unused argument(s) compilation warning */ |
||
| 2205 | UNUSED(DevAddress); |
||
| 2206 | |||
| 2207 | /* Abort Master transfer during Receive or Transmit process */ |
||
| 2208 | if(hi2c->Mode == HAL_I2C_MODE_MASTER) |
||
| 2209 | { |
||
| 2210 | /* Process Locked */ |
||
| 2211 | __HAL_LOCK(hi2c); |
||
| 2212 | |||
| 2213 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 2214 | hi2c->State = HAL_I2C_STATE_ABORT; |
||
| 2215 | |||
| 2216 | /* Disable Acknowledge */ |
||
| 2217 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 2218 | |||
| 2219 | /* Generate Stop */ |
||
| 2220 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 2221 | |||
| 2222 | hi2c->XferCount = 0U; |
||
| 2223 | |||
| 2224 | /* Disable EVT, BUF and ERR interrupt */ |
||
| 2225 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 2226 | |||
| 2227 | /* Process Unlocked */ |
||
| 2228 | __HAL_UNLOCK(hi2c); |
||
| 2229 | |||
| 2230 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
| 2231 | I2C_ITError(hi2c); |
||
| 2232 | |||
| 2233 | return HAL_OK; |
||
| 2234 | } |
||
| 2235 | else |
||
| 2236 | { |
||
| 2237 | /* Wrong usage of abort function */ |
||
| 2238 | /* This function should be used only in case of abort monitored by master device */ |
||
| 2239 | return HAL_ERROR; |
||
| 2240 | } |
||
| 2241 | } |
||
| 2242 | |||
| 2243 | /** |
||
| 2244 | * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA |
||
| 2245 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 2246 | * the configuration information for the specified I2C. |
||
| 2247 | * @param pData Pointer to data buffer |
||
| 2248 | * @param Size Amount of data to be sent |
||
| 2249 | * @retval HAL status |
||
| 2250 | */ |
||
| 2251 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
| 2252 | { |
||
| 2253 | __IO uint32_t count = 0U; |
||
| 2254 | |||
| 2255 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 2256 | { |
||
| 2257 | if((pData == NULL) || (Size == 0U)) |
||
| 2258 | { |
||
| 2259 | return HAL_ERROR; |
||
| 2260 | } |
||
| 2261 | |||
| 2262 | /* Wait until BUSY flag is reset */ |
||
| 2263 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 2264 | do |
||
| 2265 | { |
||
| 2266 | if(count-- == 0U) |
||
| 2267 | { |
||
| 2268 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 2269 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 2270 | |||
| 2271 | /* Process Unlocked */ |
||
| 2272 | __HAL_UNLOCK(hi2c); |
||
| 2273 | |||
| 2274 | return HAL_TIMEOUT; |
||
| 2275 | } |
||
| 2276 | } |
||
| 2277 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 2278 | |||
| 2279 | /* Process Locked */ |
||
| 2280 | __HAL_LOCK(hi2c); |
||
| 2281 | |||
| 2282 | /* Check if the I2C is already enabled */ |
||
| 2283 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 2284 | { |
||
| 2285 | /* Enable I2C peripheral */ |
||
| 2286 | __HAL_I2C_ENABLE(hi2c); |
||
| 2287 | } |
||
| 2288 | |||
| 2289 | /* Disable Pos */ |
||
| 2290 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 2291 | |||
| 2292 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 2293 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
| 2294 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 2295 | |||
| 2296 | /* Prepare transfer parameters */ |
||
| 2297 | hi2c->pBuffPtr = pData; |
||
| 2298 | hi2c->XferCount = Size; |
||
| 2299 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 2300 | hi2c->XferSize = hi2c->XferCount; |
||
| 2301 | |||
| 2302 | /* Set the I2C DMA transfer complete callback */ |
||
| 2303 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
| 2304 | |||
| 2305 | /* Set the DMA error callback */ |
||
| 2306 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
| 2307 | |||
| 2308 | /* Set the unused DMA callbacks to NULL */ |
||
| 2309 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
| 2310 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
| 2311 | |||
| 2312 | /* Enable the DMA channel */ |
||
| 2313 | HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
| 2314 | |||
| 2315 | /* Enable Address Acknowledge */ |
||
| 2316 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 2317 | |||
| 2318 | /* Process Unlocked */ |
||
| 2319 | __HAL_UNLOCK(hi2c); |
||
| 2320 | |||
| 2321 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 2322 | to avoid the risk of I2C interrupt handle execution before current |
||
| 2323 | process unlock */ |
||
| 2324 | /* Enable EVT and ERR interrupt */ |
||
| 2325 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
| 2326 | |||
| 2327 | /* Enable DMA Request */ |
||
| 2328 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
| 2329 | |||
| 2330 | return HAL_OK; |
||
| 2331 | } |
||
| 2332 | else |
||
| 2333 | { |
||
| 2334 | return HAL_BUSY; |
||
| 2335 | } |
||
| 2336 | } |
||
| 2337 | |||
| 2338 | /** |
||
| 2339 | * @brief Receive in slave mode an amount of data in non-blocking mode with DMA |
||
| 2340 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 2341 | * the configuration information for the specified I2C. |
||
| 2342 | * @param pData Pointer to data buffer |
||
| 2343 | * @param Size Amount of data to be sent |
||
| 2344 | * @retval HAL status |
||
| 2345 | */ |
||
| 2346 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
| 2347 | { |
||
| 2348 | __IO uint32_t count = 0U; |
||
| 2349 | |||
| 2350 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 2351 | { |
||
| 2352 | if((pData == NULL) || (Size == 0U)) |
||
| 2353 | { |
||
| 2354 | return HAL_ERROR; |
||
| 2355 | } |
||
| 2356 | |||
| 2357 | /* Wait until BUSY flag is reset */ |
||
| 2358 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 2359 | do |
||
| 2360 | { |
||
| 2361 | if(count-- == 0U) |
||
| 2362 | { |
||
| 2363 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 2364 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 2365 | |||
| 2366 | /* Process Unlocked */ |
||
| 2367 | __HAL_UNLOCK(hi2c); |
||
| 2368 | |||
| 2369 | return HAL_TIMEOUT; |
||
| 2370 | } |
||
| 2371 | } |
||
| 2372 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 2373 | |||
| 2374 | /* Process Locked */ |
||
| 2375 | __HAL_LOCK(hi2c); |
||
| 2376 | |||
| 2377 | /* Check if the I2C is already enabled */ |
||
| 2378 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 2379 | { |
||
| 2380 | /* Enable I2C peripheral */ |
||
| 2381 | __HAL_I2C_ENABLE(hi2c); |
||
| 2382 | } |
||
| 2383 | |||
| 2384 | /* Disable Pos */ |
||
| 2385 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 2386 | |||
| 2387 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 2388 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
| 2389 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 2390 | |||
| 2391 | /* Prepare transfer parameters */ |
||
| 2392 | hi2c->pBuffPtr = pData; |
||
| 2393 | hi2c->XferCount = Size; |
||
| 2394 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 2395 | hi2c->XferSize = hi2c->XferCount; |
||
| 2396 | |||
| 2397 | /* Set the I2C DMA transfer complete callback */ |
||
| 2398 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
| 2399 | |||
| 2400 | /* Set the DMA error callback */ |
||
| 2401 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
| 2402 | |||
| 2403 | /* Set the unused DMA callbacks to NULL */ |
||
| 2404 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
| 2405 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
| 2406 | |||
| 2407 | /* Enable the DMA channel */ |
||
| 2408 | HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
| 2409 | |||
| 2410 | /* Enable Address Acknowledge */ |
||
| 2411 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 2412 | |||
| 2413 | /* Process Unlocked */ |
||
| 2414 | __HAL_UNLOCK(hi2c); |
||
| 2415 | |||
| 2416 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 2417 | to avoid the risk of I2C interrupt handle execution before current |
||
| 2418 | process unlock */ |
||
| 2419 | /* Enable EVT and ERR interrupt */ |
||
| 2420 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
| 2421 | |||
| 2422 | /* Enable DMA Request */ |
||
| 2423 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
| 2424 | |||
| 2425 | return HAL_OK; |
||
| 2426 | } |
||
| 2427 | else |
||
| 2428 | { |
||
| 2429 | return HAL_BUSY; |
||
| 2430 | } |
||
| 2431 | } |
||
| 2432 | /** |
||
| 2433 | * @brief Write an amount of data in blocking mode to a specific memory address |
||
| 2434 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 2435 | * the configuration information for the specified I2C. |
||
| 2436 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 2437 | * in datasheet must be shifted to the left before calling the interface |
||
| 2438 | * @param MemAddress Internal memory address |
||
| 2439 | * @param MemAddSize Size of internal memory address |
||
| 2440 | * @param pData Pointer to data buffer |
||
| 2441 | * @param Size Amount of data to be sent |
||
| 2442 | * @param Timeout Timeout duration |
||
| 2443 | * @retval HAL status |
||
| 2444 | */ |
||
| 2445 | HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
| 2446 | { |
||
| 2447 | uint32_t tickstart = 0x00U; |
||
| 2448 | |||
| 2449 | /* Init tickstart for timeout management*/ |
||
| 2450 | tickstart = HAL_GetTick(); |
||
| 2451 | |||
| 2452 | /* Check the parameters */ |
||
| 2453 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
| 2454 | |||
| 2455 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 2456 | { |
||
| 2457 | /* Wait until BUSY flag is reset */ |
||
| 2458 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
| 2459 | { |
||
| 2460 | return HAL_BUSY; |
||
| 2461 | } |
||
| 2462 | |||
| 2463 | /* Process Locked */ |
||
| 2464 | __HAL_LOCK(hi2c); |
||
| 2465 | |||
| 2466 | /* Check if the I2C is already enabled */ |
||
| 2467 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 2468 | { |
||
| 2469 | /* Enable I2C peripheral */ |
||
| 2470 | __HAL_I2C_ENABLE(hi2c); |
||
| 2471 | } |
||
| 2472 | |||
| 2473 | /* Disable Pos */ |
||
| 2474 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 2475 | |||
| 2476 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 2477 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
| 2478 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 2479 | |||
| 2480 | /* Prepare transfer parameters */ |
||
| 2481 | hi2c->pBuffPtr = pData; |
||
| 2482 | hi2c->XferCount = Size; |
||
| 2483 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 2484 | hi2c->XferSize = hi2c->XferCount; |
||
| 2485 | |||
| 2486 | /* Send Slave Address and Memory Address */ |
||
| 2487 | if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
||
| 2488 | { |
||
| 2489 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 2490 | { |
||
| 2491 | /* Process Unlocked */ |
||
| 2492 | __HAL_UNLOCK(hi2c); |
||
| 2493 | return HAL_ERROR; |
||
| 2494 | } |
||
| 2495 | else |
||
| 2496 | { |
||
| 2497 | /* Process Unlocked */ |
||
| 2498 | __HAL_UNLOCK(hi2c); |
||
| 2499 | return HAL_TIMEOUT; |
||
| 2500 | } |
||
| 2501 | } |
||
| 2502 | |||
| 2503 | while(hi2c->XferSize > 0U) |
||
| 2504 | { |
||
| 2505 | /* Wait until TXE flag is set */ |
||
| 2506 | if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 2507 | { |
||
| 2508 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 2509 | { |
||
| 2510 | /* Generate Stop */ |
||
| 2511 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 2512 | return HAL_ERROR; |
||
| 2513 | } |
||
| 2514 | else |
||
| 2515 | { |
||
| 2516 | return HAL_TIMEOUT; |
||
| 2517 | } |
||
| 2518 | } |
||
| 2519 | |||
| 2520 | /* Write data to DR */ |
||
| 2521 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 2522 | hi2c->XferSize--; |
||
| 2523 | hi2c->XferCount--; |
||
| 2524 | |||
| 2525 | if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
| 2526 | { |
||
| 2527 | /* Write data to DR */ |
||
| 2528 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 2529 | hi2c->XferSize--; |
||
| 2530 | hi2c->XferCount--; |
||
| 2531 | } |
||
| 2532 | } |
||
| 2533 | |||
| 2534 | /* Wait until BTF flag is set */ |
||
| 2535 | if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 2536 | { |
||
| 2537 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 2538 | { |
||
| 2539 | /* Generate Stop */ |
||
| 2540 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 2541 | return HAL_ERROR; |
||
| 2542 | } |
||
| 2543 | else |
||
| 2544 | { |
||
| 2545 | return HAL_TIMEOUT; |
||
| 2546 | } |
||
| 2547 | } |
||
| 2548 | |||
| 2549 | /* Generate Stop */ |
||
| 2550 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 2551 | |||
| 2552 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 2553 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 2554 | |||
| 2555 | /* Process Unlocked */ |
||
| 2556 | __HAL_UNLOCK(hi2c); |
||
| 2557 | |||
| 2558 | return HAL_OK; |
||
| 2559 | } |
||
| 2560 | else |
||
| 2561 | { |
||
| 2562 | return HAL_BUSY; |
||
| 2563 | } |
||
| 2564 | } |
||
| 2565 | |||
| 2566 | /** |
||
| 2567 | * @brief Read an amount of data in blocking mode from a specific memory address |
||
| 2568 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 2569 | * the configuration information for the specified I2C. |
||
| 2570 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 2571 | * in datasheet must be shifted to the left before calling the interface |
||
| 2572 | * @param MemAddress Internal memory address |
||
| 2573 | * @param MemAddSize Size of internal memory address |
||
| 2574 | * @param pData Pointer to data buffer |
||
| 2575 | * @param Size Amount of data to be sent |
||
| 2576 | * @param Timeout Timeout duration |
||
| 2577 | * @retval HAL status |
||
| 2578 | */ |
||
| 2579 | HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
| 2580 | { |
||
| 2581 | uint32_t tickstart = 0x00U; |
||
| 2582 | |||
| 2583 | /* Init tickstart for timeout management*/ |
||
| 2584 | tickstart = HAL_GetTick(); |
||
| 2585 | |||
| 2586 | /* Check the parameters */ |
||
| 2587 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
| 2588 | |||
| 2589 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 2590 | { |
||
| 2591 | /* Wait until BUSY flag is reset */ |
||
| 2592 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
| 2593 | { |
||
| 2594 | return HAL_BUSY; |
||
| 2595 | } |
||
| 2596 | |||
| 2597 | /* Process Locked */ |
||
| 2598 | __HAL_LOCK(hi2c); |
||
| 2599 | |||
| 2600 | /* Check if the I2C is already enabled */ |
||
| 2601 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 2602 | { |
||
| 2603 | /* Enable I2C peripheral */ |
||
| 2604 | __HAL_I2C_ENABLE(hi2c); |
||
| 2605 | } |
||
| 2606 | |||
| 2607 | /* Disable Pos */ |
||
| 2608 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 2609 | |||
| 2610 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 2611 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
| 2612 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 2613 | |||
| 2614 | /* Prepare transfer parameters */ |
||
| 2615 | hi2c->pBuffPtr = pData; |
||
| 2616 | hi2c->XferCount = Size; |
||
| 2617 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 2618 | hi2c->XferSize = hi2c->XferCount; |
||
| 2619 | |||
| 2620 | /* Send Slave Address and Memory Address */ |
||
| 2621 | if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
||
| 2622 | { |
||
| 2623 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 2624 | { |
||
| 2625 | /* Process Unlocked */ |
||
| 2626 | __HAL_UNLOCK(hi2c); |
||
| 2627 | return HAL_ERROR; |
||
| 2628 | } |
||
| 2629 | else |
||
| 2630 | { |
||
| 2631 | /* Process Unlocked */ |
||
| 2632 | __HAL_UNLOCK(hi2c); |
||
| 2633 | return HAL_TIMEOUT; |
||
| 2634 | } |
||
| 2635 | } |
||
| 2636 | |||
| 2637 | if(hi2c->XferSize == 0U) |
||
| 2638 | { |
||
| 2639 | /* Clear ADDR flag */ |
||
| 2640 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 2641 | |||
| 2642 | /* Generate Stop */ |
||
| 2643 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 2644 | } |
||
| 2645 | else if(hi2c->XferSize == 1U) |
||
| 2646 | { |
||
| 2647 | /* Disable Acknowledge */ |
||
| 2648 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 2649 | |||
| 2650 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
| 2651 | software sequence must complete before the current byte end of transfer */ |
||
| 2652 | __disable_irq(); |
||
| 2653 | |||
| 2654 | /* Clear ADDR flag */ |
||
| 2655 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 2656 | |||
| 2657 | /* Generate Stop */ |
||
| 2658 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 2659 | |||
| 2660 | /* Re-enable IRQs */ |
||
| 2661 | __enable_irq(); |
||
| 2662 | } |
||
| 2663 | else if(hi2c->XferSize == 2U) |
||
| 2664 | { |
||
| 2665 | /* Enable Pos */ |
||
| 2666 | hi2c->Instance->CR1 |= I2C_CR1_POS; |
||
| 2667 | |||
| 2668 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
| 2669 | software sequence must complete before the current byte end of transfer */ |
||
| 2670 | __disable_irq(); |
||
| 2671 | |||
| 2672 | /* Clear ADDR flag */ |
||
| 2673 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 2674 | |||
| 2675 | /* Disable Acknowledge */ |
||
| 2676 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 2677 | |||
| 2678 | /* Re-enable IRQs */ |
||
| 2679 | __enable_irq(); |
||
| 2680 | } |
||
| 2681 | else |
||
| 2682 | { |
||
| 2683 | /* Enable Acknowledge */ |
||
| 2684 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
| 2685 | |||
| 2686 | /* Clear ADDR flag */ |
||
| 2687 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 2688 | } |
||
| 2689 | |||
| 2690 | while(hi2c->XferSize > 0U) |
||
| 2691 | { |
||
| 2692 | if(hi2c->XferSize <= 3U) |
||
| 2693 | { |
||
| 2694 | /* One byte */ |
||
| 2695 | if(hi2c->XferSize== 1U) |
||
| 2696 | { |
||
| 2697 | /* Wait until RXNE flag is set */ |
||
| 2698 | if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 2699 | { |
||
| 2700 | if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) |
||
| 2701 | { |
||
| 2702 | return HAL_TIMEOUT; |
||
| 2703 | } |
||
| 2704 | else |
||
| 2705 | { |
||
| 2706 | return HAL_ERROR; |
||
| 2707 | } |
||
| 2708 | } |
||
| 2709 | |||
| 2710 | /* Read data from DR */ |
||
| 2711 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 2712 | hi2c->XferSize--; |
||
| 2713 | hi2c->XferCount--; |
||
| 2714 | } |
||
| 2715 | /* Two bytes */ |
||
| 2716 | else if(hi2c->XferSize == 2U) |
||
| 2717 | { |
||
| 2718 | /* Wait until BTF flag is set */ |
||
| 2719 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
| 2720 | { |
||
| 2721 | return HAL_TIMEOUT; |
||
| 2722 | } |
||
| 2723 | |||
| 2724 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
| 2725 | software sequence must complete before the current byte end of transfer */ |
||
| 2726 | __disable_irq(); |
||
| 2727 | |||
| 2728 | /* Generate Stop */ |
||
| 2729 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 2730 | |||
| 2731 | /* Read data from DR */ |
||
| 2732 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 2733 | hi2c->XferSize--; |
||
| 2734 | hi2c->XferCount--; |
||
| 2735 | |||
| 2736 | /* Re-enable IRQs */ |
||
| 2737 | __enable_irq(); |
||
| 2738 | |||
| 2739 | /* Read data from DR */ |
||
| 2740 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 2741 | hi2c->XferSize--; |
||
| 2742 | hi2c->XferCount--; |
||
| 2743 | } |
||
| 2744 | /* 3 Last bytes */ |
||
| 2745 | else |
||
| 2746 | { |
||
| 2747 | /* Wait until BTF flag is set */ |
||
| 2748 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
| 2749 | { |
||
| 2750 | return HAL_TIMEOUT; |
||
| 2751 | } |
||
| 2752 | |||
| 2753 | /* Disable Acknowledge */ |
||
| 2754 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 2755 | |||
| 2756 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
||
| 2757 | software sequence must complete before the current byte end of transfer */ |
||
| 2758 | __disable_irq(); |
||
| 2759 | |||
| 2760 | /* Read data from DR */ |
||
| 2761 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 2762 | hi2c->XferSize--; |
||
| 2763 | hi2c->XferCount--; |
||
| 2764 | |||
| 2765 | /* Wait until BTF flag is set */ |
||
| 2766 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
| 2767 | { |
||
| 2768 | return HAL_TIMEOUT; |
||
| 2769 | } |
||
| 2770 | |||
| 2771 | /* Generate Stop */ |
||
| 2772 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 2773 | |||
| 2774 | /* Read data from DR */ |
||
| 2775 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 2776 | hi2c->XferSize--; |
||
| 2777 | hi2c->XferCount--; |
||
| 2778 | |||
| 2779 | /* Re-enable IRQs */ |
||
| 2780 | __enable_irq(); |
||
| 2781 | |||
| 2782 | /* Read data from DR */ |
||
| 2783 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 2784 | hi2c->XferSize--; |
||
| 2785 | hi2c->XferCount--; |
||
| 2786 | } |
||
| 2787 | } |
||
| 2788 | else |
||
| 2789 | { |
||
| 2790 | /* Wait until RXNE flag is set */ |
||
| 2791 | if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
| 2792 | { |
||
| 2793 | if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) |
||
| 2794 | { |
||
| 2795 | return HAL_TIMEOUT; |
||
| 2796 | } |
||
| 2797 | else |
||
| 2798 | { |
||
| 2799 | return HAL_ERROR; |
||
| 2800 | } |
||
| 2801 | } |
||
| 2802 | |||
| 2803 | /* Read data from DR */ |
||
| 2804 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 2805 | hi2c->XferSize--; |
||
| 2806 | hi2c->XferCount--; |
||
| 2807 | |||
| 2808 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
||
| 2809 | { |
||
| 2810 | /* Read data from DR */ |
||
| 2811 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 2812 | hi2c->XferSize--; |
||
| 2813 | hi2c->XferCount--; |
||
| 2814 | } |
||
| 2815 | } |
||
| 2816 | } |
||
| 2817 | |||
| 2818 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 2819 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 2820 | |||
| 2821 | /* Process Unlocked */ |
||
| 2822 | __HAL_UNLOCK(hi2c); |
||
| 2823 | |||
| 2824 | return HAL_OK; |
||
| 2825 | } |
||
| 2826 | else |
||
| 2827 | { |
||
| 2828 | return HAL_BUSY; |
||
| 2829 | } |
||
| 2830 | } |
||
| 2831 | |||
| 2832 | /** |
||
| 2833 | * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address |
||
| 2834 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 2835 | * the configuration information for the specified I2C. |
||
| 2836 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 2837 | * in datasheet must be shifted to the left before calling the interface |
||
| 2838 | * @param MemAddress Internal memory address |
||
| 2839 | * @param MemAddSize Size of internal memory address |
||
| 2840 | * @param pData Pointer to data buffer |
||
| 2841 | * @param Size Amount of data to be sent |
||
| 2842 | * @retval HAL status |
||
| 2843 | */ |
||
| 2844 | HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
| 2845 | { |
||
| 2846 | __IO uint32_t count = 0U; |
||
| 2847 | |||
| 2848 | /* Check the parameters */ |
||
| 2849 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
| 2850 | |||
| 2851 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 2852 | { |
||
| 2853 | /* Wait until BUSY flag is reset */ |
||
| 2854 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 2855 | do |
||
| 2856 | { |
||
| 2857 | if(count-- == 0U) |
||
| 2858 | { |
||
| 2859 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 2860 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 2861 | |||
| 2862 | /* Process Unlocked */ |
||
| 2863 | __HAL_UNLOCK(hi2c); |
||
| 2864 | |||
| 2865 | return HAL_TIMEOUT; |
||
| 2866 | } |
||
| 2867 | } |
||
| 2868 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 2869 | |||
| 2870 | /* Process Locked */ |
||
| 2871 | __HAL_LOCK(hi2c); |
||
| 2872 | |||
| 2873 | /* Check if the I2C is already enabled */ |
||
| 2874 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 2875 | { |
||
| 2876 | /* Enable I2C peripheral */ |
||
| 2877 | __HAL_I2C_ENABLE(hi2c); |
||
| 2878 | } |
||
| 2879 | |||
| 2880 | /* Disable Pos */ |
||
| 2881 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 2882 | |||
| 2883 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 2884 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
| 2885 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 2886 | |||
| 2887 | /* Prepare transfer parameters */ |
||
| 2888 | hi2c->pBuffPtr = pData; |
||
| 2889 | hi2c->XferSize = Size; |
||
| 2890 | hi2c->XferCount = Size; |
||
| 2891 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 2892 | hi2c->Devaddress = DevAddress; |
||
| 2893 | hi2c->Memaddress = MemAddress; |
||
| 2894 | hi2c->MemaddSize = MemAddSize; |
||
| 2895 | hi2c->EventCount = 0U; |
||
| 2896 | |||
| 2897 | /* Generate Start */ |
||
| 2898 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 2899 | |||
| 2900 | /* Process Unlocked */ |
||
| 2901 | __HAL_UNLOCK(hi2c); |
||
| 2902 | |||
| 2903 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 2904 | to avoid the risk of I2C interrupt handle execution before current |
||
| 2905 | process unlock */ |
||
| 2906 | |||
| 2907 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 2908 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 2909 | |||
| 2910 | return HAL_OK; |
||
| 2911 | } |
||
| 2912 | else |
||
| 2913 | { |
||
| 2914 | return HAL_BUSY; |
||
| 2915 | } |
||
| 2916 | } |
||
| 2917 | |||
| 2918 | /** |
||
| 2919 | * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address |
||
| 2920 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 2921 | * the configuration information for the specified I2C. |
||
| 2922 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 2923 | * in datasheet must be shifted to the left before calling the interface |
||
| 2924 | * @param MemAddress Internal memory address |
||
| 2925 | * @param MemAddSize Size of internal memory address |
||
| 2926 | * @param pData Pointer to data buffer |
||
| 2927 | * @param Size Amount of data to be sent |
||
| 2928 | * @retval HAL status |
||
| 2929 | */ |
||
| 2930 | HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
| 2931 | { |
||
| 2932 | __IO uint32_t count = 0U; |
||
| 2933 | |||
| 2934 | /* Check the parameters */ |
||
| 2935 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
| 2936 | |||
| 2937 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 2938 | { |
||
| 2939 | /* Wait until BUSY flag is reset */ |
||
| 2940 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 2941 | do |
||
| 2942 | { |
||
| 2943 | if(count-- == 0U) |
||
| 2944 | { |
||
| 2945 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 2946 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 2947 | |||
| 2948 | /* Process Unlocked */ |
||
| 2949 | __HAL_UNLOCK(hi2c); |
||
| 2950 | |||
| 2951 | return HAL_TIMEOUT; |
||
| 2952 | } |
||
| 2953 | } |
||
| 2954 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 2955 | |||
| 2956 | /* Process Locked */ |
||
| 2957 | __HAL_LOCK(hi2c); |
||
| 2958 | |||
| 2959 | /* Check if the I2C is already enabled */ |
||
| 2960 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 2961 | { |
||
| 2962 | /* Enable I2C peripheral */ |
||
| 2963 | __HAL_I2C_ENABLE(hi2c); |
||
| 2964 | } |
||
| 2965 | |||
| 2966 | /* Disable Pos */ |
||
| 2967 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 2968 | |||
| 2969 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 2970 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
| 2971 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 2972 | |||
| 2973 | /* Prepare transfer parameters */ |
||
| 2974 | hi2c->pBuffPtr = pData; |
||
| 2975 | hi2c->XferSize = Size; |
||
| 2976 | hi2c->XferCount = Size; |
||
| 2977 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 2978 | hi2c->Devaddress = DevAddress; |
||
| 2979 | hi2c->Memaddress = MemAddress; |
||
| 2980 | hi2c->MemaddSize = MemAddSize; |
||
| 2981 | hi2c->EventCount = 0U; |
||
| 2982 | |||
| 2983 | /* Enable Acknowledge */ |
||
| 2984 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 2985 | |||
| 2986 | /* Generate Start */ |
||
| 2987 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 2988 | |||
| 2989 | /* Process Unlocked */ |
||
| 2990 | __HAL_UNLOCK(hi2c); |
||
| 2991 | |||
| 2992 | if(hi2c->XferSize > 0U) |
||
| 2993 | { |
||
| 2994 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 2995 | to avoid the risk of I2C interrupt handle execution before current |
||
| 2996 | process unlock */ |
||
| 2997 | |||
| 2998 | /* Enable EVT, BUF and ERR interrupt */ |
||
| 2999 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 3000 | } |
||
| 3001 | return HAL_OK; |
||
| 3002 | } |
||
| 3003 | else |
||
| 3004 | { |
||
| 3005 | return HAL_BUSY; |
||
| 3006 | } |
||
| 3007 | } |
||
| 3008 | |||
| 3009 | /** |
||
| 3010 | * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address |
||
| 3011 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3012 | * the configuration information for the specified I2C. |
||
| 3013 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 3014 | * in datasheet must be shifted to the left before calling the interface |
||
| 3015 | * @param MemAddress Internal memory address |
||
| 3016 | * @param MemAddSize Size of internal memory address |
||
| 3017 | * @param pData Pointer to data buffer |
||
| 3018 | * @param Size Amount of data to be sent |
||
| 3019 | * @retval HAL status |
||
| 3020 | */ |
||
| 3021 | HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
| 3022 | { |
||
| 3023 | __IO uint32_t count = 0U; |
||
| 3024 | |||
| 3025 | uint32_t tickstart = 0x00U; |
||
| 3026 | |||
| 3027 | /* Init tickstart for timeout management*/ |
||
| 3028 | tickstart = HAL_GetTick(); |
||
| 3029 | |||
| 3030 | /* Check the parameters */ |
||
| 3031 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
| 3032 | |||
| 3033 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 3034 | { |
||
| 3035 | /* Wait until BUSY flag is reset */ |
||
| 3036 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 3037 | do |
||
| 3038 | { |
||
| 3039 | if(count-- == 0U) |
||
| 3040 | { |
||
| 3041 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 3042 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 3043 | |||
| 3044 | /* Process Unlocked */ |
||
| 3045 | __HAL_UNLOCK(hi2c); |
||
| 3046 | |||
| 3047 | return HAL_TIMEOUT; |
||
| 3048 | } |
||
| 3049 | } |
||
| 3050 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 3051 | |||
| 3052 | /* Process Locked */ |
||
| 3053 | __HAL_LOCK(hi2c); |
||
| 3054 | |||
| 3055 | /* Check if the I2C is already enabled */ |
||
| 3056 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 3057 | { |
||
| 3058 | /* Enable I2C peripheral */ |
||
| 3059 | __HAL_I2C_ENABLE(hi2c); |
||
| 3060 | } |
||
| 3061 | |||
| 3062 | /* Disable Pos */ |
||
| 3063 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 3064 | |||
| 3065 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
| 3066 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
| 3067 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 3068 | |||
| 3069 | /* Prepare transfer parameters */ |
||
| 3070 | hi2c->pBuffPtr = pData; |
||
| 3071 | hi2c->XferSize = Size; |
||
| 3072 | hi2c->XferCount = Size; |
||
| 3073 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 3074 | |||
| 3075 | if(hi2c->XferSize > 0U) |
||
| 3076 | { |
||
| 3077 | /* Set the I2C DMA transfer complete callback */ |
||
| 3078 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
| 3079 | |||
| 3080 | /* Set the DMA error callback */ |
||
| 3081 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
| 3082 | |||
| 3083 | /* Set the unused DMA callbacks to NULL */ |
||
| 3084 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
| 3085 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
| 3086 | |||
| 3087 | /* Enable the DMA channel */ |
||
| 3088 | HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
| 3089 | |||
| 3090 | /* Send Slave Address and Memory Address */ |
||
| 3091 | if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
||
| 3092 | { |
||
| 3093 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 3094 | { |
||
| 3095 | /* Process Unlocked */ |
||
| 3096 | __HAL_UNLOCK(hi2c); |
||
| 3097 | return HAL_ERROR; |
||
| 3098 | } |
||
| 3099 | else |
||
| 3100 | { |
||
| 3101 | /* Process Unlocked */ |
||
| 3102 | __HAL_UNLOCK(hi2c); |
||
| 3103 | return HAL_TIMEOUT; |
||
| 3104 | } |
||
| 3105 | } |
||
| 3106 | |||
| 3107 | /* Clear ADDR flag */ |
||
| 3108 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 3109 | |||
| 3110 | /* Process Unlocked */ |
||
| 3111 | __HAL_UNLOCK(hi2c); |
||
| 3112 | |||
| 3113 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 3114 | to avoid the risk of I2C interrupt handle execution before current |
||
| 3115 | process unlock */ |
||
| 3116 | /* Enable ERR interrupt */ |
||
| 3117 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
||
| 3118 | |||
| 3119 | /* Enable DMA Request */ |
||
| 3120 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
| 3121 | } |
||
| 3122 | return HAL_OK; |
||
| 3123 | } |
||
| 3124 | else |
||
| 3125 | { |
||
| 3126 | return HAL_BUSY; |
||
| 3127 | } |
||
| 3128 | } |
||
| 3129 | |||
| 3130 | /** |
||
| 3131 | * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. |
||
| 3132 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3133 | * the configuration information for the specified I2C. |
||
| 3134 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 3135 | * in datasheet must be shifted to the left before calling the interface |
||
| 3136 | * @param MemAddress Internal memory address |
||
| 3137 | * @param MemAddSize Size of internal memory address |
||
| 3138 | * @param pData Pointer to data buffer |
||
| 3139 | * @param Size Amount of data to be read |
||
| 3140 | * @retval HAL status |
||
| 3141 | */ |
||
| 3142 | HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
| 3143 | { |
||
| 3144 | uint32_t tickstart = 0x00U; |
||
| 3145 | __IO uint32_t count = 0U; |
||
| 3146 | |||
| 3147 | /* Init tickstart for timeout management*/ |
||
| 3148 | tickstart = HAL_GetTick(); |
||
| 3149 | |||
| 3150 | /* Check the parameters */ |
||
| 3151 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
| 3152 | |||
| 3153 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 3154 | { |
||
| 3155 | /* Wait until BUSY flag is reset */ |
||
| 3156 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); |
||
| 3157 | do |
||
| 3158 | { |
||
| 3159 | if(count-- == 0U) |
||
| 3160 | { |
||
| 3161 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 3162 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 3163 | |||
| 3164 | /* Process Unlocked */ |
||
| 3165 | __HAL_UNLOCK(hi2c); |
||
| 3166 | |||
| 3167 | return HAL_TIMEOUT; |
||
| 3168 | } |
||
| 3169 | } |
||
| 3170 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
| 3171 | |||
| 3172 | /* Process Locked */ |
||
| 3173 | __HAL_LOCK(hi2c); |
||
| 3174 | |||
| 3175 | /* Check if the I2C is already enabled */ |
||
| 3176 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 3177 | { |
||
| 3178 | /* Enable I2C peripheral */ |
||
| 3179 | __HAL_I2C_ENABLE(hi2c); |
||
| 3180 | } |
||
| 3181 | |||
| 3182 | /* Disable Pos */ |
||
| 3183 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 3184 | |||
| 3185 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
| 3186 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
| 3187 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 3188 | |||
| 3189 | /* Prepare transfer parameters */ |
||
| 3190 | hi2c->pBuffPtr = pData; |
||
| 3191 | hi2c->XferCount = Size; |
||
| 3192 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 3193 | hi2c->XferSize = hi2c->XferCount; |
||
| 3194 | |||
| 3195 | if(hi2c->XferSize > 0U) |
||
| 3196 | { |
||
| 3197 | /* Set the I2C DMA transfer complete callback */ |
||
| 3198 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
| 3199 | |||
| 3200 | /* Set the DMA error callback */ |
||
| 3201 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
| 3202 | |||
| 3203 | /* Set the unused DMA callbacks to NULL */ |
||
| 3204 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
| 3205 | |||
| 3206 | /* Enable the DMA channel */ |
||
| 3207 | HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
| 3208 | |||
| 3209 | /* Send Slave Address and Memory Address */ |
||
| 3210 | if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
||
| 3211 | { |
||
| 3212 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 3213 | { |
||
| 3214 | /* Process Unlocked */ |
||
| 3215 | __HAL_UNLOCK(hi2c); |
||
| 3216 | return HAL_ERROR; |
||
| 3217 | } |
||
| 3218 | else |
||
| 3219 | { |
||
| 3220 | /* Process Unlocked */ |
||
| 3221 | __HAL_UNLOCK(hi2c); |
||
| 3222 | return HAL_TIMEOUT; |
||
| 3223 | } |
||
| 3224 | } |
||
| 3225 | |||
| 3226 | if(Size == 1U) |
||
| 3227 | { |
||
| 3228 | /* Disable Acknowledge */ |
||
| 3229 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 3230 | } |
||
| 3231 | else |
||
| 3232 | { |
||
| 3233 | /* Enable Last DMA bit */ |
||
| 3234 | hi2c->Instance->CR2 |= I2C_CR2_LAST; |
||
| 3235 | } |
||
| 3236 | |||
| 3237 | /* Clear ADDR flag */ |
||
| 3238 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 3239 | |||
| 3240 | /* Process Unlocked */ |
||
| 3241 | __HAL_UNLOCK(hi2c); |
||
| 3242 | |||
| 3243 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
| 3244 | to avoid the risk of I2C interrupt handle execution before current |
||
| 3245 | process unlock */ |
||
| 3246 | /* Enable ERR interrupt */ |
||
| 3247 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
||
| 3248 | |||
| 3249 | /* Enable DMA Request */ |
||
| 3250 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
| 3251 | } |
||
| 3252 | else |
||
| 3253 | { |
||
| 3254 | /* Send Slave Address and Memory Address */ |
||
| 3255 | if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
||
| 3256 | { |
||
| 3257 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 3258 | { |
||
| 3259 | /* Process Unlocked */ |
||
| 3260 | __HAL_UNLOCK(hi2c); |
||
| 3261 | return HAL_ERROR; |
||
| 3262 | } |
||
| 3263 | else |
||
| 3264 | { |
||
| 3265 | /* Process Unlocked */ |
||
| 3266 | __HAL_UNLOCK(hi2c); |
||
| 3267 | return HAL_TIMEOUT; |
||
| 3268 | } |
||
| 3269 | } |
||
| 3270 | |||
| 3271 | /* Clear ADDR flag */ |
||
| 3272 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 3273 | |||
| 3274 | /* Generate Stop */ |
||
| 3275 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 3276 | |||
| 3277 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 3278 | |||
| 3279 | /* Process Unlocked */ |
||
| 3280 | __HAL_UNLOCK(hi2c); |
||
| 3281 | } |
||
| 3282 | |||
| 3283 | return HAL_OK; |
||
| 3284 | } |
||
| 3285 | else |
||
| 3286 | { |
||
| 3287 | return HAL_BUSY; |
||
| 3288 | } |
||
| 3289 | } |
||
| 3290 | |||
| 3291 | /** |
||
| 3292 | * @brief Checks if target device is ready for communication. |
||
| 3293 | * @note This function is used with Memory devices |
||
| 3294 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3295 | * the configuration information for the specified I2C. |
||
| 3296 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 3297 | * in datasheet must be shifted to the left before calling the interface |
||
| 3298 | * @param Trials Number of trials |
||
| 3299 | * @param Timeout Timeout duration |
||
| 3300 | * @retval HAL status |
||
| 3301 | */ |
||
| 3302 | HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) |
||
| 3303 | { |
||
| 3304 | uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U; |
||
| 3305 | |||
| 3306 | /* Get tick */ |
||
| 3307 | tickstart = HAL_GetTick(); |
||
| 3308 | |||
| 3309 | if(hi2c->State == HAL_I2C_STATE_READY) |
||
| 3310 | { |
||
| 3311 | /* Wait until BUSY flag is reset */ |
||
| 3312 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
| 3313 | { |
||
| 3314 | return HAL_BUSY; |
||
| 3315 | } |
||
| 3316 | |||
| 3317 | /* Process Locked */ |
||
| 3318 | __HAL_LOCK(hi2c); |
||
| 3319 | |||
| 3320 | /* Check if the I2C is already enabled */ |
||
| 3321 | if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
| 3322 | { |
||
| 3323 | /* Enable I2C peripheral */ |
||
| 3324 | __HAL_I2C_ENABLE(hi2c); |
||
| 3325 | } |
||
| 3326 | |||
| 3327 | /* Disable Pos */ |
||
| 3328 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 3329 | |||
| 3330 | hi2c->State = HAL_I2C_STATE_BUSY; |
||
| 3331 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 3332 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 3333 | |||
| 3334 | do |
||
| 3335 | { |
||
| 3336 | /* Generate Start */ |
||
| 3337 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 3338 | |||
| 3339 | /* Wait until SB flag is set */ |
||
| 3340 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) |
||
| 3341 | { |
||
| 3342 | return HAL_TIMEOUT; |
||
| 3343 | } |
||
| 3344 | |||
| 3345 | /* Send slave address */ |
||
| 3346 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
| 3347 | |||
| 3348 | /* Wait until ADDR or AF flag are set */ |
||
| 3349 | /* Get tick */ |
||
| 3350 | tickstart = HAL_GetTick(); |
||
| 3351 | |||
| 3352 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
||
| 3353 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
||
| 3354 | tmp3 = hi2c->State; |
||
| 3355 | while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) |
||
| 3356 | { |
||
| 3357 | if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
||
| 3358 | { |
||
| 3359 | hi2c->State = HAL_I2C_STATE_TIMEOUT; |
||
| 3360 | } |
||
| 3361 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
||
| 3362 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
||
| 3363 | tmp3 = hi2c->State; |
||
| 3364 | } |
||
| 3365 | |||
| 3366 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 3367 | |||
| 3368 | /* Check if the ADDR flag has been set */ |
||
| 3369 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) |
||
| 3370 | { |
||
| 3371 | /* Generate Stop */ |
||
| 3372 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 3373 | |||
| 3374 | /* Clear ADDR Flag */ |
||
| 3375 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 3376 | |||
| 3377 | /* Wait until BUSY flag is reset */ |
||
| 3378 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
| 3379 | { |
||
| 3380 | return HAL_TIMEOUT; |
||
| 3381 | } |
||
| 3382 | |||
| 3383 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 3384 | |||
| 3385 | /* Process Unlocked */ |
||
| 3386 | __HAL_UNLOCK(hi2c); |
||
| 3387 | |||
| 3388 | return HAL_OK; |
||
| 3389 | } |
||
| 3390 | else |
||
| 3391 | { |
||
| 3392 | /* Generate Stop */ |
||
| 3393 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 3394 | |||
| 3395 | /* Clear AF Flag */ |
||
| 3396 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
| 3397 | |||
| 3398 | /* Wait until BUSY flag is reset */ |
||
| 3399 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
| 3400 | { |
||
| 3401 | return HAL_TIMEOUT; |
||
| 3402 | } |
||
| 3403 | } |
||
| 3404 | }while(I2C_Trials++ < Trials); |
||
| 3405 | |||
| 3406 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 3407 | |||
| 3408 | /* Process Unlocked */ |
||
| 3409 | __HAL_UNLOCK(hi2c); |
||
| 3410 | |||
| 3411 | return HAL_ERROR; |
||
| 3412 | } |
||
| 3413 | else |
||
| 3414 | { |
||
| 3415 | return HAL_BUSY; |
||
| 3416 | } |
||
| 3417 | } |
||
| 3418 | |||
| 3419 | /** |
||
| 3420 | * @brief This function handles I2C event interrupt request. |
||
| 3421 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3422 | * the configuration information for the specified I2C. |
||
| 3423 | * @retval None |
||
| 3424 | */ |
||
| 3425 | void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) |
||
| 3426 | { |
||
| 3427 | uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2); |
||
| 3428 | uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
| 3429 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
||
| 3430 | |||
| 3431 | uint32_t CurrentMode = hi2c->Mode; |
||
| 3432 | |||
| 3433 | /* Master or Memory mode selected */ |
||
| 3434 | if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) |
||
| 3435 | { |
||
| 3436 | /* SB Set ----------------------------------------------------------------*/ |
||
| 3437 | if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) |
||
| 3438 | { |
||
| 3439 | I2C_Master_SB(hi2c); |
||
| 3440 | } |
||
| 3441 | /* ADD10 Set -------------------------------------------------------------*/ |
||
| 3442 | else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) |
||
| 3443 | { |
||
| 3444 | I2C_Master_ADD10(hi2c); |
||
| 3445 | } |
||
| 3446 | /* ADDR Set --------------------------------------------------------------*/ |
||
| 3447 | else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) |
||
| 3448 | { |
||
| 3449 | I2C_Master_ADDR(hi2c); |
||
| 3450 | } |
||
| 3451 | |||
| 3452 | /* I2C in mode Transmitter -----------------------------------------------*/ |
||
| 3453 | if((sr2itflags & I2C_FLAG_TRA) != RESET) |
||
| 3454 | { |
||
| 3455 | /* TXE set and BTF reset -----------------------------------------------*/ |
||
| 3456 | if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) |
||
| 3457 | { |
||
| 3458 | I2C_MasterTransmit_TXE(hi2c); |
||
| 3459 | } |
||
| 3460 | /* BTF set -------------------------------------------------------------*/ |
||
| 3461 | else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) |
||
| 3462 | { |
||
| 3463 | I2C_MasterTransmit_BTF(hi2c); |
||
| 3464 | } |
||
| 3465 | } |
||
| 3466 | /* I2C in mode Receiver --------------------------------------------------*/ |
||
| 3467 | else |
||
| 3468 | { |
||
| 3469 | /* RXNE set and BTF reset -----------------------------------------------*/ |
||
| 3470 | if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) |
||
| 3471 | { |
||
| 3472 | I2C_MasterReceive_RXNE(hi2c); |
||
| 3473 | } |
||
| 3474 | /* BTF set -------------------------------------------------------------*/ |
||
| 3475 | else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) |
||
| 3476 | { |
||
| 3477 | I2C_MasterReceive_BTF(hi2c); |
||
| 3478 | } |
||
| 3479 | } |
||
| 3480 | } |
||
| 3481 | /* Slave mode selected */ |
||
| 3482 | else |
||
| 3483 | { |
||
| 3484 | /* ADDR set --------------------------------------------------------------*/ |
||
| 3485 | if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) |
||
| 3486 | { |
||
| 3487 | I2C_Slave_ADDR(hi2c); |
||
| 3488 | } |
||
| 3489 | /* STOPF set --------------------------------------------------------------*/ |
||
| 3490 | else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) |
||
| 3491 | { |
||
| 3492 | I2C_Slave_STOPF(hi2c); |
||
| 3493 | } |
||
| 3494 | /* I2C in mode Transmitter -----------------------------------------------*/ |
||
| 3495 | else if((sr2itflags & I2C_FLAG_TRA) != RESET) |
||
| 3496 | { |
||
| 3497 | /* TXE set and BTF reset -----------------------------------------------*/ |
||
| 3498 | if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) |
||
| 3499 | { |
||
| 3500 | I2C_SlaveTransmit_TXE(hi2c); |
||
| 3501 | } |
||
| 3502 | /* BTF set -------------------------------------------------------------*/ |
||
| 3503 | else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) |
||
| 3504 | { |
||
| 3505 | I2C_SlaveTransmit_BTF(hi2c); |
||
| 3506 | } |
||
| 3507 | } |
||
| 3508 | /* I2C in mode Receiver --------------------------------------------------*/ |
||
| 3509 | else |
||
| 3510 | { |
||
| 3511 | /* RXNE set and BTF reset ----------------------------------------------*/ |
||
| 3512 | if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) |
||
| 3513 | { |
||
| 3514 | I2C_SlaveReceive_RXNE(hi2c); |
||
| 3515 | } |
||
| 3516 | /* BTF set -------------------------------------------------------------*/ |
||
| 3517 | else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) |
||
| 3518 | { |
||
| 3519 | I2C_SlaveReceive_BTF(hi2c); |
||
| 3520 | } |
||
| 3521 | } |
||
| 3522 | } |
||
| 3523 | } |
||
| 3524 | |||
| 3525 | /** |
||
| 3526 | * @brief This function handles I2C error interrupt request. |
||
| 3527 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3528 | * the configuration information for the specified I2C. |
||
| 3529 | * @retval None |
||
| 3530 | */ |
||
| 3531 | void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) |
||
| 3532 | { |
||
| 3533 | uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U; |
||
| 3534 | uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
| 3535 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
||
| 3536 | |||
| 3537 | /* I2C Bus error interrupt occurred ----------------------------------------*/ |
||
| 3538 | if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) |
||
| 3539 | { |
||
| 3540 | hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; |
||
| 3541 | |||
| 3542 | /* Clear BERR flag */ |
||
| 3543 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); |
||
| 3544 | |||
| 3545 | /* Workaround: Start cannot be generated after a misplaced Stop */ |
||
| 3546 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST); |
||
| 3547 | } |
||
| 3548 | |||
| 3549 | /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ |
||
| 3550 | if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) |
||
| 3551 | { |
||
| 3552 | hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; |
||
| 3553 | |||
| 3554 | /* Clear ARLO flag */ |
||
| 3555 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); |
||
| 3556 | } |
||
| 3557 | |||
| 3558 | /* I2C Acknowledge failure error interrupt occurred ------------------------*/ |
||
| 3559 | if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) |
||
| 3560 | { |
||
| 3561 | tmp1 = hi2c->Mode; |
||
| 3562 | tmp2 = hi2c->XferCount; |
||
| 3563 | tmp3 = hi2c->State; |
||
| 3564 | tmp4 = hi2c->PreviousState; |
||
| 3565 | if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ |
||
| 3566 | ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ |
||
| 3567 | ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) |
||
| 3568 | { |
||
| 3569 | I2C_Slave_AF(hi2c); |
||
| 3570 | } |
||
| 3571 | else |
||
| 3572 | { |
||
| 3573 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
| 3574 | |||
| 3575 | /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ |
||
| 3576 | if(hi2c->Mode == HAL_I2C_MODE_MASTER) |
||
| 3577 | { |
||
| 3578 | /* Generate Stop */ |
||
| 3579 | SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); |
||
| 3580 | } |
||
| 3581 | |||
| 3582 | /* Clear AF flag */ |
||
| 3583 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
| 3584 | } |
||
| 3585 | } |
||
| 3586 | |||
| 3587 | /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ |
||
| 3588 | if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) |
||
| 3589 | { |
||
| 3590 | hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; |
||
| 3591 | /* Clear OVR flag */ |
||
| 3592 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); |
||
| 3593 | } |
||
| 3594 | |||
| 3595 | /* Call the Error Callback in case of Error detected -----------------------*/ |
||
| 3596 | if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
| 3597 | { |
||
| 3598 | I2C_ITError(hi2c); |
||
| 3599 | } |
||
| 3600 | } |
||
| 3601 | |||
| 3602 | /** |
||
| 3603 | * @brief Master Tx Transfer completed callback. |
||
| 3604 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3605 | * the configuration information for the specified I2C. |
||
| 3606 | * @retval None |
||
| 3607 | */ |
||
| 3608 | __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
| 3609 | { |
||
| 3610 | /* Prevent unused argument(s) compilation warning */ |
||
| 3611 | UNUSED(hi2c); |
||
| 3612 | |||
| 3613 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3614 | the HAL_I2C_MasterTxCpltCallback can be implemented in the user file |
||
| 3615 | */ |
||
| 3616 | } |
||
| 3617 | |||
| 3618 | /** |
||
| 3619 | * @brief Master Rx Transfer completed callback. |
||
| 3620 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3621 | * the configuration information for the specified I2C. |
||
| 3622 | * @retval None |
||
| 3623 | */ |
||
| 3624 | __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
| 3625 | { |
||
| 3626 | /* Prevent unused argument(s) compilation warning */ |
||
| 3627 | UNUSED(hi2c); |
||
| 3628 | |||
| 3629 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3630 | the HAL_I2C_MasterRxCpltCallback can be implemented in the user file |
||
| 3631 | */ |
||
| 3632 | } |
||
| 3633 | |||
| 3634 | /** @brief Slave Tx Transfer completed callback. |
||
| 3635 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3636 | * the configuration information for the specified I2C. |
||
| 3637 | * @retval None |
||
| 3638 | */ |
||
| 3639 | __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
| 3640 | { |
||
| 3641 | /* Prevent unused argument(s) compilation warning */ |
||
| 3642 | UNUSED(hi2c); |
||
| 3643 | |||
| 3644 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3645 | the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file |
||
| 3646 | */ |
||
| 3647 | } |
||
| 3648 | |||
| 3649 | /** |
||
| 3650 | * @brief Slave Rx Transfer completed callback. |
||
| 3651 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3652 | * the configuration information for the specified I2C. |
||
| 3653 | * @retval None |
||
| 3654 | */ |
||
| 3655 | __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
| 3656 | { |
||
| 3657 | /* Prevent unused argument(s) compilation warning */ |
||
| 3658 | UNUSED(hi2c); |
||
| 3659 | |||
| 3660 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3661 | the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file |
||
| 3662 | */ |
||
| 3663 | } |
||
| 3664 | |||
| 3665 | /** |
||
| 3666 | * @brief Slave Address Match callback. |
||
| 3667 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3668 | * the configuration information for the specified I2C. |
||
| 3669 | * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition |
||
| 3670 | * @param AddrMatchCode Address Match Code |
||
| 3671 | * @retval None |
||
| 3672 | */ |
||
| 3673 | __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) |
||
| 3674 | { |
||
| 3675 | /* Prevent unused argument(s) compilation warning */ |
||
| 3676 | UNUSED(hi2c); |
||
| 3677 | UNUSED(TransferDirection); |
||
| 3678 | UNUSED(AddrMatchCode); |
||
| 3679 | |||
| 3680 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3681 | the HAL_I2C_AddrCallback can be implemented in the user file |
||
| 3682 | */ |
||
| 3683 | } |
||
| 3684 | |||
| 3685 | /** |
||
| 3686 | * @brief Listen Complete callback. |
||
| 3687 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3688 | * the configuration information for the specified I2C. |
||
| 3689 | * @retval None |
||
| 3690 | */ |
||
| 3691 | __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) |
||
| 3692 | { |
||
| 3693 | /* Prevent unused argument(s) compilation warning */ |
||
| 3694 | UNUSED(hi2c); |
||
| 3695 | |||
| 3696 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3697 | the HAL_I2C_ListenCpltCallback can be implemented in the user file |
||
| 3698 | */ |
||
| 3699 | } |
||
| 3700 | |||
| 3701 | /** |
||
| 3702 | * @brief Memory Tx Transfer completed callback. |
||
| 3703 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3704 | * the configuration information for the specified I2C. |
||
| 3705 | * @retval None |
||
| 3706 | */ |
||
| 3707 | __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
| 3708 | { |
||
| 3709 | /* Prevent unused argument(s) compilation warning */ |
||
| 3710 | UNUSED(hi2c); |
||
| 3711 | |||
| 3712 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3713 | the HAL_I2C_MemTxCpltCallback can be implemented in the user file |
||
| 3714 | */ |
||
| 3715 | } |
||
| 3716 | |||
| 3717 | /** |
||
| 3718 | * @brief Memory Rx Transfer completed callback. |
||
| 3719 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3720 | * the configuration information for the specified I2C. |
||
| 3721 | * @retval None |
||
| 3722 | */ |
||
| 3723 | __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
| 3724 | { |
||
| 3725 | /* Prevent unused argument(s) compilation warning */ |
||
| 3726 | UNUSED(hi2c); |
||
| 3727 | |||
| 3728 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3729 | the HAL_I2C_MemRxCpltCallback can be implemented in the user file |
||
| 3730 | */ |
||
| 3731 | } |
||
| 3732 | |||
| 3733 | /** |
||
| 3734 | * @brief I2C error callback. |
||
| 3735 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3736 | * the configuration information for the specified I2C. |
||
| 3737 | * @retval None |
||
| 3738 | */ |
||
| 3739 | __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) |
||
| 3740 | { |
||
| 3741 | /* Prevent unused argument(s) compilation warning */ |
||
| 3742 | UNUSED(hi2c); |
||
| 3743 | |||
| 3744 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3745 | the HAL_I2C_ErrorCallback can be implemented in the user file |
||
| 3746 | */ |
||
| 3747 | } |
||
| 3748 | |||
| 3749 | /** |
||
| 3750 | * @brief I2C abort callback. |
||
| 3751 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3752 | * the configuration information for the specified I2C. |
||
| 3753 | * @retval None |
||
| 3754 | */ |
||
| 3755 | __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) |
||
| 3756 | { |
||
| 3757 | /* Prevent unused argument(s) compilation warning */ |
||
| 3758 | UNUSED(hi2c); |
||
| 3759 | |||
| 3760 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 3761 | the HAL_I2C_AbortCpltCallback could be implemented in the user file |
||
| 3762 | */ |
||
| 3763 | } |
||
| 3764 | |||
| 3765 | /** |
||
| 3766 | * @} |
||
| 3767 | */ |
||
| 3768 | |||
| 3769 | /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions |
||
| 3770 | * @brief Peripheral State and Errors functions |
||
| 3771 | * |
||
| 3772 | @verbatim |
||
| 3773 | =============================================================================== |
||
| 3774 | ##### Peripheral State, Mode and Error functions ##### |
||
| 3775 | =============================================================================== |
||
| 3776 | [..] |
||
| 3777 | This subsection permits to get in run-time the status of the peripheral |
||
| 3778 | and the data flow. |
||
| 3779 | |||
| 3780 | @endverbatim |
||
| 3781 | * @{ |
||
| 3782 | */ |
||
| 3783 | |||
| 3784 | /** |
||
| 3785 | * @brief Return the I2C handle state. |
||
| 3786 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3787 | * the configuration information for the specified I2C. |
||
| 3788 | * @retval HAL state |
||
| 3789 | */ |
||
| 3790 | HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) |
||
| 3791 | { |
||
| 3792 | /* Return I2C handle state */ |
||
| 3793 | return hi2c->State; |
||
| 3794 | } |
||
| 3795 | |||
| 3796 | /** |
||
| 3797 | * @brief Return the I2C Master, Slave, Memory or no mode. |
||
| 3798 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3799 | * the configuration information for I2C module |
||
| 3800 | * @retval HAL mode |
||
| 3801 | */ |
||
| 3802 | HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) |
||
| 3803 | { |
||
| 3804 | return hi2c->Mode; |
||
| 3805 | } |
||
| 3806 | |||
| 3807 | /** |
||
| 3808 | * @brief Return the I2C error code |
||
| 3809 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3810 | * the configuration information for the specified I2C. |
||
| 3811 | * @retval I2C Error Code |
||
| 3812 | */ |
||
| 3813 | uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) |
||
| 3814 | { |
||
| 3815 | return hi2c->ErrorCode; |
||
| 3816 | } |
||
| 3817 | |||
| 3818 | /** |
||
| 3819 | * @} |
||
| 3820 | */ |
||
| 3821 | |||
| 3822 | /** |
||
| 3823 | * @brief Handle TXE flag for Master |
||
| 3824 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3825 | * the configuration information for I2C module |
||
| 3826 | * @retval HAL status |
||
| 3827 | */ |
||
| 3828 | static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) |
||
| 3829 | { |
||
| 3830 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
| 3831 | uint32_t CurrentState = hi2c->State; |
||
| 3832 | uint32_t CurrentMode = hi2c->Mode; |
||
| 3833 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
| 3834 | |||
| 3835 | if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
||
| 3836 | { |
||
| 3837 | /* Call TxCpltCallback() directly if no stop mode is set */ |
||
| 3838 | if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
||
| 3839 | { |
||
| 3840 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 3841 | |||
| 3842 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
||
| 3843 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 3844 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 3845 | |||
| 3846 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
| 3847 | } |
||
| 3848 | else /* Generate Stop condition then Call TxCpltCallback() */ |
||
| 3849 | { |
||
| 3850 | /* Disable EVT, BUF and ERR interrupt */ |
||
| 3851 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 3852 | |||
| 3853 | /* Generate Stop */ |
||
| 3854 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 3855 | |||
| 3856 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 3857 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 3858 | |||
| 3859 | if(hi2c->Mode == HAL_I2C_MODE_MEM) |
||
| 3860 | { |
||
| 3861 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 3862 | HAL_I2C_MemTxCpltCallback(hi2c); |
||
| 3863 | } |
||
| 3864 | else |
||
| 3865 | { |
||
| 3866 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 3867 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
| 3868 | } |
||
| 3869 | } |
||
| 3870 | } |
||
| 3871 | else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ |
||
| 3872 | ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) |
||
| 3873 | { |
||
| 3874 | if(hi2c->XferCount == 0U) |
||
| 3875 | { |
||
| 3876 | /* Disable BUF interrupt */ |
||
| 3877 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
| 3878 | } |
||
| 3879 | else |
||
| 3880 | { |
||
| 3881 | if(hi2c->Mode == HAL_I2C_MODE_MEM) |
||
| 3882 | { |
||
| 3883 | if(hi2c->EventCount == 0) |
||
| 3884 | { |
||
| 3885 | /* If Memory address size is 8Bit */ |
||
| 3886 | if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) |
||
| 3887 | { |
||
| 3888 | /* Send Memory Address */ |
||
| 3889 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
||
| 3890 | |||
| 3891 | hi2c->EventCount += 2; |
||
| 3892 | } |
||
| 3893 | /* If Memory address size is 16Bit */ |
||
| 3894 | else |
||
| 3895 | { |
||
| 3896 | /* Send MSB of Memory Address */ |
||
| 3897 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); |
||
| 3898 | |||
| 3899 | hi2c->EventCount++; |
||
| 3900 | } |
||
| 3901 | } |
||
| 3902 | else if(hi2c->EventCount == 1) |
||
| 3903 | { |
||
| 3904 | /* Send LSB of Memory Address */ |
||
| 3905 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
||
| 3906 | |||
| 3907 | hi2c->EventCount++; |
||
| 3908 | } |
||
| 3909 | else if(hi2c->EventCount == 2) |
||
| 3910 | { |
||
| 3911 | if(hi2c->State == HAL_I2C_STATE_BUSY_RX) |
||
| 3912 | { |
||
| 3913 | /* Generate Restart */ |
||
| 3914 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 3915 | } |
||
| 3916 | else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) |
||
| 3917 | { |
||
| 3918 | /* Write data to DR */ |
||
| 3919 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 3920 | hi2c->XferCount--; |
||
| 3921 | } |
||
| 3922 | } |
||
| 3923 | } |
||
| 3924 | else |
||
| 3925 | { |
||
| 3926 | /* Write data to DR */ |
||
| 3927 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 3928 | hi2c->XferCount--; |
||
| 3929 | } |
||
| 3930 | } |
||
| 3931 | } |
||
| 3932 | return HAL_OK; |
||
| 3933 | } |
||
| 3934 | |||
| 3935 | /** |
||
| 3936 | * @brief Handle BTF flag for Master transmitter |
||
| 3937 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3938 | * the configuration information for I2C module |
||
| 3939 | * @retval HAL status |
||
| 3940 | */ |
||
| 3941 | static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) |
||
| 3942 | { |
||
| 3943 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
| 3944 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
| 3945 | |||
| 3946 | if(hi2c->State == HAL_I2C_STATE_BUSY_TX) |
||
| 3947 | { |
||
| 3948 | if(hi2c->XferCount != 0U) |
||
| 3949 | { |
||
| 3950 | /* Write data to DR */ |
||
| 3951 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 3952 | hi2c->XferCount--; |
||
| 3953 | } |
||
| 3954 | else |
||
| 3955 | { |
||
| 3956 | /* Call TxCpltCallback() directly if no stop mode is set */ |
||
| 3957 | if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
||
| 3958 | { |
||
| 3959 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 3960 | |||
| 3961 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
||
| 3962 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 3963 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 3964 | |||
| 3965 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
| 3966 | } |
||
| 3967 | else /* Generate Stop condition then Call TxCpltCallback() */ |
||
| 3968 | { |
||
| 3969 | /* Disable EVT, BUF and ERR interrupt */ |
||
| 3970 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 3971 | |||
| 3972 | /* Generate Stop */ |
||
| 3973 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 3974 | |||
| 3975 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 3976 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 3977 | |||
| 3978 | if(hi2c->Mode == HAL_I2C_MODE_MEM) |
||
| 3979 | { |
||
| 3980 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 3981 | |||
| 3982 | HAL_I2C_MemTxCpltCallback(hi2c); |
||
| 3983 | } |
||
| 3984 | else |
||
| 3985 | { |
||
| 3986 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 3987 | |||
| 3988 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
| 3989 | } |
||
| 3990 | } |
||
| 3991 | } |
||
| 3992 | } |
||
| 3993 | return HAL_OK; |
||
| 3994 | } |
||
| 3995 | |||
| 3996 | /** |
||
| 3997 | * @brief Handle RXNE flag for Master |
||
| 3998 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 3999 | * the configuration information for I2C module |
||
| 4000 | * @retval HAL status |
||
| 4001 | */ |
||
| 4002 | static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) |
||
| 4003 | { |
||
| 4004 | if(hi2c->State == HAL_I2C_STATE_BUSY_RX) |
||
| 4005 | { |
||
| 4006 | uint32_t tmp = 0U; |
||
| 4007 | |||
| 4008 | tmp = hi2c->XferCount; |
||
| 4009 | if(tmp > 3U) |
||
| 4010 | { |
||
| 4011 | /* Read data from DR */ |
||
| 4012 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4013 | hi2c->XferCount--; |
||
| 4014 | } |
||
| 4015 | else if((tmp == 2U) || (tmp == 3U)) |
||
| 4016 | { |
||
| 4017 | if(hi2c->XferOptions != I2C_NEXT_FRAME) |
||
| 4018 | { |
||
| 4019 | /* Disable Acknowledge */ |
||
| 4020 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4021 | |||
| 4022 | /* Enable Pos */ |
||
| 4023 | hi2c->Instance->CR1 |= I2C_CR1_POS; |
||
| 4024 | } |
||
| 4025 | else |
||
| 4026 | { |
||
| 4027 | /* Enable Acknowledge */ |
||
| 4028 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 4029 | } |
||
| 4030 | |||
| 4031 | /* Disable BUF interrupt */ |
||
| 4032 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
| 4033 | } |
||
| 4034 | else |
||
| 4035 | { |
||
| 4036 | if(hi2c->XferOptions != I2C_NEXT_FRAME) |
||
| 4037 | { |
||
| 4038 | /* Disable Acknowledge */ |
||
| 4039 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4040 | } |
||
| 4041 | else |
||
| 4042 | { |
||
| 4043 | /* Enable Acknowledge */ |
||
| 4044 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 4045 | } |
||
| 4046 | |||
| 4047 | /* Disable EVT, BUF and ERR interrupt */ |
||
| 4048 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 4049 | |||
| 4050 | /* Read data from DR */ |
||
| 4051 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4052 | hi2c->XferCount--; |
||
| 4053 | |||
| 4054 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4055 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 4056 | |||
| 4057 | if(hi2c->Mode == HAL_I2C_MODE_MEM) |
||
| 4058 | { |
||
| 4059 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4060 | HAL_I2C_MemRxCpltCallback(hi2c); |
||
| 4061 | } |
||
| 4062 | else |
||
| 4063 | { |
||
| 4064 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4065 | HAL_I2C_MasterRxCpltCallback(hi2c); |
||
| 4066 | } |
||
| 4067 | } |
||
| 4068 | } |
||
| 4069 | return HAL_OK; |
||
| 4070 | } |
||
| 4071 | |||
| 4072 | /** |
||
| 4073 | * @brief Handle BTF flag for Master receiver |
||
| 4074 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4075 | * the configuration information for I2C module |
||
| 4076 | * @retval HAL status |
||
| 4077 | */ |
||
| 4078 | static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) |
||
| 4079 | { |
||
| 4080 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
| 4081 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
| 4082 | |||
| 4083 | if(hi2c->XferCount == 3U) |
||
| 4084 | { |
||
| 4085 | if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
||
| 4086 | { |
||
| 4087 | /* Disable Acknowledge */ |
||
| 4088 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4089 | } |
||
| 4090 | |||
| 4091 | /* Read data from DR */ |
||
| 4092 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4093 | hi2c->XferCount--; |
||
| 4094 | } |
||
| 4095 | else if(hi2c->XferCount == 2U) |
||
| 4096 | { |
||
| 4097 | /* Prepare next transfer or stop current transfer */ |
||
| 4098 | if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
||
| 4099 | { |
||
| 4100 | if(CurrentXferOptions != I2C_NEXT_FRAME) |
||
| 4101 | { |
||
| 4102 | /* Disable Acknowledge */ |
||
| 4103 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4104 | } |
||
| 4105 | else |
||
| 4106 | { |
||
| 4107 | /* Enable Acknowledge */ |
||
| 4108 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 4109 | } |
||
| 4110 | |||
| 4111 | /* Disable EVT and ERR interrupt */ |
||
| 4112 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
| 4113 | } |
||
| 4114 | else |
||
| 4115 | { |
||
| 4116 | /* Disable EVT and ERR interrupt */ |
||
| 4117 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
| 4118 | |||
| 4119 | /* Generate Stop */ |
||
| 4120 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 4121 | } |
||
| 4122 | |||
| 4123 | /* Read data from DR */ |
||
| 4124 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4125 | hi2c->XferCount--; |
||
| 4126 | |||
| 4127 | /* Read data from DR */ |
||
| 4128 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4129 | hi2c->XferCount--; |
||
| 4130 | |||
| 4131 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4132 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 4133 | |||
| 4134 | if(hi2c->Mode == HAL_I2C_MODE_MEM) |
||
| 4135 | { |
||
| 4136 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4137 | |||
| 4138 | HAL_I2C_MemRxCpltCallback(hi2c); |
||
| 4139 | } |
||
| 4140 | else |
||
| 4141 | { |
||
| 4142 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4143 | |||
| 4144 | HAL_I2C_MasterRxCpltCallback(hi2c); |
||
| 4145 | } |
||
| 4146 | } |
||
| 4147 | else |
||
| 4148 | { |
||
| 4149 | /* Read data from DR */ |
||
| 4150 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4151 | hi2c->XferCount--; |
||
| 4152 | } |
||
| 4153 | return HAL_OK; |
||
| 4154 | } |
||
| 4155 | |||
| 4156 | /** |
||
| 4157 | * @brief Handle SB flag for Master |
||
| 4158 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4159 | * the configuration information for I2C module |
||
| 4160 | * @retval HAL status |
||
| 4161 | */ |
||
| 4162 | static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) |
||
| 4163 | { |
||
| 4164 | if(hi2c->Mode == HAL_I2C_MODE_MEM) |
||
| 4165 | { |
||
| 4166 | if(hi2c->EventCount == 0U) |
||
| 4167 | { |
||
| 4168 | /* Send slave address */ |
||
| 4169 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
||
| 4170 | } |
||
| 4171 | else |
||
| 4172 | { |
||
| 4173 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
||
| 4174 | } |
||
| 4175 | } |
||
| 4176 | else |
||
| 4177 | { |
||
| 4178 | if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
||
| 4179 | { |
||
| 4180 | /* Send slave 7 Bits address */ |
||
| 4181 | if(hi2c->State == HAL_I2C_STATE_BUSY_TX) |
||
| 4182 | { |
||
| 4183 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
||
| 4184 | } |
||
| 4185 | else |
||
| 4186 | { |
||
| 4187 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
||
| 4188 | } |
||
| 4189 | } |
||
| 4190 | else |
||
| 4191 | { |
||
| 4192 | if(hi2c->EventCount == 0U) |
||
| 4193 | { |
||
| 4194 | /* Send header of slave address */ |
||
| 4195 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); |
||
| 4196 | } |
||
| 4197 | else if(hi2c->EventCount == 1U) |
||
| 4198 | { |
||
| 4199 | /* Send header of slave address */ |
||
| 4200 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); |
||
| 4201 | } |
||
| 4202 | } |
||
| 4203 | } |
||
| 4204 | |||
| 4205 | return HAL_OK; |
||
| 4206 | } |
||
| 4207 | |||
| 4208 | /** |
||
| 4209 | * @brief Handle ADD10 flag for Master |
||
| 4210 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4211 | * the configuration information for I2C module |
||
| 4212 | * @retval HAL status |
||
| 4213 | */ |
||
| 4214 | static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) |
||
| 4215 | { |
||
| 4216 | /* Send slave address */ |
||
| 4217 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); |
||
| 4218 | |||
| 4219 | return HAL_OK; |
||
| 4220 | } |
||
| 4221 | |||
| 4222 | /** |
||
| 4223 | * @brief Handle ADDR flag for Master |
||
| 4224 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4225 | * the configuration information for I2C module |
||
| 4226 | * @retval HAL status |
||
| 4227 | */ |
||
| 4228 | static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) |
||
| 4229 | { |
||
| 4230 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
| 4231 | uint32_t CurrentMode = hi2c->Mode; |
||
| 4232 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
| 4233 | uint32_t Prev_State = hi2c->PreviousState; |
||
| 4234 | |||
| 4235 | if(hi2c->State == HAL_I2C_STATE_BUSY_RX) |
||
| 4236 | { |
||
| 4237 | if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) |
||
| 4238 | { |
||
| 4239 | /* Clear ADDR flag */ |
||
| 4240 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4241 | } |
||
| 4242 | else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) |
||
| 4243 | { |
||
| 4244 | /* Clear ADDR flag */ |
||
| 4245 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4246 | |||
| 4247 | /* Generate Restart */ |
||
| 4248 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 4249 | |||
| 4250 | hi2c->EventCount++; |
||
| 4251 | } |
||
| 4252 | else |
||
| 4253 | { |
||
| 4254 | if(hi2c->XferCount == 0U) |
||
| 4255 | { |
||
| 4256 | /* Clear ADDR flag */ |
||
| 4257 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4258 | |||
| 4259 | /* Generate Stop */ |
||
| 4260 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 4261 | } |
||
| 4262 | else if(hi2c->XferCount == 1U) |
||
| 4263 | { |
||
| 4264 | if(CurrentXferOptions == I2C_NO_OPTION_FRAME) |
||
| 4265 | { |
||
| 4266 | /* Disable Acknowledge */ |
||
| 4267 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4268 | |||
| 4269 | if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
| 4270 | { |
||
| 4271 | /* Disable Acknowledge */ |
||
| 4272 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4273 | |||
| 4274 | /* Clear ADDR flag */ |
||
| 4275 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4276 | } |
||
| 4277 | else |
||
| 4278 | { |
||
| 4279 | /* Clear ADDR flag */ |
||
| 4280 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4281 | |||
| 4282 | /* Generate Stop */ |
||
| 4283 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 4284 | } |
||
| 4285 | } |
||
| 4286 | /* Prepare next transfer or stop current transfer */ |
||
| 4287 | else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ |
||
| 4288 | && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) |
||
| 4289 | { |
||
| 4290 | if(hi2c->XferOptions != I2C_NEXT_FRAME) |
||
| 4291 | { |
||
| 4292 | /* Disable Acknowledge */ |
||
| 4293 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4294 | } |
||
| 4295 | else |
||
| 4296 | { |
||
| 4297 | /* Enable Acknowledge */ |
||
| 4298 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 4299 | } |
||
| 4300 | |||
| 4301 | /* Clear ADDR flag */ |
||
| 4302 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4303 | } |
||
| 4304 | else |
||
| 4305 | { |
||
| 4306 | /* Disable Acknowledge */ |
||
| 4307 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4308 | |||
| 4309 | /* Clear ADDR flag */ |
||
| 4310 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4311 | |||
| 4312 | /* Generate Stop */ |
||
| 4313 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 4314 | } |
||
| 4315 | } |
||
| 4316 | else if(hi2c->XferCount == 2U) |
||
| 4317 | { |
||
| 4318 | if(hi2c->XferOptions != I2C_NEXT_FRAME) |
||
| 4319 | { |
||
| 4320 | /* Enable Pos */ |
||
| 4321 | hi2c->Instance->CR1 |= I2C_CR1_POS; |
||
| 4322 | |||
| 4323 | /* Clear ADDR flag */ |
||
| 4324 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4325 | |||
| 4326 | /* Disable Acknowledge */ |
||
| 4327 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4328 | } |
||
| 4329 | else |
||
| 4330 | { |
||
| 4331 | /* Enable Acknowledge */ |
||
| 4332 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 4333 | |||
| 4334 | /* Clear ADDR flag */ |
||
| 4335 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4336 | } |
||
| 4337 | |||
| 4338 | if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
| 4339 | { |
||
| 4340 | /* Enable Last DMA bit */ |
||
| 4341 | hi2c->Instance->CR2 |= I2C_CR2_LAST; |
||
| 4342 | } |
||
| 4343 | } |
||
| 4344 | else |
||
| 4345 | { |
||
| 4346 | /* Enable Acknowledge */ |
||
| 4347 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 4348 | |||
| 4349 | if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
| 4350 | { |
||
| 4351 | /* Enable Last DMA bit */ |
||
| 4352 | hi2c->Instance->CR2 |= I2C_CR2_LAST; |
||
| 4353 | } |
||
| 4354 | |||
| 4355 | /* Clear ADDR flag */ |
||
| 4356 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4357 | } |
||
| 4358 | |||
| 4359 | /* Reset Event counter */ |
||
| 4360 | hi2c->EventCount = 0U; |
||
| 4361 | } |
||
| 4362 | } |
||
| 4363 | else |
||
| 4364 | { |
||
| 4365 | /* Clear ADDR flag */ |
||
| 4366 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4367 | } |
||
| 4368 | |||
| 4369 | return HAL_OK; |
||
| 4370 | } |
||
| 4371 | |||
| 4372 | /** |
||
| 4373 | * @brief Handle TXE flag for Slave |
||
| 4374 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4375 | * the configuration information for I2C module |
||
| 4376 | * @retval HAL status |
||
| 4377 | */ |
||
| 4378 | static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) |
||
| 4379 | { |
||
| 4380 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
| 4381 | uint32_t CurrentState = hi2c->State; |
||
| 4382 | |||
| 4383 | if(hi2c->XferCount != 0U) |
||
| 4384 | { |
||
| 4385 | /* Write data to DR */ |
||
| 4386 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 4387 | hi2c->XferCount--; |
||
| 4388 | |||
| 4389 | if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
||
| 4390 | { |
||
| 4391 | /* Last Byte is received, disable Interrupt */ |
||
| 4392 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
| 4393 | |||
| 4394 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
| 4395 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
||
| 4396 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
| 4397 | |||
| 4398 | /* Call the Tx complete callback to inform upper layer of the end of receive process */ |
||
| 4399 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
||
| 4400 | } |
||
| 4401 | } |
||
| 4402 | return HAL_OK; |
||
| 4403 | } |
||
| 4404 | |||
| 4405 | /** |
||
| 4406 | * @brief Handle BTF flag for Slave transmitter |
||
| 4407 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4408 | * the configuration information for I2C module |
||
| 4409 | * @retval HAL status |
||
| 4410 | */ |
||
| 4411 | static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) |
||
| 4412 | { |
||
| 4413 | if(hi2c->XferCount != 0U) |
||
| 4414 | { |
||
| 4415 | /* Write data to DR */ |
||
| 4416 | hi2c->Instance->DR = (*hi2c->pBuffPtr++); |
||
| 4417 | hi2c->XferCount--; |
||
| 4418 | } |
||
| 4419 | return HAL_OK; |
||
| 4420 | } |
||
| 4421 | |||
| 4422 | /** |
||
| 4423 | * @brief Handle RXNE flag for Slave |
||
| 4424 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4425 | * the configuration information for I2C module |
||
| 4426 | * @retval HAL status |
||
| 4427 | */ |
||
| 4428 | static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) |
||
| 4429 | { |
||
| 4430 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
| 4431 | uint32_t CurrentState = hi2c->State; |
||
| 4432 | |||
| 4433 | if(hi2c->XferCount != 0U) |
||
| 4434 | { |
||
| 4435 | /* Read data from DR */ |
||
| 4436 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4437 | hi2c->XferCount--; |
||
| 4438 | |||
| 4439 | if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
||
| 4440 | { |
||
| 4441 | /* Last Byte is received, disable Interrupt */ |
||
| 4442 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
| 4443 | |||
| 4444 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
| 4445 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
||
| 4446 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
| 4447 | |||
| 4448 | /* Call the Rx complete callback to inform upper layer of the end of receive process */ |
||
| 4449 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
| 4450 | } |
||
| 4451 | } |
||
| 4452 | return HAL_OK; |
||
| 4453 | } |
||
| 4454 | |||
| 4455 | /** |
||
| 4456 | * @brief Handle BTF flag for Slave receiver |
||
| 4457 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4458 | * the configuration information for I2C module |
||
| 4459 | * @retval HAL status |
||
| 4460 | */ |
||
| 4461 | static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) |
||
| 4462 | { |
||
| 4463 | if(hi2c->XferCount != 0U) |
||
| 4464 | { |
||
| 4465 | /* Read data from DR */ |
||
| 4466 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4467 | hi2c->XferCount--; |
||
| 4468 | } |
||
| 4469 | return HAL_OK; |
||
| 4470 | } |
||
| 4471 | |||
| 4472 | /** |
||
| 4473 | * @brief Handle ADD flag for Slave |
||
| 4474 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4475 | * the configuration information for I2C module |
||
| 4476 | * @retval HAL status |
||
| 4477 | */ |
||
| 4478 | static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) |
||
| 4479 | { |
||
| 4480 | uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; |
||
| 4481 | uint16_t SlaveAddrCode = 0U; |
||
| 4482 | |||
| 4483 | /* Transfer Direction requested by Master */ |
||
| 4484 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET) |
||
| 4485 | { |
||
| 4486 | TransferDirection = I2C_DIRECTION_TRANSMIT; |
||
| 4487 | } |
||
| 4488 | |||
| 4489 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET) |
||
| 4490 | { |
||
| 4491 | SlaveAddrCode = hi2c->Init.OwnAddress1; |
||
| 4492 | } |
||
| 4493 | else |
||
| 4494 | { |
||
| 4495 | SlaveAddrCode = hi2c->Init.OwnAddress2; |
||
| 4496 | } |
||
| 4497 | |||
| 4498 | /* Call Slave Addr callback */ |
||
| 4499 | HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); |
||
| 4500 | |||
| 4501 | return HAL_OK; |
||
| 4502 | } |
||
| 4503 | |||
| 4504 | /** |
||
| 4505 | * @brief Handle STOPF flag for Slave |
||
| 4506 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4507 | * the configuration information for I2C module |
||
| 4508 | * @retval HAL status |
||
| 4509 | */ |
||
| 4510 | static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) |
||
| 4511 | { |
||
| 4512 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
| 4513 | uint32_t CurrentState = hi2c->State; |
||
| 4514 | |||
| 4515 | /* Disable EVT, BUF and ERR interrupt */ |
||
| 4516 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 4517 | |||
| 4518 | /* Clear STOPF flag */ |
||
| 4519 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
||
| 4520 | |||
| 4521 | /* Disable Acknowledge */ |
||
| 4522 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4523 | |||
| 4524 | /* If a DMA is ongoing, Update handle size context */ |
||
| 4525 | if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
| 4526 | { |
||
| 4527 | if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
||
| 4528 | { |
||
| 4529 | hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx); |
||
| 4530 | } |
||
| 4531 | else |
||
| 4532 | { |
||
| 4533 | hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx); |
||
| 4534 | } |
||
| 4535 | } |
||
| 4536 | |||
| 4537 | /* All data are not transferred, so set error code accordingly */ |
||
| 4538 | if(hi2c->XferCount != 0U) |
||
| 4539 | { |
||
| 4540 | /* Store Last receive data if any */ |
||
| 4541 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
||
| 4542 | { |
||
| 4543 | /* Read data from DR */ |
||
| 4544 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4545 | hi2c->XferCount--; |
||
| 4546 | } |
||
| 4547 | |||
| 4548 | /* Store Last receive data if any */ |
||
| 4549 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
| 4550 | { |
||
| 4551 | /* Read data from DR */ |
||
| 4552 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4553 | hi2c->XferCount--; |
||
| 4554 | } |
||
| 4555 | |||
| 4556 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
||
| 4557 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
| 4558 | } |
||
| 4559 | |||
| 4560 | if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
| 4561 | { |
||
| 4562 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
| 4563 | I2C_ITError(hi2c); |
||
| 4564 | } |
||
| 4565 | else |
||
| 4566 | { |
||
| 4567 | if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \ |
||
| 4568 | (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
||
| 4569 | { |
||
| 4570 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 4571 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 4572 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4573 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4574 | |||
| 4575 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
||
| 4576 | HAL_I2C_ListenCpltCallback(hi2c); |
||
| 4577 | } |
||
| 4578 | else |
||
| 4579 | { |
||
| 4580 | if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) |
||
| 4581 | { |
||
| 4582 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 4583 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4584 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4585 | |||
| 4586 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
| 4587 | } |
||
| 4588 | } |
||
| 4589 | } |
||
| 4590 | return HAL_OK; |
||
| 4591 | } |
||
| 4592 | |||
| 4593 | /** |
||
| 4594 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4595 | * the configuration information for I2C module |
||
| 4596 | * @retval HAL status |
||
| 4597 | */ |
||
| 4598 | static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) |
||
| 4599 | { |
||
| 4600 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
| 4601 | uint32_t CurrentState = hi2c->State; |
||
| 4602 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
| 4603 | |||
| 4604 | if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ |
||
| 4605 | (CurrentState == HAL_I2C_STATE_LISTEN)) |
||
| 4606 | { |
||
| 4607 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 4608 | |||
| 4609 | /* Disable EVT, BUF and ERR interrupt */ |
||
| 4610 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 4611 | |||
| 4612 | /* Clear AF flag */ |
||
| 4613 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
| 4614 | |||
| 4615 | /* Disable Acknowledge */ |
||
| 4616 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4617 | |||
| 4618 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 4619 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4620 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4621 | |||
| 4622 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
||
| 4623 | HAL_I2C_ListenCpltCallback(hi2c); |
||
| 4624 | } |
||
| 4625 | else if(CurrentState == HAL_I2C_STATE_BUSY_TX) |
||
| 4626 | { |
||
| 4627 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 4628 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
||
| 4629 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4630 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4631 | |||
| 4632 | /* Disable EVT, BUF and ERR interrupt */ |
||
| 4633 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
| 4634 | |||
| 4635 | /* Clear AF flag */ |
||
| 4636 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
| 4637 | |||
| 4638 | /* Disable Acknowledge */ |
||
| 4639 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 4640 | |||
| 4641 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
||
| 4642 | } |
||
| 4643 | else |
||
| 4644 | { |
||
| 4645 | /* Clear AF flag only */ |
||
| 4646 | /* State Listen, but XferOptions == FIRST or NEXT */ |
||
| 4647 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
| 4648 | } |
||
| 4649 | |||
| 4650 | return HAL_OK; |
||
| 4651 | } |
||
| 4652 | |||
| 4653 | /** |
||
| 4654 | * @brief I2C interrupts error process |
||
| 4655 | * @param hi2c I2C handle. |
||
| 4656 | * @retval None |
||
| 4657 | */ |
||
| 4658 | static void I2C_ITError(I2C_HandleTypeDef *hi2c) |
||
| 4659 | { |
||
| 4660 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
| 4661 | uint32_t CurrentState = hi2c->State; |
||
| 4662 | |||
| 4663 | if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
||
| 4664 | { |
||
| 4665 | /* keep HAL_I2C_STATE_LISTEN */ |
||
| 4666 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 4667 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
| 4668 | } |
||
| 4669 | else |
||
| 4670 | { |
||
| 4671 | /* If state is an abort treatment on going, don't change state */ |
||
| 4672 | /* This change will be do later */ |
||
| 4673 | if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) |
||
| 4674 | { |
||
| 4675 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4676 | } |
||
| 4677 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 4678 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4679 | } |
||
| 4680 | |||
| 4681 | /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ |
||
| 4682 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
| 4683 | |||
| 4684 | /* Abort DMA transfer */ |
||
| 4685 | if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
| 4686 | { |
||
| 4687 | hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; |
||
| 4688 | |||
| 4689 | if(hi2c->hdmatx->State != HAL_DMA_STATE_READY) |
||
| 4690 | { |
||
| 4691 | /* Set the DMA Abort callback : |
||
| 4692 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
| 4693 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
||
| 4694 | |||
| 4695 | if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
||
| 4696 | { |
||
| 4697 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
| 4698 | __HAL_I2C_DISABLE(hi2c); |
||
| 4699 | |||
| 4700 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4701 | |||
| 4702 | /* Call Directly XferAbortCallback function in case of error */ |
||
| 4703 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
||
| 4704 | } |
||
| 4705 | } |
||
| 4706 | else |
||
| 4707 | { |
||
| 4708 | /* Set the DMA Abort callback : |
||
| 4709 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
| 4710 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
||
| 4711 | |||
| 4712 | if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
||
| 4713 | { |
||
| 4714 | /* Store Last receive data if any */ |
||
| 4715 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
| 4716 | { |
||
| 4717 | /* Read data from DR */ |
||
| 4718 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4719 | } |
||
| 4720 | |||
| 4721 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
| 4722 | __HAL_I2C_DISABLE(hi2c); |
||
| 4723 | |||
| 4724 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4725 | |||
| 4726 | /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ |
||
| 4727 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
||
| 4728 | } |
||
| 4729 | } |
||
| 4730 | } |
||
| 4731 | else if(hi2c->State == HAL_I2C_STATE_ABORT) |
||
| 4732 | { |
||
| 4733 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4734 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 4735 | |||
| 4736 | /* Store Last receive data if any */ |
||
| 4737 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
| 4738 | { |
||
| 4739 | /* Read data from DR */ |
||
| 4740 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4741 | } |
||
| 4742 | |||
| 4743 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
| 4744 | __HAL_I2C_DISABLE(hi2c); |
||
| 4745 | |||
| 4746 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
| 4747 | HAL_I2C_AbortCpltCallback(hi2c); |
||
| 4748 | } |
||
| 4749 | else |
||
| 4750 | { |
||
| 4751 | /* Store Last receive data if any */ |
||
| 4752 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
| 4753 | { |
||
| 4754 | /* Read data from DR */ |
||
| 4755 | (*hi2c->pBuffPtr++) = hi2c->Instance->DR; |
||
| 4756 | } |
||
| 4757 | |||
| 4758 | /* Call user error callback */ |
||
| 4759 | HAL_I2C_ErrorCallback(hi2c); |
||
| 4760 | } |
||
| 4761 | /* STOP Flag is not set after a NACK reception */ |
||
| 4762 | /* So may inform upper layer that listen phase is stopped */ |
||
| 4763 | /* during NACK error treatment */ |
||
| 4764 | if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) |
||
| 4765 | { |
||
| 4766 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
| 4767 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 4768 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 4769 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 4770 | |||
| 4771 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
||
| 4772 | HAL_I2C_ListenCpltCallback(hi2c); |
||
| 4773 | } |
||
| 4774 | } |
||
| 4775 | |||
| 4776 | /** |
||
| 4777 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4778 | * the configuration information for I2C module |
||
| 4779 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 4780 | * in datasheet must be shifted to the left before calling the interface |
||
| 4781 | * @param Timeout Timeout duration |
||
| 4782 | * @param Tickstart Tick start value |
||
| 4783 | * @retval HAL status |
||
| 4784 | */ |
||
| 4785 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
||
| 4786 | { |
||
| 4787 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
| 4788 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
| 4789 | |||
| 4790 | /* Generate Start condition if first transfer */ |
||
| 4791 | if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
||
| 4792 | { |
||
| 4793 | /* Generate Start */ |
||
| 4794 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 4795 | } |
||
| 4796 | else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) |
||
| 4797 | { |
||
| 4798 | /* Generate ReStart */ |
||
| 4799 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 4800 | } |
||
| 4801 | |||
| 4802 | /* Wait until SB flag is set */ |
||
| 4803 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
| 4804 | { |
||
| 4805 | return HAL_TIMEOUT; |
||
| 4806 | } |
||
| 4807 | |||
| 4808 | if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
||
| 4809 | { |
||
| 4810 | /* Send slave address */ |
||
| 4811 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
| 4812 | } |
||
| 4813 | else |
||
| 4814 | { |
||
| 4815 | /* Send header of slave address */ |
||
| 4816 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
||
| 4817 | |||
| 4818 | /* Wait until ADD10 flag is set */ |
||
| 4819 | if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
||
| 4820 | { |
||
| 4821 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 4822 | { |
||
| 4823 | return HAL_ERROR; |
||
| 4824 | } |
||
| 4825 | else |
||
| 4826 | { |
||
| 4827 | return HAL_TIMEOUT; |
||
| 4828 | } |
||
| 4829 | } |
||
| 4830 | |||
| 4831 | /* Send slave address */ |
||
| 4832 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
||
| 4833 | } |
||
| 4834 | |||
| 4835 | /* Wait until ADDR flag is set */ |
||
| 4836 | if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
| 4837 | { |
||
| 4838 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 4839 | { |
||
| 4840 | return HAL_ERROR; |
||
| 4841 | } |
||
| 4842 | else |
||
| 4843 | { |
||
| 4844 | return HAL_TIMEOUT; |
||
| 4845 | } |
||
| 4846 | } |
||
| 4847 | |||
| 4848 | return HAL_OK; |
||
| 4849 | } |
||
| 4850 | |||
| 4851 | /** |
||
| 4852 | * @brief Master sends target device address for read request. |
||
| 4853 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4854 | * the configuration information for I2C module |
||
| 4855 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 4856 | * in datasheet must be shifted to the left before calling the interface |
||
| 4857 | * @param Timeout Timeout duration |
||
| 4858 | * @param Tickstart Tick start value |
||
| 4859 | * @retval HAL status |
||
| 4860 | */ |
||
| 4861 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
||
| 4862 | { |
||
| 4863 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
| 4864 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
| 4865 | |||
| 4866 | /* Enable Acknowledge */ |
||
| 4867 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 4868 | |||
| 4869 | /* Generate Start condition if first transfer */ |
||
| 4870 | if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
||
| 4871 | { |
||
| 4872 | /* Generate Start */ |
||
| 4873 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 4874 | } |
||
| 4875 | else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) |
||
| 4876 | { |
||
| 4877 | /* Generate ReStart */ |
||
| 4878 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 4879 | } |
||
| 4880 | |||
| 4881 | /* Wait until SB flag is set */ |
||
| 4882 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
| 4883 | { |
||
| 4884 | return HAL_TIMEOUT; |
||
| 4885 | } |
||
| 4886 | |||
| 4887 | if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
||
| 4888 | { |
||
| 4889 | /* Send slave address */ |
||
| 4890 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
||
| 4891 | } |
||
| 4892 | else |
||
| 4893 | { |
||
| 4894 | /* Send header of slave address */ |
||
| 4895 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
||
| 4896 | |||
| 4897 | /* Wait until ADD10 flag is set */ |
||
| 4898 | if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
||
| 4899 | { |
||
| 4900 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 4901 | { |
||
| 4902 | return HAL_ERROR; |
||
| 4903 | } |
||
| 4904 | else |
||
| 4905 | { |
||
| 4906 | return HAL_TIMEOUT; |
||
| 4907 | } |
||
| 4908 | } |
||
| 4909 | |||
| 4910 | /* Send slave address */ |
||
| 4911 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
||
| 4912 | |||
| 4913 | /* Wait until ADDR flag is set */ |
||
| 4914 | if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
| 4915 | { |
||
| 4916 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 4917 | { |
||
| 4918 | return HAL_ERROR; |
||
| 4919 | } |
||
| 4920 | else |
||
| 4921 | { |
||
| 4922 | return HAL_TIMEOUT; |
||
| 4923 | } |
||
| 4924 | } |
||
| 4925 | |||
| 4926 | /* Clear ADDR flag */ |
||
| 4927 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4928 | |||
| 4929 | /* Generate Restart */ |
||
| 4930 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 4931 | |||
| 4932 | /* Wait until SB flag is set */ |
||
| 4933 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
| 4934 | { |
||
| 4935 | return HAL_TIMEOUT; |
||
| 4936 | } |
||
| 4937 | |||
| 4938 | /* Send header of slave address */ |
||
| 4939 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); |
||
| 4940 | } |
||
| 4941 | |||
| 4942 | /* Wait until ADDR flag is set */ |
||
| 4943 | if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
| 4944 | { |
||
| 4945 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 4946 | { |
||
| 4947 | return HAL_ERROR; |
||
| 4948 | } |
||
| 4949 | else |
||
| 4950 | { |
||
| 4951 | return HAL_TIMEOUT; |
||
| 4952 | } |
||
| 4953 | } |
||
| 4954 | |||
| 4955 | return HAL_OK; |
||
| 4956 | } |
||
| 4957 | |||
| 4958 | /** |
||
| 4959 | * @brief Master sends target device address followed by internal memory address for write request. |
||
| 4960 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 4961 | * the configuration information for I2C module |
||
| 4962 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 4963 | * in datasheet must be shifted to the left before calling the interface |
||
| 4964 | * @param MemAddress Internal memory address |
||
| 4965 | * @param MemAddSize Size of internal memory address |
||
| 4966 | * @param Timeout Timeout duration |
||
| 4967 | * @param Tickstart Tick start value |
||
| 4968 | * @retval HAL status |
||
| 4969 | */ |
||
| 4970 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
||
| 4971 | { |
||
| 4972 | /* Generate Start */ |
||
| 4973 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 4974 | |||
| 4975 | /* Wait until SB flag is set */ |
||
| 4976 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
| 4977 | { |
||
| 4978 | return HAL_TIMEOUT; |
||
| 4979 | } |
||
| 4980 | |||
| 4981 | /* Send slave address */ |
||
| 4982 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
| 4983 | |||
| 4984 | /* Wait until ADDR flag is set */ |
||
| 4985 | if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
| 4986 | { |
||
| 4987 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 4988 | { |
||
| 4989 | return HAL_ERROR; |
||
| 4990 | } |
||
| 4991 | else |
||
| 4992 | { |
||
| 4993 | return HAL_TIMEOUT; |
||
| 4994 | } |
||
| 4995 | } |
||
| 4996 | |||
| 4997 | /* Clear ADDR flag */ |
||
| 4998 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 4999 | |||
| 5000 | /* Wait until TXE flag is set */ |
||
| 5001 | if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
| 5002 | { |
||
| 5003 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 5004 | { |
||
| 5005 | /* Generate Stop */ |
||
| 5006 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 5007 | return HAL_ERROR; |
||
| 5008 | } |
||
| 5009 | else |
||
| 5010 | { |
||
| 5011 | return HAL_TIMEOUT; |
||
| 5012 | } |
||
| 5013 | } |
||
| 5014 | |||
| 5015 | /* If Memory address size is 8Bit */ |
||
| 5016 | if(MemAddSize == I2C_MEMADD_SIZE_8BIT) |
||
| 5017 | { |
||
| 5018 | /* Send Memory Address */ |
||
| 5019 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
| 5020 | } |
||
| 5021 | /* If Memory address size is 16Bit */ |
||
| 5022 | else |
||
| 5023 | { |
||
| 5024 | /* Send MSB of Memory Address */ |
||
| 5025 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
||
| 5026 | |||
| 5027 | /* Wait until TXE flag is set */ |
||
| 5028 | if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
| 5029 | { |
||
| 5030 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 5031 | { |
||
| 5032 | /* Generate Stop */ |
||
| 5033 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 5034 | return HAL_ERROR; |
||
| 5035 | } |
||
| 5036 | else |
||
| 5037 | { |
||
| 5038 | return HAL_TIMEOUT; |
||
| 5039 | } |
||
| 5040 | } |
||
| 5041 | |||
| 5042 | /* Send LSB of Memory Address */ |
||
| 5043 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
| 5044 | } |
||
| 5045 | |||
| 5046 | return HAL_OK; |
||
| 5047 | } |
||
| 5048 | |||
| 5049 | /** |
||
| 5050 | * @brief Master sends target device address followed by internal memory address for read request. |
||
| 5051 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 5052 | * the configuration information for I2C module |
||
| 5053 | * @param DevAddress Target device address: The device 7 bits address value |
||
| 5054 | * in datasheet must be shifted to the left before calling the interface |
||
| 5055 | * @param MemAddress Internal memory address |
||
| 5056 | * @param MemAddSize Size of internal memory address |
||
| 5057 | * @param Timeout Timeout duration |
||
| 5058 | * @param Tickstart Tick start value |
||
| 5059 | * @retval HAL status |
||
| 5060 | */ |
||
| 5061 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
||
| 5062 | { |
||
| 5063 | /* Enable Acknowledge */ |
||
| 5064 | hi2c->Instance->CR1 |= I2C_CR1_ACK; |
||
| 5065 | |||
| 5066 | /* Generate Start */ |
||
| 5067 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 5068 | |||
| 5069 | /* Wait until SB flag is set */ |
||
| 5070 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
| 5071 | { |
||
| 5072 | return HAL_TIMEOUT; |
||
| 5073 | } |
||
| 5074 | |||
| 5075 | /* Send slave address */ |
||
| 5076 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
| 5077 | |||
| 5078 | /* Wait until ADDR flag is set */ |
||
| 5079 | if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
| 5080 | { |
||
| 5081 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 5082 | { |
||
| 5083 | return HAL_ERROR; |
||
| 5084 | } |
||
| 5085 | else |
||
| 5086 | { |
||
| 5087 | return HAL_TIMEOUT; |
||
| 5088 | } |
||
| 5089 | } |
||
| 5090 | |||
| 5091 | /* Clear ADDR flag */ |
||
| 5092 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
| 5093 | |||
| 5094 | /* Wait until TXE flag is set */ |
||
| 5095 | if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
| 5096 | { |
||
| 5097 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 5098 | { |
||
| 5099 | /* Generate Stop */ |
||
| 5100 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 5101 | return HAL_ERROR; |
||
| 5102 | } |
||
| 5103 | else |
||
| 5104 | { |
||
| 5105 | return HAL_TIMEOUT; |
||
| 5106 | } |
||
| 5107 | } |
||
| 5108 | |||
| 5109 | /* If Memory address size is 8Bit */ |
||
| 5110 | if(MemAddSize == I2C_MEMADD_SIZE_8BIT) |
||
| 5111 | { |
||
| 5112 | /* Send Memory Address */ |
||
| 5113 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
| 5114 | } |
||
| 5115 | /* If Memory address size is 16Bit */ |
||
| 5116 | else |
||
| 5117 | { |
||
| 5118 | /* Send MSB of Memory Address */ |
||
| 5119 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
||
| 5120 | |||
| 5121 | /* Wait until TXE flag is set */ |
||
| 5122 | if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
| 5123 | { |
||
| 5124 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 5125 | { |
||
| 5126 | /* Generate Stop */ |
||
| 5127 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 5128 | return HAL_ERROR; |
||
| 5129 | } |
||
| 5130 | else |
||
| 5131 | { |
||
| 5132 | return HAL_TIMEOUT; |
||
| 5133 | } |
||
| 5134 | } |
||
| 5135 | |||
| 5136 | /* Send LSB of Memory Address */ |
||
| 5137 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
| 5138 | } |
||
| 5139 | |||
| 5140 | /* Wait until TXE flag is set */ |
||
| 5141 | if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
| 5142 | { |
||
| 5143 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 5144 | { |
||
| 5145 | /* Generate Stop */ |
||
| 5146 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 5147 | return HAL_ERROR; |
||
| 5148 | } |
||
| 5149 | else |
||
| 5150 | { |
||
| 5151 | return HAL_TIMEOUT; |
||
| 5152 | } |
||
| 5153 | } |
||
| 5154 | |||
| 5155 | /* Generate Restart */ |
||
| 5156 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
| 5157 | |||
| 5158 | /* Wait until SB flag is set */ |
||
| 5159 | if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
| 5160 | { |
||
| 5161 | return HAL_TIMEOUT; |
||
| 5162 | } |
||
| 5163 | |||
| 5164 | /* Send slave address */ |
||
| 5165 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
||
| 5166 | |||
| 5167 | /* Wait until ADDR flag is set */ |
||
| 5168 | if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
| 5169 | { |
||
| 5170 | if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
| 5171 | { |
||
| 5172 | return HAL_ERROR; |
||
| 5173 | } |
||
| 5174 | else |
||
| 5175 | { |
||
| 5176 | return HAL_TIMEOUT; |
||
| 5177 | } |
||
| 5178 | } |
||
| 5179 | |||
| 5180 | return HAL_OK; |
||
| 5181 | } |
||
| 5182 | |||
| 5183 | /** |
||
| 5184 | * @brief DMA I2C process complete callback. |
||
| 5185 | * @param hdma DMA handle |
||
| 5186 | * @retval None |
||
| 5187 | */ |
||
| 5188 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) |
||
| 5189 | { |
||
| 5190 | I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
||
| 5191 | |||
| 5192 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
| 5193 | uint32_t CurrentState = hi2c->State; |
||
| 5194 | uint32_t CurrentMode = hi2c->Mode; |
||
| 5195 | |||
| 5196 | if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) |
||
| 5197 | { |
||
| 5198 | /* Disable DMA Request */ |
||
| 5199 | hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; |
||
| 5200 | |||
| 5201 | hi2c->XferCount = 0U; |
||
| 5202 | |||
| 5203 | /* Enable EVT and ERR interrupt */ |
||
| 5204 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
| 5205 | } |
||
| 5206 | else |
||
| 5207 | { |
||
| 5208 | /* Disable Acknowledge */ |
||
| 5209 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 5210 | |||
| 5211 | /* Generate Stop */ |
||
| 5212 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 5213 | |||
| 5214 | /* Disable Last DMA */ |
||
| 5215 | hi2c->Instance->CR2 &= ~I2C_CR2_LAST; |
||
| 5216 | |||
| 5217 | /* Disable DMA Request */ |
||
| 5218 | hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; |
||
| 5219 | |||
| 5220 | hi2c->XferCount = 0U; |
||
| 5221 | |||
| 5222 | /* Check if Errors has been detected during transfer */ |
||
| 5223 | if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
| 5224 | { |
||
| 5225 | HAL_I2C_ErrorCallback(hi2c); |
||
| 5226 | } |
||
| 5227 | else |
||
| 5228 | { |
||
| 5229 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 5230 | |||
| 5231 | if(hi2c->Mode == HAL_I2C_MODE_MEM) |
||
| 5232 | { |
||
| 5233 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 5234 | |||
| 5235 | HAL_I2C_MemRxCpltCallback(hi2c); |
||
| 5236 | } |
||
| 5237 | else |
||
| 5238 | { |
||
| 5239 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 5240 | |||
| 5241 | HAL_I2C_MasterRxCpltCallback(hi2c); |
||
| 5242 | } |
||
| 5243 | } |
||
| 5244 | } |
||
| 5245 | } |
||
| 5246 | |||
| 5247 | /** |
||
| 5248 | * @brief DMA I2C communication error callback. |
||
| 5249 | * @param hdma DMA handle |
||
| 5250 | * @retval None |
||
| 5251 | */ |
||
| 5252 | static void I2C_DMAError(DMA_HandleTypeDef *hdma) |
||
| 5253 | { |
||
| 5254 | I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
||
| 5255 | |||
| 5256 | /* Disable Acknowledge */ |
||
| 5257 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 5258 | |||
| 5259 | hi2c->XferCount = 0U; |
||
| 5260 | |||
| 5261 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 5262 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 5263 | |||
| 5264 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
| 5265 | |||
| 5266 | HAL_I2C_ErrorCallback(hi2c); |
||
| 5267 | } |
||
| 5268 | |||
| 5269 | /** |
||
| 5270 | * @brief DMA I2C communication abort callback |
||
| 5271 | * (To be called at end of DMA Abort procedure). |
||
| 5272 | * @param hdma: DMA handle. |
||
| 5273 | * @retval None |
||
| 5274 | */ |
||
| 5275 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) |
||
| 5276 | { |
||
| 5277 | I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
| 5278 | |||
| 5279 | /* Disable Acknowledge */ |
||
| 5280 | hi2c->Instance->CR1 &= ~I2C_CR1_ACK; |
||
| 5281 | |||
| 5282 | hi2c->XferCount = 0U; |
||
| 5283 | |||
| 5284 | /* Reset XferAbortCallback */ |
||
| 5285 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
| 5286 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
| 5287 | |||
| 5288 | /* Check if come from abort from user */ |
||
| 5289 | if(hi2c->State == HAL_I2C_STATE_ABORT) |
||
| 5290 | { |
||
| 5291 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 5292 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 5293 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 5294 | |||
| 5295 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
| 5296 | __HAL_I2C_DISABLE(hi2c); |
||
| 5297 | |||
| 5298 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
| 5299 | HAL_I2C_AbortCpltCallback(hi2c); |
||
| 5300 | } |
||
| 5301 | else |
||
| 5302 | { |
||
| 5303 | hi2c->State = HAL_I2C_STATE_READY; |
||
| 5304 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 5305 | |||
| 5306 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
| 5307 | __HAL_I2C_DISABLE(hi2c); |
||
| 5308 | |||
| 5309 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
| 5310 | HAL_I2C_ErrorCallback(hi2c); |
||
| 5311 | } |
||
| 5312 | } |
||
| 5313 | |||
| 5314 | /** |
||
| 5315 | * @brief This function handles I2C Communication Timeout. |
||
| 5316 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 5317 | * the configuration information for I2C module |
||
| 5318 | * @param Flag specifies the I2C flag to check. |
||
| 5319 | * @param Status The new Flag status (SET or RESET). |
||
| 5320 | * @param Timeout Timeout duration |
||
| 5321 | * @param Tickstart Tick start value |
||
| 5322 | * @retval HAL status |
||
| 5323 | */ |
||
| 5324 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) |
||
| 5325 | { |
||
| 5326 | /* Wait until flag is set */ |
||
| 5327 | while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) |
||
| 5328 | { |
||
| 5329 | /* Check for the Timeout */ |
||
| 5330 | if(Timeout != HAL_MAX_DELAY) |
||
| 5331 | { |
||
| 5332 | if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) |
||
| 5333 | { |
||
| 5334 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 5335 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 5336 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
| 5337 | |||
| 5338 | /* Process Unlocked */ |
||
| 5339 | __HAL_UNLOCK(hi2c); |
||
| 5340 | |||
| 5341 | return HAL_TIMEOUT; |
||
| 5342 | } |
||
| 5343 | } |
||
| 5344 | } |
||
| 5345 | |||
| 5346 | return HAL_OK; |
||
| 5347 | } |
||
| 5348 | |||
| 5349 | /** |
||
| 5350 | * @brief This function handles I2C Communication Timeout for Master addressing phase. |
||
| 5351 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 5352 | * the configuration information for I2C module |
||
| 5353 | * @param Flag specifies the I2C flag to check. |
||
| 5354 | * @param Timeout Timeout duration |
||
| 5355 | * @param Tickstart Tick start value |
||
| 5356 | * @retval HAL status |
||
| 5357 | */ |
||
| 5358 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) |
||
| 5359 | { |
||
| 5360 | while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) |
||
| 5361 | { |
||
| 5362 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
||
| 5363 | { |
||
| 5364 | /* Generate Stop */ |
||
| 5365 | hi2c->Instance->CR1 |= I2C_CR1_STOP; |
||
| 5366 | |||
| 5367 | /* Clear AF Flag */ |
||
| 5368 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
| 5369 | |||
| 5370 | hi2c->ErrorCode = HAL_I2C_ERROR_AF; |
||
| 5371 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 5372 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 5373 | |||
| 5374 | /* Process Unlocked */ |
||
| 5375 | __HAL_UNLOCK(hi2c); |
||
| 5376 | |||
| 5377 | return HAL_ERROR; |
||
| 5378 | } |
||
| 5379 | |||
| 5380 | /* Check for the Timeout */ |
||
| 5381 | if(Timeout != HAL_MAX_DELAY) |
||
| 5382 | { |
||
| 5383 | if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) |
||
| 5384 | { |
||
| 5385 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 5386 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 5387 | |||
| 5388 | /* Process Unlocked */ |
||
| 5389 | __HAL_UNLOCK(hi2c); |
||
| 5390 | |||
| 5391 | return HAL_TIMEOUT; |
||
| 5392 | } |
||
| 5393 | } |
||
| 5394 | } |
||
| 5395 | return HAL_OK; |
||
| 5396 | } |
||
| 5397 | |||
| 5398 | /** |
||
| 5399 | * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. |
||
| 5400 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 5401 | * the configuration information for the specified I2C. |
||
| 5402 | * @param Timeout Timeout duration |
||
| 5403 | * @param Tickstart Tick start value |
||
| 5404 | * @retval HAL status |
||
| 5405 | */ |
||
| 5406 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
| 5407 | { |
||
| 5408 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) |
||
| 5409 | { |
||
| 5410 | /* Check if a NACK is detected */ |
||
| 5411 | if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
||
| 5412 | { |
||
| 5413 | return HAL_ERROR; |
||
| 5414 | } |
||
| 5415 | |||
| 5416 | /* Check for the Timeout */ |
||
| 5417 | if(Timeout != HAL_MAX_DELAY) |
||
| 5418 | { |
||
| 5419 | if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) |
||
| 5420 | { |
||
| 5421 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
| 5422 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 5423 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 5424 | |||
| 5425 | /* Process Unlocked */ |
||
| 5426 | __HAL_UNLOCK(hi2c); |
||
| 5427 | |||
| 5428 | return HAL_TIMEOUT; |
||
| 5429 | } |
||
| 5430 | } |
||
| 5431 | } |
||
| 5432 | return HAL_OK; |
||
| 5433 | } |
||
| 5434 | |||
| 5435 | /** |
||
| 5436 | * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. |
||
| 5437 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 5438 | * the configuration information for the specified I2C. |
||
| 5439 | * @param Timeout Timeout duration |
||
| 5440 | * @param Tickstart Tick start value |
||
| 5441 | * @retval HAL status |
||
| 5442 | */ |
||
| 5443 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
| 5444 | { |
||
| 5445 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) |
||
| 5446 | { |
||
| 5447 | /* Check if a NACK is detected */ |
||
| 5448 | if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
||
| 5449 | { |
||
| 5450 | return HAL_ERROR; |
||
| 5451 | } |
||
| 5452 | |||
| 5453 | /* Check for the Timeout */ |
||
| 5454 | if(Timeout != HAL_MAX_DELAY) |
||
| 5455 | { |
||
| 5456 | if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) |
||
| 5457 | { |
||
| 5458 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
| 5459 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 5460 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 5461 | |||
| 5462 | /* Process Unlocked */ |
||
| 5463 | __HAL_UNLOCK(hi2c); |
||
| 5464 | |||
| 5465 | return HAL_TIMEOUT; |
||
| 5466 | } |
||
| 5467 | } |
||
| 5468 | } |
||
| 5469 | return HAL_OK; |
||
| 5470 | } |
||
| 5471 | |||
| 5472 | /** |
||
| 5473 | * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. |
||
| 5474 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 5475 | * the configuration information for the specified I2C. |
||
| 5476 | * @param Timeout Timeout duration |
||
| 5477 | * @param Tickstart Tick start value |
||
| 5478 | * @retval HAL status |
||
| 5479 | */ |
||
| 5480 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
| 5481 | { |
||
| 5482 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) |
||
| 5483 | { |
||
| 5484 | /* Check if a NACK is detected */ |
||
| 5485 | if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
||
| 5486 | { |
||
| 5487 | return HAL_ERROR; |
||
| 5488 | } |
||
| 5489 | |||
| 5490 | /* Check for the Timeout */ |
||
| 5491 | if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) |
||
| 5492 | { |
||
| 5493 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
| 5494 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 5495 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 5496 | |||
| 5497 | /* Process Unlocked */ |
||
| 5498 | __HAL_UNLOCK(hi2c); |
||
| 5499 | |||
| 5500 | return HAL_TIMEOUT; |
||
| 5501 | } |
||
| 5502 | } |
||
| 5503 | return HAL_OK; |
||
| 5504 | } |
||
| 5505 | |||
| 5506 | /** |
||
| 5507 | * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. |
||
| 5508 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 5509 | * the configuration information for the specified I2C. |
||
| 5510 | * @param Timeout Timeout duration |
||
| 5511 | * @param Tickstart Tick start value |
||
| 5512 | * @retval HAL status |
||
| 5513 | */ |
||
| 5514 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
| 5515 | { |
||
| 5516 | |||
| 5517 | while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) |
||
| 5518 | { |
||
| 5519 | /* Check if a STOPF is detected */ |
||
| 5520 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) |
||
| 5521 | { |
||
| 5522 | /* Clear STOP Flag */ |
||
| 5523 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
||
| 5524 | |||
| 5525 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
| 5526 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 5527 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 5528 | |||
| 5529 | /* Process Unlocked */ |
||
| 5530 | __HAL_UNLOCK(hi2c); |
||
| 5531 | |||
| 5532 | return HAL_ERROR; |
||
| 5533 | } |
||
| 5534 | |||
| 5535 | /* Check for the Timeout */ |
||
| 5536 | if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) |
||
| 5537 | { |
||
| 5538 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
| 5539 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 5540 | |||
| 5541 | /* Process Unlocked */ |
||
| 5542 | __HAL_UNLOCK(hi2c); |
||
| 5543 | |||
| 5544 | return HAL_TIMEOUT; |
||
| 5545 | } |
||
| 5546 | } |
||
| 5547 | return HAL_OK; |
||
| 5548 | } |
||
| 5549 | |||
| 5550 | /** |
||
| 5551 | * @brief This function handles Acknowledge failed detection during an I2C Communication. |
||
| 5552 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
| 5553 | * the configuration information for the specified I2C. |
||
| 5554 | * @retval HAL status |
||
| 5555 | */ |
||
| 5556 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) |
||
| 5557 | { |
||
| 5558 | if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
||
| 5559 | { |
||
| 5560 | /* Clear NACKF Flag */ |
||
| 5561 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
| 5562 | |||
| 5563 | hi2c->ErrorCode = HAL_I2C_ERROR_AF; |
||
| 5564 | hi2c->PreviousState = I2C_STATE_NONE; |
||
| 5565 | hi2c->State= HAL_I2C_STATE_READY; |
||
| 5566 | |||
| 5567 | /* Process Unlocked */ |
||
| 5568 | __HAL_UNLOCK(hi2c); |
||
| 5569 | |||
| 5570 | return HAL_ERROR; |
||
| 5571 | } |
||
| 5572 | return HAL_OK; |
||
| 5573 | } |
||
| 5574 | /** |
||
| 5575 | * @} |
||
| 5576 | */ |
||
| 5577 | |||
| 5578 | #endif /* HAL_I2C_MODULE_ENABLED */ |
||
| 5579 | |||
| 5580 | /** |
||
| 5581 | * @} |
||
| 5582 | */ |
||
| 5583 | |||
| 5584 | /** |
||
| 5585 | * @} |
||
| 5586 | */ |
||
| 5587 | |||
| 5588 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |