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/**
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  ******************************************************************************
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  * @file    stm32f1xx_hal_i2c.c
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  * @author  MCD Application Team
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  * @brief   I2C HAL module driver.
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  *          This file provides firmware functions to manage the following
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  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
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  *           + Initialization and de-initialization functions
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  *           + IO operation functions
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  *           + Peripheral State, Mode and Error functions
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  *
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  ******************************************************************************
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  * @attention
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  *
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  * Copyright (c) 2016 STMicroelectronics.
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  * All rights reserved.
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  *
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  * This software is licensed under terms that can be found in the LICENSE file
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  * in the root directory of this software component.
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  * If no LICENSE file comes with this software, it is provided AS-IS.
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  *
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  ******************************************************************************
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  @verbatim
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  ==============================================================================
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                        ##### How to use this driver #####
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  ==============================================================================
27
  [..]
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    The I2C HAL driver can be used as follows:
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30
    (#) Declare a I2C_HandleTypeDef handle structure, for example:
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        I2C_HandleTypeDef  hi2c;
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    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
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        (##) Enable the I2Cx interface clock
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        (##) I2C pins configuration
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            (+++) Enable the clock for the I2C GPIOs
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            (+++) Configure I2C pins as alternate function open-drain
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        (##) NVIC configuration if you need to use interrupt process
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            (+++) Configure the I2Cx interrupt priority
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            (+++) Enable the NVIC I2C IRQ Channel
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        (##) DMA Configuration if you need to use DMA process
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            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
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            (+++) Enable the DMAx interface clock using
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            (+++) Configure the DMA handle parameters
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            (+++) Configure the DMA Tx or Rx channel
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            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
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            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
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                  the DMA Tx or Rx channel
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    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
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        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
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    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
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        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API.
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56
    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
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58
    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
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60
    *** Polling mode IO operation ***
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    =================================
62
    [..]
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      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
64
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
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      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
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      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
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    *** Polling mode IO MEM operation ***
69
    =====================================
70
    [..]
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      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
72
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
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    *** Interrupt mode IO operation ***
76
    ===================================
77
    [..]
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      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
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      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
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      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
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      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
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      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
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      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
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      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
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      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
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      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
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           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
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      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
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      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
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    *** Interrupt mode or DMA mode IO sequential operation ***
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    ==========================================================
98
    [..]
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      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
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          when a direction change during transfer
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    [..]
102
      (+) A specific option field manage the different steps of a sequential transfer
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      (+) Option field values are defined through I2C_XferOptions_definition and are listed below:
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      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
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      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
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                            and data to transfer without a final stop condition
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      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
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                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
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                            several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
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                            or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
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      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
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                            and with new data to transfer if the direction change or manage only the new data to transfer
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                            if no direction change and without a final stop condition in both cases
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      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
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                            and with new data to transfer if the direction change or manage only the new data to transfer
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                            if no direction change and with a final stop condition in both cases
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      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
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                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
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                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
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                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
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                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
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                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
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                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
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                              without stopping the communication and so generate a restart condition.
125
      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
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                            interface.
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                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
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                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
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                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
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                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
131
                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
132
 
133
      (+) Different sequential I2C interfaces are listed below:
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      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT()
135
            or using HAL_I2C_Master_Seq_Transmit_DMA()
136
      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
138
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT()
139
            or using HAL_I2C_Master_Seq_Receive_DMA()
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      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
142
      (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
143
      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
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      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
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      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
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           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
148
      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
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      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT()
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            or using HAL_I2C_Slave_Seq_Transmit_DMA()
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      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
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      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT()
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            or using HAL_I2C_Slave_Seq_Receive_DMA()
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      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
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      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
159
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
160
 
161
    *** Interrupt mode IO MEM operation ***
162
    =======================================
163
    [..]
164
      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
165
          HAL_I2C_Mem_Write_IT()
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      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
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      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
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          HAL_I2C_Mem_Read_IT()
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      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
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      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
173
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
174
 
175
    *** DMA mode IO operation ***
176
    ==============================
177
    [..]
178
      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
179
          HAL_I2C_Master_Transmit_DMA()
180
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
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      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
183
          HAL_I2C_Master_Receive_DMA()
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      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
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      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
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          HAL_I2C_Slave_Transmit_DMA()
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      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
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      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
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          HAL_I2C_Slave_Receive_DMA()
192
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
194
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
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           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
196
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
197
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
199
 
200
    *** DMA mode IO MEM operation ***
201
    =================================
202
    [..]
203
      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
204
          HAL_I2C_Mem_Write_DMA()
205
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
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      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
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          HAL_I2C_Mem_Read_DMA()
209
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
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           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
211
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
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           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
213
 
214
 
215
     *** I2C HAL driver macros list ***
216
     ==================================
217
     [..]
218
       Below the list of most used macros in I2C HAL driver.
219
 
220
      (+) __HAL_I2C_ENABLE:     Enable the I2C peripheral
221
      (+) __HAL_I2C_DISABLE:    Disable the I2C peripheral
222
      (+) __HAL_I2C_GET_FLAG:   Checks whether the specified I2C flag is set or not
223
      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
224
      (+) __HAL_I2C_ENABLE_IT:  Enable the specified I2C interrupt
225
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
226
 
227
     *** Callback registration ***
228
     =============================================
229
    [..]
230
     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
231
     allows the user to configure dynamically the driver callbacks.
232
     Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
233
     to register an interrupt callback.
234
    [..]
235
     Function HAL_I2C_RegisterCallback() allows to register following callbacks:
236
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
237
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
238
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
239
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
240
       (+) ListenCpltCallback   : callback for end of listen mode.
241
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
242
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
243
       (+) ErrorCallback        : callback for error detection.
244
       (+) AbortCpltCallback    : callback for abort completion process.
245
       (+) MspInitCallback      : callback for Msp Init.
246
       (+) MspDeInitCallback    : callback for Msp DeInit.
247
     This function takes as parameters the HAL peripheral handle, the Callback ID
248
     and a pointer to the user callback function.
249
    [..]
250
     For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
251
    [..]
252
     Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
253
     weak function.
254
     HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
255
     and the Callback ID.
256
     This function allows to reset following callbacks:
257
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
258
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
259
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
260
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
261
       (+) ListenCpltCallback   : callback for end of listen mode.
262
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
263
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
264
       (+) ErrorCallback        : callback for error detection.
265
       (+) AbortCpltCallback    : callback for abort completion process.
266
       (+) MspInitCallback      : callback for Msp Init.
267
       (+) MspDeInitCallback    : callback for Msp DeInit.
268
    [..]
269
     For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
270
    [..]
271
     By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
272
     all callbacks are set to the corresponding weak functions:
273
     examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
274
     Exception done for MspInit and MspDeInit functions that are
275
     reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
276
     these callbacks are null (not registered beforehand).
277
     If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
278
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
279
    [..]
280
     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
281
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
282
     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
283
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
284
     Then, the user first registers the MspInit/MspDeInit user callbacks
285
     using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
286
     or HAL_I2C_Init() function.
287
    [..]
288
     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
289
     not defined, the callback registration feature is not available and all callbacks
290
     are set to the corresponding weak functions.
291
 
292
 
293
     *** I2C Workarounds linked to Silicon Limitation ***
294
     ====================================================
295
     [..]
296
       Below the list of all silicon limitations implemented for HAL on STM32F1xx product.
297
       (@) See ErrataSheet to know full silicon limitation list of your product.
298
 
299
       (+) Workarounds Implemented inside I2C HAL Driver
300
          (++) Wrong data read into data register (Polling and Interrupt mode)
301
          (++) Start cannot be generated after a misplaced Stop
302
          (++) Some software events must be managed before the current byte is being transferred:
303
               Workaround: Use DMA in general, except when the Master is receiving a single byte.
304
               For Interrupt mode, I2C should have the highest priority in the application.
305
          (++) Mismatch on the "Setup time for a repeated Start condition" timing parameter:
306
               Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if
307
               supported by the slave.
308
          (++) Data valid time (tVD;DAT) violated without the OVR flag being set:
309
               Workaround: If the slave device allows it, use the clock stretching mechanism
310
               by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init.
311
 
312
     [..]
313
       (@) You can refer to the I2C HAL driver header file for more useful macros
314
 
315
  @endverbatim
316
  */
317
 
318
/* Includes ------------------------------------------------------------------*/
319
#include "stm32f1xx_hal.h"
320
 
321
/** @addtogroup STM32F1xx_HAL_Driver
322
  * @{
323
  */
324
 
325
/** @defgroup I2C I2C
326
  * @brief I2C HAL module driver
327
  * @{
328
  */
329
 
330
#ifdef HAL_I2C_MODULE_ENABLED
331
 
332
/* Private typedef -----------------------------------------------------------*/
333
/* Private define ------------------------------------------------------------*/
334
/** @defgroup I2C_Private_Define I2C Private Define
335
  * @{
336
  */
337
#define I2C_TIMEOUT_FLAG          35U         /*!< Timeout 35 ms             */
338
#define I2C_TIMEOUT_BUSY_FLAG     25U         /*!< Timeout 25 ms             */
339
#define I2C_TIMEOUT_STOP_FLAG     5U          /*!< Timeout 5 ms              */
340
#define I2C_NO_OPTION_FRAME       0xFFFF0000U /*!< XferOptions default value */
341
 
342
/* Private define for @ref PreviousState usage */
343
#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
344
#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
345
#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
346
#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
347
#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
348
#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
349
 
350
/**
351
  * @}
352
  */
353
 
354
/* Private macro -------------------------------------------------------------*/
355
/** @addtogroup I2C_Private_Macros
356
  * @{
357
  */
358
/* Macro to get remaining data to transfer on DMA side */
359
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)     __HAL_DMA_GET_COUNTER(__HANDLE__)
360
/**
361
  * @}
362
  */
363
/* Private variables ---------------------------------------------------------*/
364
/* Private function prototypes -----------------------------------------------*/
365
 
366
/** @defgroup I2C_Private_Functions I2C Private Functions
367
  * @{
368
  */
369
/* Private functions to handle DMA transfer */
370
static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
371
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
372
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
373
 
374
static void I2C_ITError(I2C_HandleTypeDef *hi2c);
375
 
376
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
377
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
378
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
379
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
380
 
381
/* Private functions to handle flags during polling transfer */
382
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
383
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
384
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
385
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
386
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
387
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
388
static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
389
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
390
 
391
/* Private functions for I2C transfer IRQ handler */
392
static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
393
static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
394
static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
395
static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
396
static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
397
static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
398
static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
399
 
400
static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
401
static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
402
static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
403
static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
404
static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
405
static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
406
static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
407
 
408
static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
409
 
410
/* Private function to Convert Specific options */
411
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
412
 
413
/* Private function to flush DR register */
414
static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c);
415
/**
416
  * @}
417
  */
418
 
419
/* Exported functions --------------------------------------------------------*/
420
 
421
/** @defgroup I2C_Exported_Functions I2C Exported Functions
422
  * @{
423
  */
424
 
425
/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
426
 *  @brief    Initialization and Configuration functions
427
 *
428
@verbatim
429
 ===============================================================================
430
              ##### Initialization and de-initialization functions #####
431
 ===============================================================================
432
    [..]  This subsection provides a set of functions allowing to initialize and
433
          deinitialize the I2Cx peripheral:
434
 
435
      (+) User must Implement HAL_I2C_MspInit() function in which he configures
436
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
437
 
438
      (+) Call the function HAL_I2C_Init() to configure the selected device with
439
          the selected configuration:
440
        (++) Communication Speed
441
        (++) Duty cycle
442
        (++) Addressing mode
443
        (++) Own Address 1
444
        (++) Dual Addressing mode
445
        (++) Own Address 2
446
        (++) General call mode
447
        (++) Nostretch mode
448
 
449
      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
450
          of the selected I2Cx peripheral.
451
 
452
@endverbatim
453
  * @{
454
  */
455
 
456
/**
457
  * @brief  Initializes the I2C according to the specified parameters
458
  *         in the I2C_InitTypeDef and initialize the associated handle.
459
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
460
  *                the configuration information for the specified I2C.
461
  * @retval HAL status
462
  */
463
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
464
{
465
  uint32_t freqrange;
466
  uint32_t pclk1;
467
 
468
  /* Check the I2C handle allocation */
469
  if (hi2c == NULL)
470
  {
471
    return HAL_ERROR;
472
  }
473
 
474
  /* Check the parameters */
475
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
476
  assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
477
  assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
478
  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
479
  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
480
  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
481
  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
482
  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
483
  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
484
 
485
  if (hi2c->State == HAL_I2C_STATE_RESET)
486
  {
487
    /* Allocate lock resource and initialize it */
488
    hi2c->Lock = HAL_UNLOCKED;
489
 
490
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
491
    /* Init the I2C Callback settings */
492
    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
493
    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
494
    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
495
    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
496
    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
497
    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
498
    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
499
    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
500
    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
501
    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
502
 
503
    if (hi2c->MspInitCallback == NULL)
504
    {
505
      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
506
    }
507
 
508
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
509
    hi2c->MspInitCallback(hi2c);
510
#else
511
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
512
    HAL_I2C_MspInit(hi2c);
513
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
514
  }
515
 
516
  hi2c->State = HAL_I2C_STATE_BUSY;
517
 
518
  /* Disable the selected I2C peripheral */
519
  __HAL_I2C_DISABLE(hi2c);
520
 
521
  /*Reset I2C*/
522
  hi2c->Instance->CR1 |= I2C_CR1_SWRST;
523
  hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
524
 
525
  /* Get PCLK1 frequency */
526
  pclk1 = HAL_RCC_GetPCLK1Freq();
527
 
528
  /* Check the minimum allowed PCLK1 frequency */
529
  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
530
  {
531
    return HAL_ERROR;
532
  }
533
 
534
  /* Calculate frequency range */
535
  freqrange = I2C_FREQRANGE(pclk1);
536
 
537
  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
538
  /* Configure I2Cx: Frequency range */
539
  MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
540
 
541
  /*---------------------------- I2Cx TRISE Configuration --------------------*/
542
  /* Configure I2Cx: Rise Time */
543
  MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
544
 
545
  /*---------------------------- I2Cx CCR Configuration ----------------------*/
546
  /* Configure I2Cx: Speed */
547
  MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
548
 
549
  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
550
  /* Configure I2Cx: Generalcall and NoStretch mode */
551
  MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
552
 
553
  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
554
  /* Configure I2Cx: Own Address1 and addressing mode */
555
  MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
556
 
557
  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
558
  /* Configure I2Cx: Dual mode and Own Address2 */
559
  MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
560
 
561
  /* Enable the selected I2C peripheral */
562
  __HAL_I2C_ENABLE(hi2c);
563
 
564
  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
565
  hi2c->State = HAL_I2C_STATE_READY;
566
  hi2c->PreviousState = I2C_STATE_NONE;
567
  hi2c->Mode = HAL_I2C_MODE_NONE;
568
 
569
  return HAL_OK;
570
}
571
 
572
/**
573
  * @brief  DeInitialize the I2C peripheral.
574
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
575
  *         the configuration information for the specified I2C.
576
  * @retval HAL status
577
  */
578
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
579
{
580
  /* Check the I2C handle allocation */
581
  if (hi2c == NULL)
582
  {
583
    return HAL_ERROR;
584
  }
585
 
586
  /* Check the parameters */
587
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
588
 
589
  hi2c->State = HAL_I2C_STATE_BUSY;
590
 
591
  /* Disable the I2C Peripheral Clock */
592
  __HAL_I2C_DISABLE(hi2c);
593
 
594
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
595
  if (hi2c->MspDeInitCallback == NULL)
596
  {
597
    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
598
  }
599
 
600
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
601
  hi2c->MspDeInitCallback(hi2c);
602
#else
603
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
604
  HAL_I2C_MspDeInit(hi2c);
605
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
606
 
607
  hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
608
  hi2c->State         = HAL_I2C_STATE_RESET;
609
  hi2c->PreviousState = I2C_STATE_NONE;
610
  hi2c->Mode          = HAL_I2C_MODE_NONE;
611
 
612
  /* Release Lock */
613
  __HAL_UNLOCK(hi2c);
614
 
615
  return HAL_OK;
616
}
617
 
618
/**
619
  * @brief  Initialize the I2C MSP.
620
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
621
  *         the configuration information for the specified I2C.
622
  * @retval None
623
  */
624
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
625
{
626
  /* Prevent unused argument(s) compilation warning */
627
  UNUSED(hi2c);
628
 
629
  /* NOTE : This function should not be modified, when the callback is needed,
630
            the HAL_I2C_MspInit could be implemented in the user file
631
   */
632
}
633
 
634
/**
635
  * @brief  DeInitialize the I2C MSP.
636
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
637
  *         the configuration information for the specified I2C.
638
  * @retval None
639
  */
640
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
641
{
642
  /* Prevent unused argument(s) compilation warning */
643
  UNUSED(hi2c);
644
 
645
  /* NOTE : This function should not be modified, when the callback is needed,
646
            the HAL_I2C_MspDeInit could be implemented in the user file
647
   */
648
}
649
 
650
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
651
/**
652
  * @brief  Register a User I2C Callback
653
  *         To be used instead of the weak predefined callback
654
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
655
  *                the configuration information for the specified I2C.
656
  * @param  CallbackID ID of the callback to be registered
657
  *         This parameter can be one of the following values:
658
  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
659
  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
660
  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
661
  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
662
  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
663
  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
664
  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
665
  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
666
  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
667
  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
668
  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
669
  * @param  pCallback pointer to the Callback function
670
  * @retval HAL status
671
  */
672
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
673
{
674
  HAL_StatusTypeDef status = HAL_OK;
675
 
676
  if (pCallback == NULL)
677
  {
678
    /* Update the error code */
679
    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
680
 
681
    return HAL_ERROR;
682
  }
683
  /* Process locked */
684
  __HAL_LOCK(hi2c);
685
 
686
  if (HAL_I2C_STATE_READY == hi2c->State)
687
  {
688
    switch (CallbackID)
689
    {
690
      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
691
        hi2c->MasterTxCpltCallback = pCallback;
692
        break;
693
 
694
      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
695
        hi2c->MasterRxCpltCallback = pCallback;
696
        break;
697
 
698
      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
699
        hi2c->SlaveTxCpltCallback = pCallback;
700
        break;
701
 
702
      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
703
        hi2c->SlaveRxCpltCallback = pCallback;
704
        break;
705
 
706
      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
707
        hi2c->ListenCpltCallback = pCallback;
708
        break;
709
 
710
      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
711
        hi2c->MemTxCpltCallback = pCallback;
712
        break;
713
 
714
      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
715
        hi2c->MemRxCpltCallback = pCallback;
716
        break;
717
 
718
      case HAL_I2C_ERROR_CB_ID :
719
        hi2c->ErrorCallback = pCallback;
720
        break;
721
 
722
      case HAL_I2C_ABORT_CB_ID :
723
        hi2c->AbortCpltCallback = pCallback;
724
        break;
725
 
726
      case HAL_I2C_MSPINIT_CB_ID :
727
        hi2c->MspInitCallback = pCallback;
728
        break;
729
 
730
      case HAL_I2C_MSPDEINIT_CB_ID :
731
        hi2c->MspDeInitCallback = pCallback;
732
        break;
733
 
734
      default :
735
        /* Update the error code */
736
        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
737
 
738
        /* Return error status */
739
        status =  HAL_ERROR;
740
        break;
741
    }
742
  }
743
  else if (HAL_I2C_STATE_RESET == hi2c->State)
744
  {
745
    switch (CallbackID)
746
    {
747
      case HAL_I2C_MSPINIT_CB_ID :
748
        hi2c->MspInitCallback = pCallback;
749
        break;
750
 
751
      case HAL_I2C_MSPDEINIT_CB_ID :
752
        hi2c->MspDeInitCallback = pCallback;
753
        break;
754
 
755
      default :
756
        /* Update the error code */
757
        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
758
 
759
        /* Return error status */
760
        status =  HAL_ERROR;
761
        break;
762
    }
763
  }
764
  else
765
  {
766
    /* Update the error code */
767
    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
768
 
769
    /* Return error status */
770
    status =  HAL_ERROR;
771
  }
772
 
773
  /* Release Lock */
774
  __HAL_UNLOCK(hi2c);
775
  return status;
776
}
777
 
778
/**
779
  * @brief  Unregister an I2C Callback
780
  *         I2C callback is redirected to the weak predefined callback
781
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
782
  *                the configuration information for the specified I2C.
783
  * @param  CallbackID ID of the callback to be unregistered
784
  *         This parameter can be one of the following values:
785
  *         This parameter can be one of the following values:
786
  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
787
  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
788
  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
789
  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
790
  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
791
  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
792
  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
793
  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
794
  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
795
  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
796
  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
797
  * @retval HAL status
798
  */
799
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
800
{
801
  HAL_StatusTypeDef status = HAL_OK;
802
 
803
  /* Process locked */
804
  __HAL_LOCK(hi2c);
805
 
806
  if (HAL_I2C_STATE_READY == hi2c->State)
807
  {
808
    switch (CallbackID)
809
    {
810
      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
811
        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
812
        break;
813
 
814
      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
815
        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
816
        break;
817
 
818
      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
819
        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
820
        break;
821
 
822
      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
823
        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
824
        break;
825
 
826
      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
827
        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
828
        break;
829
 
830
      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
831
        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
832
        break;
833
 
834
      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
835
        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
836
        break;
837
 
838
      case HAL_I2C_ERROR_CB_ID :
839
        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
840
        break;
841
 
842
      case HAL_I2C_ABORT_CB_ID :
843
        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
844
        break;
845
 
846
      case HAL_I2C_MSPINIT_CB_ID :
847
        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
848
        break;
849
 
850
      case HAL_I2C_MSPDEINIT_CB_ID :
851
        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
852
        break;
853
 
854
      default :
855
        /* Update the error code */
856
        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
857
 
858
        /* Return error status */
859
        status =  HAL_ERROR;
860
        break;
861
    }
862
  }
863
  else if (HAL_I2C_STATE_RESET == hi2c->State)
864
  {
865
    switch (CallbackID)
866
    {
867
      case HAL_I2C_MSPINIT_CB_ID :
868
        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
869
        break;
870
 
871
      case HAL_I2C_MSPDEINIT_CB_ID :
872
        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
873
        break;
874
 
875
      default :
876
        /* Update the error code */
877
        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
878
 
879
        /* Return error status */
880
        status =  HAL_ERROR;
881
        break;
882
    }
883
  }
884
  else
885
  {
886
    /* Update the error code */
887
    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
888
 
889
    /* Return error status */
890
    status =  HAL_ERROR;
891
  }
892
 
893
  /* Release Lock */
894
  __HAL_UNLOCK(hi2c);
895
  return status;
896
}
897
 
898
/**
899
  * @brief  Register the Slave Address Match I2C Callback
900
  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
901
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
902
  *                the configuration information for the specified I2C.
903
  * @param  pCallback pointer to the Address Match Callback function
904
  * @retval HAL status
905
  */
906
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
907
{
908
  HAL_StatusTypeDef status = HAL_OK;
909
 
910
  if (pCallback == NULL)
911
  {
912
    /* Update the error code */
913
    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
914
 
915
    return HAL_ERROR;
916
  }
917
  /* Process locked */
918
  __HAL_LOCK(hi2c);
919
 
920
  if (HAL_I2C_STATE_READY == hi2c->State)
921
  {
922
    hi2c->AddrCallback = pCallback;
923
  }
924
  else
925
  {
926
    /* Update the error code */
927
    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
928
 
929
    /* Return error status */
930
    status =  HAL_ERROR;
931
  }
932
 
933
  /* Release Lock */
934
  __HAL_UNLOCK(hi2c);
935
  return status;
936
}
937
 
938
/**
939
  * @brief  UnRegister the Slave Address Match I2C Callback
940
  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
941
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
942
  *                the configuration information for the specified I2C.
943
  * @retval HAL status
944
  */
945
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
946
{
947
  HAL_StatusTypeDef status = HAL_OK;
948
 
949
  /* Process locked */
950
  __HAL_LOCK(hi2c);
951
 
952
  if (HAL_I2C_STATE_READY == hi2c->State)
953
  {
954
    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
955
  }
956
  else
957
  {
958
    /* Update the error code */
959
    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
960
 
961
    /* Return error status */
962
    status =  HAL_ERROR;
963
  }
964
 
965
  /* Release Lock */
966
  __HAL_UNLOCK(hi2c);
967
  return status;
968
}
969
 
970
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
971
 
972
/**
973
  * @brief  I2C data register flush process.
974
  * @param  hi2c I2C handle.
975
  * @retval None
976
  */
977
static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c)
978
{
979
  /* Write a dummy data in DR to clear TXE flag */
980
  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET)
981
  {
982
    hi2c->Instance->DR = 0x00U;
983
  }
984
}
985
 
986
/**
987
  * @}
988
  */
989
 
990
/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
991
 *  @brief   Data transfers functions
992
 *
993
@verbatim
994
 ===============================================================================
995
                      ##### IO operation functions #####
996
 ===============================================================================
997
    [..]
998
    This subsection provides a set of functions allowing to manage the I2C data
999
    transfers.
1000
 
1001
    (#) There are two modes of transfer:
1002
       (++) Blocking mode : The communication is performed in the polling mode.
1003
            The status of all data processing is returned by the same function
1004
            after finishing transfer.
1005
       (++) No-Blocking mode : The communication is performed using Interrupts
1006
            or DMA. These functions return the status of the transfer startup.
1007
            The end of the data processing will be indicated through the
1008
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1009
            using DMA mode.
1010
 
1011
    (#) Blocking mode functions are :
1012
        (++) HAL_I2C_Master_Transmit()
1013
        (++) HAL_I2C_Master_Receive()
1014
        (++) HAL_I2C_Slave_Transmit()
1015
        (++) HAL_I2C_Slave_Receive()
1016
        (++) HAL_I2C_Mem_Write()
1017
        (++) HAL_I2C_Mem_Read()
1018
        (++) HAL_I2C_IsDeviceReady()
1019
 
1020
    (#) No-Blocking mode functions with Interrupt are :
1021
        (++) HAL_I2C_Master_Transmit_IT()
1022
        (++) HAL_I2C_Master_Receive_IT()
1023
        (++) HAL_I2C_Slave_Transmit_IT()
1024
        (++) HAL_I2C_Slave_Receive_IT()
1025
        (++) HAL_I2C_Mem_Write_IT()
1026
        (++) HAL_I2C_Mem_Read_IT()
1027
        (++) HAL_I2C_Master_Seq_Transmit_IT()
1028
        (++) HAL_I2C_Master_Seq_Receive_IT()
1029
        (++) HAL_I2C_Slave_Seq_Transmit_IT()
1030
        (++) HAL_I2C_Slave_Seq_Receive_IT()
1031
        (++) HAL_I2C_EnableListen_IT()
1032
        (++) HAL_I2C_DisableListen_IT()
1033
        (++) HAL_I2C_Master_Abort_IT()
1034
 
1035
    (#) No-Blocking mode functions with DMA are :
1036
        (++) HAL_I2C_Master_Transmit_DMA()
1037
        (++) HAL_I2C_Master_Receive_DMA()
1038
        (++) HAL_I2C_Slave_Transmit_DMA()
1039
        (++) HAL_I2C_Slave_Receive_DMA()
1040
        (++) HAL_I2C_Mem_Write_DMA()
1041
        (++) HAL_I2C_Mem_Read_DMA()
1042
        (++) HAL_I2C_Master_Seq_Transmit_DMA()
1043
        (++) HAL_I2C_Master_Seq_Receive_DMA()
1044
        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1045
        (++) HAL_I2C_Slave_Seq_Receive_DMA()
1046
 
1047
    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1048
        (++) HAL_I2C_MasterTxCpltCallback()
1049
        (++) HAL_I2C_MasterRxCpltCallback()
1050
        (++) HAL_I2C_SlaveTxCpltCallback()
1051
        (++) HAL_I2C_SlaveRxCpltCallback()
1052
        (++) HAL_I2C_MemTxCpltCallback()
1053
        (++) HAL_I2C_MemRxCpltCallback()
1054
        (++) HAL_I2C_AddrCallback()
1055
        (++) HAL_I2C_ListenCpltCallback()
1056
        (++) HAL_I2C_ErrorCallback()
1057
        (++) HAL_I2C_AbortCpltCallback()
1058
 
1059
@endverbatim
1060
  * @{
1061
  */
1062
 
1063
/**
1064
  * @brief  Transmits in master mode an amount of data in blocking mode.
1065
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
1066
  *                the configuration information for the specified I2C.
1067
  * @param  DevAddress Target device address: The device 7 bits address value
1068
  *         in datasheet must be shifted to the left before calling the interface
1069
  * @param  pData Pointer to data buffer
1070
  * @param  Size Amount of data to be sent
1071
  * @param  Timeout Timeout duration
1072
  * @retval HAL status
1073
  */
1074
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1075
{
1076
  /* Init tickstart for timeout management*/
1077
  uint32_t tickstart = HAL_GetTick();
1078
 
1079
  if (hi2c->State == HAL_I2C_STATE_READY)
1080
  {
1081
    /* Wait until BUSY flag is reset */
1082
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1083
    {
1084
      return HAL_BUSY;
1085
    }
1086
 
1087
    /* Process Locked */
1088
    __HAL_LOCK(hi2c);
1089
 
1090
    /* Check if the I2C is already enabled */
1091
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1092
    {
1093
      /* Enable I2C peripheral */
1094
      __HAL_I2C_ENABLE(hi2c);
1095
    }
1096
 
1097
    /* Disable Pos */
1098
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1099
 
1100
    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
1101
    hi2c->Mode        = HAL_I2C_MODE_MASTER;
1102
    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
1103
 
1104
    /* Prepare transfer parameters */
1105
    hi2c->pBuffPtr    = pData;
1106
    hi2c->XferCount   = Size;
1107
    hi2c->XferSize    = hi2c->XferCount;
1108
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1109
 
1110
    /* Send Slave Address */
1111
    if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1112
    {
1113
      return HAL_ERROR;
1114
    }
1115
 
1116
    /* Clear ADDR flag */
1117
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1118
 
1119
    while (hi2c->XferSize > 0U)
1120
    {
1121
      /* Wait until TXE flag is set */
1122
      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1123
      {
1124
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1125
        {
1126
          /* Generate Stop */
1127
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1128
        }
1129
        return HAL_ERROR;
1130
      }
1131
 
1132
      /* Write data to DR */
1133
      hi2c->Instance->DR = *hi2c->pBuffPtr;
1134
 
1135
      /* Increment Buffer pointer */
1136
      hi2c->pBuffPtr++;
1137
 
1138
      /* Update counter */
1139
      hi2c->XferCount--;
1140
      hi2c->XferSize--;
1141
 
1142
      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1143
      {
1144
        /* Write data to DR */
1145
        hi2c->Instance->DR = *hi2c->pBuffPtr;
1146
 
1147
        /* Increment Buffer pointer */
1148
        hi2c->pBuffPtr++;
1149
 
1150
        /* Update counter */
1151
        hi2c->XferCount--;
1152
        hi2c->XferSize--;
1153
      }
1154
 
1155
      /* Wait until BTF flag is set */
1156
      if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1157
      {
1158
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1159
        {
1160
          /* Generate Stop */
1161
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1162
        }
1163
        return HAL_ERROR;
1164
      }
1165
    }
1166
 
1167
    /* Generate Stop */
1168
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1169
 
1170
    hi2c->State = HAL_I2C_STATE_READY;
1171
    hi2c->Mode = HAL_I2C_MODE_NONE;
1172
 
1173
    /* Process Unlocked */
1174
    __HAL_UNLOCK(hi2c);
1175
 
1176
    return HAL_OK;
1177
  }
1178
  else
1179
  {
1180
    return HAL_BUSY;
1181
  }
1182
}
1183
 
1184
/**
1185
  * @brief  Receives in master mode an amount of data in blocking mode.
1186
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
1187
  *                the configuration information for the specified I2C.
1188
  * @param  DevAddress Target device address: The device 7 bits address value
1189
  *         in datasheet must be shifted to the left before calling the interface
1190
  * @param  pData Pointer to data buffer
1191
  * @param  Size Amount of data to be sent
1192
  * @param  Timeout Timeout duration
1193
  * @retval HAL status
1194
  */
1195
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1196
{
1197
  __IO uint32_t count = 0U;
1198
 
1199
  /* Init tickstart for timeout management*/
1200
  uint32_t tickstart = HAL_GetTick();
1201
 
1202
  if (hi2c->State == HAL_I2C_STATE_READY)
1203
  {
1204
    /* Wait until BUSY flag is reset */
1205
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1206
    {
1207
      return HAL_BUSY;
1208
    }
1209
 
1210
    /* Process Locked */
1211
    __HAL_LOCK(hi2c);
1212
 
1213
    /* Check if the I2C is already enabled */
1214
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1215
    {
1216
      /* Enable I2C peripheral */
1217
      __HAL_I2C_ENABLE(hi2c);
1218
    }
1219
 
1220
    /* Disable Pos */
1221
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1222
 
1223
    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
1224
    hi2c->Mode        = HAL_I2C_MODE_MASTER;
1225
    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
1226
 
1227
    /* Prepare transfer parameters */
1228
    hi2c->pBuffPtr    = pData;
1229
    hi2c->XferCount   = Size;
1230
    hi2c->XferSize    = hi2c->XferCount;
1231
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1232
 
1233
    /* Send Slave Address */
1234
    if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1235
    {
1236
      return HAL_ERROR;
1237
    }
1238
 
1239
    if (hi2c->XferSize == 0U)
1240
    {
1241
      /* Clear ADDR flag */
1242
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1243
 
1244
      /* Generate Stop */
1245
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1246
    }
1247
    else if (hi2c->XferSize == 1U)
1248
    {
1249
      /* Disable Acknowledge */
1250
      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1251
 
1252
      /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
1253
      software sequence must complete before the current byte end of transfer */
1254
      __disable_irq();
1255
 
1256
      /* Clear ADDR flag */
1257
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1258
 
1259
      /* Generate Stop */
1260
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1261
 
1262
      /* Re-enable IRQs */
1263
      __enable_irq();
1264
    }
1265
    else if (hi2c->XferSize == 2U)
1266
    {
1267
      /* Enable Pos */
1268
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1269
 
1270
      /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
1271
      software sequence must complete before the current byte end of transfer */
1272
      __disable_irq();
1273
 
1274
      /* Clear ADDR flag */
1275
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1276
 
1277
      /* Disable Acknowledge */
1278
      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1279
 
1280
      /* Re-enable IRQs */
1281
      __enable_irq();
1282
    }
1283
    else
1284
    {
1285
      /* Enable Acknowledge */
1286
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1287
 
1288
      /* Clear ADDR flag */
1289
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1290
    }
1291
 
1292
    while (hi2c->XferSize > 0U)
1293
    {
1294
      if (hi2c->XferSize <= 3U)
1295
      {
1296
        /* One byte */
1297
        if (hi2c->XferSize == 1U)
1298
        {
1299
          /* Wait until RXNE flag is set */
1300
          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1301
          {
1302
            return HAL_ERROR;
1303
          }
1304
 
1305
          /* Read data from DR */
1306
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1307
 
1308
          /* Increment Buffer pointer */
1309
          hi2c->pBuffPtr++;
1310
 
1311
          /* Update counter */
1312
          hi2c->XferSize--;
1313
          hi2c->XferCount--;
1314
        }
1315
        /* Two bytes */
1316
        else if (hi2c->XferSize == 2U)
1317
        {
1318
          /* Wait until BTF flag is set */
1319
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1320
          {
1321
            return HAL_ERROR;
1322
          }
1323
 
1324
          /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
1325
             software sequence must complete before the current byte end of transfer */
1326
          __disable_irq();
1327
 
1328
          /* Generate Stop */
1329
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1330
 
1331
          /* Read data from DR */
1332
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1333
 
1334
          /* Increment Buffer pointer */
1335
          hi2c->pBuffPtr++;
1336
 
1337
          /* Update counter */
1338
          hi2c->XferSize--;
1339
          hi2c->XferCount--;
1340
 
1341
          /* Re-enable IRQs */
1342
          __enable_irq();
1343
 
1344
          /* Read data from DR */
1345
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1346
 
1347
          /* Increment Buffer pointer */
1348
          hi2c->pBuffPtr++;
1349
 
1350
          /* Update counter */
1351
          hi2c->XferSize--;
1352
          hi2c->XferCount--;
1353
        }
1354
        /* 3 Last bytes */
1355
        else
1356
        {
1357
          /* Wait until BTF flag is set */
1358
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1359
          {
1360
            return HAL_ERROR;
1361
          }
1362
 
1363
          /* Disable Acknowledge */
1364
          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1365
 
1366
          /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
1367
             software sequence must complete before the current byte end of transfer */
1368
          __disable_irq();
1369
 
1370
          /* Read data from DR */
1371
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1372
 
1373
          /* Increment Buffer pointer */
1374
          hi2c->pBuffPtr++;
1375
 
1376
          /* Update counter */
1377
          hi2c->XferSize--;
1378
          hi2c->XferCount--;
1379
 
1380
          /* Wait until BTF flag is set */
1381
          count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
1382
          do
1383
          {
1384
            count--;
1385
            if (count == 0U)
1386
            {
1387
              hi2c->PreviousState       = I2C_STATE_NONE;
1388
              hi2c->State               = HAL_I2C_STATE_READY;
1389
              hi2c->Mode                = HAL_I2C_MODE_NONE;
1390
              hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
1391
 
1392
              /* Re-enable IRQs */
1393
              __enable_irq();
1394
 
1395
              /* Process Unlocked */
1396
              __HAL_UNLOCK(hi2c);
1397
 
1398
              return HAL_ERROR;
1399
            }
1400
          }
1401
          while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
1402
 
1403
          /* Generate Stop */
1404
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1405
 
1406
          /* Read data from DR */
1407
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1408
 
1409
          /* Increment Buffer pointer */
1410
          hi2c->pBuffPtr++;
1411
 
1412
          /* Update counter */
1413
          hi2c->XferSize--;
1414
          hi2c->XferCount--;
1415
 
1416
          /* Re-enable IRQs */
1417
          __enable_irq();
1418
 
1419
          /* Read data from DR */
1420
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1421
 
1422
          /* Increment Buffer pointer */
1423
          hi2c->pBuffPtr++;
1424
 
1425
          /* Update counter */
1426
          hi2c->XferSize--;
1427
          hi2c->XferCount--;
1428
        }
1429
      }
1430
      else
1431
      {
1432
        /* Wait until RXNE flag is set */
1433
        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1434
        {
1435
          return HAL_ERROR;
1436
        }
1437
 
1438
        /* Read data from DR */
1439
        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1440
 
1441
        /* Increment Buffer pointer */
1442
        hi2c->pBuffPtr++;
1443
 
1444
        /* Update counter */
1445
        hi2c->XferSize--;
1446
        hi2c->XferCount--;
1447
 
1448
        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
1449
        {
1450
 
1451
          if (hi2c->XferSize == 3U)
1452
          {
1453
            /* Disable Acknowledge */
1454
            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1455
          }
1456
 
1457
          /* Read data from DR */
1458
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1459
 
1460
          /* Increment Buffer pointer */
1461
          hi2c->pBuffPtr++;
1462
 
1463
          /* Update counter */
1464
          hi2c->XferSize--;
1465
          hi2c->XferCount--;
1466
        }
1467
      }
1468
    }
1469
 
1470
    hi2c->State = HAL_I2C_STATE_READY;
1471
    hi2c->Mode = HAL_I2C_MODE_NONE;
1472
 
1473
    /* Process Unlocked */
1474
    __HAL_UNLOCK(hi2c);
1475
 
1476
    return HAL_OK;
1477
  }
1478
  else
1479
  {
1480
    return HAL_BUSY;
1481
  }
1482
}
1483
 
1484
/**
1485
  * @brief  Transmits in slave mode an amount of data in blocking mode.
1486
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
1487
  *                the configuration information for the specified I2C.
1488
  * @param  pData Pointer to data buffer
1489
  * @param  Size Amount of data to be sent
1490
  * @param  Timeout Timeout duration
1491
  * @retval HAL status
1492
  */
1493
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1494
{
1495
  /* Init tickstart for timeout management*/
1496
  uint32_t tickstart = HAL_GetTick();
1497
 
1498
  if (hi2c->State == HAL_I2C_STATE_READY)
1499
  {
1500
    if ((pData == NULL) || (Size == 0U))
1501
    {
1502
      return  HAL_ERROR;
1503
    }
1504
 
1505
    /* Process Locked */
1506
    __HAL_LOCK(hi2c);
1507
 
1508
    /* Check if the I2C is already enabled */
1509
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1510
    {
1511
      /* Enable I2C peripheral */
1512
      __HAL_I2C_ENABLE(hi2c);
1513
    }
1514
 
1515
    /* Disable Pos */
1516
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1517
 
1518
    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
1519
    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
1520
    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
1521
 
1522
    /* Prepare transfer parameters */
1523
    hi2c->pBuffPtr    = pData;
1524
    hi2c->XferCount   = Size;
1525
    hi2c->XferSize    = hi2c->XferCount;
1526
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1527
 
1528
    /* Enable Address Acknowledge */
1529
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1530
 
1531
    /* Wait until ADDR flag is set */
1532
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1533
    {
1534
      return HAL_ERROR;
1535
    }
1536
 
1537
    /* Clear ADDR flag */
1538
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1539
 
1540
    /* If 10bit addressing mode is selected */
1541
    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1542
    {
1543
      /* Wait until ADDR flag is set */
1544
      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1545
      {
1546
        return HAL_ERROR;
1547
      }
1548
 
1549
      /* Clear ADDR flag */
1550
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1551
    }
1552
 
1553
    while (hi2c->XferSize > 0U)
1554
    {
1555
      /* Wait until TXE flag is set */
1556
      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1557
      {
1558
        /* Disable Address Acknowledge */
1559
        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1560
 
1561
        return HAL_ERROR;
1562
      }
1563
 
1564
      /* Write data to DR */
1565
      hi2c->Instance->DR = *hi2c->pBuffPtr;
1566
 
1567
      /* Increment Buffer pointer */
1568
      hi2c->pBuffPtr++;
1569
 
1570
      /* Update counter */
1571
      hi2c->XferCount--;
1572
      hi2c->XferSize--;
1573
 
1574
      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1575
      {
1576
        /* Write data to DR */
1577
        hi2c->Instance->DR = *hi2c->pBuffPtr;
1578
 
1579
        /* Increment Buffer pointer */
1580
        hi2c->pBuffPtr++;
1581
 
1582
        /* Update counter */
1583
        hi2c->XferCount--;
1584
        hi2c->XferSize--;
1585
      }
1586
    }
1587
 
1588
    /* Wait until AF flag is set */
1589
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1590
    {
1591
      return HAL_ERROR;
1592
    }
1593
 
1594
    /* Clear AF flag */
1595
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1596
 
1597
    /* Disable Address Acknowledge */
1598
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1599
 
1600
    hi2c->State = HAL_I2C_STATE_READY;
1601
    hi2c->Mode = HAL_I2C_MODE_NONE;
1602
 
1603
    /* Process Unlocked */
1604
    __HAL_UNLOCK(hi2c);
1605
 
1606
    return HAL_OK;
1607
  }
1608
  else
1609
  {
1610
    return HAL_BUSY;
1611
  }
1612
}
1613
 
1614
/**
1615
  * @brief  Receive in slave mode an amount of data in blocking mode
1616
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
1617
  *         the configuration information for the specified I2C.
1618
  * @param  pData Pointer to data buffer
1619
  * @param  Size Amount of data to be sent
1620
  * @param  Timeout Timeout duration
1621
  * @retval HAL status
1622
  */
1623
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1624
{
1625
  /* Init tickstart for timeout management*/
1626
  uint32_t tickstart = HAL_GetTick();
1627
 
1628
  if (hi2c->State == HAL_I2C_STATE_READY)
1629
  {
1630
    if ((pData == NULL) || (Size == (uint16_t)0))
1631
    {
1632
      return HAL_ERROR;
1633
    }
1634
 
1635
    /* Process Locked */
1636
    __HAL_LOCK(hi2c);
1637
 
1638
    /* Check if the I2C is already enabled */
1639
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1640
    {
1641
      /* Enable I2C peripheral */
1642
      __HAL_I2C_ENABLE(hi2c);
1643
    }
1644
 
1645
    /* Disable Pos */
1646
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1647
 
1648
    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
1649
    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
1650
    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
1651
 
1652
    /* Prepare transfer parameters */
1653
    hi2c->pBuffPtr    = pData;
1654
    hi2c->XferCount   = Size;
1655
    hi2c->XferSize    = hi2c->XferCount;
1656
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1657
 
1658
    /* Enable Address Acknowledge */
1659
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1660
 
1661
    /* Wait until ADDR flag is set */
1662
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1663
    {
1664
      return HAL_ERROR;
1665
    }
1666
 
1667
    /* Clear ADDR flag */
1668
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1669
 
1670
    while (hi2c->XferSize > 0U)
1671
    {
1672
      /* Wait until RXNE flag is set */
1673
      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1674
      {
1675
        /* Disable Address Acknowledge */
1676
        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1677
 
1678
        return HAL_ERROR;
1679
      }
1680
 
1681
      /* Read data from DR */
1682
      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1683
 
1684
      /* Increment Buffer pointer */
1685
      hi2c->pBuffPtr++;
1686
 
1687
      /* Update counter */
1688
      hi2c->XferSize--;
1689
      hi2c->XferCount--;
1690
 
1691
      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1692
      {
1693
        /* Read data from DR */
1694
        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1695
 
1696
        /* Increment Buffer pointer */
1697
        hi2c->pBuffPtr++;
1698
 
1699
        /* Update counter */
1700
        hi2c->XferSize--;
1701
        hi2c->XferCount--;
1702
      }
1703
    }
1704
 
1705
    /* Wait until STOP flag is set */
1706
    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1707
    {
1708
      /* Disable Address Acknowledge */
1709
      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1710
 
1711
      return HAL_ERROR;
1712
    }
1713
 
1714
    /* Clear STOP flag */
1715
    __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1716
 
1717
    /* Disable Address Acknowledge */
1718
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1719
 
1720
    hi2c->State = HAL_I2C_STATE_READY;
1721
    hi2c->Mode = HAL_I2C_MODE_NONE;
1722
 
1723
    /* Process Unlocked */
1724
    __HAL_UNLOCK(hi2c);
1725
 
1726
    return HAL_OK;
1727
  }
1728
  else
1729
  {
1730
    return HAL_BUSY;
1731
  }
1732
}
1733
 
1734
/**
1735
  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
1736
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
1737
  *                the configuration information for the specified I2C.
1738
  * @param  DevAddress Target device address: The device 7 bits address value
1739
  *         in datasheet must be shifted to the left before calling the interface
1740
  * @param  pData Pointer to data buffer
1741
  * @param  Size Amount of data to be sent
1742
  * @retval HAL status
1743
  */
1744
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1745
{
1746
  __IO uint32_t count = 0U;
1747
 
1748
  if (hi2c->State == HAL_I2C_STATE_READY)
1749
  {
1750
    /* Wait until BUSY flag is reset */
1751
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1752
    do
1753
    {
1754
      count--;
1755
      if (count == 0U)
1756
      {
1757
        hi2c->PreviousState       = I2C_STATE_NONE;
1758
        hi2c->State               = HAL_I2C_STATE_READY;
1759
        hi2c->Mode                = HAL_I2C_MODE_NONE;
1760
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
1761
 
1762
        return HAL_BUSY;
1763
      }
1764
    }
1765
    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1766
 
1767
    /* Process Locked */
1768
    __HAL_LOCK(hi2c);
1769
 
1770
    /* Check if the I2C is already enabled */
1771
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1772
    {
1773
      /* Enable I2C peripheral */
1774
      __HAL_I2C_ENABLE(hi2c);
1775
    }
1776
 
1777
    /* Disable Pos */
1778
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1779
 
1780
    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
1781
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
1782
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1783
 
1784
    /* Prepare transfer parameters */
1785
    hi2c->pBuffPtr    = pData;
1786
    hi2c->XferCount   = Size;
1787
    hi2c->XferSize    = hi2c->XferCount;
1788
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1789
    hi2c->Devaddress  = DevAddress;
1790
 
1791
    /* Process Unlocked */
1792
    __HAL_UNLOCK(hi2c);
1793
 
1794
    /* Note : The I2C interrupts must be enabled after unlocking current process
1795
              to avoid the risk of I2C interrupt handle execution before current
1796
              process unlock */
1797
    /* Enable EVT, BUF and ERR interrupt */
1798
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1799
 
1800
    /* Generate Start */
1801
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1802
 
1803
    return HAL_OK;
1804
  }
1805
  else
1806
  {
1807
    return HAL_BUSY;
1808
  }
1809
}
1810
 
1811
/**
1812
  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
1813
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
1814
  *                the configuration information for the specified I2C.
1815
  * @param  DevAddress Target device address: The device 7 bits address value
1816
  *         in datasheet must be shifted to the left before calling the interface
1817
  * @param  pData Pointer to data buffer
1818
  * @param  Size Amount of data to be sent
1819
  * @retval HAL status
1820
  */
1821
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1822
{
1823
  __IO uint32_t count = 0U;
1824
 
1825
  if (hi2c->State == HAL_I2C_STATE_READY)
1826
  {
1827
    /* Wait until BUSY flag is reset */
1828
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1829
    do
1830
    {
1831
      count--;
1832
      if (count == 0U)
1833
      {
1834
        hi2c->PreviousState       = I2C_STATE_NONE;
1835
        hi2c->State               = HAL_I2C_STATE_READY;
1836
        hi2c->Mode                = HAL_I2C_MODE_NONE;
1837
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
1838
 
1839
        return HAL_BUSY;
1840
      }
1841
    }
1842
    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1843
 
1844
    /* Process Locked */
1845
    __HAL_LOCK(hi2c);
1846
 
1847
    /* Check if the I2C is already enabled */
1848
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1849
    {
1850
      /* Enable I2C peripheral */
1851
      __HAL_I2C_ENABLE(hi2c);
1852
    }
1853
 
1854
    /* Disable Pos */
1855
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1856
 
1857
    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
1858
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
1859
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1860
 
1861
    /* Prepare transfer parameters */
1862
    hi2c->pBuffPtr    = pData;
1863
    hi2c->XferCount   = Size;
1864
    hi2c->XferSize    = hi2c->XferCount;
1865
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1866
    hi2c->Devaddress  = DevAddress;
1867
 
1868
 
1869
    /* Process Unlocked */
1870
    __HAL_UNLOCK(hi2c);
1871
 
1872
    /* Note : The I2C interrupts must be enabled after unlocking current process
1873
    to avoid the risk of I2C interrupt handle execution before current
1874
    process unlock */
1875
 
1876
    /* Enable EVT, BUF and ERR interrupt */
1877
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1878
 
1879
    /* Enable Acknowledge */
1880
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1881
 
1882
    /* Generate Start */
1883
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1884
 
1885
    return HAL_OK;
1886
  }
1887
  else
1888
  {
1889
    return HAL_BUSY;
1890
  }
1891
}
1892
 
1893
/**
1894
  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1895
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
1896
  *         the configuration information for the specified I2C.
1897
  * @param  pData Pointer to data buffer
1898
  * @param  Size Amount of data to be sent
1899
  * @retval HAL status
1900
  */
1901
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1902
{
1903
 
1904
  if (hi2c->State == HAL_I2C_STATE_READY)
1905
  {
1906
    if ((pData == NULL) || (Size == 0U))
1907
    {
1908
      return  HAL_ERROR;
1909
    }
1910
 
1911
    /* Process Locked */
1912
    __HAL_LOCK(hi2c);
1913
 
1914
    /* Check if the I2C is already enabled */
1915
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1916
    {
1917
      /* Enable I2C peripheral */
1918
      __HAL_I2C_ENABLE(hi2c);
1919
    }
1920
 
1921
    /* Disable Pos */
1922
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1923
 
1924
    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
1925
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
1926
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1927
 
1928
    /* Prepare transfer parameters */
1929
    hi2c->pBuffPtr    = pData;
1930
    hi2c->XferCount   = Size;
1931
    hi2c->XferSize    = hi2c->XferCount;
1932
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1933
 
1934
    /* Enable Address Acknowledge */
1935
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1936
 
1937
    /* Process Unlocked */
1938
    __HAL_UNLOCK(hi2c);
1939
 
1940
    /* Note : The I2C interrupts must be enabled after unlocking current process
1941
              to avoid the risk of I2C interrupt handle execution before current
1942
              process unlock */
1943
 
1944
    /* Enable EVT, BUF and ERR interrupt */
1945
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1946
 
1947
    return HAL_OK;
1948
  }
1949
  else
1950
  {
1951
    return HAL_BUSY;
1952
  }
1953
}
1954
 
1955
/**
1956
  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
1957
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
1958
  *                the configuration information for the specified I2C.
1959
  * @param  pData Pointer to data buffer
1960
  * @param  Size Amount of data to be sent
1961
  * @retval HAL status
1962
  */
1963
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1964
{
1965
 
1966
  if (hi2c->State == HAL_I2C_STATE_READY)
1967
  {
1968
    if ((pData == NULL) || (Size == 0U))
1969
    {
1970
      return  HAL_ERROR;
1971
    }
1972
 
1973
    /* Process Locked */
1974
    __HAL_LOCK(hi2c);
1975
 
1976
    /* Check if the I2C is already enabled */
1977
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1978
    {
1979
      /* Enable I2C peripheral */
1980
      __HAL_I2C_ENABLE(hi2c);
1981
    }
1982
 
1983
    /* Disable Pos */
1984
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1985
 
1986
    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
1987
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
1988
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1989
 
1990
    /* Prepare transfer parameters */
1991
    hi2c->pBuffPtr    = pData;
1992
    hi2c->XferCount   = Size;
1993
    hi2c->XferSize    = hi2c->XferCount;
1994
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1995
 
1996
    /* Enable Address Acknowledge */
1997
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1998
 
1999
    /* Process Unlocked */
2000
    __HAL_UNLOCK(hi2c);
2001
 
2002
    /* Note : The I2C interrupts must be enabled after unlocking current process
2003
              to avoid the risk of I2C interrupt handle execution before current
2004
              process unlock */
2005
 
2006
    /* Enable EVT, BUF and ERR interrupt */
2007
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2008
 
2009
    return HAL_OK;
2010
  }
2011
  else
2012
  {
2013
    return HAL_BUSY;
2014
  }
2015
}
2016
 
2017
/**
2018
  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
2019
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
2020
  *                the configuration information for the specified I2C.
2021
  * @param  DevAddress Target device address: The device 7 bits address value
2022
  *         in datasheet must be shifted to the left before calling the interface
2023
  * @param  pData Pointer to data buffer
2024
  * @param  Size Amount of data to be sent
2025
  * @retval HAL status
2026
  */
2027
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2028
{
2029
  __IO uint32_t count = 0U;
2030
  HAL_StatusTypeDef dmaxferstatus;
2031
 
2032
  if (hi2c->State == HAL_I2C_STATE_READY)
2033
  {
2034
    /* Wait until BUSY flag is reset */
2035
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2036
    do
2037
    {
2038
      count--;
2039
      if (count == 0U)
2040
      {
2041
        hi2c->PreviousState       = I2C_STATE_NONE;
2042
        hi2c->State               = HAL_I2C_STATE_READY;
2043
        hi2c->Mode                = HAL_I2C_MODE_NONE;
2044
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
2045
 
2046
        return HAL_BUSY;
2047
      }
2048
    }
2049
    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2050
 
2051
    /* Process Locked */
2052
    __HAL_LOCK(hi2c);
2053
 
2054
    /* Check if the I2C is already enabled */
2055
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2056
    {
2057
      /* Enable I2C peripheral */
2058
      __HAL_I2C_ENABLE(hi2c);
2059
    }
2060
 
2061
    /* Disable Pos */
2062
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2063
 
2064
    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
2065
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
2066
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2067
 
2068
    /* Prepare transfer parameters */
2069
    hi2c->pBuffPtr    = pData;
2070
    hi2c->XferCount   = Size;
2071
    hi2c->XferSize    = hi2c->XferCount;
2072
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2073
    hi2c->Devaddress  = DevAddress;
2074
 
2075
    if (hi2c->XferSize > 0U)
2076
    {
2077
      if (hi2c->hdmatx != NULL)
2078
      {
2079
        /* Set the I2C DMA transfer complete callback */
2080
        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2081
 
2082
        /* Set the DMA error callback */
2083
        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2084
 
2085
        /* Set the unused DMA callbacks to NULL */
2086
        hi2c->hdmatx->XferHalfCpltCallback = NULL;
2087
        hi2c->hdmatx->XferAbortCallback = NULL;
2088
 
2089
        /* Enable the DMA channel */
2090
        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2091
      }
2092
      else
2093
      {
2094
        /* Update I2C state */
2095
        hi2c->State     = HAL_I2C_STATE_READY;
2096
        hi2c->Mode      = HAL_I2C_MODE_NONE;
2097
 
2098
        /* Update I2C error code */
2099
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2100
 
2101
        /* Process Unlocked */
2102
        __HAL_UNLOCK(hi2c);
2103
 
2104
        return HAL_ERROR;
2105
      }
2106
 
2107
      if (dmaxferstatus == HAL_OK)
2108
      {
2109
        /* Process Unlocked */
2110
        __HAL_UNLOCK(hi2c);
2111
 
2112
        /* Note : The I2C interrupts must be enabled after unlocking current process
2113
        to avoid the risk of I2C interrupt handle execution before current
2114
        process unlock */
2115
 
2116
        /* Enable EVT and ERR interrupt */
2117
        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2118
 
2119
        /* Enable DMA Request */
2120
        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2121
 
2122
        /* Enable Acknowledge */
2123
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2124
 
2125
        /* Generate Start */
2126
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2127
      }
2128
      else
2129
      {
2130
        /* Update I2C state */
2131
        hi2c->State     = HAL_I2C_STATE_READY;
2132
        hi2c->Mode      = HAL_I2C_MODE_NONE;
2133
 
2134
        /* Update I2C error code */
2135
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2136
 
2137
        /* Process Unlocked */
2138
        __HAL_UNLOCK(hi2c);
2139
 
2140
        return HAL_ERROR;
2141
      }
2142
    }
2143
    else
2144
    {
2145
      /* Enable Acknowledge */
2146
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2147
 
2148
      /* Generate Start */
2149
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2150
 
2151
      /* Process Unlocked */
2152
      __HAL_UNLOCK(hi2c);
2153
 
2154
      /* Note : The I2C interrupts must be enabled after unlocking current process
2155
      to avoid the risk of I2C interrupt handle execution before current
2156
      process unlock */
2157
 
2158
      /* Enable EVT, BUF and ERR interrupt */
2159
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2160
    }
2161
 
2162
    return HAL_OK;
2163
  }
2164
  else
2165
  {
2166
    return HAL_BUSY;
2167
  }
2168
}
2169
 
2170
/**
2171
  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
2172
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
2173
  *                the configuration information for the specified I2C.
2174
  * @param  DevAddress Target device address: The device 7 bits address value
2175
  *         in datasheet must be shifted to the left before calling the interface
2176
  * @param  pData Pointer to data buffer
2177
  * @param  Size Amount of data to be sent
2178
  * @retval HAL status
2179
  */
2180
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2181
{
2182
  __IO uint32_t count = 0U;
2183
  HAL_StatusTypeDef dmaxferstatus;
2184
 
2185
  if (hi2c->State == HAL_I2C_STATE_READY)
2186
  {
2187
    /* Wait until BUSY flag is reset */
2188
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2189
    do
2190
    {
2191
      count--;
2192
      if (count == 0U)
2193
      {
2194
        hi2c->PreviousState       = I2C_STATE_NONE;
2195
        hi2c->State               = HAL_I2C_STATE_READY;
2196
        hi2c->Mode                = HAL_I2C_MODE_NONE;
2197
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
2198
 
2199
        return HAL_BUSY;
2200
      }
2201
    }
2202
    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2203
 
2204
    /* Process Locked */
2205
    __HAL_LOCK(hi2c);
2206
 
2207
    /* Check if the I2C is already enabled */
2208
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2209
    {
2210
      /* Enable I2C peripheral */
2211
      __HAL_I2C_ENABLE(hi2c);
2212
    }
2213
 
2214
    /* Disable Pos */
2215
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2216
 
2217
    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
2218
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
2219
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2220
 
2221
    /* Prepare transfer parameters */
2222
    hi2c->pBuffPtr    = pData;
2223
    hi2c->XferCount   = Size;
2224
    hi2c->XferSize    = hi2c->XferCount;
2225
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2226
    hi2c->Devaddress  = DevAddress;
2227
 
2228
    if (hi2c->XferSize > 0U)
2229
    {
2230
      if (hi2c->hdmarx != NULL)
2231
      {
2232
        /* Set the I2C DMA transfer complete callback */
2233
        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2234
 
2235
        /* Set the DMA error callback */
2236
        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2237
 
2238
        /* Set the unused DMA callbacks to NULL */
2239
        hi2c->hdmarx->XferHalfCpltCallback = NULL;
2240
        hi2c->hdmarx->XferAbortCallback = NULL;
2241
 
2242
        /* Enable the DMA channel */
2243
        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2244
      }
2245
      else
2246
      {
2247
        /* Update I2C state */
2248
        hi2c->State     = HAL_I2C_STATE_READY;
2249
        hi2c->Mode      = HAL_I2C_MODE_NONE;
2250
 
2251
        /* Update I2C error code */
2252
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2253
 
2254
        /* Process Unlocked */
2255
        __HAL_UNLOCK(hi2c);
2256
 
2257
        return HAL_ERROR;
2258
      }
2259
 
2260
      if (dmaxferstatus == HAL_OK)
2261
      {
2262
        /* Enable Acknowledge */
2263
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2264
 
2265
        /* Generate Start */
2266
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2267
 
2268
        /* Process Unlocked */
2269
        __HAL_UNLOCK(hi2c);
2270
 
2271
        /* Note : The I2C interrupts must be enabled after unlocking current process
2272
        to avoid the risk of I2C interrupt handle execution before current
2273
        process unlock */
2274
 
2275
        /* Enable EVT and ERR interrupt */
2276
        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2277
 
2278
        /* Enable DMA Request */
2279
        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2280
      }
2281
      else
2282
      {
2283
        /* Update I2C state */
2284
        hi2c->State     = HAL_I2C_STATE_READY;
2285
        hi2c->Mode      = HAL_I2C_MODE_NONE;
2286
 
2287
        /* Update I2C error code */
2288
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2289
 
2290
        /* Process Unlocked */
2291
        __HAL_UNLOCK(hi2c);
2292
 
2293
        return HAL_ERROR;
2294
      }
2295
    }
2296
    else
2297
    {
2298
      /* Process Unlocked */
2299
      __HAL_UNLOCK(hi2c);
2300
 
2301
      /* Note : The I2C interrupts must be enabled after unlocking current process
2302
      to avoid the risk of I2C interrupt handle execution before current
2303
      process unlock */
2304
 
2305
      /* Enable EVT, BUF and ERR interrupt */
2306
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2307
 
2308
      /* Enable Acknowledge */
2309
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2310
 
2311
      /* Generate Start */
2312
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2313
    }
2314
 
2315
    return HAL_OK;
2316
  }
2317
  else
2318
  {
2319
    return HAL_BUSY;
2320
  }
2321
}
2322
 
2323
/**
2324
  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
2325
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
2326
  *                the configuration information for the specified I2C.
2327
  * @param  pData Pointer to data buffer
2328
  * @param  Size Amount of data to be sent
2329
  * @retval HAL status
2330
  */
2331
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2332
{
2333
  HAL_StatusTypeDef dmaxferstatus;
2334
 
2335
  if (hi2c->State == HAL_I2C_STATE_READY)
2336
  {
2337
    if ((pData == NULL) || (Size == 0U))
2338
    {
2339
      return  HAL_ERROR;
2340
    }
2341
 
2342
    /* Process Locked */
2343
    __HAL_LOCK(hi2c);
2344
 
2345
    /* Check if the I2C is already enabled */
2346
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2347
    {
2348
      /* Enable I2C peripheral */
2349
      __HAL_I2C_ENABLE(hi2c);
2350
    }
2351
 
2352
    /* Disable Pos */
2353
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2354
 
2355
    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
2356
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
2357
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2358
 
2359
    /* Prepare transfer parameters */
2360
    hi2c->pBuffPtr    = pData;
2361
    hi2c->XferCount   = Size;
2362
    hi2c->XferSize    = hi2c->XferCount;
2363
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2364
 
2365
    if (hi2c->hdmatx != NULL)
2366
    {
2367
      /* Set the I2C DMA transfer complete callback */
2368
      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2369
 
2370
      /* Set the DMA error callback */
2371
      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2372
 
2373
      /* Set the unused DMA callbacks to NULL */
2374
      hi2c->hdmatx->XferHalfCpltCallback = NULL;
2375
      hi2c->hdmatx->XferAbortCallback = NULL;
2376
 
2377
      /* Enable the DMA channel */
2378
      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2379
    }
2380
    else
2381
    {
2382
      /* Update I2C state */
2383
      hi2c->State     = HAL_I2C_STATE_LISTEN;
2384
      hi2c->Mode      = HAL_I2C_MODE_NONE;
2385
 
2386
      /* Update I2C error code */
2387
      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2388
 
2389
      /* Process Unlocked */
2390
      __HAL_UNLOCK(hi2c);
2391
 
2392
      return HAL_ERROR;
2393
    }
2394
 
2395
    if (dmaxferstatus == HAL_OK)
2396
    {
2397
      /* Enable Address Acknowledge */
2398
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2399
 
2400
      /* Process Unlocked */
2401
      __HAL_UNLOCK(hi2c);
2402
 
2403
      /* Note : The I2C interrupts must be enabled after unlocking current process
2404
      to avoid the risk of I2C interrupt handle execution before current
2405
      process unlock */
2406
      /* Enable EVT and ERR interrupt */
2407
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2408
 
2409
      /* Enable DMA Request */
2410
      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2411
 
2412
      return HAL_OK;
2413
    }
2414
    else
2415
    {
2416
      /* Update I2C state */
2417
      hi2c->State     = HAL_I2C_STATE_READY;
2418
      hi2c->Mode      = HAL_I2C_MODE_NONE;
2419
 
2420
      /* Update I2C error code */
2421
      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2422
 
2423
      /* Process Unlocked */
2424
      __HAL_UNLOCK(hi2c);
2425
 
2426
      return HAL_ERROR;
2427
    }
2428
  }
2429
  else
2430
  {
2431
    return HAL_BUSY;
2432
  }
2433
}
2434
 
2435
/**
2436
  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
2437
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
2438
  *                the configuration information for the specified I2C.
2439
  * @param  pData Pointer to data buffer
2440
  * @param  Size Amount of data to be sent
2441
  * @retval HAL status
2442
  */
2443
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2444
{
2445
  HAL_StatusTypeDef dmaxferstatus;
2446
 
2447
  if (hi2c->State == HAL_I2C_STATE_READY)
2448
  {
2449
    if ((pData == NULL) || (Size == 0U))
2450
    {
2451
      return  HAL_ERROR;
2452
    }
2453
 
2454
    /* Process Locked */
2455
    __HAL_LOCK(hi2c);
2456
 
2457
    /* Check if the I2C is already enabled */
2458
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2459
    {
2460
      /* Enable I2C peripheral */
2461
      __HAL_I2C_ENABLE(hi2c);
2462
    }
2463
 
2464
    /* Disable Pos */
2465
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2466
 
2467
    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
2468
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
2469
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2470
 
2471
    /* Prepare transfer parameters */
2472
    hi2c->pBuffPtr    = pData;
2473
    hi2c->XferCount   = Size;
2474
    hi2c->XferSize    = hi2c->XferCount;
2475
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2476
 
2477
    if (hi2c->hdmarx != NULL)
2478
    {
2479
      /* Set the I2C DMA transfer complete callback */
2480
      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2481
 
2482
      /* Set the DMA error callback */
2483
      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2484
 
2485
      /* Set the unused DMA callbacks to NULL */
2486
      hi2c->hdmarx->XferHalfCpltCallback = NULL;
2487
      hi2c->hdmarx->XferAbortCallback = NULL;
2488
 
2489
      /* Enable the DMA channel */
2490
      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2491
    }
2492
    else
2493
    {
2494
      /* Update I2C state */
2495
      hi2c->State     = HAL_I2C_STATE_LISTEN;
2496
      hi2c->Mode      = HAL_I2C_MODE_NONE;
2497
 
2498
      /* Update I2C error code */
2499
      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2500
 
2501
      /* Process Unlocked */
2502
      __HAL_UNLOCK(hi2c);
2503
 
2504
      return HAL_ERROR;
2505
    }
2506
 
2507
    if (dmaxferstatus == HAL_OK)
2508
    {
2509
      /* Enable Address Acknowledge */
2510
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2511
 
2512
      /* Process Unlocked */
2513
      __HAL_UNLOCK(hi2c);
2514
 
2515
      /* Note : The I2C interrupts must be enabled after unlocking current process
2516
      to avoid the risk of I2C interrupt handle execution before current
2517
      process unlock */
2518
      /* Enable EVT and ERR interrupt */
2519
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2520
 
2521
      /* Enable DMA Request */
2522
      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2523
 
2524
      return HAL_OK;
2525
    }
2526
    else
2527
    {
2528
      /* Update I2C state */
2529
      hi2c->State     = HAL_I2C_STATE_READY;
2530
      hi2c->Mode      = HAL_I2C_MODE_NONE;
2531
 
2532
      /* Update I2C error code */
2533
      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2534
 
2535
      /* Process Unlocked */
2536
      __HAL_UNLOCK(hi2c);
2537
 
2538
      return HAL_ERROR;
2539
    }
2540
  }
2541
  else
2542
  {
2543
    return HAL_BUSY;
2544
  }
2545
}
2546
 
2547
/**
2548
  * @brief  Write an amount of data in blocking mode to a specific memory address
2549
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
2550
  *                the configuration information for the specified I2C.
2551
  * @param  DevAddress Target device address: The device 7 bits address value
2552
  *         in datasheet must be shifted to the left before calling the interface
2553
  * @param  MemAddress Internal memory address
2554
  * @param  MemAddSize Size of internal memory address
2555
  * @param  pData Pointer to data buffer
2556
  * @param  Size Amount of data to be sent
2557
  * @param  Timeout Timeout duration
2558
  * @retval HAL status
2559
  */
2560
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2561
{
2562
  /* Init tickstart for timeout management*/
2563
  uint32_t tickstart = HAL_GetTick();
2564
 
2565
  /* Check the parameters */
2566
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2567
 
2568
  if (hi2c->State == HAL_I2C_STATE_READY)
2569
  {
2570
    /* Wait until BUSY flag is reset */
2571
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2572
    {
2573
      return HAL_BUSY;
2574
    }
2575
 
2576
    /* Process Locked */
2577
    __HAL_LOCK(hi2c);
2578
 
2579
    /* Check if the I2C is already enabled */
2580
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2581
    {
2582
      /* Enable I2C peripheral */
2583
      __HAL_I2C_ENABLE(hi2c);
2584
    }
2585
 
2586
    /* Disable Pos */
2587
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2588
 
2589
    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
2590
    hi2c->Mode      = HAL_I2C_MODE_MEM;
2591
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2592
 
2593
    /* Prepare transfer parameters */
2594
    hi2c->pBuffPtr    = pData;
2595
    hi2c->XferCount   = Size;
2596
    hi2c->XferSize    = hi2c->XferCount;
2597
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2598
 
2599
    /* Send Slave Address and Memory Address */
2600
    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2601
    {
2602
      return HAL_ERROR;
2603
    }
2604
 
2605
    while (hi2c->XferSize > 0U)
2606
    {
2607
      /* Wait until TXE flag is set */
2608
      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2609
      {
2610
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2611
        {
2612
          /* Generate Stop */
2613
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2614
        }
2615
        return HAL_ERROR;
2616
      }
2617
 
2618
      /* Write data to DR */
2619
      hi2c->Instance->DR = *hi2c->pBuffPtr;
2620
 
2621
      /* Increment Buffer pointer */
2622
      hi2c->pBuffPtr++;
2623
 
2624
      /* Update counter */
2625
      hi2c->XferSize--;
2626
      hi2c->XferCount--;
2627
 
2628
      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2629
      {
2630
        /* Write data to DR */
2631
        hi2c->Instance->DR = *hi2c->pBuffPtr;
2632
 
2633
        /* Increment Buffer pointer */
2634
        hi2c->pBuffPtr++;
2635
 
2636
        /* Update counter */
2637
        hi2c->XferSize--;
2638
        hi2c->XferCount--;
2639
      }
2640
    }
2641
 
2642
    /* Wait until BTF flag is set */
2643
    if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2644
    {
2645
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2646
      {
2647
        /* Generate Stop */
2648
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2649
      }
2650
      return HAL_ERROR;
2651
    }
2652
 
2653
    /* Generate Stop */
2654
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2655
 
2656
    hi2c->State = HAL_I2C_STATE_READY;
2657
    hi2c->Mode = HAL_I2C_MODE_NONE;
2658
 
2659
    /* Process Unlocked */
2660
    __HAL_UNLOCK(hi2c);
2661
 
2662
    return HAL_OK;
2663
  }
2664
  else
2665
  {
2666
    return HAL_BUSY;
2667
  }
2668
}
2669
 
2670
/**
2671
  * @brief  Read an amount of data in blocking mode from a specific memory address
2672
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
2673
  *                the configuration information for the specified I2C.
2674
  * @param  DevAddress Target device address: The device 7 bits address value
2675
  *         in datasheet must be shifted to the left before calling the interface
2676
  * @param  MemAddress Internal memory address
2677
  * @param  MemAddSize Size of internal memory address
2678
  * @param  pData Pointer to data buffer
2679
  * @param  Size Amount of data to be sent
2680
  * @param  Timeout Timeout duration
2681
  * @retval HAL status
2682
  */
2683
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2684
{
2685
  __IO uint32_t count = 0U;
2686
 
2687
  /* Init tickstart for timeout management*/
2688
  uint32_t tickstart = HAL_GetTick();
2689
 
2690
  /* Check the parameters */
2691
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2692
 
2693
  if (hi2c->State == HAL_I2C_STATE_READY)
2694
  {
2695
    /* Wait until BUSY flag is reset */
2696
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2697
    {
2698
      return HAL_BUSY;
2699
    }
2700
 
2701
    /* Process Locked */
2702
    __HAL_LOCK(hi2c);
2703
 
2704
    /* Check if the I2C is already enabled */
2705
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2706
    {
2707
      /* Enable I2C peripheral */
2708
      __HAL_I2C_ENABLE(hi2c);
2709
    }
2710
 
2711
    /* Disable Pos */
2712
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2713
 
2714
    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
2715
    hi2c->Mode      = HAL_I2C_MODE_MEM;
2716
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2717
 
2718
    /* Prepare transfer parameters */
2719
    hi2c->pBuffPtr    = pData;
2720
    hi2c->XferCount   = Size;
2721
    hi2c->XferSize    = hi2c->XferCount;
2722
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2723
 
2724
    /* Send Slave Address and Memory Address */
2725
    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2726
    {
2727
      return HAL_ERROR;
2728
    }
2729
 
2730
    if (hi2c->XferSize == 0U)
2731
    {
2732
      /* Clear ADDR flag */
2733
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2734
 
2735
      /* Generate Stop */
2736
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2737
    }
2738
    else if (hi2c->XferSize == 1U)
2739
    {
2740
      /* Disable Acknowledge */
2741
      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2742
 
2743
      /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
2744
         software sequence must complete before the current byte end of transfer */
2745
      __disable_irq();
2746
 
2747
      /* Clear ADDR flag */
2748
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2749
 
2750
      /* Generate Stop */
2751
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2752
 
2753
      /* Re-enable IRQs */
2754
      __enable_irq();
2755
    }
2756
    else if (hi2c->XferSize == 2U)
2757
    {
2758
      /* Enable Pos */
2759
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2760
 
2761
      /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
2762
         software sequence must complete before the current byte end of transfer */
2763
      __disable_irq();
2764
 
2765
      /* Clear ADDR flag */
2766
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2767
 
2768
      /* Disable Acknowledge */
2769
      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2770
 
2771
      /* Re-enable IRQs */
2772
      __enable_irq();
2773
    }
2774
    else
2775
    {
2776
      /* Enable Acknowledge */
2777
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2778
      /* Clear ADDR flag */
2779
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2780
    }
2781
 
2782
    while (hi2c->XferSize > 0U)
2783
    {
2784
      if (hi2c->XferSize <= 3U)
2785
      {
2786
        /* One byte */
2787
        if (hi2c->XferSize == 1U)
2788
        {
2789
          /* Wait until RXNE flag is set */
2790
          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2791
          {
2792
            return HAL_ERROR;
2793
          }
2794
 
2795
          /* Read data from DR */
2796
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2797
 
2798
          /* Increment Buffer pointer */
2799
          hi2c->pBuffPtr++;
2800
 
2801
          /* Update counter */
2802
          hi2c->XferSize--;
2803
          hi2c->XferCount--;
2804
        }
2805
        /* Two bytes */
2806
        else if (hi2c->XferSize == 2U)
2807
        {
2808
          /* Wait until BTF flag is set */
2809
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2810
          {
2811
            return HAL_ERROR;
2812
          }
2813
 
2814
          /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
2815
             software sequence must complete before the current byte end of transfer */
2816
          __disable_irq();
2817
 
2818
          /* Generate Stop */
2819
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2820
 
2821
          /* Read data from DR */
2822
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2823
 
2824
          /* Increment Buffer pointer */
2825
          hi2c->pBuffPtr++;
2826
 
2827
          /* Update counter */
2828
          hi2c->XferSize--;
2829
          hi2c->XferCount--;
2830
 
2831
          /* Re-enable IRQs */
2832
          __enable_irq();
2833
 
2834
          /* Read data from DR */
2835
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2836
 
2837
          /* Increment Buffer pointer */
2838
          hi2c->pBuffPtr++;
2839
 
2840
          /* Update counter */
2841
          hi2c->XferSize--;
2842
          hi2c->XferCount--;
2843
        }
2844
        /* 3 Last bytes */
2845
        else
2846
        {
2847
          /* Wait until BTF flag is set */
2848
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2849
          {
2850
            return HAL_ERROR;
2851
          }
2852
 
2853
          /* Disable Acknowledge */
2854
          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2855
 
2856
          /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
2857
             software sequence must complete before the current byte end of transfer */
2858
          __disable_irq();
2859
 
2860
          /* Read data from DR */
2861
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2862
 
2863
          /* Increment Buffer pointer */
2864
          hi2c->pBuffPtr++;
2865
 
2866
          /* Update counter */
2867
          hi2c->XferSize--;
2868
          hi2c->XferCount--;
2869
 
2870
          /* Wait until BTF flag is set */
2871
          count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
2872
          do
2873
          {
2874
            count--;
2875
            if (count == 0U)
2876
            {
2877
              hi2c->PreviousState       = I2C_STATE_NONE;
2878
              hi2c->State               = HAL_I2C_STATE_READY;
2879
              hi2c->Mode                = HAL_I2C_MODE_NONE;
2880
              hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
2881
 
2882
              /* Re-enable IRQs */
2883
              __enable_irq();
2884
 
2885
              /* Process Unlocked */
2886
              __HAL_UNLOCK(hi2c);
2887
 
2888
              return HAL_ERROR;
2889
            }
2890
          }
2891
          while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
2892
 
2893
          /* Generate Stop */
2894
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2895
 
2896
          /* Read data from DR */
2897
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2898
 
2899
          /* Increment Buffer pointer */
2900
          hi2c->pBuffPtr++;
2901
 
2902
          /* Update counter */
2903
          hi2c->XferSize--;
2904
          hi2c->XferCount--;
2905
 
2906
          /* Re-enable IRQs */
2907
          __enable_irq();
2908
 
2909
          /* Read data from DR */
2910
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2911
 
2912
          /* Increment Buffer pointer */
2913
          hi2c->pBuffPtr++;
2914
 
2915
          /* Update counter */
2916
          hi2c->XferSize--;
2917
          hi2c->XferCount--;
2918
        }
2919
      }
2920
      else
2921
      {
2922
        /* Wait until RXNE flag is set */
2923
        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2924
        {
2925
          return HAL_ERROR;
2926
        }
2927
 
2928
        /* Read data from DR */
2929
        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2930
 
2931
        /* Increment Buffer pointer */
2932
        hi2c->pBuffPtr++;
2933
 
2934
        /* Update counter */
2935
        hi2c->XferSize--;
2936
        hi2c->XferCount--;
2937
 
2938
        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2939
        {
2940
          /* Read data from DR */
2941
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2942
 
2943
          /* Increment Buffer pointer */
2944
          hi2c->pBuffPtr++;
2945
 
2946
          /* Update counter */
2947
          hi2c->XferSize--;
2948
          hi2c->XferCount--;
2949
        }
2950
      }
2951
    }
2952
 
2953
    hi2c->State = HAL_I2C_STATE_READY;
2954
    hi2c->Mode = HAL_I2C_MODE_NONE;
2955
 
2956
    /* Process Unlocked */
2957
    __HAL_UNLOCK(hi2c);
2958
 
2959
    return HAL_OK;
2960
  }
2961
  else
2962
  {
2963
    return HAL_BUSY;
2964
  }
2965
}
2966
 
2967
/**
2968
  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2969
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
2970
  *                the configuration information for the specified I2C.
2971
  * @param  DevAddress Target device address: The device 7 bits address value
2972
  *         in datasheet must be shifted to the left before calling the interface
2973
  * @param  MemAddress Internal memory address
2974
  * @param  MemAddSize Size of internal memory address
2975
  * @param  pData Pointer to data buffer
2976
  * @param  Size Amount of data to be sent
2977
  * @retval HAL status
2978
  */
2979
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2980
{
2981
  __IO uint32_t count = 0U;
2982
 
2983
  /* Check the parameters */
2984
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2985
 
2986
  if (hi2c->State == HAL_I2C_STATE_READY)
2987
  {
2988
    /* Wait until BUSY flag is reset */
2989
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2990
    do
2991
    {
2992
      count--;
2993
      if (count == 0U)
2994
      {
2995
        hi2c->PreviousState       = I2C_STATE_NONE;
2996
        hi2c->State               = HAL_I2C_STATE_READY;
2997
        hi2c->Mode                = HAL_I2C_MODE_NONE;
2998
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
2999
 
3000
        return HAL_BUSY;
3001
      }
3002
    }
3003
    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3004
 
3005
    /* Process Locked */
3006
    __HAL_LOCK(hi2c);
3007
 
3008
    /* Check if the I2C is already enabled */
3009
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3010
    {
3011
      /* Enable I2C peripheral */
3012
      __HAL_I2C_ENABLE(hi2c);
3013
    }
3014
 
3015
    /* Disable Pos */
3016
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3017
 
3018
    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
3019
    hi2c->Mode      = HAL_I2C_MODE_MEM;
3020
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3021
 
3022
    /* Prepare transfer parameters */
3023
    hi2c->pBuffPtr    = pData;
3024
    hi2c->XferCount   = Size;
3025
    hi2c->XferSize    = hi2c->XferCount;
3026
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3027
    hi2c->Devaddress  = DevAddress;
3028
    hi2c->Memaddress  = MemAddress;
3029
    hi2c->MemaddSize  = MemAddSize;
3030
    hi2c->EventCount  = 0U;
3031
 
3032
    /* Generate Start */
3033
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3034
 
3035
    /* Process Unlocked */
3036
    __HAL_UNLOCK(hi2c);
3037
 
3038
    /* Note : The I2C interrupts must be enabled after unlocking current process
3039
    to avoid the risk of I2C interrupt handle execution before current
3040
    process unlock */
3041
 
3042
    /* Enable EVT, BUF and ERR interrupt */
3043
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3044
 
3045
    return HAL_OK;
3046
  }
3047
  else
3048
  {
3049
    return HAL_BUSY;
3050
  }
3051
}
3052
 
3053
/**
3054
  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
3055
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
3056
  *                the configuration information for the specified I2C.
3057
  * @param  DevAddress Target device address
3058
  * @param  MemAddress Internal memory address
3059
  * @param  MemAddSize Size of internal memory address
3060
  * @param  pData Pointer to data buffer
3061
  * @param  Size Amount of data to be sent
3062
  * @retval HAL status
3063
  */
3064
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3065
{
3066
  __IO uint32_t count = 0U;
3067
 
3068
  /* Check the parameters */
3069
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3070
 
3071
  if (hi2c->State == HAL_I2C_STATE_READY)
3072
  {
3073
    /* Wait until BUSY flag is reset */
3074
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3075
    do
3076
    {
3077
      count--;
3078
      if (count == 0U)
3079
      {
3080
        hi2c->PreviousState       = I2C_STATE_NONE;
3081
        hi2c->State               = HAL_I2C_STATE_READY;
3082
        hi2c->Mode                = HAL_I2C_MODE_NONE;
3083
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
3084
 
3085
        return HAL_BUSY;
3086
      }
3087
    }
3088
    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3089
 
3090
    /* Process Locked */
3091
    __HAL_LOCK(hi2c);
3092
 
3093
    /* Check if the I2C is already enabled */
3094
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3095
    {
3096
      /* Enable I2C peripheral */
3097
      __HAL_I2C_ENABLE(hi2c);
3098
    }
3099
 
3100
    /* Disable Pos */
3101
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3102
 
3103
    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
3104
    hi2c->Mode      = HAL_I2C_MODE_MEM;
3105
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3106
 
3107
    /* Prepare transfer parameters */
3108
    hi2c->pBuffPtr    = pData;
3109
    hi2c->XferCount   = Size;
3110
    hi2c->XferSize    = hi2c->XferCount;
3111
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3112
    hi2c->Devaddress  = DevAddress;
3113
    hi2c->Memaddress  = MemAddress;
3114
    hi2c->MemaddSize  = MemAddSize;
3115
    hi2c->EventCount  = 0U;
3116
 
3117
    /* Enable Acknowledge */
3118
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3119
 
3120
    /* Generate Start */
3121
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3122
 
3123
    /* Process Unlocked */
3124
    __HAL_UNLOCK(hi2c);
3125
 
3126
    if (hi2c->XferSize > 0U)
3127
    {
3128
      /* Note : The I2C interrupts must be enabled after unlocking current process
3129
      to avoid the risk of I2C interrupt handle execution before current
3130
      process unlock */
3131
 
3132
      /* Enable EVT, BUF and ERR interrupt */
3133
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3134
    }
3135
    return HAL_OK;
3136
  }
3137
  else
3138
  {
3139
    return HAL_BUSY;
3140
  }
3141
}
3142
 
3143
/**
3144
  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
3145
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
3146
  *                the configuration information for the specified I2C.
3147
  * @param  DevAddress Target device address: The device 7 bits address value
3148
  *         in datasheet must be shifted to the left before calling the interface
3149
  * @param  MemAddress Internal memory address
3150
  * @param  MemAddSize Size of internal memory address
3151
  * @param  pData Pointer to data buffer
3152
  * @param  Size Amount of data to be sent
3153
  * @retval HAL status
3154
  */
3155
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3156
{
3157
  __IO uint32_t count = 0U;
3158
  HAL_StatusTypeDef dmaxferstatus;
3159
 
3160
  /* Init tickstart for timeout management*/
3161
  uint32_t tickstart = HAL_GetTick();
3162
 
3163
  /* Check the parameters */
3164
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3165
 
3166
  if (hi2c->State == HAL_I2C_STATE_READY)
3167
  {
3168
    /* Wait until BUSY flag is reset */
3169
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3170
    do
3171
    {
3172
      count--;
3173
      if (count == 0U)
3174
      {
3175
        hi2c->PreviousState       = I2C_STATE_NONE;
3176
        hi2c->State               = HAL_I2C_STATE_READY;
3177
        hi2c->Mode                = HAL_I2C_MODE_NONE;
3178
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
3179
 
3180
        return HAL_BUSY;
3181
      }
3182
    }
3183
    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3184
 
3185
    /* Process Locked */
3186
    __HAL_LOCK(hi2c);
3187
 
3188
    /* Check if the I2C is already enabled */
3189
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3190
    {
3191
      /* Enable I2C peripheral */
3192
      __HAL_I2C_ENABLE(hi2c);
3193
    }
3194
 
3195
    /* Disable Pos */
3196
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3197
 
3198
    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
3199
    hi2c->Mode      = HAL_I2C_MODE_MEM;
3200
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3201
 
3202
    /* Prepare transfer parameters */
3203
    hi2c->pBuffPtr    = pData;
3204
    hi2c->XferCount   = Size;
3205
    hi2c->XferSize    = hi2c->XferCount;
3206
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3207
    hi2c->Devaddress  = DevAddress;
3208
    hi2c->Memaddress  = MemAddress;
3209
    hi2c->MemaddSize  = MemAddSize;
3210
    hi2c->EventCount  = 0U;
3211
 
3212
    if (hi2c->XferSize > 0U)
3213
    {
3214
      if (hi2c->hdmatx != NULL)
3215
      {
3216
        /* Set the I2C DMA transfer complete callback */
3217
        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3218
 
3219
        /* Set the DMA error callback */
3220
        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3221
 
3222
        /* Set the unused DMA callbacks to NULL */
3223
        hi2c->hdmatx->XferHalfCpltCallback = NULL;
3224
        hi2c->hdmatx->XferAbortCallback = NULL;
3225
 
3226
        /* Enable the DMA channel */
3227
        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3228
      }
3229
      else
3230
      {
3231
        /* Update I2C state */
3232
        hi2c->State     = HAL_I2C_STATE_READY;
3233
        hi2c->Mode      = HAL_I2C_MODE_NONE;
3234
 
3235
        /* Update I2C error code */
3236
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3237
 
3238
        /* Process Unlocked */
3239
        __HAL_UNLOCK(hi2c);
3240
 
3241
        return HAL_ERROR;
3242
      }
3243
 
3244
      if (dmaxferstatus == HAL_OK)
3245
      {
3246
        /* Send Slave Address and Memory Address */
3247
        if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3248
        {
3249
          /* Abort the ongoing DMA */
3250
          dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
3251
 
3252
          /* Prevent unused argument(s) compilation and MISRA warning */
3253
          UNUSED(dmaxferstatus);
3254
 
3255
          /* Set the unused I2C DMA transfer complete callback to NULL */
3256
          hi2c->hdmatx->XferCpltCallback = NULL;
3257
 
3258
          /* Disable Acknowledge */
3259
          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3260
 
3261
          hi2c->XferSize = 0U;
3262
          hi2c->XferCount = 0U;
3263
 
3264
          /* Disable I2C peripheral to prevent dummy data in buffer */
3265
          __HAL_I2C_DISABLE(hi2c);
3266
 
3267
          return HAL_ERROR;
3268
        }
3269
 
3270
        /* Clear ADDR flag */
3271
        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3272
 
3273
        /* Process Unlocked */
3274
        __HAL_UNLOCK(hi2c);
3275
 
3276
        /* Note : The I2C interrupts must be enabled after unlocking current process
3277
        to avoid the risk of I2C interrupt handle execution before current
3278
        process unlock */
3279
        /* Enable ERR interrupt */
3280
        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3281
 
3282
        /* Enable DMA Request */
3283
        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3284
 
3285
        return HAL_OK;
3286
      }
3287
      else
3288
      {
3289
        /* Update I2C state */
3290
        hi2c->State     = HAL_I2C_STATE_READY;
3291
        hi2c->Mode      = HAL_I2C_MODE_NONE;
3292
 
3293
        /* Update I2C error code */
3294
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3295
 
3296
        /* Process Unlocked */
3297
        __HAL_UNLOCK(hi2c);
3298
 
3299
        return HAL_ERROR;
3300
      }
3301
    }
3302
    else
3303
    {
3304
      /* Update I2C state */
3305
      hi2c->State     = HAL_I2C_STATE_READY;
3306
      hi2c->Mode      = HAL_I2C_MODE_NONE;
3307
 
3308
      /* Update I2C error code */
3309
      hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
3310
 
3311
      /* Process Unlocked */
3312
      __HAL_UNLOCK(hi2c);
3313
 
3314
      return HAL_ERROR;
3315
    }
3316
  }
3317
  else
3318
  {
3319
    return HAL_BUSY;
3320
  }
3321
}
3322
 
3323
/**
3324
  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3325
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
3326
  *                the configuration information for the specified I2C.
3327
  * @param  DevAddress Target device address: The device 7 bits address value
3328
  *         in datasheet must be shifted to the left before calling the interface
3329
  * @param  MemAddress Internal memory address
3330
  * @param  MemAddSize Size of internal memory address
3331
  * @param  pData Pointer to data buffer
3332
  * @param  Size Amount of data to be read
3333
  * @retval HAL status
3334
  */
3335
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3336
{
3337
  /* Init tickstart for timeout management*/
3338
  uint32_t tickstart = HAL_GetTick();
3339
  __IO uint32_t count = 0U;
3340
  HAL_StatusTypeDef dmaxferstatus;
3341
 
3342
  /* Check the parameters */
3343
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3344
 
3345
  if (hi2c->State == HAL_I2C_STATE_READY)
3346
  {
3347
    /* Wait until BUSY flag is reset */
3348
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3349
    do
3350
    {
3351
      count--;
3352
      if (count == 0U)
3353
      {
3354
        hi2c->PreviousState       = I2C_STATE_NONE;
3355
        hi2c->State               = HAL_I2C_STATE_READY;
3356
        hi2c->Mode                = HAL_I2C_MODE_NONE;
3357
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
3358
 
3359
        return HAL_BUSY;
3360
      }
3361
    }
3362
    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3363
 
3364
    /* Process Locked */
3365
    __HAL_LOCK(hi2c);
3366
 
3367
    /* Check if the I2C is already enabled */
3368
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3369
    {
3370
      /* Enable I2C peripheral */
3371
      __HAL_I2C_ENABLE(hi2c);
3372
    }
3373
 
3374
    /* Disable Pos */
3375
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3376
 
3377
    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
3378
    hi2c->Mode      = HAL_I2C_MODE_MEM;
3379
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3380
 
3381
    /* Prepare transfer parameters */
3382
    hi2c->pBuffPtr    = pData;
3383
    hi2c->XferCount   = Size;
3384
    hi2c->XferSize    = hi2c->XferCount;
3385
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3386
    hi2c->Devaddress  = DevAddress;
3387
    hi2c->Memaddress  = MemAddress;
3388
    hi2c->MemaddSize  = MemAddSize;
3389
    hi2c->EventCount  = 0U;
3390
 
3391
    if (hi2c->XferSize > 0U)
3392
    {
3393
      if (hi2c->hdmarx != NULL)
3394
      {
3395
        /* Set the I2C DMA transfer complete callback */
3396
        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3397
 
3398
        /* Set the DMA error callback */
3399
        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3400
 
3401
        /* Set the unused DMA callbacks to NULL */
3402
        hi2c->hdmarx->XferHalfCpltCallback = NULL;
3403
        hi2c->hdmarx->XferAbortCallback = NULL;
3404
 
3405
        /* Enable the DMA channel */
3406
        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3407
      }
3408
      else
3409
      {
3410
        /* Update I2C state */
3411
        hi2c->State     = HAL_I2C_STATE_READY;
3412
        hi2c->Mode      = HAL_I2C_MODE_NONE;
3413
 
3414
        /* Update I2C error code */
3415
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3416
 
3417
        /* Process Unlocked */
3418
        __HAL_UNLOCK(hi2c);
3419
 
3420
        return HAL_ERROR;
3421
      }
3422
 
3423
      if (dmaxferstatus == HAL_OK)
3424
      {
3425
        /* Send Slave Address and Memory Address */
3426
        if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3427
        {
3428
          /* Abort the ongoing DMA */
3429
          dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
3430
 
3431
          /* Prevent unused argument(s) compilation and MISRA warning */
3432
          UNUSED(dmaxferstatus);
3433
 
3434
          /* Set the unused I2C DMA transfer complete callback to NULL */
3435
          hi2c->hdmarx->XferCpltCallback = NULL;
3436
 
3437
          /* Disable Acknowledge */
3438
          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3439
 
3440
          hi2c->XferSize = 0U;
3441
          hi2c->XferCount = 0U;
3442
 
3443
          /* Disable I2C peripheral to prevent dummy data in buffer */
3444
          __HAL_I2C_DISABLE(hi2c);
3445
 
3446
          return HAL_ERROR;
3447
        }
3448
 
3449
        if (hi2c->XferSize == 1U)
3450
        {
3451
          /* Disable Acknowledge */
3452
          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3453
        }
3454
        else
3455
        {
3456
          /* Enable Last DMA bit */
3457
          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3458
        }
3459
 
3460
        /* Clear ADDR flag */
3461
        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3462
 
3463
        /* Process Unlocked */
3464
        __HAL_UNLOCK(hi2c);
3465
 
3466
        /* Note : The I2C interrupts must be enabled after unlocking current process
3467
        to avoid the risk of I2C interrupt handle execution before current
3468
        process unlock */
3469
        /* Enable ERR interrupt */
3470
        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3471
 
3472
        /* Enable DMA Request */
3473
        hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3474
      }
3475
      else
3476
      {
3477
        /* Update I2C state */
3478
        hi2c->State     = HAL_I2C_STATE_READY;
3479
        hi2c->Mode      = HAL_I2C_MODE_NONE;
3480
 
3481
        /* Update I2C error code */
3482
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3483
 
3484
        /* Process Unlocked */
3485
        __HAL_UNLOCK(hi2c);
3486
 
3487
        return HAL_ERROR;
3488
      }
3489
    }
3490
    else
3491
    {
3492
      /* Send Slave Address and Memory Address */
3493
      if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3494
      {
3495
        return HAL_ERROR;
3496
      }
3497
 
3498
      /* Clear ADDR flag */
3499
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3500
 
3501
      /* Generate Stop */
3502
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3503
 
3504
      hi2c->State = HAL_I2C_STATE_READY;
3505
 
3506
      /* Process Unlocked */
3507
      __HAL_UNLOCK(hi2c);
3508
    }
3509
 
3510
    return HAL_OK;
3511
  }
3512
  else
3513
  {
3514
    return HAL_BUSY;
3515
  }
3516
}
3517
 
3518
/**
3519
  * @brief  Checks if target device is ready for communication.
3520
  * @note   This function is used with Memory devices
3521
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
3522
  *                the configuration information for the specified I2C.
3523
  * @param  DevAddress Target device address: The device 7 bits address value
3524
  *         in datasheet must be shifted to the left before calling the interface
3525
  * @param  Trials Number of trials
3526
  * @param  Timeout Timeout duration
3527
  * @retval HAL status
3528
  */
3529
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3530
{
3531
  /* Get tick */
3532
  uint32_t tickstart = HAL_GetTick();
3533
  uint32_t I2C_Trials = 0U;
3534
  FlagStatus tmp1;
3535
  FlagStatus tmp2;
3536
 
3537
  if (hi2c->State == HAL_I2C_STATE_READY)
3538
  {
3539
    /* Wait until BUSY flag is reset */
3540
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3541
    {
3542
      return HAL_BUSY;
3543
    }
3544
 
3545
    /* Process Locked */
3546
    __HAL_LOCK(hi2c);
3547
 
3548
    /* Check if the I2C is already enabled */
3549
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3550
    {
3551
      /* Enable I2C peripheral */
3552
      __HAL_I2C_ENABLE(hi2c);
3553
    }
3554
 
3555
    /* Disable Pos */
3556
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3557
 
3558
    hi2c->State = HAL_I2C_STATE_BUSY;
3559
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3560
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3561
 
3562
    do
3563
    {
3564
      /* Generate Start */
3565
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3566
 
3567
      /* Wait until SB flag is set */
3568
      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3569
      {
3570
        if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
3571
        {
3572
          hi2c->ErrorCode = HAL_I2C_WRONG_START;
3573
        }
3574
        return HAL_TIMEOUT;
3575
      }
3576
 
3577
      /* Send slave address */
3578
      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3579
 
3580
      /* Wait until ADDR or AF flag are set */
3581
      /* Get tick */
3582
      tickstart = HAL_GetTick();
3583
 
3584
      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3585
      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3586
      while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
3587
      {
3588
        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3589
        {
3590
          hi2c->State = HAL_I2C_STATE_TIMEOUT;
3591
        }
3592
        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3593
        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3594
      }
3595
 
3596
      hi2c->State = HAL_I2C_STATE_READY;
3597
 
3598
      /* Check if the ADDR flag has been set */
3599
      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3600
      {
3601
        /* Generate Stop */
3602
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3603
 
3604
        /* Clear ADDR Flag */
3605
        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3606
 
3607
        /* Wait until BUSY flag is reset */
3608
        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3609
        {
3610
          return HAL_ERROR;
3611
        }
3612
 
3613
        hi2c->State = HAL_I2C_STATE_READY;
3614
 
3615
        /* Process Unlocked */
3616
        __HAL_UNLOCK(hi2c);
3617
 
3618
        return HAL_OK;
3619
      }
3620
      else
3621
      {
3622
        /* Generate Stop */
3623
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3624
 
3625
        /* Clear AF Flag */
3626
        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3627
 
3628
        /* Wait until BUSY flag is reset */
3629
        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3630
        {
3631
          return HAL_ERROR;
3632
        }
3633
      }
3634
 
3635
      /* Increment Trials */
3636
      I2C_Trials++;
3637
    }
3638
    while (I2C_Trials < Trials);
3639
 
3640
    hi2c->State = HAL_I2C_STATE_READY;
3641
 
3642
    /* Process Unlocked */
3643
    __HAL_UNLOCK(hi2c);
3644
 
3645
    return HAL_ERROR;
3646
  }
3647
  else
3648
  {
3649
    return HAL_BUSY;
3650
  }
3651
}
3652
 
3653
/**
3654
  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3655
  * @note   This interface allow to manage repeated start condition when a direction change during transfer
3656
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
3657
  *         the configuration information for the specified I2C.
3658
  * @param  DevAddress Target device address: The device 7 bits address value
3659
  *         in datasheet must be shifted to the left before calling the interface
3660
  * @param  pData Pointer to data buffer
3661
  * @param  Size Amount of data to be sent
3662
  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3663
  * @retval HAL status
3664
  */
3665
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3666
{
3667
  __IO uint32_t Prev_State = 0x00U;
3668
  __IO uint32_t count      = 0x00U;
3669
 
3670
  /* Check the parameters */
3671
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3672
 
3673
  if (hi2c->State == HAL_I2C_STATE_READY)
3674
  {
3675
    /* Check Busy Flag only if FIRST call of Master interface */
3676
    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3677
    {
3678
      /* Wait until BUSY flag is reset */
3679
      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3680
      do
3681
      {
3682
        count--;
3683
        if (count == 0U)
3684
        {
3685
          hi2c->PreviousState       = I2C_STATE_NONE;
3686
          hi2c->State               = HAL_I2C_STATE_READY;
3687
          hi2c->Mode                = HAL_I2C_MODE_NONE;
3688
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
3689
 
3690
          return HAL_BUSY;
3691
        }
3692
      }
3693
      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3694
    }
3695
 
3696
    /* Process Locked */
3697
    __HAL_LOCK(hi2c);
3698
 
3699
    /* Check if the I2C is already enabled */
3700
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3701
    {
3702
      /* Enable I2C peripheral */
3703
      __HAL_I2C_ENABLE(hi2c);
3704
    }
3705
 
3706
    /* Disable Pos */
3707
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3708
 
3709
    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
3710
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
3711
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3712
 
3713
    /* Prepare transfer parameters */
3714
    hi2c->pBuffPtr    = pData;
3715
    hi2c->XferCount   = Size;
3716
    hi2c->XferSize    = hi2c->XferCount;
3717
    hi2c->XferOptions = XferOptions;
3718
    hi2c->Devaddress  = DevAddress;
3719
 
3720
    Prev_State = hi2c->PreviousState;
3721
 
3722
    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3723
    /* Mean Previous state is same as current state */
3724
    if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3725
    {
3726
      /* Generate Start */
3727
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3728
    }
3729
 
3730
    /* Process Unlocked */
3731
    __HAL_UNLOCK(hi2c);
3732
 
3733
    /* Note : The I2C interrupts must be enabled after unlocking current process
3734
    to avoid the risk of I2C interrupt handle execution before current
3735
    process unlock */
3736
 
3737
    /* Enable EVT, BUF and ERR interrupt */
3738
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3739
 
3740
    return HAL_OK;
3741
  }
3742
  else
3743
  {
3744
    return HAL_BUSY;
3745
  }
3746
}
3747
 
3748
/**
3749
  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3750
  * @note   This interface allow to manage repeated start condition when a direction change during transfer
3751
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
3752
  *         the configuration information for the specified I2C.
3753
  * @param  DevAddress Target device address: The device 7 bits address value
3754
  *         in datasheet must be shifted to the left before calling the interface
3755
  * @param  pData Pointer to data buffer
3756
  * @param  Size Amount of data to be sent
3757
  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3758
  * @retval HAL status
3759
  */
3760
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3761
{
3762
  __IO uint32_t Prev_State = 0x00U;
3763
  __IO uint32_t count      = 0x00U;
3764
  HAL_StatusTypeDef dmaxferstatus;
3765
 
3766
  /* Check the parameters */
3767
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3768
 
3769
  if (hi2c->State == HAL_I2C_STATE_READY)
3770
  {
3771
    /* Check Busy Flag only if FIRST call of Master interface */
3772
    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3773
    {
3774
      /* Wait until BUSY flag is reset */
3775
      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3776
      do
3777
      {
3778
        count--;
3779
        if (count == 0U)
3780
        {
3781
          hi2c->PreviousState       = I2C_STATE_NONE;
3782
          hi2c->State               = HAL_I2C_STATE_READY;
3783
          hi2c->Mode                = HAL_I2C_MODE_NONE;
3784
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
3785
 
3786
          return HAL_BUSY;
3787
        }
3788
      }
3789
      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3790
    }
3791
 
3792
    /* Process Locked */
3793
    __HAL_LOCK(hi2c);
3794
 
3795
    /* Check if the I2C is already enabled */
3796
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3797
    {
3798
      /* Enable I2C peripheral */
3799
      __HAL_I2C_ENABLE(hi2c);
3800
    }
3801
 
3802
    /* Disable Pos */
3803
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3804
 
3805
    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
3806
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
3807
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3808
 
3809
    /* Prepare transfer parameters */
3810
    hi2c->pBuffPtr    = pData;
3811
    hi2c->XferCount   = Size;
3812
    hi2c->XferSize    = hi2c->XferCount;
3813
    hi2c->XferOptions = XferOptions;
3814
    hi2c->Devaddress  = DevAddress;
3815
 
3816
    Prev_State = hi2c->PreviousState;
3817
 
3818
    if (hi2c->XferSize > 0U)
3819
    {
3820
      if (hi2c->hdmatx != NULL)
3821
      {
3822
        /* Set the I2C DMA transfer complete callback */
3823
        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3824
 
3825
        /* Set the DMA error callback */
3826
        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3827
 
3828
        /* Set the unused DMA callbacks to NULL */
3829
        hi2c->hdmatx->XferHalfCpltCallback = NULL;
3830
        hi2c->hdmatx->XferAbortCallback = NULL;
3831
 
3832
        /* Enable the DMA channel */
3833
        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3834
      }
3835
      else
3836
      {
3837
        /* Update I2C state */
3838
        hi2c->State     = HAL_I2C_STATE_READY;
3839
        hi2c->Mode      = HAL_I2C_MODE_NONE;
3840
 
3841
        /* Update I2C error code */
3842
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3843
 
3844
        /* Process Unlocked */
3845
        __HAL_UNLOCK(hi2c);
3846
 
3847
        return HAL_ERROR;
3848
      }
3849
 
3850
      if (dmaxferstatus == HAL_OK)
3851
      {
3852
        /* Enable Acknowledge */
3853
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3854
 
3855
        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3856
        /* Mean Previous state is same as current state */
3857
        if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3858
        {
3859
          /* Generate Start */
3860
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3861
        }
3862
 
3863
        /* Process Unlocked */
3864
        __HAL_UNLOCK(hi2c);
3865
 
3866
        /* Note : The I2C interrupts must be enabled after unlocking current process
3867
        to avoid the risk of I2C interrupt handle execution before current
3868
        process unlock */
3869
 
3870
        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3871
        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3872
        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3873
        {
3874
          /* Enable DMA Request */
3875
          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3876
        }
3877
 
3878
        /* Enable EVT and ERR interrupt */
3879
        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3880
      }
3881
      else
3882
      {
3883
        /* Update I2C state */
3884
        hi2c->State     = HAL_I2C_STATE_READY;
3885
        hi2c->Mode      = HAL_I2C_MODE_NONE;
3886
 
3887
        /* Update I2C error code */
3888
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3889
 
3890
        /* Process Unlocked */
3891
        __HAL_UNLOCK(hi2c);
3892
 
3893
        return HAL_ERROR;
3894
      }
3895
    }
3896
    else
3897
    {
3898
      /* Enable Acknowledge */
3899
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3900
 
3901
      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3902
      /* Mean Previous state is same as current state */
3903
      if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3904
      {
3905
        /* Generate Start */
3906
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3907
      }
3908
 
3909
      /* Process Unlocked */
3910
      __HAL_UNLOCK(hi2c);
3911
 
3912
      /* Note : The I2C interrupts must be enabled after unlocking current process
3913
      to avoid the risk of I2C interrupt handle execution before current
3914
      process unlock */
3915
 
3916
      /* Enable EVT, BUF and ERR interrupt */
3917
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3918
    }
3919
 
3920
    return HAL_OK;
3921
  }
3922
  else
3923
  {
3924
    return HAL_BUSY;
3925
  }
3926
}
3927
 
3928
/**
3929
  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3930
  * @note   This interface allow to manage repeated start condition when a direction change during transfer
3931
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
3932
  *         the configuration information for the specified I2C.
3933
  * @param  DevAddress Target device address: The device 7 bits address value
3934
  *         in datasheet must be shifted to the left before calling the interface
3935
  * @param  pData Pointer to data buffer
3936
  * @param  Size Amount of data to be sent
3937
  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3938
  * @retval HAL status
3939
  */
3940
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3941
{
3942
  __IO uint32_t Prev_State = 0x00U;
3943
  __IO uint32_t count = 0U;
3944
  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3945
 
3946
  /* Check the parameters */
3947
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3948
 
3949
  if (hi2c->State == HAL_I2C_STATE_READY)
3950
  {
3951
    /* Check Busy Flag only if FIRST call of Master interface */
3952
    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3953
    {
3954
      /* Wait until BUSY flag is reset */
3955
      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3956
      do
3957
      {
3958
        count--;
3959
        if (count == 0U)
3960
        {
3961
          hi2c->PreviousState       = I2C_STATE_NONE;
3962
          hi2c->State               = HAL_I2C_STATE_READY;
3963
          hi2c->Mode                = HAL_I2C_MODE_NONE;
3964
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
3965
 
3966
          return HAL_BUSY;
3967
        }
3968
      }
3969
      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3970
    }
3971
 
3972
    /* Process Locked */
3973
    __HAL_LOCK(hi2c);
3974
 
3975
    /* Check if the I2C is already enabled */
3976
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3977
    {
3978
      /* Enable I2C peripheral */
3979
      __HAL_I2C_ENABLE(hi2c);
3980
    }
3981
 
3982
    /* Disable Pos */
3983
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3984
 
3985
    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
3986
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
3987
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3988
 
3989
    /* Prepare transfer parameters */
3990
    hi2c->pBuffPtr    = pData;
3991
    hi2c->XferCount   = Size;
3992
    hi2c->XferSize    = hi2c->XferCount;
3993
    hi2c->XferOptions = XferOptions;
3994
    hi2c->Devaddress  = DevAddress;
3995
 
3996
    Prev_State = hi2c->PreviousState;
3997
 
3998
    if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3999
    {
4000
      if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
4001
      {
4002
        /* Disable Acknowledge */
4003
        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4004
 
4005
        /* Enable Pos */
4006
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4007
 
4008
        /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
4009
        enableIT &= ~I2C_IT_BUF;
4010
      }
4011
      else
4012
      {
4013
        /* Enable Acknowledge */
4014
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4015
      }
4016
    }
4017
    else
4018
    {
4019
      /* Enable Acknowledge */
4020
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4021
    }
4022
 
4023
    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4024
    /* Mean Previous state is same as current state */
4025
    if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4026
    {
4027
      /* Generate Start */
4028
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4029
    }
4030
 
4031
    /* Process Unlocked */
4032
    __HAL_UNLOCK(hi2c);
4033
 
4034
    /* Note : The I2C interrupts must be enabled after unlocking current process
4035
    to avoid the risk of I2C interrupt handle execution before current
4036
    process unlock */
4037
 
4038
    /* Enable interrupts */
4039
    __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4040
 
4041
    return HAL_OK;
4042
  }
4043
  else
4044
  {
4045
    return HAL_BUSY;
4046
  }
4047
}
4048
 
4049
/**
4050
  * @brief  Sequential receive in master mode an amount of data in non-blocking mode with DMA
4051
  * @note   This interface allow to manage repeated start condition when a direction change during transfer
4052
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
4053
  *         the configuration information for the specified I2C.
4054
  * @param  DevAddress Target device address: The device 7 bits address value
4055
  *         in datasheet must be shifted to the left before calling the interface
4056
  * @param  pData Pointer to data buffer
4057
  * @param  Size Amount of data to be sent
4058
  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4059
  * @retval HAL status
4060
  */
4061
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4062
{
4063
  __IO uint32_t Prev_State = 0x00U;
4064
  __IO uint32_t count = 0U;
4065
  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4066
  HAL_StatusTypeDef dmaxferstatus;
4067
 
4068
  /* Check the parameters */
4069
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4070
 
4071
  if (hi2c->State == HAL_I2C_STATE_READY)
4072
  {
4073
    /* Check Busy Flag only if FIRST call of Master interface */
4074
    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
4075
    {
4076
      /* Wait until BUSY flag is reset */
4077
      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
4078
      do
4079
      {
4080
        count--;
4081
        if (count == 0U)
4082
        {
4083
          hi2c->PreviousState       = I2C_STATE_NONE;
4084
          hi2c->State               = HAL_I2C_STATE_READY;
4085
          hi2c->Mode                = HAL_I2C_MODE_NONE;
4086
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
4087
 
4088
          return HAL_BUSY;
4089
        }
4090
      }
4091
      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
4092
    }
4093
 
4094
    /* Process Locked */
4095
    __HAL_LOCK(hi2c);
4096
 
4097
    /* Check if the I2C is already enabled */
4098
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4099
    {
4100
      /* Enable I2C peripheral */
4101
      __HAL_I2C_ENABLE(hi2c);
4102
    }
4103
 
4104
    /* Disable Pos */
4105
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4106
 
4107
    /* Clear Last DMA bit */
4108
    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4109
 
4110
    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
4111
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
4112
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4113
 
4114
    /* Prepare transfer parameters */
4115
    hi2c->pBuffPtr    = pData;
4116
    hi2c->XferCount   = Size;
4117
    hi2c->XferSize    = hi2c->XferCount;
4118
    hi2c->XferOptions = XferOptions;
4119
    hi2c->Devaddress  = DevAddress;
4120
 
4121
    Prev_State = hi2c->PreviousState;
4122
 
4123
    if (hi2c->XferSize > 0U)
4124
    {
4125
      if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
4126
      {
4127
        if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
4128
        {
4129
          /* Disable Acknowledge */
4130
          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4131
 
4132
          /* Enable Pos */
4133
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4134
 
4135
          /* Enable Last DMA bit */
4136
          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4137
        }
4138
        else
4139
        {
4140
          /* Enable Acknowledge */
4141
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4142
        }
4143
      }
4144
      else
4145
      {
4146
        /* Enable Acknowledge */
4147
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4148
 
4149
        if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4150
        {
4151
          /* Enable Last DMA bit */
4152
          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4153
        }
4154
      }
4155
      if (hi2c->hdmarx != NULL)
4156
      {
4157
        /* Set the I2C DMA transfer complete callback */
4158
        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4159
 
4160
        /* Set the DMA error callback */
4161
        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4162
 
4163
        /* Set the unused DMA callbacks to NULL */
4164
        hi2c->hdmarx->XferHalfCpltCallback = NULL;
4165
        hi2c->hdmarx->XferAbortCallback = NULL;
4166
 
4167
        /* Enable the DMA channel */
4168
        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4169
      }
4170
      else
4171
      {
4172
        /* Update I2C state */
4173
        hi2c->State     = HAL_I2C_STATE_READY;
4174
        hi2c->Mode      = HAL_I2C_MODE_NONE;
4175
 
4176
        /* Update I2C error code */
4177
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4178
 
4179
        /* Process Unlocked */
4180
        __HAL_UNLOCK(hi2c);
4181
 
4182
        return HAL_ERROR;
4183
      }
4184
      if (dmaxferstatus == HAL_OK)
4185
      {
4186
        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4187
        /* Mean Previous state is same as current state */
4188
        if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4189
        {
4190
          /* Generate Start */
4191
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4192
 
4193
          /* Update interrupt for only EVT and ERR */
4194
          enableIT = (I2C_IT_EVT | I2C_IT_ERR);
4195
        }
4196
        else
4197
        {
4198
          /* Update interrupt for only ERR */
4199
          enableIT = I2C_IT_ERR;
4200
        }
4201
 
4202
        /* Process Unlocked */
4203
        __HAL_UNLOCK(hi2c);
4204
 
4205
        /* Note : The I2C interrupts must be enabled after unlocking current process
4206
        to avoid the risk of I2C interrupt handle execution before current
4207
        process unlock */
4208
 
4209
        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
4210
        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
4211
        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4212
        {
4213
          /* Enable DMA Request */
4214
          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4215
        }
4216
 
4217
        /* Enable EVT and ERR interrupt */
4218
        __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4219
      }
4220
      else
4221
      {
4222
        /* Update I2C state */
4223
        hi2c->State     = HAL_I2C_STATE_READY;
4224
        hi2c->Mode      = HAL_I2C_MODE_NONE;
4225
 
4226
        /* Update I2C error code */
4227
        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4228
 
4229
        /* Process Unlocked */
4230
        __HAL_UNLOCK(hi2c);
4231
 
4232
        return HAL_ERROR;
4233
      }
4234
    }
4235
    else
4236
    {
4237
      /* Enable Acknowledge */
4238
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4239
 
4240
      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4241
      /* Mean Previous state is same as current state */
4242
      if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4243
      {
4244
        /* Generate Start */
4245
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4246
      }
4247
 
4248
      /* Process Unlocked */
4249
      __HAL_UNLOCK(hi2c);
4250
 
4251
      /* Note : The I2C interrupts must be enabled after unlocking current process
4252
      to avoid the risk of I2C interrupt handle execution before current
4253
      process unlock */
4254
 
4255
      /* Enable interrupts */
4256
      __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4257
    }
4258
    return HAL_OK;
4259
  }
4260
  else
4261
  {
4262
    return HAL_BUSY;
4263
  }
4264
}
4265
 
4266
/**
4267
  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
4268
  * @note   This interface allow to manage repeated start condition when a direction change during transfer
4269
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
4270
  *         the configuration information for the specified I2C.
4271
  * @param  pData Pointer to data buffer
4272
  * @param  Size Amount of data to be sent
4273
  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4274
  * @retval HAL status
4275
  */
4276
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4277
{
4278
  /* Check the parameters */
4279
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4280
 
4281
  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4282
  {
4283
    if ((pData == NULL) || (Size == 0U))
4284
    {
4285
      return  HAL_ERROR;
4286
    }
4287
 
4288
    /* Process Locked */
4289
    __HAL_LOCK(hi2c);
4290
 
4291
    /* Check if the I2C is already enabled */
4292
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4293
    {
4294
      /* Enable I2C peripheral */
4295
      __HAL_I2C_ENABLE(hi2c);
4296
    }
4297
 
4298
    /* Disable Pos */
4299
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4300
 
4301
    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
4302
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
4303
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4304
 
4305
    /* Prepare transfer parameters */
4306
    hi2c->pBuffPtr    = pData;
4307
    hi2c->XferCount   = Size;
4308
    hi2c->XferSize    = hi2c->XferCount;
4309
    hi2c->XferOptions = XferOptions;
4310
 
4311
    /* Clear ADDR flag */
4312
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4313
 
4314
    /* Process Unlocked */
4315
    __HAL_UNLOCK(hi2c);
4316
 
4317
    /* Note : The I2C interrupts must be enabled after unlocking current process
4318
              to avoid the risk of I2C interrupt handle execution before current
4319
              process unlock */
4320
 
4321
    /* Enable EVT, BUF and ERR interrupt */
4322
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4323
 
4324
    return HAL_OK;
4325
  }
4326
  else
4327
  {
4328
    return HAL_BUSY;
4329
  }
4330
}
4331
 
4332
/**
4333
  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
4334
  * @note   This interface allow to manage repeated start condition when a direction change during transfer
4335
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
4336
  *         the configuration information for the specified I2C.
4337
  * @param  pData Pointer to data buffer
4338
  * @param  Size Amount of data to be sent
4339
  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4340
  * @retval HAL status
4341
  */
4342
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4343
{
4344
  HAL_StatusTypeDef dmaxferstatus;
4345
 
4346
  /* Check the parameters */
4347
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4348
 
4349
  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4350
  {
4351
    if ((pData == NULL) || (Size == 0U))
4352
    {
4353
      return  HAL_ERROR;
4354
    }
4355
 
4356
    /* Process Locked */
4357
    __HAL_LOCK(hi2c);
4358
 
4359
    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4360
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4361
 
4362
    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4363
    /* and then toggle the HAL slave RX state to TX state */
4364
    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4365
    {
4366
      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4367
      {
4368
        /* Abort DMA Xfer if any */
4369
        if (hi2c->hdmarx != NULL)
4370
        {
4371
          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4372
 
4373
          /* Set the I2C DMA Abort callback :
4374
           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4375
          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4376
 
4377
          /* Abort DMA RX */
4378
          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4379
          {
4380
            /* Call Directly XferAbortCallback function in case of error */
4381
            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4382
          }
4383
        }
4384
      }
4385
    }
4386
    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4387
    {
4388
      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4389
      {
4390
        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4391
 
4392
        /* Abort DMA Xfer if any */
4393
        if (hi2c->hdmatx != NULL)
4394
        {
4395
          /* Set the I2C DMA Abort callback :
4396
           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4397
          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4398
 
4399
          /* Abort DMA TX */
4400
          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4401
          {
4402
            /* Call Directly XferAbortCallback function in case of error */
4403
            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4404
          }
4405
        }
4406
      }
4407
    }
4408
    else
4409
    {
4410
      /* Nothing to do */
4411
    }
4412
 
4413
    /* Check if the I2C is already enabled */
4414
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4415
    {
4416
      /* Enable I2C peripheral */
4417
      __HAL_I2C_ENABLE(hi2c);
4418
    }
4419
 
4420
    /* Disable Pos */
4421
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4422
 
4423
    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
4424
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
4425
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4426
 
4427
    /* Prepare transfer parameters */
4428
    hi2c->pBuffPtr    = pData;
4429
    hi2c->XferCount   = Size;
4430
    hi2c->XferSize    = hi2c->XferCount;
4431
    hi2c->XferOptions = XferOptions;
4432
 
4433
    if (hi2c->hdmatx != NULL)
4434
    {
4435
      /* Set the I2C DMA transfer complete callback */
4436
      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
4437
 
4438
      /* Set the DMA error callback */
4439
      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4440
 
4441
      /* Set the unused DMA callbacks to NULL */
4442
      hi2c->hdmatx->XferHalfCpltCallback = NULL;
4443
      hi2c->hdmatx->XferAbortCallback = NULL;
4444
 
4445
      /* Enable the DMA channel */
4446
      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
4447
    }
4448
    else
4449
    {
4450
      /* Update I2C state */
4451
      hi2c->State     = HAL_I2C_STATE_LISTEN;
4452
      hi2c->Mode      = HAL_I2C_MODE_NONE;
4453
 
4454
      /* Update I2C error code */
4455
      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4456
 
4457
      /* Process Unlocked */
4458
      __HAL_UNLOCK(hi2c);
4459
 
4460
      return HAL_ERROR;
4461
    }
4462
 
4463
    if (dmaxferstatus == HAL_OK)
4464
    {
4465
      /* Enable Address Acknowledge */
4466
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4467
 
4468
      /* Clear ADDR flag */
4469
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4470
 
4471
      /* Process Unlocked */
4472
      __HAL_UNLOCK(hi2c);
4473
 
4474
      /* Note : The I2C interrupts must be enabled after unlocking current process
4475
      to avoid the risk of I2C interrupt handle execution before current
4476
      process unlock */
4477
      /* Enable EVT and ERR interrupt */
4478
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4479
 
4480
      /* Enable DMA Request */
4481
      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
4482
 
4483
      return HAL_OK;
4484
    }
4485
    else
4486
    {
4487
      /* Update I2C state */
4488
      hi2c->State     = HAL_I2C_STATE_READY;
4489
      hi2c->Mode      = HAL_I2C_MODE_NONE;
4490
 
4491
      /* Update I2C error code */
4492
      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4493
 
4494
      /* Process Unlocked */
4495
      __HAL_UNLOCK(hi2c);
4496
 
4497
      return HAL_ERROR;
4498
    }
4499
  }
4500
  else
4501
  {
4502
    return HAL_BUSY;
4503
  }
4504
}
4505
 
4506
/**
4507
  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
4508
  * @note   This interface allow to manage repeated start condition when a direction change during transfer
4509
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
4510
  *         the configuration information for the specified I2C.
4511
  * @param  pData Pointer to data buffer
4512
  * @param  Size Amount of data to be sent
4513
  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4514
  * @retval HAL status
4515
  */
4516
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4517
{
4518
  /* Check the parameters */
4519
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4520
 
4521
  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4522
  {
4523
    if ((pData == NULL) || (Size == 0U))
4524
    {
4525
      return  HAL_ERROR;
4526
    }
4527
 
4528
    /* Process Locked */
4529
    __HAL_LOCK(hi2c);
4530
 
4531
    /* Check if the I2C is already enabled */
4532
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4533
    {
4534
      /* Enable I2C peripheral */
4535
      __HAL_I2C_ENABLE(hi2c);
4536
    }
4537
 
4538
    /* Disable Pos */
4539
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4540
 
4541
    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
4542
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
4543
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4544
 
4545
    /* Prepare transfer parameters */
4546
    hi2c->pBuffPtr    = pData;
4547
    hi2c->XferCount   = Size;
4548
    hi2c->XferSize    = hi2c->XferCount;
4549
    hi2c->XferOptions = XferOptions;
4550
 
4551
    /* Clear ADDR flag */
4552
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4553
 
4554
    /* Process Unlocked */
4555
    __HAL_UNLOCK(hi2c);
4556
 
4557
    /* Note : The I2C interrupts must be enabled after unlocking current process
4558
              to avoid the risk of I2C interrupt handle execution before current
4559
              process unlock */
4560
 
4561
    /* Enable EVT, BUF and ERR interrupt */
4562
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4563
 
4564
    return HAL_OK;
4565
  }
4566
  else
4567
  {
4568
    return HAL_BUSY;
4569
  }
4570
}
4571
 
4572
/**
4573
  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with DMA
4574
  * @note   This interface allow to manage repeated start condition when a direction change during transfer
4575
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
4576
  *         the configuration information for the specified I2C.
4577
  * @param  pData Pointer to data buffer
4578
  * @param  Size Amount of data to be sent
4579
  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4580
  * @retval HAL status
4581
  */
4582
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4583
{
4584
  HAL_StatusTypeDef dmaxferstatus;
4585
 
4586
  /* Check the parameters */
4587
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4588
 
4589
  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4590
  {
4591
    if ((pData == NULL) || (Size == 0U))
4592
    {
4593
      return  HAL_ERROR;
4594
    }
4595
 
4596
    /* Process Locked */
4597
    __HAL_LOCK(hi2c);
4598
 
4599
    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4600
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4601
 
4602
    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4603
    /* and then toggle the HAL slave RX state to TX state */
4604
    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4605
    {
4606
      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4607
      {
4608
        /* Abort DMA Xfer if any */
4609
        if (hi2c->hdmarx != NULL)
4610
        {
4611
          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4612
 
4613
          /* Set the I2C DMA Abort callback :
4614
           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4615
          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4616
 
4617
          /* Abort DMA RX */
4618
          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4619
          {
4620
            /* Call Directly XferAbortCallback function in case of error */
4621
            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4622
          }
4623
        }
4624
      }
4625
    }
4626
    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4627
    {
4628
      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4629
      {
4630
        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4631
 
4632
        /* Abort DMA Xfer if any */
4633
        if (hi2c->hdmatx != NULL)
4634
        {
4635
          /* Set the I2C DMA Abort callback :
4636
           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4637
          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4638
 
4639
          /* Abort DMA TX */
4640
          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4641
          {
4642
            /* Call Directly XferAbortCallback function in case of error */
4643
            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4644
          }
4645
        }
4646
      }
4647
    }
4648
    else
4649
    {
4650
      /* Nothing to do */
4651
    }
4652
 
4653
    /* Check if the I2C is already enabled */
4654
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4655
    {
4656
      /* Enable I2C peripheral */
4657
      __HAL_I2C_ENABLE(hi2c);
4658
    }
4659
 
4660
    /* Disable Pos */
4661
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4662
 
4663
    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
4664
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
4665
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4666
 
4667
    /* Prepare transfer parameters */
4668
    hi2c->pBuffPtr    = pData;
4669
    hi2c->XferCount   = Size;
4670
    hi2c->XferSize    = hi2c->XferCount;
4671
    hi2c->XferOptions = XferOptions;
4672
 
4673
    if (hi2c->hdmarx != NULL)
4674
    {
4675
      /* Set the I2C DMA transfer complete callback */
4676
      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4677
 
4678
      /* Set the DMA error callback */
4679
      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4680
 
4681
      /* Set the unused DMA callbacks to NULL */
4682
      hi2c->hdmarx->XferHalfCpltCallback = NULL;
4683
      hi2c->hdmarx->XferAbortCallback = NULL;
4684
 
4685
      /* Enable the DMA channel */
4686
      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4687
    }
4688
    else
4689
    {
4690
      /* Update I2C state */
4691
      hi2c->State     = HAL_I2C_STATE_LISTEN;
4692
      hi2c->Mode      = HAL_I2C_MODE_NONE;
4693
 
4694
      /* Update I2C error code */
4695
      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4696
 
4697
      /* Process Unlocked */
4698
      __HAL_UNLOCK(hi2c);
4699
 
4700
      return HAL_ERROR;
4701
    }
4702
 
4703
    if (dmaxferstatus == HAL_OK)
4704
    {
4705
      /* Enable Address Acknowledge */
4706
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4707
 
4708
      /* Clear ADDR flag */
4709
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4710
 
4711
      /* Process Unlocked */
4712
      __HAL_UNLOCK(hi2c);
4713
 
4714
      /* Enable DMA Request */
4715
      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4716
 
4717
      /* Note : The I2C interrupts must be enabled after unlocking current process
4718
      to avoid the risk of I2C interrupt handle execution before current
4719
      process unlock */
4720
      /* Enable EVT and ERR interrupt */
4721
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4722
 
4723
      return HAL_OK;
4724
    }
4725
    else
4726
    {
4727
      /* Update I2C state */
4728
      hi2c->State     = HAL_I2C_STATE_READY;
4729
      hi2c->Mode      = HAL_I2C_MODE_NONE;
4730
 
4731
      /* Update I2C error code */
4732
      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4733
 
4734
      /* Process Unlocked */
4735
      __HAL_UNLOCK(hi2c);
4736
 
4737
      return HAL_ERROR;
4738
    }
4739
  }
4740
  else
4741
  {
4742
    return HAL_BUSY;
4743
  }
4744
}
4745
 
4746
/**
4747
  * @brief  Enable the Address listen mode with Interrupt.
4748
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
4749
  *                the configuration information for the specified I2C.
4750
  * @retval HAL status
4751
  */
4752
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4753
{
4754
  if (hi2c->State == HAL_I2C_STATE_READY)
4755
  {
4756
    hi2c->State = HAL_I2C_STATE_LISTEN;
4757
 
4758
    /* Check if the I2C is already enabled */
4759
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4760
    {
4761
      /* Enable I2C peripheral */
4762
      __HAL_I2C_ENABLE(hi2c);
4763
    }
4764
 
4765
    /* Enable Address Acknowledge */
4766
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4767
 
4768
    /* Enable EVT and ERR interrupt */
4769
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4770
 
4771
    return HAL_OK;
4772
  }
4773
  else
4774
  {
4775
    return HAL_BUSY;
4776
  }
4777
}
4778
 
4779
/**
4780
  * @brief  Disable the Address listen mode with Interrupt.
4781
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
4782
  *                the configuration information for the specified I2C.
4783
  * @retval HAL status
4784
  */
4785
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4786
{
4787
  /* Declaration of tmp to prevent undefined behavior of volatile usage */
4788
  uint32_t tmp;
4789
 
4790
  /* Disable Address listen mode only if a transfer is not ongoing */
4791
  if (hi2c->State == HAL_I2C_STATE_LISTEN)
4792
  {
4793
    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4794
    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4795
    hi2c->State = HAL_I2C_STATE_READY;
4796
    hi2c->Mode = HAL_I2C_MODE_NONE;
4797
 
4798
    /* Disable Address Acknowledge */
4799
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4800
 
4801
    /* Disable EVT and ERR interrupt */
4802
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4803
 
4804
    return HAL_OK;
4805
  }
4806
  else
4807
  {
4808
    return HAL_BUSY;
4809
  }
4810
}
4811
 
4812
/**
4813
  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
4814
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
4815
  *         the configuration information for the specified I2C.
4816
  * @param  DevAddress Target device address: The device 7 bits address value
4817
  *         in datasheet must be shifted to the left before calling the interface
4818
  * @retval HAL status
4819
  */
4820
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4821
{
4822
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4823
  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
4824
 
4825
  /* Prevent unused argument(s) compilation warning */
4826
  UNUSED(DevAddress);
4827
 
4828
  /* Abort Master transfer during Receive or Transmit process    */
4829
  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
4830
  {
4831
    /* Process Locked */
4832
    __HAL_LOCK(hi2c);
4833
 
4834
    hi2c->PreviousState = I2C_STATE_NONE;
4835
    hi2c->State = HAL_I2C_STATE_ABORT;
4836
 
4837
    /* Disable Acknowledge */
4838
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4839
 
4840
    /* Generate Stop */
4841
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4842
 
4843
    hi2c->XferCount = 0U;
4844
 
4845
    /* Disable EVT, BUF and ERR interrupt */
4846
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4847
 
4848
    /* Process Unlocked */
4849
    __HAL_UNLOCK(hi2c);
4850
 
4851
    /* Call the corresponding callback to inform upper layer of End of Transfer */
4852
    I2C_ITError(hi2c);
4853
 
4854
    return HAL_OK;
4855
  }
4856
  else
4857
  {
4858
    /* Wrong usage of abort function */
4859
    /* This function should be used only in case of abort monitored by master device */
4860
    /* Or periphal is not in busy state, mean there is no active sequence to be abort */
4861
    return HAL_ERROR;
4862
  }
4863
}
4864
 
4865
/**
4866
  * @}
4867
  */
4868
 
4869
/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4870
 * @{
4871
 */
4872
 
4873
/**
4874
  * @brief  This function handles I2C event interrupt request.
4875
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
4876
  *                the configuration information for the specified I2C.
4877
  * @retval None
4878
  */
4879
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4880
{
4881
  uint32_t sr1itflags;
4882
  uint32_t sr2itflags               = 0U;
4883
  uint32_t itsources                = READ_REG(hi2c->Instance->CR2);
4884
  uint32_t CurrentXferOptions       = hi2c->XferOptions;
4885
  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
4886
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
4887
 
4888
  /* Master or Memory mode selected */
4889
  if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4890
  {
4891
    sr2itflags   = READ_REG(hi2c->Instance->SR2);
4892
    sr1itflags   = READ_REG(hi2c->Instance->SR1);
4893
 
4894
    /* Exit IRQ event until Start Bit detected in case of Other frame requested */
4895
    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
4896
    {
4897
      return;
4898
    }
4899
 
4900
    /* SB Set ----------------------------------------------------------------*/
4901
    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4902
    {
4903
      /* Convert OTHER_xxx XferOptions if any */
4904
      I2C_ConvertOtherXferOptions(hi2c);
4905
 
4906
      I2C_Master_SB(hi2c);
4907
    }
4908
    /* ADD10 Set -------------------------------------------------------------*/
4909
    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4910
    {
4911
      I2C_Master_ADD10(hi2c);
4912
    }
4913
    /* ADDR Set --------------------------------------------------------------*/
4914
    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4915
    {
4916
      I2C_Master_ADDR(hi2c);
4917
    }
4918
    /* I2C in mode Transmitter -----------------------------------------------*/
4919
    else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
4920
    {
4921
      /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4922
      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4923
      {
4924
        /* TXE set and BTF reset -----------------------------------------------*/
4925
        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4926
        {
4927
          I2C_MasterTransmit_TXE(hi2c);
4928
        }
4929
        /* BTF set -------------------------------------------------------------*/
4930
        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4931
        {
4932
          if (CurrentState == HAL_I2C_STATE_BUSY_TX)
4933
          {
4934
            I2C_MasterTransmit_BTF(hi2c);
4935
          }
4936
          else /* HAL_I2C_MODE_MEM */
4937
          {
4938
            if (CurrentMode == HAL_I2C_MODE_MEM)
4939
            {
4940
              I2C_MemoryTransmit_TXE_BTF(hi2c);
4941
            }
4942
          }
4943
        }
4944
        else
4945
        {
4946
          /* Do nothing */
4947
        }
4948
      }
4949
    }
4950
    /* I2C in mode Receiver --------------------------------------------------*/
4951
    else
4952
    {
4953
      /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4954
      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4955
      {
4956
        /* RXNE set and BTF reset -----------------------------------------------*/
4957
        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4958
        {
4959
          I2C_MasterReceive_RXNE(hi2c);
4960
        }
4961
        /* BTF set -------------------------------------------------------------*/
4962
        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4963
        {
4964
          I2C_MasterReceive_BTF(hi2c);
4965
        }
4966
        else
4967
        {
4968
          /* Do nothing */
4969
        }
4970
      }
4971
    }
4972
  }
4973
  /* Slave mode selected */
4974
  else
4975
  {
4976
    /* If an error is detected, read only SR1 register to prevent */
4977
    /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
4978
    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4979
    {
4980
      sr1itflags   = READ_REG(hi2c->Instance->SR1);
4981
    }
4982
    else
4983
    {
4984
      sr2itflags   = READ_REG(hi2c->Instance->SR2);
4985
      sr1itflags   = READ_REG(hi2c->Instance->SR1);
4986
    }
4987
 
4988
    /* ADDR set --------------------------------------------------------------*/
4989
    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4990
    {
4991
      /* Now time to read SR2, this will clear ADDR flag automatically */
4992
      if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4993
      {
4994
        sr2itflags   = READ_REG(hi2c->Instance->SR2);
4995
      }
4996
      I2C_Slave_ADDR(hi2c, sr2itflags);
4997
    }
4998
    /* STOPF set --------------------------------------------------------------*/
4999
    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
5000
    {
5001
      I2C_Slave_STOPF(hi2c);
5002
    }
5003
    /* I2C in mode Transmitter -----------------------------------------------*/
5004
    else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
5005
    {
5006
      /* TXE set and BTF reset -----------------------------------------------*/
5007
      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
5008
      {
5009
        I2C_SlaveTransmit_TXE(hi2c);
5010
      }
5011
      /* BTF set -------------------------------------------------------------*/
5012
      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
5013
      {
5014
        I2C_SlaveTransmit_BTF(hi2c);
5015
      }
5016
      else
5017
      {
5018
        /* Do nothing */
5019
      }
5020
    }
5021
    /* I2C in mode Receiver --------------------------------------------------*/
5022
    else
5023
    {
5024
      /* RXNE set and BTF reset ----------------------------------------------*/
5025
      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
5026
      {
5027
        I2C_SlaveReceive_RXNE(hi2c);
5028
      }
5029
      /* BTF set -------------------------------------------------------------*/
5030
      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
5031
      {
5032
        I2C_SlaveReceive_BTF(hi2c);
5033
      }
5034
      else
5035
      {
5036
        /* Do nothing */
5037
      }
5038
    }
5039
  }
5040
}
5041
 
5042
/**
5043
  * @brief  This function handles I2C error interrupt request.
5044
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5045
  *                the configuration information for the specified I2C.
5046
  * @retval None
5047
  */
5048
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
5049
{
5050
  HAL_I2C_ModeTypeDef tmp1;
5051
  uint32_t tmp2;
5052
  HAL_I2C_StateTypeDef tmp3;
5053
  uint32_t tmp4;
5054
  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
5055
  uint32_t itsources  = READ_REG(hi2c->Instance->CR2);
5056
  uint32_t error      = HAL_I2C_ERROR_NONE;
5057
  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
5058
 
5059
  /* I2C Bus error interrupt occurred ----------------------------------------*/
5060
  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
5061
  {
5062
    error |= HAL_I2C_ERROR_BERR;
5063
 
5064
    /* Clear BERR flag */
5065
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
5066
 
5067
    /* Workaround: Start cannot be generated after a misplaced Stop */
5068
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST);
5069
  }
5070
 
5071
  /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
5072
  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
5073
  {
5074
    error |= HAL_I2C_ERROR_ARLO;
5075
 
5076
    /* Clear ARLO flag */
5077
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
5078
  }
5079
 
5080
  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
5081
  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
5082
  {
5083
    tmp1 = CurrentMode;
5084
    tmp2 = hi2c->XferCount;
5085
    tmp3 = hi2c->State;
5086
    tmp4 = hi2c->PreviousState;
5087
    if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
5088
        ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
5089
         ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
5090
    {
5091
      I2C_Slave_AF(hi2c);
5092
    }
5093
    else
5094
    {
5095
      /* Clear AF flag */
5096
      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5097
 
5098
      error |= HAL_I2C_ERROR_AF;
5099
 
5100
      /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
5101
      if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
5102
      {
5103
        /* Generate Stop */
5104
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5105
      }
5106
    }
5107
  }
5108
 
5109
  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
5110
  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
5111
  {
5112
    error |= HAL_I2C_ERROR_OVR;
5113
    /* Clear OVR flag */
5114
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
5115
  }
5116
 
5117
  /* Call the Error Callback in case of Error detected -----------------------*/
5118
  if (error != HAL_I2C_ERROR_NONE)
5119
  {
5120
    hi2c->ErrorCode |= error;
5121
    I2C_ITError(hi2c);
5122
  }
5123
}
5124
 
5125
/**
5126
  * @brief  Master Tx Transfer completed callback.
5127
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5128
  *                the configuration information for the specified I2C.
5129
  * @retval None
5130
  */
5131
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
5132
{
5133
  /* Prevent unused argument(s) compilation warning */
5134
  UNUSED(hi2c);
5135
 
5136
  /* NOTE : This function should not be modified, when the callback is needed,
5137
            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
5138
   */
5139
}
5140
 
5141
/**
5142
  * @brief  Master Rx Transfer completed callback.
5143
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5144
  *                the configuration information for the specified I2C.
5145
  * @retval None
5146
  */
5147
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
5148
{
5149
  /* Prevent unused argument(s) compilation warning */
5150
  UNUSED(hi2c);
5151
 
5152
  /* NOTE : This function should not be modified, when the callback is needed,
5153
            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
5154
   */
5155
}
5156
 
5157
/** @brief  Slave Tx Transfer completed callback.
5158
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5159
  *                the configuration information for the specified I2C.
5160
  * @retval None
5161
  */
5162
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
5163
{
5164
  /* Prevent unused argument(s) compilation warning */
5165
  UNUSED(hi2c);
5166
 
5167
  /* NOTE : This function should not be modified, when the callback is needed,
5168
            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
5169
   */
5170
}
5171
 
5172
/**
5173
  * @brief  Slave Rx Transfer completed callback.
5174
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5175
  *                the configuration information for the specified I2C.
5176
  * @retval None
5177
  */
5178
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5179
{
5180
  /* Prevent unused argument(s) compilation warning */
5181
  UNUSED(hi2c);
5182
 
5183
  /* NOTE : This function should not be modified, when the callback is needed,
5184
            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5185
   */
5186
}
5187
 
5188
/**
5189
  * @brief  Slave Address Match callback.
5190
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5191
  *                the configuration information for the specified I2C.
5192
  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
5193
  * @param  AddrMatchCode Address Match Code
5194
  * @retval None
5195
  */
5196
__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5197
{
5198
  /* Prevent unused argument(s) compilation warning */
5199
  UNUSED(hi2c);
5200
  UNUSED(TransferDirection);
5201
  UNUSED(AddrMatchCode);
5202
 
5203
  /* NOTE : This function should not be modified, when the callback is needed,
5204
            the HAL_I2C_AddrCallback() could be implemented in the user file
5205
   */
5206
}
5207
 
5208
/**
5209
  * @brief  Listen Complete callback.
5210
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5211
  *                the configuration information for the specified I2C.
5212
  * @retval None
5213
  */
5214
__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5215
{
5216
  /* Prevent unused argument(s) compilation warning */
5217
  UNUSED(hi2c);
5218
 
5219
  /* NOTE : This function should not be modified, when the callback is needed,
5220
            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5221
  */
5222
}
5223
 
5224
/**
5225
  * @brief  Memory Tx Transfer completed callback.
5226
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5227
  *                the configuration information for the specified I2C.
5228
  * @retval None
5229
  */
5230
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5231
{
5232
  /* Prevent unused argument(s) compilation warning */
5233
  UNUSED(hi2c);
5234
 
5235
  /* NOTE : This function should not be modified, when the callback is needed,
5236
            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5237
   */
5238
}
5239
 
5240
/**
5241
  * @brief  Memory Rx Transfer completed callback.
5242
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5243
  *                the configuration information for the specified I2C.
5244
  * @retval None
5245
  */
5246
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5247
{
5248
  /* Prevent unused argument(s) compilation warning */
5249
  UNUSED(hi2c);
5250
 
5251
  /* NOTE : This function should not be modified, when the callback is needed,
5252
            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5253
   */
5254
}
5255
 
5256
/**
5257
  * @brief  I2C error callback.
5258
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5259
  *                the configuration information for the specified I2C.
5260
  * @retval None
5261
  */
5262
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5263
{
5264
  /* Prevent unused argument(s) compilation warning */
5265
  UNUSED(hi2c);
5266
 
5267
  /* NOTE : This function should not be modified, when the callback is needed,
5268
            the HAL_I2C_ErrorCallback could be implemented in the user file
5269
   */
5270
}
5271
 
5272
/**
5273
  * @brief  I2C abort callback.
5274
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5275
  *                the configuration information for the specified I2C.
5276
  * @retval None
5277
  */
5278
__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5279
{
5280
  /* Prevent unused argument(s) compilation warning */
5281
  UNUSED(hi2c);
5282
 
5283
  /* NOTE : This function should not be modified, when the callback is needed,
5284
            the HAL_I2C_AbortCpltCallback could be implemented in the user file
5285
   */
5286
}
5287
 
5288
/**
5289
  * @}
5290
  */
5291
 
5292
/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5293
 *  @brief   Peripheral State, Mode and Error functions
5294
  *
5295
@verbatim
5296
 ===============================================================================
5297
            ##### Peripheral State, Mode and Error functions #####
5298
 ===============================================================================
5299
    [..]
5300
    This subsection permit to get in run-time the status of the peripheral
5301
    and the data flow.
5302
 
5303
@endverbatim
5304
  * @{
5305
  */
5306
 
5307
/**
5308
  * @brief  Return the I2C handle state.
5309
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5310
  *                the configuration information for the specified I2C.
5311
  * @retval HAL state
5312
  */
5313
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
5314
{
5315
  /* Return I2C handle state */
5316
  return hi2c->State;
5317
}
5318
 
5319
/**
5320
  * @brief  Returns the I2C Master, Slave, Memory or no mode.
5321
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5322
  *         the configuration information for I2C module
5323
  * @retval HAL mode
5324
  */
5325
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
5326
{
5327
  return hi2c->Mode;
5328
}
5329
 
5330
/**
5331
  * @brief  Return the I2C error code.
5332
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5333
  *              the configuration information for the specified I2C.
5334
  * @retval I2C Error Code
5335
  */
5336
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
5337
{
5338
  return hi2c->ErrorCode;
5339
}
5340
 
5341
/**
5342
  * @}
5343
  */
5344
 
5345
/**
5346
  * @}
5347
  */
5348
 
5349
/** @addtogroup I2C_Private_Functions
5350
  * @{
5351
  */
5352
 
5353
/**
5354
  * @brief  Handle TXE flag for Master
5355
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5356
  *         the configuration information for I2C module
5357
  * @retval None
5358
  */
5359
static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
5360
{
5361
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5362
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5363
  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
5364
  uint32_t CurrentXferOptions       = hi2c->XferOptions;
5365
 
5366
  if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5367
  {
5368
    /* Call TxCpltCallback() directly if no stop mode is set */
5369
    if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5370
    {
5371
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5372
 
5373
      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5374
      hi2c->Mode = HAL_I2C_MODE_NONE;
5375
      hi2c->State = HAL_I2C_STATE_READY;
5376
 
5377
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5378
      hi2c->MasterTxCpltCallback(hi2c);
5379
#else
5380
      HAL_I2C_MasterTxCpltCallback(hi2c);
5381
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5382
    }
5383
    else /* Generate Stop condition then Call TxCpltCallback() */
5384
    {
5385
      /* Disable EVT, BUF and ERR interrupt */
5386
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5387
 
5388
      /* Generate Stop */
5389
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5390
 
5391
      hi2c->PreviousState = I2C_STATE_NONE;
5392
      hi2c->State = HAL_I2C_STATE_READY;
5393
 
5394
      if (hi2c->Mode == HAL_I2C_MODE_MEM)
5395
      {
5396
        hi2c->Mode = HAL_I2C_MODE_NONE;
5397
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5398
        hi2c->MemTxCpltCallback(hi2c);
5399
#else
5400
        HAL_I2C_MemTxCpltCallback(hi2c);
5401
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5402
      }
5403
      else
5404
      {
5405
        hi2c->Mode = HAL_I2C_MODE_NONE;
5406
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5407
        hi2c->MasterTxCpltCallback(hi2c);
5408
#else
5409
        HAL_I2C_MasterTxCpltCallback(hi2c);
5410
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5411
      }
5412
    }
5413
  }
5414
  else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
5415
           ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
5416
  {
5417
    if (hi2c->XferCount == 0U)
5418
    {
5419
      /* Disable BUF interrupt */
5420
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5421
    }
5422
    else
5423
    {
5424
      if (hi2c->Mode == HAL_I2C_MODE_MEM)
5425
      {
5426
        I2C_MemoryTransmit_TXE_BTF(hi2c);
5427
      }
5428
      else
5429
      {
5430
        /* Write data to DR */
5431
        hi2c->Instance->DR = *hi2c->pBuffPtr;
5432
 
5433
        /* Increment Buffer pointer */
5434
        hi2c->pBuffPtr++;
5435
 
5436
        /* Update counter */
5437
        hi2c->XferCount--;
5438
      }
5439
    }
5440
  }
5441
  else
5442
  {
5443
    /* Do nothing */
5444
  }
5445
}
5446
 
5447
/**
5448
  * @brief  Handle BTF flag for Master transmitter
5449
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5450
  *         the configuration information for I2C module
5451
  * @retval None
5452
  */
5453
static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
5454
{
5455
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5456
  uint32_t CurrentXferOptions = hi2c->XferOptions;
5457
 
5458
  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5459
  {
5460
    if (hi2c->XferCount != 0U)
5461
    {
5462
      /* Write data to DR */
5463
      hi2c->Instance->DR = *hi2c->pBuffPtr;
5464
 
5465
      /* Increment Buffer pointer */
5466
      hi2c->pBuffPtr++;
5467
 
5468
      /* Update counter */
5469
      hi2c->XferCount--;
5470
    }
5471
    else
5472
    {
5473
      /* Call TxCpltCallback() directly if no stop mode is set */
5474
      if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5475
      {
5476
        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5477
 
5478
        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5479
        hi2c->Mode = HAL_I2C_MODE_NONE;
5480
        hi2c->State = HAL_I2C_STATE_READY;
5481
 
5482
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5483
        hi2c->MasterTxCpltCallback(hi2c);
5484
#else
5485
        HAL_I2C_MasterTxCpltCallback(hi2c);
5486
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5487
      }
5488
      else /* Generate Stop condition then Call TxCpltCallback() */
5489
      {
5490
        /* Disable EVT, BUF and ERR interrupt */
5491
        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5492
 
5493
        /* Generate Stop */
5494
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5495
 
5496
        hi2c->PreviousState = I2C_STATE_NONE;
5497
        hi2c->State = HAL_I2C_STATE_READY;
5498
        if (hi2c->Mode == HAL_I2C_MODE_MEM)
5499
        {
5500
          hi2c->Mode = HAL_I2C_MODE_NONE;
5501
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5502
          hi2c->MemTxCpltCallback(hi2c);
5503
#else
5504
          HAL_I2C_MemTxCpltCallback(hi2c);
5505
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5506
        }
5507
        else
5508
        {
5509
          hi2c->Mode = HAL_I2C_MODE_NONE;
5510
 
5511
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5512
          hi2c->MasterTxCpltCallback(hi2c);
5513
#else
5514
          HAL_I2C_MasterTxCpltCallback(hi2c);
5515
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5516
        }
5517
      }
5518
    }
5519
  }
5520
  else
5521
  {
5522
    /* Do nothing */
5523
  }
5524
}
5525
 
5526
/**
5527
  * @brief  Handle TXE and BTF flag for Memory transmitter
5528
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5529
  *         the configuration information for I2C module
5530
  * @retval None
5531
  */
5532
static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
5533
{
5534
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5535
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5536
 
5537
  if (hi2c->EventCount == 0U)
5538
  {
5539
    /* If Memory address size is 8Bit */
5540
    if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
5541
    {
5542
      /* Send Memory Address */
5543
      hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5544
 
5545
      hi2c->EventCount += 2U;
5546
    }
5547
    /* If Memory address size is 16Bit */
5548
    else
5549
    {
5550
      /* Send MSB of Memory Address */
5551
      hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
5552
 
5553
      hi2c->EventCount++;
5554
    }
5555
  }
5556
  else if (hi2c->EventCount == 1U)
5557
  {
5558
    /* Send LSB of Memory Address */
5559
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5560
 
5561
    hi2c->EventCount++;
5562
  }
5563
  else if (hi2c->EventCount == 2U)
5564
  {
5565
    if (CurrentState == HAL_I2C_STATE_BUSY_RX)
5566
    {
5567
      /* Generate Restart */
5568
      hi2c->Instance->CR1 |= I2C_CR1_START;
5569
 
5570
      hi2c->EventCount++;
5571
    }
5572
    else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5573
    {
5574
      /* Write data to DR */
5575
      hi2c->Instance->DR = *hi2c->pBuffPtr;
5576
 
5577
      /* Increment Buffer pointer */
5578
      hi2c->pBuffPtr++;
5579
 
5580
      /* Update counter */
5581
      hi2c->XferCount--;
5582
    }
5583
    else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5584
    {
5585
      /* Generate Stop condition then Call TxCpltCallback() */
5586
      /* Disable EVT, BUF and ERR interrupt */
5587
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5588
 
5589
      /* Generate Stop */
5590
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5591
 
5592
      hi2c->PreviousState = I2C_STATE_NONE;
5593
      hi2c->State = HAL_I2C_STATE_READY;
5594
      hi2c->Mode = HAL_I2C_MODE_NONE;
5595
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5596
      hi2c->MemTxCpltCallback(hi2c);
5597
#else
5598
      HAL_I2C_MemTxCpltCallback(hi2c);
5599
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5600
    }
5601
    else
5602
    {
5603
      /* Do nothing */
5604
    }
5605
  }
5606
  else
5607
  {
5608
    /* Clear TXE and BTF flags */
5609
    I2C_Flush_DR(hi2c);
5610
  }
5611
}
5612
 
5613
/**
5614
  * @brief  Handle RXNE flag for Master
5615
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5616
  *         the configuration information for I2C module
5617
  * @retval None
5618
  */
5619
static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
5620
{
5621
  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5622
  {
5623
    uint32_t tmp;
5624
 
5625
    tmp = hi2c->XferCount;
5626
    if (tmp > 3U)
5627
    {
5628
      /* Read data from DR */
5629
      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5630
 
5631
      /* Increment Buffer pointer */
5632
      hi2c->pBuffPtr++;
5633
 
5634
      /* Update counter */
5635
      hi2c->XferCount--;
5636
 
5637
      if (hi2c->XferCount == (uint16_t)3)
5638
      {
5639
        /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
5640
        on BTF subroutine */
5641
        /* Disable BUF interrupt */
5642
        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5643
      }
5644
    }
5645
    else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
5646
    {
5647
      if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
5648
      {
5649
        /* Disable Acknowledge */
5650
        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5651
 
5652
        /* Disable EVT, BUF and ERR interrupt */
5653
        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5654
 
5655
        /* Read data from DR */
5656
        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5657
 
5658
        /* Increment Buffer pointer */
5659
        hi2c->pBuffPtr++;
5660
 
5661
        /* Update counter */
5662
        hi2c->XferCount--;
5663
 
5664
        hi2c->State = HAL_I2C_STATE_READY;
5665
 
5666
        if (hi2c->Mode == HAL_I2C_MODE_MEM)
5667
        {
5668
          hi2c->Mode = HAL_I2C_MODE_NONE;
5669
          hi2c->PreviousState = I2C_STATE_NONE;
5670
 
5671
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5672
          hi2c->MemRxCpltCallback(hi2c);
5673
#else
5674
          HAL_I2C_MemRxCpltCallback(hi2c);
5675
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5676
        }
5677
        else
5678
        {
5679
          hi2c->Mode = HAL_I2C_MODE_NONE;
5680
          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5681
 
5682
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5683
          hi2c->MasterRxCpltCallback(hi2c);
5684
#else
5685
          HAL_I2C_MasterRxCpltCallback(hi2c);
5686
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5687
        }
5688
      }
5689
      else
5690
      {
5691
        /* Disable EVT, BUF and ERR interrupt */
5692
        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5693
 
5694
        /* Read data from DR */
5695
        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5696
 
5697
        /* Increment Buffer pointer */
5698
        hi2c->pBuffPtr++;
5699
 
5700
        /* Update counter */
5701
        hi2c->XferCount--;
5702
 
5703
        hi2c->State = HAL_I2C_STATE_READY;
5704
        hi2c->Mode = HAL_I2C_MODE_NONE;
5705
 
5706
        /* Call user error callback */
5707
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5708
        hi2c->ErrorCallback(hi2c);
5709
#else
5710
        HAL_I2C_ErrorCallback(hi2c);
5711
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5712
      }
5713
    }
5714
    else
5715
    {
5716
      /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5717
         on BTF subroutine if there is a reception delay between N-1 and N byte */
5718
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5719
    }
5720
  }
5721
}
5722
 
5723
/**
5724
  * @brief  Handle BTF flag for Master receiver
5725
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5726
  *         the configuration information for I2C module
5727
  * @retval None
5728
  */
5729
static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
5730
{
5731
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5732
  uint32_t CurrentXferOptions = hi2c->XferOptions;
5733
 
5734
  if (hi2c->XferCount == 4U)
5735
  {
5736
    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5737
       on BTF subroutine if there is a reception delay between N-1 and N byte */
5738
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5739
 
5740
    /* Read data from DR */
5741
    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5742
 
5743
    /* Increment Buffer pointer */
5744
    hi2c->pBuffPtr++;
5745
 
5746
    /* Update counter */
5747
    hi2c->XferCount--;
5748
  }
5749
  else if (hi2c->XferCount == 3U)
5750
  {
5751
    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5752
       on BTF subroutine if there is a reception delay between N-1 and N byte */
5753
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5754
 
5755
    if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
5756
    {
5757
      /* Disable Acknowledge */
5758
      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5759
    }
5760
 
5761
    /* Read data from DR */
5762
    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5763
 
5764
    /* Increment Buffer pointer */
5765
    hi2c->pBuffPtr++;
5766
 
5767
    /* Update counter */
5768
    hi2c->XferCount--;
5769
  }
5770
  else if (hi2c->XferCount == 2U)
5771
  {
5772
    /* Prepare next transfer or stop current transfer */
5773
    if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
5774
    {
5775
      /* Disable Acknowledge */
5776
      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5777
    }
5778
    else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
5779
    {
5780
      /* Enable Acknowledge */
5781
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5782
    }
5783
    else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
5784
    {
5785
      /* Generate Stop */
5786
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5787
    }
5788
    else
5789
    {
5790
      /* Do nothing */
5791
    }
5792
 
5793
    /* Read data from DR */
5794
    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5795
 
5796
    /* Increment Buffer pointer */
5797
    hi2c->pBuffPtr++;
5798
 
5799
    /* Update counter */
5800
    hi2c->XferCount--;
5801
 
5802
    /* Read data from DR */
5803
    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5804
 
5805
    /* Increment Buffer pointer */
5806
    hi2c->pBuffPtr++;
5807
 
5808
    /* Update counter */
5809
    hi2c->XferCount--;
5810
 
5811
    /* Disable EVT and ERR interrupt */
5812
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
5813
 
5814
    hi2c->State = HAL_I2C_STATE_READY;
5815
    if (hi2c->Mode == HAL_I2C_MODE_MEM)
5816
    {
5817
      hi2c->Mode = HAL_I2C_MODE_NONE;
5818
      hi2c->PreviousState = I2C_STATE_NONE;
5819
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5820
      hi2c->MemRxCpltCallback(hi2c);
5821
#else
5822
      HAL_I2C_MemRxCpltCallback(hi2c);
5823
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5824
    }
5825
    else
5826
    {
5827
      hi2c->Mode = HAL_I2C_MODE_NONE;
5828
      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5829
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5830
      hi2c->MasterRxCpltCallback(hi2c);
5831
#else
5832
      HAL_I2C_MasterRxCpltCallback(hi2c);
5833
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5834
    }
5835
  }
5836
  else
5837
  {
5838
    /* Read data from DR */
5839
    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5840
 
5841
    /* Increment Buffer pointer */
5842
    hi2c->pBuffPtr++;
5843
 
5844
    /* Update counter */
5845
    hi2c->XferCount--;
5846
  }
5847
}
5848
 
5849
/**
5850
  * @brief  Handle SB flag for Master
5851
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5852
  *         the configuration information for I2C module
5853
  * @retval None
5854
  */
5855
static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
5856
{
5857
  if (hi2c->Mode == HAL_I2C_MODE_MEM)
5858
  {
5859
    if (hi2c->EventCount == 0U)
5860
    {
5861
      /* Send slave address */
5862
      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5863
    }
5864
    else
5865
    {
5866
      hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5867
    }
5868
  }
5869
  else
5870
  {
5871
    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
5872
    {
5873
      /* Send slave 7 Bits address */
5874
      if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5875
      {
5876
        hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5877
      }
5878
      else
5879
      {
5880
        hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5881
      }
5882
 
5883
      if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5884
          || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5885
      {
5886
        /* Enable DMA Request */
5887
        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5888
      }
5889
    }
5890
    else
5891
    {
5892
      if (hi2c->EventCount == 0U)
5893
      {
5894
        /* Send header of slave address */
5895
        hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
5896
      }
5897
      else if (hi2c->EventCount == 1U)
5898
      {
5899
        /* Send header of slave address */
5900
        hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
5901
      }
5902
      else
5903
      {
5904
        /* Do nothing */
5905
      }
5906
    }
5907
  }
5908
}
5909
 
5910
/**
5911
  * @brief  Handle ADD10 flag for Master
5912
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5913
  *         the configuration information for I2C module
5914
  * @retval None
5915
  */
5916
static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
5917
{
5918
  /* Send slave address */
5919
  hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
5920
 
5921
  if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5922
      || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5923
  {
5924
    /* Enable DMA Request */
5925
    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5926
  }
5927
}
5928
 
5929
/**
5930
  * @brief  Handle ADDR flag for Master
5931
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
5932
  *         the configuration information for I2C module
5933
  * @retval None
5934
  */
5935
static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
5936
{
5937
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5938
  HAL_I2C_ModeTypeDef CurrentMode       = hi2c->Mode;
5939
  uint32_t CurrentXferOptions           = hi2c->XferOptions;
5940
  uint32_t Prev_State                   = hi2c->PreviousState;
5941
 
5942
  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5943
  {
5944
    if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
5945
    {
5946
      /* Clear ADDR flag */
5947
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5948
    }
5949
    else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
5950
    {
5951
      /* Clear ADDR flag */
5952
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5953
 
5954
      /* Generate Restart */
5955
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
5956
 
5957
      hi2c->EventCount++;
5958
    }
5959
    else
5960
    {
5961
      if (hi2c->XferCount == 0U)
5962
      {
5963
        /* Clear ADDR flag */
5964
        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5965
 
5966
        /* Generate Stop */
5967
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5968
      }
5969
      else if (hi2c->XferCount == 1U)
5970
      {
5971
        if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
5972
        {
5973
          /* Disable Acknowledge */
5974
          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5975
 
5976
          if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5977
          {
5978
            /* Disable Acknowledge */
5979
            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5980
 
5981
            /* Clear ADDR flag */
5982
            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5983
          }
5984
          else
5985
          {
5986
            /* Clear ADDR flag */
5987
            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5988
 
5989
            /* Generate Stop */
5990
            SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5991
          }
5992
        }
5993
        /* Prepare next transfer or stop current transfer */
5994
        else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
5995
                 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
5996
        {
5997
          if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5998
          {
5999
            /* Disable Acknowledge */
6000
            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6001
          }
6002
          else
6003
          {
6004
            /* Enable Acknowledge */
6005
            SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6006
          }
6007
 
6008
          /* Clear ADDR flag */
6009
          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6010
        }
6011
        else
6012
        {
6013
          /* Disable Acknowledge */
6014
          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6015
 
6016
          /* Clear ADDR flag */
6017
          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6018
 
6019
          /* Generate Stop */
6020
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6021
        }
6022
      }
6023
      else if (hi2c->XferCount == 2U)
6024
      {
6025
        if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
6026
        {
6027
          /* Enable Pos */
6028
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
6029
 
6030
          /* Clear ADDR flag */
6031
          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6032
 
6033
          /* Disable Acknowledge */
6034
          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6035
        }
6036
        else
6037
        {
6038
          /* Enable Acknowledge */
6039
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6040
 
6041
          /* Clear ADDR flag */
6042
          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6043
        }
6044
 
6045
        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
6046
        {
6047
          /* Enable Last DMA bit */
6048
          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
6049
        }
6050
      }
6051
      else
6052
      {
6053
        /* Enable Acknowledge */
6054
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6055
 
6056
        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
6057
        {
6058
          /* Enable Last DMA bit */
6059
          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
6060
        }
6061
 
6062
        /* Clear ADDR flag */
6063
        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6064
      }
6065
 
6066
      /* Reset Event counter  */
6067
      hi2c->EventCount = 0U;
6068
    }
6069
  }
6070
  else
6071
  {
6072
    /* Clear ADDR flag */
6073
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6074
  }
6075
}
6076
 
6077
/**
6078
  * @brief  Handle TXE flag for Slave
6079
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6080
  *         the configuration information for I2C module
6081
  * @retval None
6082
  */
6083
static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
6084
{
6085
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6086
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6087
 
6088
  if (hi2c->XferCount != 0U)
6089
  {
6090
    /* Write data to DR */
6091
    hi2c->Instance->DR = *hi2c->pBuffPtr;
6092
 
6093
    /* Increment Buffer pointer */
6094
    hi2c->pBuffPtr++;
6095
 
6096
    /* Update counter */
6097
    hi2c->XferCount--;
6098
 
6099
    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
6100
    {
6101
      /* Last Byte is received, disable Interrupt */
6102
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
6103
 
6104
      /* Set state at HAL_I2C_STATE_LISTEN */
6105
      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6106
      hi2c->State = HAL_I2C_STATE_LISTEN;
6107
 
6108
      /* Call the corresponding callback to inform upper layer of End of Transfer */
6109
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6110
      hi2c->SlaveTxCpltCallback(hi2c);
6111
#else
6112
      HAL_I2C_SlaveTxCpltCallback(hi2c);
6113
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6114
    }
6115
  }
6116
}
6117
 
6118
/**
6119
  * @brief  Handle BTF flag for Slave transmitter
6120
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6121
  *         the configuration information for I2C module
6122
  * @retval None
6123
  */
6124
static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
6125
{
6126
  if (hi2c->XferCount != 0U)
6127
  {
6128
    /* Write data to DR */
6129
    hi2c->Instance->DR = *hi2c->pBuffPtr;
6130
 
6131
    /* Increment Buffer pointer */
6132
    hi2c->pBuffPtr++;
6133
 
6134
    /* Update counter */
6135
    hi2c->XferCount--;
6136
  }
6137
}
6138
 
6139
/**
6140
  * @brief  Handle RXNE flag for Slave
6141
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6142
  *         the configuration information for I2C module
6143
  * @retval None
6144
  */
6145
static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
6146
{
6147
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6148
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6149
 
6150
  if (hi2c->XferCount != 0U)
6151
  {
6152
    /* Read data from DR */
6153
    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6154
 
6155
    /* Increment Buffer pointer */
6156
    hi2c->pBuffPtr++;
6157
 
6158
    /* Update counter */
6159
    hi2c->XferCount--;
6160
 
6161
    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6162
    {
6163
      /* Last Byte is received, disable Interrupt */
6164
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
6165
 
6166
      /* Set state at HAL_I2C_STATE_LISTEN */
6167
      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6168
      hi2c->State = HAL_I2C_STATE_LISTEN;
6169
 
6170
      /* Call the corresponding callback to inform upper layer of End of Transfer */
6171
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6172
      hi2c->SlaveRxCpltCallback(hi2c);
6173
#else
6174
      HAL_I2C_SlaveRxCpltCallback(hi2c);
6175
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6176
    }
6177
  }
6178
}
6179
 
6180
/**
6181
  * @brief  Handle BTF flag for Slave receiver
6182
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6183
  *         the configuration information for I2C module
6184
  * @retval None
6185
  */
6186
static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
6187
{
6188
  if (hi2c->XferCount != 0U)
6189
  {
6190
    /* Read data from DR */
6191
    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6192
 
6193
    /* Increment Buffer pointer */
6194
    hi2c->pBuffPtr++;
6195
 
6196
    /* Update counter */
6197
    hi2c->XferCount--;
6198
  }
6199
}
6200
 
6201
/**
6202
  * @brief  Handle ADD flag for Slave
6203
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6204
  *         the configuration information for I2C module
6205
  * @param  IT2Flags Interrupt2 flags to handle.
6206
  * @retval None
6207
  */
6208
static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
6209
{
6210
  uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
6211
  uint16_t SlaveAddrCode;
6212
 
6213
  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6214
  {
6215
    /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
6216
    __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
6217
 
6218
    /* Transfer Direction requested by Master */
6219
    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
6220
    {
6221
      TransferDirection = I2C_DIRECTION_TRANSMIT;
6222
    }
6223
 
6224
    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
6225
    {
6226
      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
6227
    }
6228
    else
6229
    {
6230
      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
6231
    }
6232
 
6233
    /* Process Unlocked */
6234
    __HAL_UNLOCK(hi2c);
6235
 
6236
    /* Call Slave Addr callback */
6237
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6238
    hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6239
#else
6240
    HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6241
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6242
  }
6243
  else
6244
  {
6245
    /* Clear ADDR flag */
6246
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6247
 
6248
    /* Process Unlocked */
6249
    __HAL_UNLOCK(hi2c);
6250
  }
6251
}
6252
 
6253
/**
6254
  * @brief  Handle STOPF flag for Slave
6255
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6256
  *         the configuration information for I2C module
6257
  * @retval None
6258
  */
6259
static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
6260
{
6261
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6262
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6263
 
6264
  /* Disable EVT, BUF and ERR interrupt */
6265
  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6266
 
6267
  /* Clear STOPF flag */
6268
  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
6269
 
6270
  /* Disable Acknowledge */
6271
  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6272
 
6273
  /* If a DMA is ongoing, Update handle size context */
6274
  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6275
  {
6276
    if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6277
    {
6278
      hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx));
6279
 
6280
      if (hi2c->XferCount != 0U)
6281
      {
6282
        /* Set ErrorCode corresponding to a Non-Acknowledge */
6283
        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6284
      }
6285
 
6286
      /* Disable, stop the current DMA */
6287
      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6288
 
6289
      /* Abort DMA Xfer if any */
6290
      if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6291
      {
6292
        /* Set the I2C DMA Abort callback :
6293
        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6294
        hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6295
 
6296
        /* Abort DMA RX */
6297
        if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6298
        {
6299
          /* Call Directly XferAbortCallback function in case of error */
6300
          hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6301
        }
6302
      }
6303
    }
6304
    else
6305
    {
6306
      hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx));
6307
 
6308
      if (hi2c->XferCount != 0U)
6309
      {
6310
        /* Set ErrorCode corresponding to a Non-Acknowledge */
6311
        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6312
      }
6313
 
6314
      /* Disable, stop the current DMA */
6315
      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6316
 
6317
      /* Abort DMA Xfer if any */
6318
      if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6319
      {
6320
        /* Set the I2C DMA Abort callback :
6321
        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6322
        hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6323
 
6324
        /* Abort DMA TX */
6325
        if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6326
        {
6327
          /* Call Directly XferAbortCallback function in case of error */
6328
          hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6329
        }
6330
      }
6331
    }
6332
  }
6333
 
6334
  /* All data are not transferred, so set error code accordingly */
6335
  if (hi2c->XferCount != 0U)
6336
  {
6337
    /* Store Last receive data if any */
6338
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
6339
    {
6340
      /* Read data from DR */
6341
      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6342
 
6343
      /* Increment Buffer pointer */
6344
      hi2c->pBuffPtr++;
6345
 
6346
      /* Update counter */
6347
      hi2c->XferCount--;
6348
    }
6349
 
6350
    /* Store Last receive data if any */
6351
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6352
    {
6353
      /* Read data from DR */
6354
      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6355
 
6356
      /* Increment Buffer pointer */
6357
      hi2c->pBuffPtr++;
6358
 
6359
      /* Update counter */
6360
      hi2c->XferCount--;
6361
    }
6362
 
6363
    if (hi2c->XferCount != 0U)
6364
    {
6365
      /* Set ErrorCode corresponding to a Non-Acknowledge */
6366
      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6367
    }
6368
  }
6369
 
6370
  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6371
  {
6372
    /* Call the corresponding callback to inform upper layer of End of Transfer */
6373
    I2C_ITError(hi2c);
6374
  }
6375
  else
6376
  {
6377
    if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6378
    {
6379
      /* Set state at HAL_I2C_STATE_LISTEN */
6380
      hi2c->PreviousState = I2C_STATE_NONE;
6381
      hi2c->State = HAL_I2C_STATE_LISTEN;
6382
 
6383
      /* Call the corresponding callback to inform upper layer of End of Transfer */
6384
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6385
      hi2c->SlaveRxCpltCallback(hi2c);
6386
#else
6387
      HAL_I2C_SlaveRxCpltCallback(hi2c);
6388
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6389
    }
6390
 
6391
    if (hi2c->State == HAL_I2C_STATE_LISTEN)
6392
    {
6393
      hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6394
      hi2c->PreviousState = I2C_STATE_NONE;
6395
      hi2c->State = HAL_I2C_STATE_READY;
6396
      hi2c->Mode = HAL_I2C_MODE_NONE;
6397
 
6398
      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6399
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6400
      hi2c->ListenCpltCallback(hi2c);
6401
#else
6402
      HAL_I2C_ListenCpltCallback(hi2c);
6403
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6404
    }
6405
    else
6406
    {
6407
      if ((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
6408
      {
6409
        hi2c->PreviousState = I2C_STATE_NONE;
6410
        hi2c->State = HAL_I2C_STATE_READY;
6411
        hi2c->Mode = HAL_I2C_MODE_NONE;
6412
 
6413
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6414
        hi2c->SlaveRxCpltCallback(hi2c);
6415
#else
6416
        HAL_I2C_SlaveRxCpltCallback(hi2c);
6417
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6418
      }
6419
    }
6420
  }
6421
}
6422
 
6423
/**
6424
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6425
  *         the configuration information for I2C module
6426
  * @retval None
6427
  */
6428
static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
6429
{
6430
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6431
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6432
  uint32_t CurrentXferOptions       = hi2c->XferOptions;
6433
 
6434
  if (((CurrentXferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
6435
      (CurrentState == HAL_I2C_STATE_LISTEN))
6436
  {
6437
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6438
 
6439
    /* Disable EVT, BUF and ERR interrupt */
6440
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6441
 
6442
    /* Clear AF flag */
6443
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6444
 
6445
    /* Disable Acknowledge */
6446
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6447
 
6448
    hi2c->PreviousState = I2C_STATE_NONE;
6449
    hi2c->State         = HAL_I2C_STATE_READY;
6450
    hi2c->Mode          = HAL_I2C_MODE_NONE;
6451
 
6452
    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6453
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6454
    hi2c->ListenCpltCallback(hi2c);
6455
#else
6456
    HAL_I2C_ListenCpltCallback(hi2c);
6457
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6458
  }
6459
  else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
6460
  {
6461
    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
6462
    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6463
    hi2c->State         = HAL_I2C_STATE_READY;
6464
    hi2c->Mode          = HAL_I2C_MODE_NONE;
6465
 
6466
    /* Disable EVT, BUF and ERR interrupt */
6467
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6468
 
6469
    /* Clear AF flag */
6470
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6471
 
6472
    /* Disable Acknowledge */
6473
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6474
 
6475
    /* Clear TXE flag */
6476
    I2C_Flush_DR(hi2c);
6477
 
6478
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6479
    hi2c->SlaveTxCpltCallback(hi2c);
6480
#else
6481
    HAL_I2C_SlaveTxCpltCallback(hi2c);
6482
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6483
  }
6484
  else
6485
  {
6486
    /* Clear AF flag only */
6487
    /* State Listen, but XferOptions == FIRST or NEXT */
6488
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6489
  }
6490
}
6491
 
6492
/**
6493
  * @brief  I2C interrupts error process
6494
  * @param  hi2c I2C handle.
6495
  * @retval None
6496
  */
6497
static void I2C_ITError(I2C_HandleTypeDef *hi2c)
6498
{
6499
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6500
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6501
  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6502
  uint32_t CurrentError;
6503
 
6504
  if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
6505
  {
6506
    /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
6507
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
6508
  }
6509
 
6510
  if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6511
  {
6512
    /* keep HAL_I2C_STATE_LISTEN */
6513
    hi2c->PreviousState = I2C_STATE_NONE;
6514
    hi2c->State = HAL_I2C_STATE_LISTEN;
6515
  }
6516
  else
6517
  {
6518
    /* If state is an abort treatment on going, don't change state */
6519
    /* This change will be do later */
6520
    if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
6521
    {
6522
      hi2c->State = HAL_I2C_STATE_READY;
6523
      hi2c->Mode = HAL_I2C_MODE_NONE;
6524
    }
6525
    hi2c->PreviousState = I2C_STATE_NONE;
6526
  }
6527
 
6528
  /* Abort DMA transfer */
6529
  if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6530
  {
6531
    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
6532
 
6533
    if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
6534
    {
6535
      /* Set the DMA Abort callback :
6536
      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6537
      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6538
 
6539
      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6540
      {
6541
        /* Disable I2C peripheral to prevent dummy data in buffer */
6542
        __HAL_I2C_DISABLE(hi2c);
6543
 
6544
        hi2c->State = HAL_I2C_STATE_READY;
6545
 
6546
        /* Call Directly XferAbortCallback function in case of error */
6547
        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6548
      }
6549
    }
6550
    else
6551
    {
6552
      /* Set the DMA Abort callback :
6553
      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6554
      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6555
 
6556
      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6557
      {
6558
        /* Store Last receive data if any */
6559
        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6560
        {
6561
          /* Read data from DR */
6562
          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6563
 
6564
          /* Increment Buffer pointer */
6565
          hi2c->pBuffPtr++;
6566
        }
6567
 
6568
        /* Disable I2C peripheral to prevent dummy data in buffer */
6569
        __HAL_I2C_DISABLE(hi2c);
6570
 
6571
        hi2c->State = HAL_I2C_STATE_READY;
6572
 
6573
        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6574
        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6575
      }
6576
    }
6577
  }
6578
  else if (hi2c->State == HAL_I2C_STATE_ABORT)
6579
  {
6580
    hi2c->State = HAL_I2C_STATE_READY;
6581
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6582
 
6583
    /* Store Last receive data if any */
6584
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6585
    {
6586
      /* Read data from DR */
6587
      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6588
 
6589
      /* Increment Buffer pointer */
6590
      hi2c->pBuffPtr++;
6591
    }
6592
 
6593
    /* Disable I2C peripheral to prevent dummy data in buffer */
6594
    __HAL_I2C_DISABLE(hi2c);
6595
 
6596
    /* Call the corresponding callback to inform upper layer of End of Transfer */
6597
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6598
    hi2c->AbortCpltCallback(hi2c);
6599
#else
6600
    HAL_I2C_AbortCpltCallback(hi2c);
6601
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6602
  }
6603
  else
6604
  {
6605
    /* Store Last receive data if any */
6606
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6607
    {
6608
      /* Read data from DR */
6609
      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6610
 
6611
      /* Increment Buffer pointer */
6612
      hi2c->pBuffPtr++;
6613
    }
6614
 
6615
    /* Call user error callback */
6616
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6617
    hi2c->ErrorCallback(hi2c);
6618
#else
6619
    HAL_I2C_ErrorCallback(hi2c);
6620
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6621
  }
6622
 
6623
  /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
6624
  CurrentError = hi2c->ErrorCode;
6625
 
6626
  if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
6627
      ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
6628
      ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)     || \
6629
      ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
6630
  {
6631
    /* Disable EVT, BUF and ERR interrupt */
6632
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6633
  }
6634
 
6635
  /* So may inform upper layer that listen phase is stopped */
6636
  /* during NACK error treatment */
6637
  CurrentState = hi2c->State;
6638
  if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
6639
  {
6640
    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
6641
    hi2c->PreviousState = I2C_STATE_NONE;
6642
    hi2c->State         = HAL_I2C_STATE_READY;
6643
    hi2c->Mode          = HAL_I2C_MODE_NONE;
6644
 
6645
    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6646
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6647
    hi2c->ListenCpltCallback(hi2c);
6648
#else
6649
    HAL_I2C_ListenCpltCallback(hi2c);
6650
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6651
  }
6652
}
6653
 
6654
/**
6655
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6656
  *         the configuration information for I2C module
6657
  * @param  DevAddress Target device address: The device 7 bits address value
6658
  *         in datasheet must be shifted to the left before calling the interface
6659
  * @param  Timeout Timeout duration
6660
  * @param  Tickstart Tick start value
6661
  * @retval HAL status
6662
  */
6663
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6664
{
6665
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6666
  uint32_t CurrentXferOptions = hi2c->XferOptions;
6667
 
6668
  /* Generate Start condition if first transfer */
6669
  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6670
  {
6671
    /* Generate Start */
6672
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6673
  }
6674
  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
6675
  {
6676
    /* Generate ReStart */
6677
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6678
  }
6679
  else
6680
  {
6681
    /* Do nothing */
6682
  }
6683
 
6684
  /* Wait until SB flag is set */
6685
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6686
  {
6687
    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6688
    {
6689
      hi2c->ErrorCode = HAL_I2C_WRONG_START;
6690
    }
6691
    return HAL_TIMEOUT;
6692
  }
6693
 
6694
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6695
  {
6696
    /* Send slave address */
6697
    hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6698
  }
6699
  else
6700
  {
6701
    /* Send header of slave address */
6702
    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6703
 
6704
    /* Wait until ADD10 flag is set */
6705
    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6706
    {
6707
      return HAL_ERROR;
6708
    }
6709
 
6710
    /* Send slave address */
6711
    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6712
  }
6713
 
6714
  /* Wait until ADDR flag is set */
6715
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6716
  {
6717
    return HAL_ERROR;
6718
  }
6719
 
6720
  return HAL_OK;
6721
}
6722
 
6723
/**
6724
  * @brief  Master sends target device address for read request.
6725
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6726
  *         the configuration information for I2C module
6727
  * @param  DevAddress Target device address: The device 7 bits address value
6728
  *         in datasheet must be shifted to the left before calling the interface
6729
  * @param  Timeout Timeout duration
6730
  * @param  Tickstart Tick start value
6731
  * @retval HAL status
6732
  */
6733
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6734
{
6735
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6736
  uint32_t CurrentXferOptions = hi2c->XferOptions;
6737
 
6738
  /* Enable Acknowledge */
6739
  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6740
 
6741
  /* Generate Start condition if first transfer */
6742
  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)  || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6743
  {
6744
    /* Generate Start */
6745
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6746
  }
6747
  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
6748
  {
6749
    /* Generate ReStart */
6750
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6751
  }
6752
  else
6753
  {
6754
    /* Do nothing */
6755
  }
6756
 
6757
  /* Wait until SB flag is set */
6758
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6759
  {
6760
    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6761
    {
6762
      hi2c->ErrorCode = HAL_I2C_WRONG_START;
6763
    }
6764
    return HAL_TIMEOUT;
6765
  }
6766
 
6767
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6768
  {
6769
    /* Send slave address */
6770
    hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6771
  }
6772
  else
6773
  {
6774
    /* Send header of slave address */
6775
    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6776
 
6777
    /* Wait until ADD10 flag is set */
6778
    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6779
    {
6780
      return HAL_ERROR;
6781
    }
6782
 
6783
    /* Send slave address */
6784
    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6785
 
6786
    /* Wait until ADDR flag is set */
6787
    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6788
    {
6789
      return HAL_ERROR;
6790
    }
6791
 
6792
    /* Clear ADDR flag */
6793
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6794
 
6795
    /* Generate Restart */
6796
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6797
 
6798
    /* Wait until SB flag is set */
6799
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6800
    {
6801
      if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6802
      {
6803
        hi2c->ErrorCode = HAL_I2C_WRONG_START;
6804
      }
6805
      return HAL_TIMEOUT;
6806
    }
6807
 
6808
    /* Send header of slave address */
6809
    hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
6810
  }
6811
 
6812
  /* Wait until ADDR flag is set */
6813
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6814
  {
6815
    return HAL_ERROR;
6816
  }
6817
 
6818
  return HAL_OK;
6819
}
6820
 
6821
/**
6822
  * @brief  Master sends target device address followed by internal memory address for write request.
6823
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6824
  *         the configuration information for I2C module
6825
  * @param  DevAddress Target device address: The device 7 bits address value
6826
  *         in datasheet must be shifted to the left before calling the interface
6827
  * @param  MemAddress Internal memory address
6828
  * @param  MemAddSize Size of internal memory address
6829
  * @param  Timeout Timeout duration
6830
  * @param  Tickstart Tick start value
6831
  * @retval HAL status
6832
  */
6833
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6834
{
6835
  /* Generate Start */
6836
  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6837
 
6838
  /* Wait until SB flag is set */
6839
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6840
  {
6841
    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6842
    {
6843
      hi2c->ErrorCode = HAL_I2C_WRONG_START;
6844
    }
6845
    return HAL_TIMEOUT;
6846
  }
6847
 
6848
  /* Send slave address */
6849
  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6850
 
6851
  /* Wait until ADDR flag is set */
6852
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6853
  {
6854
    return HAL_ERROR;
6855
  }
6856
 
6857
  /* Clear ADDR flag */
6858
  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6859
 
6860
  /* Wait until TXE flag is set */
6861
  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6862
  {
6863
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6864
    {
6865
      /* Generate Stop */
6866
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6867
    }
6868
    return HAL_ERROR;
6869
  }
6870
 
6871
  /* If Memory address size is 8Bit */
6872
  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6873
  {
6874
    /* Send Memory Address */
6875
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6876
  }
6877
  /* If Memory address size is 16Bit */
6878
  else
6879
  {
6880
    /* Send MSB of Memory Address */
6881
    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6882
 
6883
    /* Wait until TXE flag is set */
6884
    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6885
    {
6886
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6887
      {
6888
        /* Generate Stop */
6889
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6890
      }
6891
      return HAL_ERROR;
6892
    }
6893
 
6894
    /* Send LSB of Memory Address */
6895
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6896
  }
6897
 
6898
  return HAL_OK;
6899
}
6900
 
6901
/**
6902
  * @brief  Master sends target device address followed by internal memory address for read request.
6903
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
6904
  *         the configuration information for I2C module
6905
  * @param  DevAddress Target device address: The device 7 bits address value
6906
  *         in datasheet must be shifted to the left before calling the interface
6907
  * @param  MemAddress Internal memory address
6908
  * @param  MemAddSize Size of internal memory address
6909
  * @param  Timeout Timeout duration
6910
  * @param  Tickstart Tick start value
6911
  * @retval HAL status
6912
  */
6913
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6914
{
6915
  /* Enable Acknowledge */
6916
  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6917
 
6918
  /* Generate Start */
6919
  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6920
 
6921
  /* Wait until SB flag is set */
6922
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6923
  {
6924
    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6925
    {
6926
      hi2c->ErrorCode = HAL_I2C_WRONG_START;
6927
    }
6928
    return HAL_TIMEOUT;
6929
  }
6930
 
6931
  /* Send slave address */
6932
  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6933
 
6934
  /* Wait until ADDR flag is set */
6935
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6936
  {
6937
    return HAL_ERROR;
6938
  }
6939
 
6940
  /* Clear ADDR flag */
6941
  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6942
 
6943
  /* Wait until TXE flag is set */
6944
  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6945
  {
6946
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6947
    {
6948
      /* Generate Stop */
6949
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6950
    }
6951
    return HAL_ERROR;
6952
  }
6953
 
6954
  /* If Memory address size is 8Bit */
6955
  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6956
  {
6957
    /* Send Memory Address */
6958
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6959
  }
6960
  /* If Memory address size is 16Bit */
6961
  else
6962
  {
6963
    /* Send MSB of Memory Address */
6964
    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6965
 
6966
    /* Wait until TXE flag is set */
6967
    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6968
    {
6969
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6970
      {
6971
        /* Generate Stop */
6972
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6973
      }
6974
      return HAL_ERROR;
6975
    }
6976
 
6977
    /* Send LSB of Memory Address */
6978
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6979
  }
6980
 
6981
  /* Wait until TXE flag is set */
6982
  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6983
  {
6984
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6985
    {
6986
      /* Generate Stop */
6987
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6988
    }
6989
    return HAL_ERROR;
6990
  }
6991
 
6992
  /* Generate Restart */
6993
  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6994
 
6995
  /* Wait until SB flag is set */
6996
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6997
  {
6998
    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6999
    {
7000
      hi2c->ErrorCode = HAL_I2C_WRONG_START;
7001
    }
7002
    return HAL_TIMEOUT;
7003
  }
7004
 
7005
  /* Send slave address */
7006
  hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
7007
 
7008
  /* Wait until ADDR flag is set */
7009
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
7010
  {
7011
    return HAL_ERROR;
7012
  }
7013
 
7014
  return HAL_OK;
7015
}
7016
 
7017
/**
7018
  * @brief  DMA I2C process complete callback.
7019
  * @param  hdma DMA handle
7020
  * @retval None
7021
  */
7022
static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
7023
{
7024
  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7025
 
7026
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
7027
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
7028
  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
7029
  uint32_t CurrentXferOptions       = hi2c->XferOptions;
7030
 
7031
  /* Disable EVT and ERR interrupt */
7032
  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
7033
 
7034
  /* Clear Complete callback */
7035
  if (hi2c->hdmatx != NULL)
7036
  {
7037
    hi2c->hdmatx->XferCpltCallback = NULL;
7038
  }
7039
  if (hi2c->hdmarx != NULL)
7040
  {
7041
    hi2c->hdmarx->XferCpltCallback = NULL;
7042
  }
7043
 
7044
  if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
7045
  {
7046
    /* Disable DMA Request */
7047
    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
7048
 
7049
    hi2c->XferCount = 0U;
7050
 
7051
    if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
7052
    {
7053
      /* Set state at HAL_I2C_STATE_LISTEN */
7054
      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
7055
      hi2c->State = HAL_I2C_STATE_LISTEN;
7056
 
7057
      /* Call the corresponding callback to inform upper layer of End of Transfer */
7058
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7059
      hi2c->SlaveTxCpltCallback(hi2c);
7060
#else
7061
      HAL_I2C_SlaveTxCpltCallback(hi2c);
7062
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7063
    }
7064
    else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
7065
    {
7066
      /* Set state at HAL_I2C_STATE_LISTEN */
7067
      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
7068
      hi2c->State = HAL_I2C_STATE_LISTEN;
7069
 
7070
      /* Call the corresponding callback to inform upper layer of End of Transfer */
7071
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7072
      hi2c->SlaveRxCpltCallback(hi2c);
7073
#else
7074
      HAL_I2C_SlaveRxCpltCallback(hi2c);
7075
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7076
    }
7077
    else
7078
    {
7079
      /* Do nothing */
7080
    }
7081
 
7082
    /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
7083
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
7084
  }
7085
  /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
7086
  else if (hi2c->Mode != HAL_I2C_MODE_NONE)
7087
  {
7088
    if (hi2c->XferCount == (uint16_t)1)
7089
    {
7090
      /* Disable Acknowledge */
7091
      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7092
    }
7093
 
7094
    /* Disable EVT and ERR interrupt */
7095
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
7096
 
7097
    /* Prepare next transfer or stop current transfer */
7098
    if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
7099
    {
7100
      /* Generate Stop */
7101
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
7102
    }
7103
 
7104
    /* Disable Last DMA */
7105
    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
7106
 
7107
    /* Disable DMA Request */
7108
    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
7109
 
7110
    hi2c->XferCount = 0U;
7111
 
7112
    /* Check if Errors has been detected during transfer */
7113
    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
7114
    {
7115
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7116
      hi2c->ErrorCallback(hi2c);
7117
#else
7118
      HAL_I2C_ErrorCallback(hi2c);
7119
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7120
    }
7121
    else
7122
    {
7123
      hi2c->State = HAL_I2C_STATE_READY;
7124
 
7125
      if (hi2c->Mode == HAL_I2C_MODE_MEM)
7126
      {
7127
        hi2c->Mode = HAL_I2C_MODE_NONE;
7128
        hi2c->PreviousState = I2C_STATE_NONE;
7129
 
7130
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7131
        hi2c->MemRxCpltCallback(hi2c);
7132
#else
7133
        HAL_I2C_MemRxCpltCallback(hi2c);
7134
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7135
      }
7136
      else
7137
      {
7138
        hi2c->Mode = HAL_I2C_MODE_NONE;
7139
        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
7140
 
7141
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7142
        hi2c->MasterRxCpltCallback(hi2c);
7143
#else
7144
        HAL_I2C_MasterRxCpltCallback(hi2c);
7145
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7146
      }
7147
    }
7148
  }
7149
  else
7150
  {
7151
    /* Do nothing */
7152
  }
7153
}
7154
 
7155
/**
7156
  * @brief  DMA I2C communication error callback.
7157
  * @param  hdma DMA handle
7158
  * @retval None
7159
  */
7160
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7161
{
7162
  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7163
 
7164
  /* Clear Complete callback */
7165
  if (hi2c->hdmatx != NULL)
7166
  {
7167
    hi2c->hdmatx->XferCpltCallback = NULL;
7168
  }
7169
  if (hi2c->hdmarx != NULL)
7170
  {
7171
    hi2c->hdmarx->XferCpltCallback = NULL;
7172
  }
7173
 
7174
  /* Disable Acknowledge */
7175
  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7176
 
7177
  hi2c->XferCount       = 0U;
7178
  hi2c->State           = HAL_I2C_STATE_READY;
7179
  hi2c->Mode            = HAL_I2C_MODE_NONE;
7180
  hi2c->ErrorCode       |= HAL_I2C_ERROR_DMA;
7181
 
7182
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7183
  hi2c->ErrorCallback(hi2c);
7184
#else
7185
  HAL_I2C_ErrorCallback(hi2c);
7186
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7187
}
7188
 
7189
/**
7190
  * @brief DMA I2C communication abort callback
7191
  *        (To be called at end of DMA Abort procedure).
7192
  * @param hdma DMA handle.
7193
  * @retval None
7194
  */
7195
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7196
{
7197
  __IO uint32_t count = 0U;
7198
  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7199
 
7200
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
7201
  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
7202
 
7203
  /* During abort treatment, check that there is no pending STOP request */
7204
  /* Wait until STOP flag is reset */
7205
  count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
7206
  do
7207
  {
7208
    if (count == 0U)
7209
    {
7210
      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7211
      break;
7212
    }
7213
    count--;
7214
  }
7215
  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7216
 
7217
  /* Clear Complete callback */
7218
  if (hi2c->hdmatx != NULL)
7219
  {
7220
    hi2c->hdmatx->XferCpltCallback = NULL;
7221
  }
7222
  if (hi2c->hdmarx != NULL)
7223
  {
7224
    hi2c->hdmarx->XferCpltCallback = NULL;
7225
  }
7226
 
7227
  /* Disable Acknowledge */
7228
  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7229
 
7230
  hi2c->XferCount = 0U;
7231
 
7232
  /* Reset XferAbortCallback */
7233
  if (hi2c->hdmatx != NULL)
7234
  {
7235
    hi2c->hdmatx->XferAbortCallback = NULL;
7236
  }
7237
  if (hi2c->hdmarx != NULL)
7238
  {
7239
    hi2c->hdmarx->XferAbortCallback = NULL;
7240
  }
7241
 
7242
  /* Disable I2C peripheral to prevent dummy data in buffer */
7243
  __HAL_I2C_DISABLE(hi2c);
7244
 
7245
  /* Check if come from abort from user */
7246
  if (hi2c->State == HAL_I2C_STATE_ABORT)
7247
  {
7248
    hi2c->State         = HAL_I2C_STATE_READY;
7249
    hi2c->Mode          = HAL_I2C_MODE_NONE;
7250
    hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
7251
 
7252
    /* Call the corresponding callback to inform upper layer of End of Transfer */
7253
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7254
    hi2c->AbortCpltCallback(hi2c);
7255
#else
7256
    HAL_I2C_AbortCpltCallback(hi2c);
7257
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7258
  }
7259
  else
7260
  {
7261
    if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
7262
    {
7263
      /* Renable I2C peripheral */
7264
      __HAL_I2C_ENABLE(hi2c);
7265
 
7266
      /* Enable Acknowledge */
7267
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7268
 
7269
      /* keep HAL_I2C_STATE_LISTEN */
7270
      hi2c->PreviousState = I2C_STATE_NONE;
7271
      hi2c->State = HAL_I2C_STATE_LISTEN;
7272
    }
7273
    else
7274
    {
7275
      hi2c->State = HAL_I2C_STATE_READY;
7276
      hi2c->Mode = HAL_I2C_MODE_NONE;
7277
    }
7278
 
7279
    /* Call the corresponding callback to inform upper layer of End of Transfer */
7280
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7281
    hi2c->ErrorCallback(hi2c);
7282
#else
7283
    HAL_I2C_ErrorCallback(hi2c);
7284
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7285
  }
7286
}
7287
 
7288
/**
7289
  * @brief  This function handles I2C Communication Timeout.
7290
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
7291
  *         the configuration information for I2C module
7292
  * @param  Flag specifies the I2C flag to check.
7293
  * @param  Status The new Flag status (SET or RESET).
7294
  * @param  Timeout Timeout duration
7295
  * @param  Tickstart Tick start value
7296
  * @retval HAL status
7297
  */
7298
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
7299
{
7300
  /* Wait until flag is set */
7301
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7302
  {
7303
    /* Check for the Timeout */
7304
    if (Timeout != HAL_MAX_DELAY)
7305
    {
7306
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7307
      {
7308
        if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
7309
        {
7310
          hi2c->PreviousState     = I2C_STATE_NONE;
7311
          hi2c->State             = HAL_I2C_STATE_READY;
7312
          hi2c->Mode              = HAL_I2C_MODE_NONE;
7313
          hi2c->ErrorCode         |= HAL_I2C_ERROR_TIMEOUT;
7314
 
7315
          /* Process Unlocked */
7316
          __HAL_UNLOCK(hi2c);
7317
 
7318
          return HAL_ERROR;
7319
        }
7320
      }
7321
    }
7322
  }
7323
  return HAL_OK;
7324
}
7325
 
7326
/**
7327
  * @brief  This function handles I2C Communication Timeout for Master addressing phase.
7328
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
7329
  *         the configuration information for I2C module
7330
  * @param  Flag specifies the I2C flag to check.
7331
  * @param  Timeout Timeout duration
7332
  * @param  Tickstart Tick start value
7333
  * @retval HAL status
7334
  */
7335
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
7336
{
7337
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
7338
  {
7339
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7340
    {
7341
      /* Generate Stop */
7342
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
7343
 
7344
      /* Clear AF Flag */
7345
      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7346
 
7347
      hi2c->PreviousState       = I2C_STATE_NONE;
7348
      hi2c->State               = HAL_I2C_STATE_READY;
7349
      hi2c->Mode                = HAL_I2C_MODE_NONE;
7350
      hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
7351
 
7352
      /* Process Unlocked */
7353
      __HAL_UNLOCK(hi2c);
7354
 
7355
      return HAL_ERROR;
7356
    }
7357
 
7358
    /* Check for the Timeout */
7359
    if (Timeout != HAL_MAX_DELAY)
7360
    {
7361
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7362
      {
7363
        if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
7364
        {
7365
          hi2c->PreviousState       = I2C_STATE_NONE;
7366
          hi2c->State               = HAL_I2C_STATE_READY;
7367
          hi2c->Mode                = HAL_I2C_MODE_NONE;
7368
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
7369
 
7370
          /* Process Unlocked */
7371
          __HAL_UNLOCK(hi2c);
7372
 
7373
          return HAL_ERROR;
7374
        }
7375
      }
7376
    }
7377
  }
7378
  return HAL_OK;
7379
}
7380
 
7381
/**
7382
  * @brief  This function handles I2C Communication Timeout for specific usage of TXE flag.
7383
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
7384
  *                the configuration information for the specified I2C.
7385
  * @param  Timeout Timeout duration
7386
  * @param  Tickstart Tick start value
7387
  * @retval HAL status
7388
  */
7389
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7390
{
7391
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
7392
  {
7393
    /* Check if a NACK is detected */
7394
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7395
    {
7396
      return HAL_ERROR;
7397
    }
7398
 
7399
    /* Check for the Timeout */
7400
    if (Timeout != HAL_MAX_DELAY)
7401
    {
7402
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7403
      {
7404
        if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
7405
        {
7406
          hi2c->PreviousState       = I2C_STATE_NONE;
7407
          hi2c->State               = HAL_I2C_STATE_READY;
7408
          hi2c->Mode                = HAL_I2C_MODE_NONE;
7409
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
7410
 
7411
          /* Process Unlocked */
7412
          __HAL_UNLOCK(hi2c);
7413
 
7414
          return HAL_ERROR;
7415
        }
7416
      }
7417
    }
7418
  }
7419
  return HAL_OK;
7420
}
7421
 
7422
/**
7423
  * @brief  This function handles I2C Communication Timeout for specific usage of BTF flag.
7424
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
7425
  *                the configuration information for the specified I2C.
7426
  * @param  Timeout Timeout duration
7427
  * @param  Tickstart Tick start value
7428
  * @retval HAL status
7429
  */
7430
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7431
{
7432
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
7433
  {
7434
    /* Check if a NACK is detected */
7435
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7436
    {
7437
      return HAL_ERROR;
7438
    }
7439
 
7440
    /* Check for the Timeout */
7441
    if (Timeout != HAL_MAX_DELAY)
7442
    {
7443
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7444
      {
7445
        if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
7446
        {
7447
          hi2c->PreviousState       = I2C_STATE_NONE;
7448
          hi2c->State               = HAL_I2C_STATE_READY;
7449
          hi2c->Mode                = HAL_I2C_MODE_NONE;
7450
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
7451
 
7452
          /* Process Unlocked */
7453
          __HAL_UNLOCK(hi2c);
7454
 
7455
          return HAL_ERROR;
7456
        }
7457
      }
7458
    }
7459
  }
7460
  return HAL_OK;
7461
}
7462
 
7463
/**
7464
  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
7465
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
7466
  *                the configuration information for the specified I2C.
7467
  * @param  Timeout Timeout duration
7468
  * @param  Tickstart Tick start value
7469
  * @retval HAL status
7470
  */
7471
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7472
{
7473
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7474
  {
7475
    /* Check if a NACK is detected */
7476
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7477
    {
7478
      return HAL_ERROR;
7479
    }
7480
 
7481
    /* Check for the Timeout */
7482
    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7483
    {
7484
      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7485
      {
7486
        hi2c->PreviousState       = I2C_STATE_NONE;
7487
        hi2c->State               = HAL_I2C_STATE_READY;
7488
        hi2c->Mode                = HAL_I2C_MODE_NONE;
7489
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
7490
 
7491
        /* Process Unlocked */
7492
        __HAL_UNLOCK(hi2c);
7493
 
7494
        return HAL_ERROR;
7495
      }
7496
    }
7497
  }
7498
  return HAL_OK;
7499
}
7500
 
7501
/**
7502
  * @brief  This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
7503
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
7504
  *                the configuration information for the specified I2C.
7505
  * @retval HAL status
7506
  */
7507
static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
7508
{
7509
  __IO uint32_t count = 0U;
7510
 
7511
  /* Wait until STOP flag is reset */
7512
  count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
7513
  do
7514
  {
7515
    count--;
7516
    if (count == 0U)
7517
    {
7518
      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
7519
 
7520
      return HAL_ERROR;
7521
    }
7522
  }
7523
  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7524
 
7525
  return HAL_OK;
7526
}
7527
 
7528
/**
7529
  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
7530
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
7531
  *                the configuration information for the specified I2C.
7532
  * @param  Timeout Timeout duration
7533
  * @param  Tickstart Tick start value
7534
  * @retval HAL status
7535
  */
7536
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7537
{
7538
 
7539
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7540
  {
7541
    /* Check if a STOPF is detected */
7542
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7543
    {
7544
      /* Clear STOP Flag */
7545
      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7546
 
7547
      hi2c->PreviousState       = I2C_STATE_NONE;
7548
      hi2c->State               = HAL_I2C_STATE_READY;
7549
      hi2c->Mode                = HAL_I2C_MODE_NONE;
7550
      hi2c->ErrorCode           |= HAL_I2C_ERROR_NONE;
7551
 
7552
      /* Process Unlocked */
7553
      __HAL_UNLOCK(hi2c);
7554
 
7555
      return HAL_ERROR;
7556
    }
7557
 
7558
    /* Check for the Timeout */
7559
    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7560
    {
7561
      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7562
      {
7563
        hi2c->PreviousState       = I2C_STATE_NONE;
7564
        hi2c->State               = HAL_I2C_STATE_READY;
7565
        hi2c->Mode                = HAL_I2C_MODE_NONE;
7566
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
7567
 
7568
        /* Process Unlocked */
7569
        __HAL_UNLOCK(hi2c);
7570
 
7571
        return HAL_ERROR;
7572
      }
7573
    }
7574
  }
7575
  return HAL_OK;
7576
}
7577
 
7578
/**
7579
  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
7580
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
7581
  *                the configuration information for the specified I2C.
7582
  * @retval HAL status
7583
  */
7584
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
7585
{
7586
  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7587
  {
7588
    /* Clear NACKF Flag */
7589
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7590
 
7591
    hi2c->PreviousState       = I2C_STATE_NONE;
7592
    hi2c->State               = HAL_I2C_STATE_READY;
7593
    hi2c->Mode                = HAL_I2C_MODE_NONE;
7594
    hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
7595
 
7596
    /* Process Unlocked */
7597
    __HAL_UNLOCK(hi2c);
7598
 
7599
    return HAL_ERROR;
7600
  }
7601
  return HAL_OK;
7602
}
7603
 
7604
/**
7605
  * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7606
  * @param  hi2c I2C handle.
7607
  * @retval None
7608
  */
7609
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7610
{
7611
  /* if user set XferOptions to I2C_OTHER_FRAME            */
7612
  /* it request implicitly to generate a restart condition */
7613
  /* set XferOptions to I2C_FIRST_FRAME                    */
7614
  if (hi2c->XferOptions == I2C_OTHER_FRAME)
7615
  {
7616
    hi2c->XferOptions = I2C_FIRST_FRAME;
7617
  }
7618
  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7619
  /* it request implicitly to generate a restart condition    */
7620
  /* then generate a stop condition at the end of transfer    */
7621
  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
7622
  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7623
  {
7624
    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7625
  }
7626
  else
7627
  {
7628
    /* Nothing to do */
7629
  }
7630
}
7631
 
7632
/**
7633
  * @}
7634
  */
7635
 
7636
#endif /* HAL_I2C_MODULE_ENABLED */
7637
/**
7638
  * @}
7639
  */
7640
 
7641
/**
7642
  * @}
7643
  */
7644