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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f1xx_hal_gpio.c |
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4 | * @author MCD Application Team |
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5 | mjames | 5 | * @version V1.0.4 |
6 | * @date 29-April-2016 |
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2 | mjames | 7 | * @brief GPIO HAL module driver. |
8 | * This file provides firmware functions to manage the following |
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9 | * functionalities of the General Purpose Input/Output (GPIO) peripheral: |
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10 | * + Initialization and de-initialization functions |
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11 | * + IO operation functions |
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12 | * |
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13 | @verbatim |
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14 | ============================================================================== |
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15 | ##### GPIO Peripheral features ##### |
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16 | ============================================================================== |
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17 | [..] |
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18 | Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each |
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19 | port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software |
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20 | in several modes: |
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21 | (+) Input mode |
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22 | (+) Analog mode |
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23 | (+) Output mode |
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24 | (+) Alternate function mode |
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25 | (+) External interrupt/event lines |
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26 | |||
27 | [..] |
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28 | During and just after reset, the alternate functions and external interrupt |
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29 | lines are not active and the I/O ports are configured in input floating mode. |
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30 | |||
31 | [..] |
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32 | All GPIO pins have weak internal pull-up and pull-down resistors, which can be |
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33 | activated or not. |
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34 | |||
35 | [..] |
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36 | In Output or Alternate mode, each IO can be configured on open-drain or push-pull |
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37 | type and the IO speed can be selected depending on the VDD value. |
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38 | |||
39 | [..] |
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40 | All ports have external interrupt/event capability. To use external interrupt |
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41 | lines, the port must be configured in input mode. All available GPIO pins are |
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42 | connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. |
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43 | |||
44 | [..] |
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45 | The external interrupt/event controller consists of up to 20 edge detectors in connectivity |
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46 | line devices, or 19 edge detectors in other devices for generating event/interrupt requests. |
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47 | Each input line can be independently configured to select the type (event or interrupt) and |
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48 | the corresponding trigger event (rising or falling or both). Each line can also masked |
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49 | independently. A pending register maintains the status line of the interrupt requests |
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50 | |||
51 | ##### How to use this driver ##### |
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52 | ============================================================================== |
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53 | [..] |
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54 | (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). |
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55 | |||
56 | (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). |
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57 | (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure |
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58 | (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef |
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59 | structure. |
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60 | (++) In case of Output or alternate function mode selection: the speed is |
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61 | configured through "Speed" member from GPIO_InitTypeDef structure |
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62 | (++) Analog mode is required when a pin is to be used as ADC channel |
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63 | or DAC output. |
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64 | (++) In case of external interrupt/event selection the "Mode" member from |
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65 | GPIO_InitTypeDef structure select the type (interrupt or event) and |
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66 | the corresponding trigger event (rising or falling or both). |
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67 | |||
68 | (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority |
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69 | mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using |
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70 | HAL_NVIC_EnableIRQ(). |
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71 | |||
72 | (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). |
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73 | |||
74 | (#) To set/reset the level of a pin configured in output mode use |
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75 | HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). |
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76 | |||
77 | (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). |
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78 | |||
79 | (#) During and just after reset, the alternate functions are not |
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80 | active and the GPIO pins are configured in input floating mode (except JTAG |
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81 | pins). |
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82 | |||
83 | (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose |
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84 | (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has |
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85 | priority over the GPIO function. |
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86 | |||
87 | (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as |
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88 | general purpose PD0 and PD1, respectively, when the HSE oscillator is off. |
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89 | The HSE has priority over the GPIO function. |
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90 | |||
91 | @endverbatim |
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92 | ****************************************************************************** |
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93 | * @attention |
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94 | * |
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5 | mjames | 95 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
2 | mjames | 96 | * |
97 | * Redistribution and use in source and binary forms, with or without modification, |
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98 | * are permitted provided that the following conditions are met: |
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99 | * 1. Redistributions of source code must retain the above copyright notice, |
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100 | * this list of conditions and the following disclaimer. |
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101 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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102 | * this list of conditions and the following disclaimer in the documentation |
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103 | * and/or other materials provided with the distribution. |
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104 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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105 | * may be used to endorse or promote products derived from this software |
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106 | * without specific prior written permission. |
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107 | * |
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108 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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109 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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110 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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111 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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112 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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113 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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114 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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115 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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116 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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117 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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118 | * |
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119 | ****************************************************************************** |
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120 | */ |
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121 | |||
122 | /* Includes ------------------------------------------------------------------*/ |
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123 | #include "stm32f1xx_hal.h" |
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124 | |||
125 | /** @addtogroup STM32F1xx_HAL_Driver |
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126 | * @{ |
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127 | */ |
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128 | |||
129 | /** @defgroup GPIO GPIO |
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130 | * @brief GPIO HAL module driver |
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131 | * @{ |
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132 | */ |
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133 | |||
134 | #ifdef HAL_GPIO_MODULE_ENABLED |
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135 | |||
136 | /* Private typedef -----------------------------------------------------------*/ |
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137 | /* Private define ------------------------------------------------------------*/ |
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138 | /** @defgroup GPIO_Private_Constants GPIO Private Constants |
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139 | * @{ |
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140 | */ |
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141 | |||
142 | #define GPIO_MODE ((uint32_t)0x00000003) |
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143 | #define EXTI_MODE ((uint32_t)0x10000000) |
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144 | #define GPIO_MODE_IT ((uint32_t)0x00010000) |
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145 | #define GPIO_MODE_EVT ((uint32_t)0x00020000) |
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146 | #define RISING_EDGE ((uint32_t)0x00100000) |
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147 | #define FALLING_EDGE ((uint32_t)0x00200000) |
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148 | #define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) |
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149 | #define GPIO_NUMBER ((uint32_t)16) |
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150 | |||
151 | /* Definitions for bit manipulation of CRL and CRH register */ |
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152 | #define GPIO_CR_MODE_INPUT ((uint32_t)0x00000000) /*!< 00: Input mode (reset state) */ |
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153 | #define GPIO_CR_CNF_ANALOG ((uint32_t)0x00000000) /*!< 00: Analog mode */ |
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154 | #define GPIO_CR_CNF_INPUT_FLOATING ((uint32_t)0x00000004) /*!< 01: Floating input (reset state) */ |
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155 | #define GPIO_CR_CNF_INPUT_PU_PD ((uint32_t)0x00000008) /*!< 10: Input with pull-up / pull-down */ |
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156 | #define GPIO_CR_CNF_GP_OUTPUT_PP ((uint32_t)0x00000000) /*!< 00: General purpose output push-pull */ |
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157 | #define GPIO_CR_CNF_GP_OUTPUT_OD ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain */ |
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158 | #define GPIO_CR_CNF_AF_OUTPUT_PP ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull */ |
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159 | #define GPIO_CR_CNF_AF_OUTPUT_OD ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain */ |
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160 | |||
161 | /** |
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162 | * @} |
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163 | */ |
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164 | |||
165 | /* Private macro -------------------------------------------------------------*/ |
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166 | /* Private variables ---------------------------------------------------------*/ |
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167 | /* Private function prototypes -----------------------------------------------*/ |
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168 | /* Private functions ---------------------------------------------------------*/ |
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169 | |||
170 | /** @defgroup GPIO_Exported_Functions GPIO Exported Functions |
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171 | * @{ |
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172 | */ |
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173 | |||
174 | /** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions |
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175 | * @brief Initialization and Configuration functions |
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176 | * |
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177 | @verbatim |
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178 | =============================================================================== |
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179 | ##### Initialization and deinitialization functions ##### |
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180 | =============================================================================== |
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181 | [..] |
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182 | This section provides functions allowing to initialize and de-initialize the GPIOs |
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183 | to be ready for use. |
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184 | |||
185 | @endverbatim |
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186 | * @{ |
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187 | */ |
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188 | |||
189 | /** |
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190 | * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. |
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191 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
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192 | * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains |
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193 | * the configuration information for the specified GPIO peripheral. |
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194 | * @retval None |
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195 | */ |
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196 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) |
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197 | { |
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198 | uint32_t position; |
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199 | uint32_t ioposition = 0x00; |
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200 | uint32_t iocurrent = 0x00; |
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201 | uint32_t temp = 0x00; |
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202 | uint32_t config = 0x00; |
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203 | __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ |
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204 | uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ |
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205 | |||
206 | /* Check the parameters */ |
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207 | assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
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208 | assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); |
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209 | assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); |
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210 | |||
211 | /* Configure the port pins */ |
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212 | for (position = 0; position < GPIO_NUMBER; position++) |
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213 | { |
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214 | /* Get the IO position */ |
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215 | ioposition = ((uint32_t)0x01) << position; |
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216 | |||
217 | /* Get the current IO position */ |
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218 | iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; |
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219 | |||
220 | if (iocurrent == ioposition) |
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221 | { |
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222 | /* Check the Alternate function parameters */ |
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223 | assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); |
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224 | |||
225 | /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ |
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226 | switch (GPIO_Init->Mode) |
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227 | { |
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228 | /* If we are configuring the pin in OUTPUT push-pull mode */ |
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229 | case GPIO_MODE_OUTPUT_PP: |
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230 | /* Check the GPIO speed parameter */ |
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231 | assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
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232 | config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; |
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233 | break; |
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234 | |||
235 | /* If we are configuring the pin in OUTPUT open-drain mode */ |
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236 | case GPIO_MODE_OUTPUT_OD: |
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237 | /* Check the GPIO speed parameter */ |
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238 | assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
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239 | config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; |
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240 | break; |
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241 | |||
242 | /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ |
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243 | case GPIO_MODE_AF_PP: |
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244 | /* Check the GPIO speed parameter */ |
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245 | assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
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246 | config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; |
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247 | break; |
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248 | |||
249 | /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ |
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250 | case GPIO_MODE_AF_OD: |
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251 | /* Check the GPIO speed parameter */ |
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252 | assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
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253 | config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; |
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254 | break; |
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255 | |||
256 | /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ |
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257 | case GPIO_MODE_INPUT: |
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258 | case GPIO_MODE_IT_RISING: |
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259 | case GPIO_MODE_IT_FALLING: |
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260 | case GPIO_MODE_IT_RISING_FALLING: |
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261 | case GPIO_MODE_EVT_RISING: |
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262 | case GPIO_MODE_EVT_FALLING: |
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263 | case GPIO_MODE_EVT_RISING_FALLING: |
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264 | /* Check the GPIO pull parameter */ |
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265 | assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); |
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266 | if(GPIO_Init->Pull == GPIO_NOPULL) |
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267 | { |
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268 | config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; |
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269 | } |
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270 | else if(GPIO_Init->Pull == GPIO_PULLUP) |
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271 | { |
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272 | config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; |
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273 | |||
274 | /* Set the corresponding ODR bit */ |
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275 | GPIOx->BSRR = ioposition; |
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276 | } |
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277 | else /* GPIO_PULLDOWN */ |
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278 | { |
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279 | config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; |
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280 | |||
281 | /* Reset the corresponding ODR bit */ |
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282 | GPIOx->BRR = ioposition; |
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283 | } |
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284 | break; |
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285 | |||
286 | /* If we are configuring the pin in INPUT analog mode */ |
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287 | case GPIO_MODE_ANALOG: |
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288 | config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; |
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289 | break; |
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290 | |||
291 | /* Parameters are checked with assert_param */ |
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292 | default: |
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293 | break; |
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294 | } |
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295 | |||
296 | /* Check if the current bit belongs to first half or last half of the pin count number |
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297 | in order to address CRH or CRL register*/ |
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298 | configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; |
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299 | registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); |
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300 | |||
301 | /* Apply the new configuration of the pin to the register */ |
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302 | MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset)); |
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303 | |||
304 | /*--------------------- EXTI Mode Configuration ------------------------*/ |
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305 | /* Configure the External Interrupt or event for the current IO */ |
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306 | if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) |
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307 | { |
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308 | /* Enable AFIO Clock */ |
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309 | __HAL_RCC_AFIO_CLK_ENABLE(); |
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310 | temp = AFIO->EXTICR[position >> 2]; |
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311 | CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03))); |
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312 | SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); |
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313 | AFIO->EXTICR[position >> 2] = temp; |
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314 | |||
315 | |||
316 | /* Configure the interrupt mask */ |
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317 | if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) |
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318 | { |
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319 | SET_BIT(EXTI->IMR, iocurrent); |
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320 | } |
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321 | else |
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322 | { |
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323 | CLEAR_BIT(EXTI->IMR, iocurrent); |
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324 | } |
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325 | |||
326 | /* Configure the event mask */ |
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327 | if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) |
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328 | { |
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329 | SET_BIT(EXTI->EMR, iocurrent); |
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330 | } |
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331 | else |
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332 | { |
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333 | CLEAR_BIT(EXTI->EMR, iocurrent); |
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334 | } |
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335 | |||
336 | /* Enable or disable the rising trigger */ |
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337 | if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) |
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338 | { |
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339 | SET_BIT(EXTI->RTSR, iocurrent); |
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340 | } |
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341 | else |
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342 | { |
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343 | CLEAR_BIT(EXTI->RTSR, iocurrent); |
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344 | } |
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345 | |||
346 | /* Enable or disable the falling trigger */ |
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347 | if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) |
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348 | { |
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349 | SET_BIT(EXTI->FTSR, iocurrent); |
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350 | } |
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351 | else |
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352 | { |
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353 | CLEAR_BIT(EXTI->FTSR, iocurrent); |
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354 | } |
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355 | } |
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356 | } |
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357 | } |
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358 | } |
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359 | |||
360 | /** |
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361 | * @brief De-initializes the GPIOx peripheral registers to their default reset values. |
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362 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
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363 | * @param GPIO_Pin: specifies the port bit to be written. |
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364 | * This parameter can be one of GPIO_PIN_x where x can be (0..15). |
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365 | * @retval None |
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366 | */ |
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367 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) |
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368 | { |
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369 | uint32_t position = 0x00; |
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370 | uint32_t iocurrent = 0x00; |
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371 | uint32_t tmp = 0x00; |
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372 | __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ |
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373 | uint32_t registeroffset = 0; |
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374 | |||
375 | /* Check the parameters */ |
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376 | assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
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377 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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378 | |||
379 | /* Configure the port pins */ |
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380 | while ((GPIO_Pin >> position) != 0) |
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381 | { |
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382 | /* Get current io position */ |
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383 | iocurrent = (GPIO_Pin) & ((uint32_t)1 << position); |
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384 | |||
385 | if (iocurrent) |
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386 | { |
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387 | /*------------------------- GPIO Mode Configuration --------------------*/ |
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388 | /* Check if the current bit belongs to first half or last half of the pin count number |
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389 | in order to address CRH or CRL register */ |
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390 | configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; |
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391 | registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); |
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392 | |||
393 | /* CRL/CRH default value is floating input(0x04) shifted to correct position */ |
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394 | MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset); |
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395 | |||
396 | /* ODR default value is 0 */ |
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397 | CLEAR_BIT(GPIOx->ODR, iocurrent); |
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398 | |||
399 | /*------------------------- EXTI Mode Configuration --------------------*/ |
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400 | /* Clear the External Interrupt or Event for the current IO */ |
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401 | |||
402 | tmp = AFIO->EXTICR[position >> 2]; |
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403 | tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); |
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404 | if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) |
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405 | { |
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406 | tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); |
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407 | CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp); |
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408 | |||
409 | /* Clear EXTI line configuration */ |
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410 | CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); |
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411 | CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); |
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412 | |||
413 | /* Clear Rising Falling edge configuration */ |
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414 | CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); |
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415 | CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); |
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416 | } |
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417 | } |
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418 | |||
419 | position++; |
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420 | } |
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421 | } |
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422 | |||
423 | /** |
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424 | * @} |
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425 | */ |
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426 | |||
427 | /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions |
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428 | * @brief GPIO Read and Write |
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429 | * |
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430 | @verbatim |
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431 | =============================================================================== |
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432 | ##### IO operation functions ##### |
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433 | =============================================================================== |
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434 | [..] |
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435 | This subsection provides a set of functions allowing to manage the GPIOs. |
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436 | |||
437 | @endverbatim |
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438 | * @{ |
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439 | */ |
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440 | /** |
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441 | * @brief Reads the specified input port pin. |
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442 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
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443 | * @param GPIO_Pin: specifies the port bit to read. |
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444 | * This parameter can be GPIO_PIN_x where x can be (0..15). |
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445 | * @retval The input port pin value. |
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446 | */ |
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447 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
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448 | { |
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449 | GPIO_PinState bitstatus; |
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450 | |||
451 | /* Check the parameters */ |
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452 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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453 | |||
454 | if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) |
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455 | { |
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456 | bitstatus = GPIO_PIN_SET; |
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457 | } |
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458 | else |
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459 | { |
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460 | bitstatus = GPIO_PIN_RESET; |
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461 | } |
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462 | return bitstatus; |
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463 | } |
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464 | |||
465 | /** |
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466 | * @brief Sets or clears the selected data port bit. |
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467 | * |
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468 | * @note This function uses GPIOx_BSRR register to allow atomic read/modify |
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469 | * accesses. In this way, there is no risk of an IRQ occurring between |
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470 | * the read and the modify access. |
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471 | * |
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472 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
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473 | * @param GPIO_Pin: specifies the port bit to be written. |
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474 | * This parameter can be one of GPIO_PIN_x where x can be (0..15). |
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475 | * @param PinState: specifies the value to be written to the selected bit. |
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476 | * This parameter can be one of the GPIO_PinState enum values: |
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477 | * @arg GPIO_BIT_RESET: to clear the port pin |
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478 | * @arg GPIO_BIT_SET: to set the port pin |
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479 | * @retval None |
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480 | */ |
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481 | void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) |
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482 | { |
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483 | /* Check the parameters */ |
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484 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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485 | assert_param(IS_GPIO_PIN_ACTION(PinState)); |
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486 | |||
487 | if(PinState != GPIO_PIN_RESET) |
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488 | { |
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489 | GPIOx->BSRR = GPIO_Pin; |
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490 | } |
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491 | else |
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492 | { |
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493 | GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; |
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494 | } |
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495 | } |
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496 | |||
497 | /** |
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498 | * @brief Toggles the specified GPIO pin |
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499 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
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500 | * @param GPIO_Pin: Specifies the pins to be toggled. |
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501 | * @retval None |
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502 | */ |
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503 | void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
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504 | { |
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505 | /* Check the parameters */ |
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506 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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507 | |||
508 | GPIOx->ODR ^= GPIO_Pin; |
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509 | } |
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510 | |||
511 | /** |
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512 | * @brief Locks GPIO Pins configuration registers. |
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513 | * @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence |
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514 | * has been applied on a port bit, it is no longer possible to modify the value of the port bit until |
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515 | * the next reset. |
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516 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
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517 | * @param GPIO_Pin: specifies the port bit to be locked. |
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518 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). |
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519 | * @retval None |
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520 | */ |
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521 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
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522 | { |
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523 | __IO uint32_t tmp = GPIO_LCKR_LCKK; |
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524 | |||
525 | /* Check the parameters */ |
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526 | assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); |
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527 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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528 | |||
529 | /* Apply lock key write sequence */ |
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530 | SET_BIT(tmp, GPIO_Pin); |
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531 | /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
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532 | GPIOx->LCKR = tmp; |
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533 | /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ |
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534 | GPIOx->LCKR = GPIO_Pin; |
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535 | /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
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536 | GPIOx->LCKR = tmp; |
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537 | /* Read LCKK bit*/ |
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538 | tmp = GPIOx->LCKR; |
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539 | |||
540 | if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) |
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541 | { |
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542 | return HAL_OK; |
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543 | } |
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544 | else |
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545 | { |
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546 | return HAL_ERROR; |
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547 | } |
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548 | } |
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549 | |||
550 | /** |
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551 | * @brief This function handles EXTI interrupt request. |
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552 | * @param GPIO_Pin: Specifies the pins connected EXTI line |
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553 | * @retval None |
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554 | */ |
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555 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) |
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556 | { |
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557 | /* EXTI line interrupt detected */ |
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558 | if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) |
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559 | { |
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560 | __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); |
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561 | HAL_GPIO_EXTI_Callback(GPIO_Pin); |
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562 | } |
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563 | } |
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564 | |||
565 | /** |
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566 | * @brief EXTI line detection callback |
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567 | * @param GPIO_Pin: Specifies the pins connected EXTI line |
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568 | * @retval None |
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569 | */ |
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570 | __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) |
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571 | { |
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5 | mjames | 572 | /* Prevent unused argument(s) compilation warning */ |
573 | UNUSED(GPIO_Pin); |
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2 | mjames | 574 | /* NOTE : This function Should not be modified, when the callback is needed, |
575 | the HAL_GPIO_EXTI_Callback could be implemented in the user file |
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576 | */ |
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577 | } |
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578 | |||
579 | /** |
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580 | * @} |
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581 | */ |
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582 | |||
583 | |||
584 | /** |
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585 | * @} |
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586 | */ |
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587 | |||
588 | #endif /* HAL_GPIO_MODULE_ENABLED */ |
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589 | /** |
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590 | * @} |
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591 | */ |
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592 | |||
593 | /** |
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594 | * @} |
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595 | */ |
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596 | |||
597 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |