Rev 2 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
||
| 3 | * @file stm32f1xx_hal_gpio.c |
||
| 4 | * @author MCD Application Team |
||
| 5 | mjames | 5 | * @version V1.0.4 |
| 6 | * @date 29-April-2016 |
||
| 2 | mjames | 7 | * @brief GPIO HAL module driver. |
| 8 | * This file provides firmware functions to manage the following |
||
| 9 | * functionalities of the General Purpose Input/Output (GPIO) peripheral: |
||
| 10 | * + Initialization and de-initialization functions |
||
| 11 | * + IO operation functions |
||
| 12 | * |
||
| 13 | @verbatim |
||
| 14 | ============================================================================== |
||
| 15 | ##### GPIO Peripheral features ##### |
||
| 16 | ============================================================================== |
||
| 17 | [..] |
||
| 18 | Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each |
||
| 19 | port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software |
||
| 20 | in several modes: |
||
| 21 | (+) Input mode |
||
| 22 | (+) Analog mode |
||
| 23 | (+) Output mode |
||
| 24 | (+) Alternate function mode |
||
| 25 | (+) External interrupt/event lines |
||
| 26 | |||
| 27 | [..] |
||
| 28 | During and just after reset, the alternate functions and external interrupt |
||
| 29 | lines are not active and the I/O ports are configured in input floating mode. |
||
| 30 | |||
| 31 | [..] |
||
| 32 | All GPIO pins have weak internal pull-up and pull-down resistors, which can be |
||
| 33 | activated or not. |
||
| 34 | |||
| 35 | [..] |
||
| 36 | In Output or Alternate mode, each IO can be configured on open-drain or push-pull |
||
| 37 | type and the IO speed can be selected depending on the VDD value. |
||
| 38 | |||
| 39 | [..] |
||
| 40 | All ports have external interrupt/event capability. To use external interrupt |
||
| 41 | lines, the port must be configured in input mode. All available GPIO pins are |
||
| 42 | connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. |
||
| 43 | |||
| 44 | [..] |
||
| 45 | The external interrupt/event controller consists of up to 20 edge detectors in connectivity |
||
| 46 | line devices, or 19 edge detectors in other devices for generating event/interrupt requests. |
||
| 47 | Each input line can be independently configured to select the type (event or interrupt) and |
||
| 48 | the corresponding trigger event (rising or falling or both). Each line can also masked |
||
| 49 | independently. A pending register maintains the status line of the interrupt requests |
||
| 50 | |||
| 51 | ##### How to use this driver ##### |
||
| 52 | ============================================================================== |
||
| 53 | [..] |
||
| 54 | (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). |
||
| 55 | |||
| 56 | (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). |
||
| 57 | (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure |
||
| 58 | (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef |
||
| 59 | structure. |
||
| 60 | (++) In case of Output or alternate function mode selection: the speed is |
||
| 61 | configured through "Speed" member from GPIO_InitTypeDef structure |
||
| 62 | (++) Analog mode is required when a pin is to be used as ADC channel |
||
| 63 | or DAC output. |
||
| 64 | (++) In case of external interrupt/event selection the "Mode" member from |
||
| 65 | GPIO_InitTypeDef structure select the type (interrupt or event) and |
||
| 66 | the corresponding trigger event (rising or falling or both). |
||
| 67 | |||
| 68 | (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority |
||
| 69 | mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using |
||
| 70 | HAL_NVIC_EnableIRQ(). |
||
| 71 | |||
| 72 | (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). |
||
| 73 | |||
| 74 | (#) To set/reset the level of a pin configured in output mode use |
||
| 75 | HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). |
||
| 76 | |||
| 77 | (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). |
||
| 78 | |||
| 79 | (#) During and just after reset, the alternate functions are not |
||
| 80 | active and the GPIO pins are configured in input floating mode (except JTAG |
||
| 81 | pins). |
||
| 82 | |||
| 83 | (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose |
||
| 84 | (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has |
||
| 85 | priority over the GPIO function. |
||
| 86 | |||
| 87 | (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as |
||
| 88 | general purpose PD0 and PD1, respectively, when the HSE oscillator is off. |
||
| 89 | The HSE has priority over the GPIO function. |
||
| 90 | |||
| 91 | @endverbatim |
||
| 92 | ****************************************************************************** |
||
| 93 | * @attention |
||
| 94 | * |
||
| 5 | mjames | 95 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| 2 | mjames | 96 | * |
| 97 | * Redistribution and use in source and binary forms, with or without modification, |
||
| 98 | * are permitted provided that the following conditions are met: |
||
| 99 | * 1. Redistributions of source code must retain the above copyright notice, |
||
| 100 | * this list of conditions and the following disclaimer. |
||
| 101 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
||
| 102 | * this list of conditions and the following disclaimer in the documentation |
||
| 103 | * and/or other materials provided with the distribution. |
||
| 104 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
||
| 105 | * may be used to endorse or promote products derived from this software |
||
| 106 | * without specific prior written permission. |
||
| 107 | * |
||
| 108 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||
| 109 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||
| 110 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||
| 111 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||
| 112 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||
| 113 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||
| 114 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||
| 115 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||
| 116 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||
| 117 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
| 118 | * |
||
| 119 | ****************************************************************************** |
||
| 120 | */ |
||
| 121 | |||
| 122 | /* Includes ------------------------------------------------------------------*/ |
||
| 123 | #include "stm32f1xx_hal.h" |
||
| 124 | |||
| 125 | /** @addtogroup STM32F1xx_HAL_Driver |
||
| 126 | * @{ |
||
| 127 | */ |
||
| 128 | |||
| 129 | /** @defgroup GPIO GPIO |
||
| 130 | * @brief GPIO HAL module driver |
||
| 131 | * @{ |
||
| 132 | */ |
||
| 133 | |||
| 134 | #ifdef HAL_GPIO_MODULE_ENABLED |
||
| 135 | |||
| 136 | /* Private typedef -----------------------------------------------------------*/ |
||
| 137 | /* Private define ------------------------------------------------------------*/ |
||
| 138 | /** @defgroup GPIO_Private_Constants GPIO Private Constants |
||
| 139 | * @{ |
||
| 140 | */ |
||
| 141 | |||
| 142 | #define GPIO_MODE ((uint32_t)0x00000003) |
||
| 143 | #define EXTI_MODE ((uint32_t)0x10000000) |
||
| 144 | #define GPIO_MODE_IT ((uint32_t)0x00010000) |
||
| 145 | #define GPIO_MODE_EVT ((uint32_t)0x00020000) |
||
| 146 | #define RISING_EDGE ((uint32_t)0x00100000) |
||
| 147 | #define FALLING_EDGE ((uint32_t)0x00200000) |
||
| 148 | #define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) |
||
| 149 | #define GPIO_NUMBER ((uint32_t)16) |
||
| 150 | |||
| 151 | /* Definitions for bit manipulation of CRL and CRH register */ |
||
| 152 | #define GPIO_CR_MODE_INPUT ((uint32_t)0x00000000) /*!< 00: Input mode (reset state) */ |
||
| 153 | #define GPIO_CR_CNF_ANALOG ((uint32_t)0x00000000) /*!< 00: Analog mode */ |
||
| 154 | #define GPIO_CR_CNF_INPUT_FLOATING ((uint32_t)0x00000004) /*!< 01: Floating input (reset state) */ |
||
| 155 | #define GPIO_CR_CNF_INPUT_PU_PD ((uint32_t)0x00000008) /*!< 10: Input with pull-up / pull-down */ |
||
| 156 | #define GPIO_CR_CNF_GP_OUTPUT_PP ((uint32_t)0x00000000) /*!< 00: General purpose output push-pull */ |
||
| 157 | #define GPIO_CR_CNF_GP_OUTPUT_OD ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain */ |
||
| 158 | #define GPIO_CR_CNF_AF_OUTPUT_PP ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull */ |
||
| 159 | #define GPIO_CR_CNF_AF_OUTPUT_OD ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain */ |
||
| 160 | |||
| 161 | /** |
||
| 162 | * @} |
||
| 163 | */ |
||
| 164 | |||
| 165 | /* Private macro -------------------------------------------------------------*/ |
||
| 166 | /* Private variables ---------------------------------------------------------*/ |
||
| 167 | /* Private function prototypes -----------------------------------------------*/ |
||
| 168 | /* Private functions ---------------------------------------------------------*/ |
||
| 169 | |||
| 170 | /** @defgroup GPIO_Exported_Functions GPIO Exported Functions |
||
| 171 | * @{ |
||
| 172 | */ |
||
| 173 | |||
| 174 | /** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions |
||
| 175 | * @brief Initialization and Configuration functions |
||
| 176 | * |
||
| 177 | @verbatim |
||
| 178 | =============================================================================== |
||
| 179 | ##### Initialization and deinitialization functions ##### |
||
| 180 | =============================================================================== |
||
| 181 | [..] |
||
| 182 | This section provides functions allowing to initialize and de-initialize the GPIOs |
||
| 183 | to be ready for use. |
||
| 184 | |||
| 185 | @endverbatim |
||
| 186 | * @{ |
||
| 187 | */ |
||
| 188 | |||
| 189 | /** |
||
| 190 | * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. |
||
| 191 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||
| 192 | * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains |
||
| 193 | * the configuration information for the specified GPIO peripheral. |
||
| 194 | * @retval None |
||
| 195 | */ |
||
| 196 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) |
||
| 197 | { |
||
| 198 | uint32_t position; |
||
| 199 | uint32_t ioposition = 0x00; |
||
| 200 | uint32_t iocurrent = 0x00; |
||
| 201 | uint32_t temp = 0x00; |
||
| 202 | uint32_t config = 0x00; |
||
| 203 | __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ |
||
| 204 | uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ |
||
| 205 | |||
| 206 | /* Check the parameters */ |
||
| 207 | assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
||
| 208 | assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); |
||
| 209 | assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); |
||
| 210 | |||
| 211 | /* Configure the port pins */ |
||
| 212 | for (position = 0; position < GPIO_NUMBER; position++) |
||
| 213 | { |
||
| 214 | /* Get the IO position */ |
||
| 215 | ioposition = ((uint32_t)0x01) << position; |
||
| 216 | |||
| 217 | /* Get the current IO position */ |
||
| 218 | iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; |
||
| 219 | |||
| 220 | if (iocurrent == ioposition) |
||
| 221 | { |
||
| 222 | /* Check the Alternate function parameters */ |
||
| 223 | assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); |
||
| 224 | |||
| 225 | /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ |
||
| 226 | switch (GPIO_Init->Mode) |
||
| 227 | { |
||
| 228 | /* If we are configuring the pin in OUTPUT push-pull mode */ |
||
| 229 | case GPIO_MODE_OUTPUT_PP: |
||
| 230 | /* Check the GPIO speed parameter */ |
||
| 231 | assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
||
| 232 | config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; |
||
| 233 | break; |
||
| 234 | |||
| 235 | /* If we are configuring the pin in OUTPUT open-drain mode */ |
||
| 236 | case GPIO_MODE_OUTPUT_OD: |
||
| 237 | /* Check the GPIO speed parameter */ |
||
| 238 | assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
||
| 239 | config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; |
||
| 240 | break; |
||
| 241 | |||
| 242 | /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ |
||
| 243 | case GPIO_MODE_AF_PP: |
||
| 244 | /* Check the GPIO speed parameter */ |
||
| 245 | assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
||
| 246 | config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; |
||
| 247 | break; |
||
| 248 | |||
| 249 | /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ |
||
| 250 | case GPIO_MODE_AF_OD: |
||
| 251 | /* Check the GPIO speed parameter */ |
||
| 252 | assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
||
| 253 | config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; |
||
| 254 | break; |
||
| 255 | |||
| 256 | /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ |
||
| 257 | case GPIO_MODE_INPUT: |
||
| 258 | case GPIO_MODE_IT_RISING: |
||
| 259 | case GPIO_MODE_IT_FALLING: |
||
| 260 | case GPIO_MODE_IT_RISING_FALLING: |
||
| 261 | case GPIO_MODE_EVT_RISING: |
||
| 262 | case GPIO_MODE_EVT_FALLING: |
||
| 263 | case GPIO_MODE_EVT_RISING_FALLING: |
||
| 264 | /* Check the GPIO pull parameter */ |
||
| 265 | assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); |
||
| 266 | if(GPIO_Init->Pull == GPIO_NOPULL) |
||
| 267 | { |
||
| 268 | config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; |
||
| 269 | } |
||
| 270 | else if(GPIO_Init->Pull == GPIO_PULLUP) |
||
| 271 | { |
||
| 272 | config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; |
||
| 273 | |||
| 274 | /* Set the corresponding ODR bit */ |
||
| 275 | GPIOx->BSRR = ioposition; |
||
| 276 | } |
||
| 277 | else /* GPIO_PULLDOWN */ |
||
| 278 | { |
||
| 279 | config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; |
||
| 280 | |||
| 281 | /* Reset the corresponding ODR bit */ |
||
| 282 | GPIOx->BRR = ioposition; |
||
| 283 | } |
||
| 284 | break; |
||
| 285 | |||
| 286 | /* If we are configuring the pin in INPUT analog mode */ |
||
| 287 | case GPIO_MODE_ANALOG: |
||
| 288 | config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; |
||
| 289 | break; |
||
| 290 | |||
| 291 | /* Parameters are checked with assert_param */ |
||
| 292 | default: |
||
| 293 | break; |
||
| 294 | } |
||
| 295 | |||
| 296 | /* Check if the current bit belongs to first half or last half of the pin count number |
||
| 297 | in order to address CRH or CRL register*/ |
||
| 298 | configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; |
||
| 299 | registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); |
||
| 300 | |||
| 301 | /* Apply the new configuration of the pin to the register */ |
||
| 302 | MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset)); |
||
| 303 | |||
| 304 | /*--------------------- EXTI Mode Configuration ------------------------*/ |
||
| 305 | /* Configure the External Interrupt or event for the current IO */ |
||
| 306 | if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) |
||
| 307 | { |
||
| 308 | /* Enable AFIO Clock */ |
||
| 309 | __HAL_RCC_AFIO_CLK_ENABLE(); |
||
| 310 | temp = AFIO->EXTICR[position >> 2]; |
||
| 311 | CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03))); |
||
| 312 | SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); |
||
| 313 | AFIO->EXTICR[position >> 2] = temp; |
||
| 314 | |||
| 315 | |||
| 316 | /* Configure the interrupt mask */ |
||
| 317 | if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) |
||
| 318 | { |
||
| 319 | SET_BIT(EXTI->IMR, iocurrent); |
||
| 320 | } |
||
| 321 | else |
||
| 322 | { |
||
| 323 | CLEAR_BIT(EXTI->IMR, iocurrent); |
||
| 324 | } |
||
| 325 | |||
| 326 | /* Configure the event mask */ |
||
| 327 | if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) |
||
| 328 | { |
||
| 329 | SET_BIT(EXTI->EMR, iocurrent); |
||
| 330 | } |
||
| 331 | else |
||
| 332 | { |
||
| 333 | CLEAR_BIT(EXTI->EMR, iocurrent); |
||
| 334 | } |
||
| 335 | |||
| 336 | /* Enable or disable the rising trigger */ |
||
| 337 | if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) |
||
| 338 | { |
||
| 339 | SET_BIT(EXTI->RTSR, iocurrent); |
||
| 340 | } |
||
| 341 | else |
||
| 342 | { |
||
| 343 | CLEAR_BIT(EXTI->RTSR, iocurrent); |
||
| 344 | } |
||
| 345 | |||
| 346 | /* Enable or disable the falling trigger */ |
||
| 347 | if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) |
||
| 348 | { |
||
| 349 | SET_BIT(EXTI->FTSR, iocurrent); |
||
| 350 | } |
||
| 351 | else |
||
| 352 | { |
||
| 353 | CLEAR_BIT(EXTI->FTSR, iocurrent); |
||
| 354 | } |
||
| 355 | } |
||
| 356 | } |
||
| 357 | } |
||
| 358 | } |
||
| 359 | |||
| 360 | /** |
||
| 361 | * @brief De-initializes the GPIOx peripheral registers to their default reset values. |
||
| 362 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||
| 363 | * @param GPIO_Pin: specifies the port bit to be written. |
||
| 364 | * This parameter can be one of GPIO_PIN_x where x can be (0..15). |
||
| 365 | * @retval None |
||
| 366 | */ |
||
| 367 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) |
||
| 368 | { |
||
| 369 | uint32_t position = 0x00; |
||
| 370 | uint32_t iocurrent = 0x00; |
||
| 371 | uint32_t tmp = 0x00; |
||
| 372 | __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ |
||
| 373 | uint32_t registeroffset = 0; |
||
| 374 | |||
| 375 | /* Check the parameters */ |
||
| 376 | assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
||
| 377 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||
| 378 | |||
| 379 | /* Configure the port pins */ |
||
| 380 | while ((GPIO_Pin >> position) != 0) |
||
| 381 | { |
||
| 382 | /* Get current io position */ |
||
| 383 | iocurrent = (GPIO_Pin) & ((uint32_t)1 << position); |
||
| 384 | |||
| 385 | if (iocurrent) |
||
| 386 | { |
||
| 387 | /*------------------------- GPIO Mode Configuration --------------------*/ |
||
| 388 | /* Check if the current bit belongs to first half or last half of the pin count number |
||
| 389 | in order to address CRH or CRL register */ |
||
| 390 | configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; |
||
| 391 | registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); |
||
| 392 | |||
| 393 | /* CRL/CRH default value is floating input(0x04) shifted to correct position */ |
||
| 394 | MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset); |
||
| 395 | |||
| 396 | /* ODR default value is 0 */ |
||
| 397 | CLEAR_BIT(GPIOx->ODR, iocurrent); |
||
| 398 | |||
| 399 | /*------------------------- EXTI Mode Configuration --------------------*/ |
||
| 400 | /* Clear the External Interrupt or Event for the current IO */ |
||
| 401 | |||
| 402 | tmp = AFIO->EXTICR[position >> 2]; |
||
| 403 | tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); |
||
| 404 | if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) |
||
| 405 | { |
||
| 406 | tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); |
||
| 407 | CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp); |
||
| 408 | |||
| 409 | /* Clear EXTI line configuration */ |
||
| 410 | CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); |
||
| 411 | CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); |
||
| 412 | |||
| 413 | /* Clear Rising Falling edge configuration */ |
||
| 414 | CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); |
||
| 415 | CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); |
||
| 416 | } |
||
| 417 | } |
||
| 418 | |||
| 419 | position++; |
||
| 420 | } |
||
| 421 | } |
||
| 422 | |||
| 423 | /** |
||
| 424 | * @} |
||
| 425 | */ |
||
| 426 | |||
| 427 | /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions |
||
| 428 | * @brief GPIO Read and Write |
||
| 429 | * |
||
| 430 | @verbatim |
||
| 431 | =============================================================================== |
||
| 432 | ##### IO operation functions ##### |
||
| 433 | =============================================================================== |
||
| 434 | [..] |
||
| 435 | This subsection provides a set of functions allowing to manage the GPIOs. |
||
| 436 | |||
| 437 | @endverbatim |
||
| 438 | * @{ |
||
| 439 | */ |
||
| 440 | /** |
||
| 441 | * @brief Reads the specified input port pin. |
||
| 442 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||
| 443 | * @param GPIO_Pin: specifies the port bit to read. |
||
| 444 | * This parameter can be GPIO_PIN_x where x can be (0..15). |
||
| 445 | * @retval The input port pin value. |
||
| 446 | */ |
||
| 447 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
||
| 448 | { |
||
| 449 | GPIO_PinState bitstatus; |
||
| 450 | |||
| 451 | /* Check the parameters */ |
||
| 452 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||
| 453 | |||
| 454 | if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) |
||
| 455 | { |
||
| 456 | bitstatus = GPIO_PIN_SET; |
||
| 457 | } |
||
| 458 | else |
||
| 459 | { |
||
| 460 | bitstatus = GPIO_PIN_RESET; |
||
| 461 | } |
||
| 462 | return bitstatus; |
||
| 463 | } |
||
| 464 | |||
| 465 | /** |
||
| 466 | * @brief Sets or clears the selected data port bit. |
||
| 467 | * |
||
| 468 | * @note This function uses GPIOx_BSRR register to allow atomic read/modify |
||
| 469 | * accesses. In this way, there is no risk of an IRQ occurring between |
||
| 470 | * the read and the modify access. |
||
| 471 | * |
||
| 472 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||
| 473 | * @param GPIO_Pin: specifies the port bit to be written. |
||
| 474 | * This parameter can be one of GPIO_PIN_x where x can be (0..15). |
||
| 475 | * @param PinState: specifies the value to be written to the selected bit. |
||
| 476 | * This parameter can be one of the GPIO_PinState enum values: |
||
| 477 | * @arg GPIO_BIT_RESET: to clear the port pin |
||
| 478 | * @arg GPIO_BIT_SET: to set the port pin |
||
| 479 | * @retval None |
||
| 480 | */ |
||
| 481 | void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) |
||
| 482 | { |
||
| 483 | /* Check the parameters */ |
||
| 484 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||
| 485 | assert_param(IS_GPIO_PIN_ACTION(PinState)); |
||
| 486 | |||
| 487 | if(PinState != GPIO_PIN_RESET) |
||
| 488 | { |
||
| 489 | GPIOx->BSRR = GPIO_Pin; |
||
| 490 | } |
||
| 491 | else |
||
| 492 | { |
||
| 493 | GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; |
||
| 494 | } |
||
| 495 | } |
||
| 496 | |||
| 497 | /** |
||
| 498 | * @brief Toggles the specified GPIO pin |
||
| 499 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||
| 500 | * @param GPIO_Pin: Specifies the pins to be toggled. |
||
| 501 | * @retval None |
||
| 502 | */ |
||
| 503 | void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
||
| 504 | { |
||
| 505 | /* Check the parameters */ |
||
| 506 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||
| 507 | |||
| 508 | GPIOx->ODR ^= GPIO_Pin; |
||
| 509 | } |
||
| 510 | |||
| 511 | /** |
||
| 512 | * @brief Locks GPIO Pins configuration registers. |
||
| 513 | * @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence |
||
| 514 | * has been applied on a port bit, it is no longer possible to modify the value of the port bit until |
||
| 515 | * the next reset. |
||
| 516 | * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||
| 517 | * @param GPIO_Pin: specifies the port bit to be locked. |
||
| 518 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). |
||
| 519 | * @retval None |
||
| 520 | */ |
||
| 521 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
||
| 522 | { |
||
| 523 | __IO uint32_t tmp = GPIO_LCKR_LCKK; |
||
| 524 | |||
| 525 | /* Check the parameters */ |
||
| 526 | assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); |
||
| 527 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||
| 528 | |||
| 529 | /* Apply lock key write sequence */ |
||
| 530 | SET_BIT(tmp, GPIO_Pin); |
||
| 531 | /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
||
| 532 | GPIOx->LCKR = tmp; |
||
| 533 | /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ |
||
| 534 | GPIOx->LCKR = GPIO_Pin; |
||
| 535 | /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
||
| 536 | GPIOx->LCKR = tmp; |
||
| 537 | /* Read LCKK bit*/ |
||
| 538 | tmp = GPIOx->LCKR; |
||
| 539 | |||
| 540 | if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) |
||
| 541 | { |
||
| 542 | return HAL_OK; |
||
| 543 | } |
||
| 544 | else |
||
| 545 | { |
||
| 546 | return HAL_ERROR; |
||
| 547 | } |
||
| 548 | } |
||
| 549 | |||
| 550 | /** |
||
| 551 | * @brief This function handles EXTI interrupt request. |
||
| 552 | * @param GPIO_Pin: Specifies the pins connected EXTI line |
||
| 553 | * @retval None |
||
| 554 | */ |
||
| 555 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) |
||
| 556 | { |
||
| 557 | /* EXTI line interrupt detected */ |
||
| 558 | if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) |
||
| 559 | { |
||
| 560 | __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); |
||
| 561 | HAL_GPIO_EXTI_Callback(GPIO_Pin); |
||
| 562 | } |
||
| 563 | } |
||
| 564 | |||
| 565 | /** |
||
| 566 | * @brief EXTI line detection callback |
||
| 567 | * @param GPIO_Pin: Specifies the pins connected EXTI line |
||
| 568 | * @retval None |
||
| 569 | */ |
||
| 570 | __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) |
||
| 571 | { |
||
| 5 | mjames | 572 | /* Prevent unused argument(s) compilation warning */ |
| 573 | UNUSED(GPIO_Pin); |
||
| 2 | mjames | 574 | /* NOTE : This function Should not be modified, when the callback is needed, |
| 575 | the HAL_GPIO_EXTI_Callback could be implemented in the user file |
||
| 576 | */ |
||
| 577 | } |
||
| 578 | |||
| 579 | /** |
||
| 580 | * @} |
||
| 581 | */ |
||
| 582 | |||
| 583 | |||
| 584 | /** |
||
| 585 | * @} |
||
| 586 | */ |
||
| 587 | |||
| 588 | #endif /* HAL_GPIO_MODULE_ENABLED */ |
||
| 589 | /** |
||
| 590 | * @} |
||
| 591 | */ |
||
| 592 | |||
| 593 | /** |
||
| 594 | * @} |
||
| 595 | */ |
||
| 596 | |||
| 597 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |