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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_eth.c
		4	* @author MCD Application Team
5	mjames	5	* @version V1.0.4
		6	* @date 29-April-2016
2	mjames	7	* @brief ETH HAL module driver.
		8	* This file provides firmware functions to manage the following
		9	* functionalities of the Ethernet (ETH) peripheral:
		10	* + Initialization and de-initialization functions
		11	* + IO operation functions
		12	* + Peripheral Control functions
		13	* + Peripheral State and Errors functions
		14	*
		15	@verbatim
		16	==============================================================================
		17	##### How to use this driver #####
		18	==============================================================================
		19	[..]
		20	(#)Declare a ETH_HandleTypeDef handle structure, for example:
		21	ETH_HandleTypeDef heth;
		22
		23	(#)Fill parameters of Init structure in heth handle
		24
		25	(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
		26
		27	(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
		28	(##) Enable the Ethernet interface clock using
		29	(+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
		30	(+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
		31	(+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
		32
		33	(##) Initialize the related GPIO clocks
		34	(##) Configure Ethernet pin-out
		35	(##) Configure Ethernet NVIC interrupt (IT mode)
		36
		37	(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
		38	(##) HAL_ETH_DMATxDescListInit(); for Transmission process
		39	(##) HAL_ETH_DMARxDescListInit(); for Reception process
		40
		41	(#)Enable MAC and DMA transmission and reception:
		42	(##) HAL_ETH_Start();
		43
		44	(#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
		45	the frame to MAC TX FIFO:
		46	(##) HAL_ETH_TransmitFrame();
		47
		48	(#)Poll for a received frame in ETH RX DMA Descriptors and get received
		49	frame parameters
		50	(##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
		51
		52	(#) Get a received frame when an ETH RX interrupt occurs:
		53	(##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
		54
		55	(#) Communicate with external PHY device:
		56	(##) Read a specific register from the PHY
		57	HAL_ETH_ReadPHYRegister();
		58	(##) Write data to a specific RHY register:
		59	HAL_ETH_WritePHYRegister();
		60
		61	(#) Configure the Ethernet MAC after ETH peripheral initialization
		62	HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
		63
		64	(#) Configure the Ethernet DMA after ETH peripheral initialization
		65	HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
		66
		67	-@- The PTP protocol and the DMA descriptors ring mode are not supported
		68	in this driver
		69
		70	@endverbatim
		71	******************************************************************************
		72	* @attention
		73	*
5	mjames	74	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2	mjames	75	*
		76	* Redistribution and use in source and binary forms, with or without modification,
		77	* are permitted provided that the following conditions are met:
		78	* 1. Redistributions of source code must retain the above copyright notice,
		79	* this list of conditions and the following disclaimer.
		80	* 2. Redistributions in binary form must reproduce the above copyright notice,
		81	* this list of conditions and the following disclaimer in the documentation
		82	* and/or other materials provided with the distribution.
		83	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		84	* may be used to endorse or promote products derived from this software
		85	* without specific prior written permission.
		86	*
		87	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		88	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		89	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		90	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		91	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		92	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		93	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		94	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		95	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		96	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		97	*
		98	******************************************************************************
		99	*/
		100
		101	/* Includes ------------------------------------------------------------------*/
		102	#include "stm32f1xx_hal.h"
		103
		104	/** @addtogroup STM32F1xx_HAL_Driver
		105	* @{
		106	*/
		107	#if defined (STM32F107xC)
		108
		109	/** @defgroup ETH ETH
		110	* @brief ETH HAL module driver
		111	* @{
		112	*/
		113
		114	#ifdef HAL_ETH_MODULE_ENABLED
		115
		116	/* Private typedef -----------------------------------------------------------*/
		117	/* Private define ------------------------------------------------------------*/
		118	/** @defgroup ETH_Private_Constants ETH Private Constants
		119	* @{
		120	*/
		121	#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
		122	#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
		123
		124	/**
		125	* @}
		126	*/
		127
		128	/* Private macro -------------------------------------------------------------*/
		129	/* Private variables ---------------------------------------------------------*/
		130	/* Private function prototypes -----------------------------------------------*/
		131	/** @defgroup ETH_Private_Functions ETH Private Functions
		132	* @{
		133	*/
		134	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
		135	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr);
		136	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
		137	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
		138	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
		139	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
		140	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
		141	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
		142	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
		143	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
		144	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
		145
		146	/**
		147	* @}
		148	*/
		149	/* Private functions ---------------------------------------------------------*/
		150
		151	/** @defgroup ETH_Exported_Functions ETH Exported Functions
		152	* @{
		153	*/
		154
		155	/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
		156	* @brief Initialization and Configuration functions
		157	*
		158	@verbatim
		159	===============================================================================
		160	##### Initialization and de-initialization functions #####
		161	===============================================================================
		162	[..] This section provides functions allowing to:
		163	(+) Initialize and configure the Ethernet peripheral
		164	(+) De-initialize the Ethernet peripheral
		165
		166	@endverbatim
		167	* @{
		168	*/
		169
		170	/**
		171	* @brief Initializes the Ethernet MAC and DMA according to default
		172	* parameters.
		173	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		174	* the configuration information for ETHERNET module
		175	* @retval HAL status
		176	*/
		177	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
		178	{
		179	uint32_t tmpreg = 0, phyreg = 0;
		180	uint32_t hclk = 60000000;
		181	uint32_t tickstart = 0;
		182	uint32_t err = ETH_SUCCESS;
		183
		184	/* Check the ETH peripheral state */
		185	if(heth == NULL)
		186	{
		187	return HAL_ERROR;
		188	}
		189
		190	/* Check parameters */
		191	assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
		192	assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
		193	assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
		194	assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
		195
		196	if(heth->State == HAL_ETH_STATE_RESET)
		197	{
		198	/* Allocate lock resource and initialize it */
		199	heth->Lock = HAL_UNLOCKED;
		200
		201	/* Init the low level hardware : GPIO, CLOCK, NVIC. */
		202	HAL_ETH_MspInit(heth);
		203	}
		204
		205	/* Select MII or RMII Mode*/
		206	AFIO->MAPR &= ~(AFIO_MAPR_MII_RMII_SEL);
		207	AFIO->MAPR \|= (uint32_t)heth->Init.MediaInterface;
		208
		209	/* Ethernet Software reset */
		210	/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
		211	/* After reset all the registers holds their respective reset values */
		212	(heth->Instance)->DMABMR \|= ETH_DMABMR_SR;
		213
		214	/* Wait for software reset */
		215	while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
		216	{
		217	}
		218
		219	/-------------------------------- MAC Initialization ----------------------/
		220	/* Get the ETHERNET MACMIIAR value */
		221	tmpreg = (heth->Instance)->MACMIIAR;
		222	/* Clear CSR Clock Range CR[2:0] bits */
		223	tmpreg &= ETH_MACMIIAR_CR_MASK;
		224
		225	/* Get hclk frequency value */
		226	hclk = HAL_RCC_GetHCLKFreq();
		227
		228	/* Set CR bits depending on hclk value */
		229	if((hclk >= 20000000)&&(hclk < 35000000))
		230	{
		231	/* CSR Clock Range between 20-35 MHz */
		232	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_DIV16;
		233	}
		234	else if((hclk >= 35000000)&&(hclk < 60000000))
		235	{
		236	/* CSR Clock Range between 35-60 MHz */
		237	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_DIV26;
		238	}
		239	else
		240	{
		241	/* CSR Clock Range between 60-72 MHz */
		242	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_DIV42;
		243	}
		244
		245	/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
		246	(heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
		247
		248	/-------------------- PHY initialization and configuration ----------------/
		249	/* Put the PHY in reset mode */
		250	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
		251	{
		252	/* In case of write timeout */
		253	err = ETH_ERROR;
		254
		255	/* Config MAC and DMA */
		256	ETH_MACDMAConfig(heth, err);
		257
		258	/* Set the ETH peripheral state to READY */
		259	heth->State = HAL_ETH_STATE_READY;
		260
		261	/* Return HAL_ERROR */
		262	return HAL_ERROR;
		263	}
		264
		265	/* Delay to assure PHY reset */
		266	HAL_Delay(PHY_RESET_DELAY);
		267
		268	if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
		269	{
		270	/* Get tick */
		271	tickstart = HAL_GetTick();
		272
		273	/* We wait for linked status */
		274	do
		275	{
		276	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
		277
		278	/* Check for the Timeout */
		279	if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
		280	{
		281	/* In case of write timeout */
		282	err = ETH_ERROR;
		283
		284	/* Config MAC and DMA */
		285	ETH_MACDMAConfig(heth, err);
		286
		287	heth->State= HAL_ETH_STATE_READY;
		288
		289	/* Process Unlocked */
		290	__HAL_UNLOCK(heth);
		291
		292	return HAL_TIMEOUT;
		293	}
		294	} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
		295
		296
		297	/* Enable Auto-Negotiation */
		298	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
		299	{
		300	/* In case of write timeout */
		301	err = ETH_ERROR;
		302
		303	/* Config MAC and DMA */
		304	ETH_MACDMAConfig(heth, err);
		305
		306	/* Set the ETH peripheral state to READY */
		307	heth->State = HAL_ETH_STATE_READY;
		308
		309	/* Return HAL_ERROR */
		310	return HAL_ERROR;
		311	}
		312
		313	/* Get tick */
		314	tickstart = HAL_GetTick();
		315
		316	/* Wait until the auto-negotiation will be completed */
		317	do
		318	{
		319	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
		320
		321	/* Check for the Timeout */
		322	if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
		323	{
		324	/* In case of write timeout */
		325	err = ETH_ERROR;
		326
		327	/* Config MAC and DMA */
		328	ETH_MACDMAConfig(heth, err);
		329
		330	heth->State= HAL_ETH_STATE_READY;
		331
		332	/* Process Unlocked */
		333	__HAL_UNLOCK(heth);
		334
		335	return HAL_TIMEOUT;
		336	}
		337
		338	} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
		339
		340	/* Read the result of the auto-negotiation */
		341	if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
		342	{
		343	/* In case of write timeout */
		344	err = ETH_ERROR;
		345
		346	/* Config MAC and DMA */
		347	ETH_MACDMAConfig(heth, err);
		348
		349	/* Set the ETH peripheral state to READY */
		350	heth->State = HAL_ETH_STATE_READY;
		351
		352	/* Return HAL_ERROR */
		353	return HAL_ERROR;
		354	}
		355
		356	/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
		357	if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
		358	{
		359	/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
		360	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
		361	}
		362	else
		363	{
		364	/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
		365	(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
		366	}
		367	/* Configure the MAC with the speed fixed by the auto-negotiation process */
		368	if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
		369	{
		370	/* Set Ethernet speed to 10M following the auto-negotiation */
		371	(heth->Init).Speed = ETH_SPEED_10M;
		372	}
		373	else
		374	{
		375	/* Set Ethernet speed to 100M following the auto-negotiation */
		376	(heth->Init).Speed = ETH_SPEED_100M;
		377	}
		378	}
		379	else /* AutoNegotiation Disable */
		380	{
		381	/* Check parameters */
		382	assert_param(IS_ETH_SPEED(heth->Init.Speed));
		383	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
		384
		385	/* Set MAC Speed and Duplex Mode */
		386	if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) \|
		387	(uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
		388	{
		389	/* In case of write timeout */
		390	err = ETH_ERROR;
		391
		392	/* Config MAC and DMA */
		393	ETH_MACDMAConfig(heth, err);
		394
		395	/* Set the ETH peripheral state to READY */
		396	heth->State = HAL_ETH_STATE_READY;
		397
		398	/* Return HAL_ERROR */
		399	return HAL_ERROR;
		400	}
		401
		402	/* Delay to assure PHY configuration */
		403	HAL_Delay(PHY_CONFIG_DELAY);
		404	}
		405
		406	/* Config MAC and DMA */
		407	ETH_MACDMAConfig(heth, err);
		408
		409	/* Set ETH HAL State to Ready */
		410	heth->State= HAL_ETH_STATE_READY;
		411
		412	/* Return function status */
		413	return HAL_OK;
		414	}
		415
		416	/**
		417	* @brief De-Initializes the ETH peripheral.
		418	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		419	* the configuration information for ETHERNET module
		420	* @retval HAL status
		421	*/
		422	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
		423	{
		424	/* Set the ETH peripheral state to BUSY */
		425	heth->State = HAL_ETH_STATE_BUSY;
		426
		427	/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
		428	HAL_ETH_MspDeInit(heth);
		429
		430	/* Set ETH HAL state to Disabled */
		431	heth->State= HAL_ETH_STATE_RESET;
		432
		433	/* Release Lock */
		434	__HAL_UNLOCK(heth);
		435
		436	/* Return function status */
		437	return HAL_OK;
		438	}
		439
		440	/**
		441	* @brief Initializes the DMA Tx descriptors in chain mode.
		442	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		443	* the configuration information for ETHERNET module
		444	* @param DMATxDescTab: Pointer to the first Tx desc list
		445	* @param TxBuff: Pointer to the first TxBuffer list
		446	* @param TxBuffCount: Number of the used Tx desc in the list
		447	* @retval HAL status
		448	*/
		449	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
		450	{
		451	uint32_t i = 0;
		452	ETH_DMADescTypeDef *dmatxdesc;
		453
		454	/* Process Locked */
		455	__HAL_LOCK(heth);
		456
		457	/* Set the ETH peripheral state to BUSY */
		458	heth->State = HAL_ETH_STATE_BUSY;
		459
		460	/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
		461	heth->TxDesc = DMATxDescTab;
		462
		463	/* Fill each DMATxDesc descriptor with the right values */
		464	for(i=0; i < TxBuffCount; i++)
		465	{
		466	/* Get the pointer on the ith member of the Tx Desc list */
		467	dmatxdesc = DMATxDescTab + i;
		468
		469	/* Set Second Address Chained bit */
		470	dmatxdesc->Status = ETH_DMATXDESC_TCH;
		471
		472	/* Set Buffer1 address pointer */
		473	dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
		474
		475	if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
		476	{
		477	/* Set the DMA Tx descriptors checksum insertion */
		478	dmatxdesc->Status \|= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
		479	}
		480
		481	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
		482	if(i < (TxBuffCount-1))
		483	{
		484	/* Set next descriptor address register with next descriptor base address */
		485	dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
		486	}
		487	else
		488	{
		489	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
		490	dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
		491	}
		492	}
		493
		494	/* Set Transmit Descriptor List Address Register */
		495	(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
		496
		497	/* Set ETH HAL State to Ready */
		498	heth->State= HAL_ETH_STATE_READY;
		499
		500	/* Process Unlocked */
		501	__HAL_UNLOCK(heth);
		502
		503	/* Return function status */
		504	return HAL_OK;
		505	}
		506
		507	/**
		508	* @brief Initializes the DMA Rx descriptors in chain mode.
		509	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		510	* the configuration information for ETHERNET module
		511	* @param DMARxDescTab: Pointer to the first Rx desc list
		512	* @param RxBuff: Pointer to the first RxBuffer list
		513	* @param RxBuffCount: Number of the used Rx desc in the list
		514	* @retval HAL status
		515	*/
		516	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
		517	{
		518	uint32_t i = 0;
		519	ETH_DMADescTypeDef *DMARxDesc;
		520
		521	/* Process Locked */
		522	__HAL_LOCK(heth);
		523
		524	/* Set the ETH peripheral state to BUSY */
		525	heth->State = HAL_ETH_STATE_BUSY;
		526
		527	/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
		528	heth->RxDesc = DMARxDescTab;
		529
		530	/* Fill each DMARxDesc descriptor with the right values */
		531	for(i=0; i < RxBuffCount; i++)
		532	{
		533	/* Get the pointer on the ith member of the Rx Desc list */
		534	DMARxDesc = DMARxDescTab+i;
		535
		536	/* Set Own bit of the Rx descriptor Status */
		537	DMARxDesc->Status = ETH_DMARXDESC_OWN;
		538
		539	/* Set Buffer1 size and Second Address Chained bit */
		540	DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH \| ETH_RX_BUF_SIZE;
		541
		542	/* Set Buffer1 address pointer */
		543	DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
		544
		545	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
		546	{
		547	/* Enable Ethernet DMA Rx Descriptor interrupt */
		548	DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
		549	}
		550
		551	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
		552	if(i < (RxBuffCount-1))
		553	{
		554	/* Set next descriptor address register with next descriptor base address */
		555	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
		556	}
		557	else
		558	{
		559	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
		560	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
		561	}
		562	}
		563
		564	/* Set Receive Descriptor List Address Register */
		565	(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
		566
		567	/* Set ETH HAL State to Ready */
		568	heth->State= HAL_ETH_STATE_READY;
		569
		570	/* Process Unlocked */
		571	__HAL_UNLOCK(heth);
		572
		573	/* Return function status */
		574	return HAL_OK;
		575	}
		576
		577	/**
		578	* @brief Initializes the ETH MSP.
		579	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		580	* the configuration information for ETHERNET module
		581	* @retval None
		582	*/
		583	__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
		584	{
5	mjames	585	/* Prevent unused argument(s) compilation warning */
		586	UNUSED(heth);
2	mjames	587	/* NOTE : This function Should not be modified, when the callback is needed,
		588	the HAL_ETH_MspInit could be implemented in the user file
		589	*/
		590	}
		591
		592	/**
		593	* @brief DeInitializes ETH MSP.
		594	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		595	* the configuration information for ETHERNET module
		596	* @retval None
		597	*/
		598	__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
		599	{
5	mjames	600	/* Prevent unused argument(s) compilation warning */
		601	UNUSED(heth);
2	mjames	602	/* NOTE : This function Should not be modified, when the callback is needed,
		603	the HAL_ETH_MspDeInit could be implemented in the user file
		604	*/
		605	}
		606
		607	/**
		608	* @}
		609	*/
		610
		611	/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
		612	* @brief Data transfers functions
		613	*
		614	@verbatim
		615	==============================================================================
		616	##### IO operation functions #####
		617	==============================================================================
		618	[..] This section provides functions allowing to:
		619	(+) Transmit a frame
		620	HAL_ETH_TransmitFrame();
		621	(+) Receive a frame
		622	HAL_ETH_GetReceivedFrame();
		623	HAL_ETH_GetReceivedFrame_IT();
		624	(+) Read from an External PHY register
		625	HAL_ETH_ReadPHYRegister();
		626	(+) Write to an External PHY register
		627	HAL_ETH_WritePHYRegister();
		628
		629	@endverbatim
		630
		631	* @{
		632	*/
		633
		634	/**
		635	* @brief Sends an Ethernet frame.
		636	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		637	* the configuration information for ETHERNET module
		638	* @param FrameLength: Amount of data to be sent
		639	* @retval HAL status
		640	*/
		641	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
		642	{
		643	uint32_t bufcount = 0, size = 0, i = 0;
		644
		645	/* Process Locked */
		646	__HAL_LOCK(heth);
		647
		648	/* Set the ETH peripheral state to BUSY */
		649	heth->State = HAL_ETH_STATE_BUSY;
		650
		651	if (FrameLength == 0)
		652	{
		653	/* Set ETH HAL state to READY */
		654	heth->State = HAL_ETH_STATE_READY;
		655
		656	/* Process Unlocked */
		657	__HAL_UNLOCK(heth);
		658
		659	return HAL_ERROR;
		660	}
		661
		662	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
		663	if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
		664	{
		665	/* OWN bit set */
		666	heth->State = HAL_ETH_STATE_BUSY_TX;
		667
		668	/* Process Unlocked */
		669	__HAL_UNLOCK(heth);
		670
		671	return HAL_ERROR;
		672	}
		673
		674	/* Get the number of needed Tx buffers for the current frame */
		675	if (FrameLength > ETH_TX_BUF_SIZE)
		676	{
		677	bufcount = FrameLength/ETH_TX_BUF_SIZE;
		678	if (FrameLength % ETH_TX_BUF_SIZE)
		679	{
		680	bufcount++;
		681	}
		682	}
		683	else
		684	{
		685	bufcount = 1;
		686	}
		687	if (bufcount == 1)
		688	{
		689	/* Set LAST and FIRST segment */
		690	heth->TxDesc->Status \|=ETH_DMATXDESC_FS\|ETH_DMATXDESC_LS;
		691	/* Set frame size */
		692	heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
		693	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
		694	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
		695	/* Point to next descriptor */
		696	heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
		697	}
		698	else
		699	{
		700	for (i=0; i< bufcount; i++)
		701	{
		702	/* Clear FIRST and LAST segment bits */
		703	heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS \| ETH_DMATXDESC_LS);
		704
		705	if (i == 0)
		706	{
		707	/* Setting the first segment bit */
		708	heth->TxDesc->Status \|= ETH_DMATXDESC_FS;
		709	}
		710
		711	/* Program size */
		712	heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
		713
		714	if (i == (bufcount-1))
		715	{
		716	/* Setting the last segment bit */
		717	heth->TxDesc->Status \|= ETH_DMATXDESC_LS;
		718	size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
		719	heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
		720	}
		721
		722	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
		723	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
		724	/* point to next descriptor */
		725	heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
		726	}
		727	}
		728
		729	/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
		730	if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
		731	{
		732	/* Clear TBUS ETHERNET DMA flag */
		733	(heth->Instance)->DMASR = ETH_DMASR_TBUS;
		734	/* Resume DMA transmission*/
		735	(heth->Instance)->DMATPDR = 0;
		736	}
		737
		738	/* Set ETH HAL State to Ready */
		739	heth->State = HAL_ETH_STATE_READY;
		740
		741	/* Process Unlocked */
		742	__HAL_UNLOCK(heth);
		743
		744	/* Return function status */
		745	return HAL_OK;
		746	}
		747
		748	/**
		749	* @brief Checks for received frames.
		750	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		751	* the configuration information for ETHERNET module
		752	* @retval HAL status
		753	*/
		754	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
		755	{
		756	uint32_t framelength = 0;
		757
		758	/* Process Locked */
		759	__HAL_LOCK(heth);
		760
		761	/* Check the ETH state to BUSY */
		762	heth->State = HAL_ETH_STATE_BUSY;
		763
		764	/* Check if segment is not owned by DMA */
		765	/* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
		766	if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
		767	{
		768	/* Check if last segment */
		769	if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
		770	{
		771	/* increment segment count */
		772	(heth->RxFrameInfos).SegCount++;
		773
		774	/* Check if last segment is first segment: one segment contains the frame */
		775	if ((heth->RxFrameInfos).SegCount == 1)
		776	{
		777	(heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
		778	}
		779
		780	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
		781
		782	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
		783	framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
		784	heth->RxFrameInfos.length = framelength;
		785
		786	/* Get the address of the buffer start address */
		787	heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
		788	/* point to next descriptor */
		789	heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
		790
		791	/* Set HAL State to Ready */
		792	heth->State = HAL_ETH_STATE_READY;
		793
		794	/* Process Unlocked */
		795	__HAL_UNLOCK(heth);
		796
		797	/* Return function status */
		798	return HAL_OK;
		799	}
		800	/* Check if first segment */
		801	else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
		802	{
		803	(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
		804	(heth->RxFrameInfos).LSRxDesc = NULL;
		805	(heth->RxFrameInfos).SegCount = 1;
		806	/* Point to next descriptor */
		807	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
		808	}
		809	/* Check if intermediate segment */
		810	else
		811	{
		812	(heth->RxFrameInfos).SegCount++;
		813	/* Point to next descriptor */
		814	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
		815	}
		816	}
		817
		818	/* Set ETH HAL State to Ready */
		819	heth->State = HAL_ETH_STATE_READY;
		820
		821	/* Process Unlocked */
		822	__HAL_UNLOCK(heth);
		823
		824	/* Return function status */
		825	return HAL_ERROR;
		826	}
		827
		828	/**
		829	* @brief Gets the Received frame in interrupt mode.
		830	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		831	* the configuration information for ETHERNET module
		832	* @retval HAL status
		833	*/
		834	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
		835	{
		836	uint32_t descriptorscancounter = 0;
		837
		838	/* Process Locked */
		839	__HAL_LOCK(heth);
		840
		841	/* Set ETH HAL State to BUSY */
		842	heth->State = HAL_ETH_STATE_BUSY;
		843
		844	/* Scan descriptors owned by CPU */
		845	while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
		846	{
		847	/* Just for security */
		848	descriptorscancounter++;
		849
		850	/* Check if first segment in frame */
		851	/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
		852	if((heth->RxDesc->Status & (ETH_DMARXDESC_FS \| ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
		853	{
		854	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
		855	heth->RxFrameInfos.SegCount = 1;
		856	/* Point to next descriptor */
		857	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
		858	}
		859	/* Check if intermediate segment */
		860	/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
		861	else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS \| ETH_DMARXDESC_FS)) == (uint32_t)RESET)
		862	{
		863	/* Increment segment count */
		864	(heth->RxFrameInfos.SegCount)++;
		865	/* Point to next descriptor */
		866	heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
		867	}
		868	/* Should be last segment */
		869	else
		870	{
		871	/* Last segment */
		872	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
		873
		874	/* Increment segment count */
		875	(heth->RxFrameInfos.SegCount)++;
		876
		877	/* Check if last segment is first segment: one segment contains the frame */
		878	if ((heth->RxFrameInfos.SegCount) == 1)
		879	{
		880	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
		881	}
		882
		883	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
		884	heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
		885
		886	/* Get the address of the buffer start address */
		887	heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
		888
		889	/* Point to next descriptor */
		890	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
		891
		892	/* Set HAL State to Ready */
		893	heth->State = HAL_ETH_STATE_READY;
		894
		895	/* Process Unlocked */
		896	__HAL_UNLOCK(heth);
		897
		898	/* Return function status */
		899	return HAL_OK;
		900	}
		901	}
		902
		903	/* Set HAL State to Ready */
		904	heth->State = HAL_ETH_STATE_READY;
		905
		906	/* Process Unlocked */
		907	__HAL_UNLOCK(heth);
		908
		909	/* Return function status */
		910	return HAL_ERROR;
		911	}
		912
		913	/**
		914	* @brief This function handles ETH interrupt request.
		915	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		916	* the configuration information for ETHERNET module
		917	* @retval HAL status
		918	*/
		919	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
		920	{
		921	/* Frame received */
		922	if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
		923	{
		924	/* Receive complete callback */
		925	HAL_ETH_RxCpltCallback(heth);
		926
		927	/* Clear the Eth DMA Rx IT pending bits */
		928	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
		929
		930	/* Set HAL State to Ready */
		931	heth->State = HAL_ETH_STATE_READY;
		932
		933	/* Process Unlocked */
		934	__HAL_UNLOCK(heth);
		935
		936	}
		937	/* Frame transmitted */
		938	else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
		939	{
		940	/* Transfer complete callback */
		941	HAL_ETH_TxCpltCallback(heth);
		942
		943	/* Clear the Eth DMA Tx IT pending bits */
		944	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
		945
		946	/* Set HAL State to Ready */
		947	heth->State = HAL_ETH_STATE_READY;
		948
		949	/* Process Unlocked */
		950	__HAL_UNLOCK(heth);
		951	}
		952
		953	/* Clear the interrupt flags */
		954	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
		955
		956	/* ETH DMA Error */
		957	if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
		958	{
		959	/* Ethernet Error callback */
		960	HAL_ETH_ErrorCallback(heth);
		961
		962	/* Clear the interrupt flags */
		963	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
		964
		965	/* Set HAL State to Ready */
		966	heth->State = HAL_ETH_STATE_READY;
		967
		968	/* Process Unlocked */
		969	__HAL_UNLOCK(heth);
		970	}
		971	}
		972
		973	/**
		974	* @brief Tx Transfer completed callbacks.
		975	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		976	* the configuration information for ETHERNET module
		977	* @retval None
		978	*/
		979	__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
		980	{
5	mjames	981	/* Prevent unused argument(s) compilation warning */
		982	UNUSED(heth);
2	mjames	983	/* NOTE : This function Should not be modified, when the callback is needed,
		984	the HAL_ETH_TxCpltCallback could be implemented in the user file
		985	*/
		986	}
		987
		988	/**
		989	* @brief Rx Transfer completed callbacks.
		990	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		991	* the configuration information for ETHERNET module
		992	* @retval None
		993	*/
		994	__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
		995	{
5	mjames	996	/* Prevent unused argument(s) compilation warning */
		997	UNUSED(heth);
2	mjames	998	/* NOTE : This function Should not be modified, when the callback is needed,
		999	the HAL_ETH_TxCpltCallback could be implemented in the user file
		1000	*/
		1001	}
		1002
		1003	/**
		1004	* @brief Ethernet transfer error callbacks
		1005	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1006	* the configuration information for ETHERNET module
		1007	* @retval None
		1008	*/
		1009	__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
		1010	{
5	mjames	1011	/* Prevent unused argument(s) compilation warning */
		1012	UNUSED(heth);
2	mjames	1013	/* NOTE : This function Should not be modified, when the callback is needed,
		1014	the HAL_ETH_TxCpltCallback could be implemented in the user file
		1015	*/
		1016	}
		1017
		1018	/**
		1019	* @brief Reads a PHY register
		1020	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1021	* the configuration information for ETHERNET module
		1022	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
		1023	* This parameter can be one of the following values:
		1024	* PHY_BCR: Transceiver Basic Control Register,
		1025	* PHY_BSR: Transceiver Basic Status Register.
		1026	* More PHY register could be read depending on the used PHY
		1027	* @param RegValue: PHY register value
		1028	* @retval HAL status
		1029	*/
		1030	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue)
		1031	{
		1032	uint32_t tmpreg = 0;
		1033	uint32_t tickstart = 0;
		1034
		1035	/* Check parameters */
		1036	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
		1037
		1038	/* Check the ETH peripheral state */
		1039	if(heth->State == HAL_ETH_STATE_BUSY_RD)
		1040	{
		1041	return HAL_BUSY;
		1042	}
		1043	/* Set ETH HAL State to BUSY_RD */
		1044	heth->State = HAL_ETH_STATE_BUSY_RD;
		1045
		1046	/* Get the ETHERNET MACMIIAR value */
		1047	tmpreg = heth->Instance->MACMIIAR;
		1048
		1049	/* Keep only the CSR Clock Range CR[2:0] bits value */
		1050	tmpreg &= ~ETH_MACMIIAR_CR_MASK;
		1051
		1052	/* Prepare the MII address register value */
		1053	tmpreg \|=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
		1054	tmpreg \|=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
		1055	tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
		1056	tmpreg \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
		1057
		1058	/* Write the result value into the MII Address register */
		1059	heth->Instance->MACMIIAR = tmpreg;
		1060
		1061	/* Get tick */
		1062	tickstart = HAL_GetTick();
		1063
		1064	/* Check for the Busy flag */
		1065	while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
		1066	{
		1067	/* Check for the Timeout */
		1068	if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
		1069	{
		1070	heth->State= HAL_ETH_STATE_READY;
		1071
		1072	/* Process Unlocked */
		1073	__HAL_UNLOCK(heth);
		1074
		1075	return HAL_TIMEOUT;
		1076	}
		1077
		1078	tmpreg = heth->Instance->MACMIIAR;
		1079	}
		1080
		1081	/* Get MACMIIDR value */
		1082	*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
		1083
		1084	/* Set ETH HAL State to READY */
		1085	heth->State = HAL_ETH_STATE_READY;
		1086
		1087	/* Return function status */
		1088	return HAL_OK;
		1089	}
		1090
		1091	/**
		1092	* @brief Writes to a PHY register.
		1093	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1094	* the configuration information for ETHERNET module
		1095	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
		1096	* This parameter can be one of the following values:
		1097	* PHY_BCR: Transceiver Control Register.
		1098	* More PHY register could be written depending on the used PHY
		1099	* @param RegValue: the value to write
		1100	* @retval HAL status
		1101	*/
		1102	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
		1103	{
		1104	uint32_t tmpreg = 0;
		1105	uint32_t tickstart = 0;
		1106
		1107	/* Check parameters */
		1108	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
		1109
		1110	/* Check the ETH peripheral state */
		1111	if(heth->State == HAL_ETH_STATE_BUSY_WR)
		1112	{
		1113	return HAL_BUSY;
		1114	}
		1115	/* Set ETH HAL State to BUSY_WR */
		1116	heth->State = HAL_ETH_STATE_BUSY_WR;
		1117
		1118	/* Get the ETHERNET MACMIIAR value */
		1119	tmpreg = heth->Instance->MACMIIAR;
		1120
		1121	/* Keep only the CSR Clock Range CR[2:0] bits value */
		1122	tmpreg &= ~ETH_MACMIIAR_CR_MASK;
		1123
		1124	/* Prepare the MII register address value */
		1125	tmpreg \|=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
		1126	tmpreg \|=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
		1127	tmpreg \|= ETH_MACMIIAR_MW; /* Set the write mode */
		1128	tmpreg \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
		1129
		1130	/* Give the value to the MII data register */
		1131	heth->Instance->MACMIIDR = (uint16_t)RegValue;
		1132
		1133	/* Write the result value into the MII Address register */
		1134	heth->Instance->MACMIIAR = tmpreg;
		1135
		1136	/* Get tick */
		1137	tickstart = HAL_GetTick();
		1138
		1139	/* Check for the Busy flag */
		1140	while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
		1141	{
		1142	/* Check for the Timeout */
		1143	if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
		1144	{
		1145	heth->State= HAL_ETH_STATE_READY;
		1146
		1147	/* Process Unlocked */
		1148	__HAL_UNLOCK(heth);
		1149
		1150	return HAL_TIMEOUT;
		1151	}
		1152
		1153	tmpreg = heth->Instance->MACMIIAR;
		1154	}
		1155
		1156	/* Set ETH HAL State to READY */
		1157	heth->State = HAL_ETH_STATE_READY;
		1158
		1159	/* Return function status */
		1160	return HAL_OK;
		1161	}
		1162
		1163	/**
		1164	* @}
		1165	*/
		1166
		1167	/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
		1168	* @brief Peripheral Control functions
		1169	*
		1170	@verbatim
		1171	===============================================================================
		1172	##### Peripheral Control functions #####
		1173	===============================================================================
		1174	[..] This section provides functions allowing to:
		1175	(+) Enable MAC and DMA transmission and reception.
		1176	HAL_ETH_Start();
		1177	(+) Disable MAC and DMA transmission and reception.
		1178	HAL_ETH_Stop();
		1179	(+) Set the MAC configuration in runtime mode
		1180	HAL_ETH_ConfigMAC();
		1181	(+) Set the DMA configuration in runtime mode
		1182	HAL_ETH_ConfigDMA();
		1183
		1184	@endverbatim
		1185	* @{
		1186	*/
		1187
		1188	/**
		1189	* @brief Enables Ethernet MAC and DMA reception/transmission
		1190	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1191	* the configuration information for ETHERNET module
		1192	* @retval HAL status
		1193	*/
		1194	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
		1195	{
		1196	/* Process Locked */
		1197	__HAL_LOCK(heth);
		1198
		1199	/* Set the ETH peripheral state to BUSY */
		1200	heth->State = HAL_ETH_STATE_BUSY;
		1201
		1202	/* Enable transmit state machine of the MAC for transmission on the MII */
		1203	ETH_MACTransmissionEnable(heth);
		1204
		1205	/* Enable receive state machine of the MAC for reception from the MII */
		1206	ETH_MACReceptionEnable(heth);
		1207
		1208	/* Flush Transmit FIFO */
		1209	ETH_FlushTransmitFIFO(heth);
		1210
		1211	/* Start DMA transmission */
		1212	ETH_DMATransmissionEnable(heth);
		1213
		1214	/* Start DMA reception */
		1215	ETH_DMAReceptionEnable(heth);
		1216
		1217	/* Set the ETH state to READY*/
		1218	heth->State= HAL_ETH_STATE_READY;
		1219
		1220	/* Process Unlocked */
		1221	__HAL_UNLOCK(heth);
		1222
		1223	/* Return function status */
		1224	return HAL_OK;
		1225	}
		1226
		1227	/**
		1228	* @brief Stop Ethernet MAC and DMA reception/transmission
		1229	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1230	* the configuration information for ETHERNET module
		1231	* @retval HAL status
		1232	*/
		1233	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
		1234	{
		1235	/* Process Locked */
		1236	__HAL_LOCK(heth);
		1237
		1238	/* Set the ETH peripheral state to BUSY */
		1239	heth->State = HAL_ETH_STATE_BUSY;
		1240
		1241	/* Stop DMA transmission */
		1242	ETH_DMATransmissionDisable(heth);
		1243
		1244	/* Stop DMA reception */
		1245	ETH_DMAReceptionDisable(heth);
		1246
		1247	/* Disable receive state machine of the MAC for reception from the MII */
		1248	ETH_MACReceptionDisable(heth);
		1249
		1250	/* Flush Transmit FIFO */
		1251	ETH_FlushTransmitFIFO(heth);
		1252
		1253	/* Disable transmit state machine of the MAC for transmission on the MII */
		1254	ETH_MACTransmissionDisable(heth);
		1255
		1256	/* Set the ETH state*/
		1257	heth->State = HAL_ETH_STATE_READY;
		1258
		1259	/* Process Unlocked */
		1260	__HAL_UNLOCK(heth);
		1261
		1262	/* Return function status */
		1263	return HAL_OK;
		1264	}
		1265
		1266	/**
		1267	* @brief Set ETH MAC Configuration.
		1268	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1269	* the configuration information for ETHERNET module
		1270	* @param macconf: MAC Configuration structure
		1271	* @retval HAL status
		1272	*/
		1273	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf)
		1274	{
		1275	uint32_t tmpreg = 0;
		1276
		1277	/* Process Locked */
		1278	__HAL_LOCK(heth);
		1279
		1280	/* Set the ETH peripheral state to BUSY */
		1281	heth->State= HAL_ETH_STATE_BUSY;
		1282
		1283	assert_param(IS_ETH_SPEED(heth->Init.Speed));
		1284	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
		1285
		1286	if (macconf != NULL)
		1287	{
		1288	/* Check the parameters */
		1289	assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
		1290	assert_param(IS_ETH_JABBER(macconf->Jabber));
		1291	assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
		1292	assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
		1293	assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
		1294	assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
		1295	assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
		1296	assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
		1297	assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
		1298	assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
		1299	assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
		1300	assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
		1301	assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
		1302	assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
		1303	assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
		1304	assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
		1305	assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
		1306	assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
		1307	assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
		1308	assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
		1309	assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
		1310	assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
		1311	assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
		1312	assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
		1313	assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
		1314	assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
		1315	assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
		1316
		1317	/------------------------ ETHERNET MACCR Configuration --------------------/
		1318	/* Get the ETHERNET MACCR value */
		1319	tmpreg = (heth->Instance)->MACCR;
		1320	/* Clear WD, PCE, PS, TE and RE bits */
		1321	tmpreg &= ETH_MACCR_CLEAR_MASK;
		1322
		1323	tmpreg \|= (uint32_t)(macconf->Watchdog \|
		1324	macconf->Jabber \|
		1325	macconf->InterFrameGap \|
		1326	macconf->CarrierSense \|
		1327	(heth->Init).Speed \|
		1328	macconf->ReceiveOwn \|
		1329	macconf->LoopbackMode \|
		1330	(heth->Init).DuplexMode \|
		1331	macconf->ChecksumOffload \|
		1332	macconf->RetryTransmission \|
		1333	macconf->AutomaticPadCRCStrip \|
		1334	macconf->BackOffLimit \|
		1335	macconf->DeferralCheck);
		1336
		1337	/* Write to ETHERNET MACCR */
		1338	(heth->Instance)->MACCR = (uint32_t)tmpreg;
		1339
		1340	/* Wait until the write operation will be taken into account :
		1341	at least four TX_CLK/RX_CLK clock cycles */
		1342	tmpreg = (heth->Instance)->MACCR;
		1343	HAL_Delay(ETH_REG_WRITE_DELAY);
		1344	(heth->Instance)->MACCR = tmpreg;
		1345
		1346	/----------------------- ETHERNET MACFFR Configuration --------------------/
		1347	/* Write to ETHERNET MACFFR */
		1348	(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll \|
		1349	macconf->SourceAddrFilter \|
		1350	macconf->PassControlFrames \|
		1351	macconf->BroadcastFramesReception \|
		1352	macconf->DestinationAddrFilter \|
		1353	macconf->PromiscuousMode \|
		1354	macconf->MulticastFramesFilter \|
		1355	macconf->UnicastFramesFilter);
		1356
		1357	/* Wait until the write operation will be taken into account :
		1358	at least four TX_CLK/RX_CLK clock cycles */
		1359	tmpreg = (heth->Instance)->MACFFR;
		1360	HAL_Delay(ETH_REG_WRITE_DELAY);
		1361	(heth->Instance)->MACFFR = tmpreg;
		1362
		1363	/--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------/
		1364	/* Write to ETHERNET MACHTHR */
		1365	(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
		1366
		1367	/* Write to ETHERNET MACHTLR */
		1368	(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
		1369	/----------------------- ETHERNET MACFCR Configuration --------------------/
		1370
		1371	/* Get the ETHERNET MACFCR value */
		1372	tmpreg = (heth->Instance)->MACFCR;
		1373	/* Clear xx bits */
		1374	tmpreg &= ETH_MACFCR_CLEAR_MASK;
		1375
		1376	tmpreg \|= (uint32_t)((macconf->PauseTime << 16) \|
		1377	macconf->ZeroQuantaPause \|
		1378	macconf->PauseLowThreshold \|
		1379	macconf->UnicastPauseFrameDetect \|
		1380	macconf->ReceiveFlowControl \|
		1381	macconf->TransmitFlowControl);
		1382
		1383	/* Write to ETHERNET MACFCR */
		1384	(heth->Instance)->MACFCR = (uint32_t)tmpreg;
		1385
		1386	/* Wait until the write operation will be taken into account :
		1387	at least four TX_CLK/RX_CLK clock cycles */
		1388	tmpreg = (heth->Instance)->MACFCR;
		1389	HAL_Delay(ETH_REG_WRITE_DELAY);
		1390	(heth->Instance)->MACFCR = tmpreg;
		1391
		1392	/----------------------- ETHERNET MACVLANTR Configuration -----------------/
		1393	(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison \|
		1394	macconf->VLANTagIdentifier);
		1395
		1396	/* Wait until the write operation will be taken into account :
		1397	at least four TX_CLK/RX_CLK clock cycles */
		1398	tmpreg = (heth->Instance)->MACVLANTR;
		1399	HAL_Delay(ETH_REG_WRITE_DELAY);
		1400	(heth->Instance)->MACVLANTR = tmpreg;
		1401	}
		1402	else /* macconf == NULL : here we just configure Speed and Duplex mode */
		1403	{
		1404	/------------------------ ETHERNET MACCR Configuration --------------------/
		1405	/* Get the ETHERNET MACCR value */
		1406	tmpreg = (heth->Instance)->MACCR;
		1407
		1408	/* Clear FES and DM bits */
		1409	tmpreg &= ~((uint32_t)0x00004800);
		1410
		1411	tmpreg \|= (uint32_t)(heth->Init.Speed \| heth->Init.DuplexMode);
		1412
		1413	/* Write to ETHERNET MACCR */
		1414	(heth->Instance)->MACCR = (uint32_t)tmpreg;
		1415
		1416	/* Wait until the write operation will be taken into account:
		1417	at least four TX_CLK/RX_CLK clock cycles */
		1418	tmpreg = (heth->Instance)->MACCR;
		1419	HAL_Delay(ETH_REG_WRITE_DELAY);
		1420	(heth->Instance)->MACCR = tmpreg;
		1421	}
		1422
		1423	/* Set the ETH state to Ready */
		1424	heth->State= HAL_ETH_STATE_READY;
		1425
		1426	/* Process Unlocked */
		1427	__HAL_UNLOCK(heth);
		1428
		1429	/* Return function status */
		1430	return HAL_OK;
		1431	}
		1432
		1433	/**
		1434	* @brief Sets ETH DMA Configuration.
		1435	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1436	* the configuration information for ETHERNET module
		1437	* @param dmaconf: DMA Configuration structure
		1438	* @retval HAL status
		1439	*/
		1440	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf)
		1441	{
		1442	uint32_t tmpreg = 0;
		1443
		1444	/* Process Locked */
		1445	__HAL_LOCK(heth);
		1446
		1447	/* Set the ETH peripheral state to BUSY */
		1448	heth->State= HAL_ETH_STATE_BUSY;
		1449
		1450	/* Check parameters */
		1451	assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
		1452	assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
		1453	assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
		1454	assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
		1455	assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
		1456	assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
		1457	assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
		1458	assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
		1459	assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
		1460	assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
		1461	assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
		1462	assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
		1463	assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
		1464	assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
		1465	assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
		1466
		1467	/----------------------- ETHERNET DMAOMR Configuration --------------------/
		1468	/* Get the ETHERNET DMAOMR value */
		1469	tmpreg = (heth->Instance)->DMAOMR;
		1470	/* Clear xx bits */
		1471	tmpreg &= ETH_DMAOMR_CLEAR_MASK;
		1472
		1473	tmpreg \|= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame \|
		1474	dmaconf->ReceiveStoreForward \|
		1475	dmaconf->FlushReceivedFrame \|
		1476	dmaconf->TransmitStoreForward \|
		1477	dmaconf->TransmitThresholdControl \|
		1478	dmaconf->ForwardErrorFrames \|
		1479	dmaconf->ForwardUndersizedGoodFrames \|
		1480	dmaconf->ReceiveThresholdControl \|
		1481	dmaconf->SecondFrameOperate);
		1482
		1483	/* Write to ETHERNET DMAOMR */
		1484	(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
		1485
		1486	/* Wait until the write operation will be taken into account:
		1487	at least four TX_CLK/RX_CLK clock cycles */
		1488	tmpreg = (heth->Instance)->DMAOMR;
		1489	HAL_Delay(ETH_REG_WRITE_DELAY);
		1490	(heth->Instance)->DMAOMR = tmpreg;
		1491
		1492	/----------------------- ETHERNET DMABMR Configuration --------------------/
		1493	(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats \|
		1494	dmaconf->FixedBurst \|
		1495	dmaconf->RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
		1496	dmaconf->TxDMABurstLength \|
		1497	(dmaconf->DescriptorSkipLength << 2) \|
		1498	dmaconf->DMAArbitration \|
		1499	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
		1500
		1501	/* Wait until the write operation will be taken into account:
		1502	at least four TX_CLK/RX_CLK clock cycles */
		1503	tmpreg = (heth->Instance)->DMABMR;
		1504	HAL_Delay(ETH_REG_WRITE_DELAY);
		1505	(heth->Instance)->DMABMR = tmpreg;
		1506
		1507	/* Set the ETH state to Ready */
		1508	heth->State= HAL_ETH_STATE_READY;
		1509
		1510	/* Process Unlocked */
		1511	__HAL_UNLOCK(heth);
		1512
		1513	/* Return function status */
		1514	return HAL_OK;
		1515	}
		1516
		1517	/**
		1518	* @}
		1519	*/
		1520
		1521	/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
		1522	* @brief Peripheral State functions
		1523	*
		1524	@verbatim
		1525	===============================================================================
		1526	##### Peripheral State functions #####
		1527	===============================================================================
		1528	[..]
		1529	This subsection permits to get in run-time the status of the peripheral
		1530	and the data flow.
		1531	(+) Get the ETH handle state:
		1532	HAL_ETH_GetState();
		1533
		1534
		1535	@endverbatim
		1536	* @{
		1537	*/
		1538
		1539	/**
		1540	* @brief Return the ETH HAL state
		1541	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1542	* the configuration information for ETHERNET module
		1543	* @retval HAL state
		1544	*/
		1545	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
		1546	{
		1547	/* Return ETH state */
		1548	return heth->State;
		1549	}
		1550
		1551	/**
		1552	* @}
		1553	*/
		1554
		1555	/**
		1556	* @}
		1557	*/
		1558
		1559	/** @addtogroup ETH_Private_Functions
		1560	* @{
		1561	*/
		1562
		1563	/**
		1564	* @brief Configures Ethernet MAC and DMA with default parameters.
		1565	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1566	* the configuration information for ETHERNET module
		1567	* @param err: Ethernet Init error
		1568	* @retval HAL status
		1569	*/
		1570	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
		1571	{
		1572	ETH_MACInitTypeDef macinit;
		1573	ETH_DMAInitTypeDef dmainit;
		1574	uint32_t tmpreg = 0;
		1575
		1576	if (err != ETH_SUCCESS) /* Auto-negotiation failed */
		1577	{
		1578	/* Set Ethernet duplex mode to Full-duplex */
		1579	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
		1580
		1581	/* Set Ethernet speed to 100M */
		1582	(heth->Init).Speed = ETH_SPEED_100M;
		1583	}
		1584
		1585	/* Ethernet MAC default initialization **************************************/
		1586	macinit.Watchdog = ETH_WATCHDOG_ENABLE;
		1587	macinit.Jabber = ETH_JABBER_ENABLE;
		1588	macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
		1589	macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
		1590	macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
		1591	macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
		1592	if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
		1593	{
		1594	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
		1595	}
		1596	else
		1597	{
		1598	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
		1599	}
		1600	macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
		1601	macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
		1602	macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
		1603	macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
		1604	macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
		1605	macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
		1606	macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
		1607	macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
		1608	macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
		1609	macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
		1610	macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
		1611	macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
		1612	macinit.HashTableHigh = 0x0;
		1613	macinit.HashTableLow = 0x0;
		1614	macinit.PauseTime = 0x0;
		1615	macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
		1616	macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
		1617	macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
		1618	macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
		1619	macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
		1620	macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
		1621	macinit.VLANTagIdentifier = 0x0;
		1622
		1623	/------------------------ ETHERNET MACCR Configuration --------------------/
		1624	/* Get the ETHERNET MACCR value */
		1625	tmpreg = (heth->Instance)->MACCR;
		1626	/* Clear WD, PCE, PS, TE and RE bits */
		1627	tmpreg &= ETH_MACCR_CLEAR_MASK;
		1628	/* Set the WD bit according to ETH Watchdog value */
		1629	/* Set the JD: bit according to ETH Jabber value */
		1630	/* Set the IFG bit according to ETH InterFrameGap value */
		1631	/* Set the DCRS bit according to ETH CarrierSense value */
		1632	/* Set the FES bit according to ETH Speed value */
		1633	/* Set the DO bit according to ETH ReceiveOwn value */
		1634	/* Set the LM bit according to ETH LoopbackMode value */
		1635	/* Set the DM bit according to ETH Mode value */
		1636	/* Set the IPCO bit according to ETH ChecksumOffload value */
		1637	/* Set the DR bit according to ETH RetryTransmission value */
		1638	/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
		1639	/* Set the BL bit according to ETH BackOffLimit value */
		1640	/* Set the DC bit according to ETH DeferralCheck value */
		1641	tmpreg \|= (uint32_t)(macinit.Watchdog \|
		1642	macinit.Jabber \|
		1643	macinit.InterFrameGap \|
		1644	macinit.CarrierSense \|
		1645	(heth->Init).Speed \|
		1646	macinit.ReceiveOwn \|
		1647	macinit.LoopbackMode \|
		1648	(heth->Init).DuplexMode \|
		1649	macinit.ChecksumOffload \|
		1650	macinit.RetryTransmission \|
		1651	macinit.AutomaticPadCRCStrip \|
		1652	macinit.BackOffLimit \|
		1653	macinit.DeferralCheck);
		1654
		1655	/* Write to ETHERNET MACCR */
		1656	(heth->Instance)->MACCR = (uint32_t)tmpreg;
		1657
		1658	/* Wait until the write operation will be taken into account:
		1659	at least four TX_CLK/RX_CLK clock cycles */
		1660	tmpreg = (heth->Instance)->MACCR;
		1661	HAL_Delay(ETH_REG_WRITE_DELAY);
		1662	(heth->Instance)->MACCR = tmpreg;
		1663
		1664	/----------------------- ETHERNET MACFFR Configuration --------------------/
		1665	/* Set the RA bit according to ETH ReceiveAll value */
		1666	/* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
		1667	/* Set the PCF bit according to ETH PassControlFrames value */
		1668	/* Set the DBF bit according to ETH BroadcastFramesReception value */
		1669	/* Set the DAIF bit according to ETH DestinationAddrFilter value */
		1670	/* Set the PR bit according to ETH PromiscuousMode value */
		1671	/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
		1672	/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
		1673	/* Write to ETHERNET MACFFR */
		1674	(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll \|
		1675	macinit.SourceAddrFilter \|
		1676	macinit.PassControlFrames \|
		1677	macinit.BroadcastFramesReception \|
		1678	macinit.DestinationAddrFilter \|
		1679	macinit.PromiscuousMode \|
		1680	macinit.MulticastFramesFilter \|
		1681	macinit.UnicastFramesFilter);
		1682
		1683	/* Wait until the write operation will be taken into account:
		1684	at least four TX_CLK/RX_CLK clock cycles */
		1685	tmpreg = (heth->Instance)->MACFFR;
		1686	HAL_Delay(ETH_REG_WRITE_DELAY);
		1687	(heth->Instance)->MACFFR = tmpreg;
		1688
		1689	/--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------/
		1690	/* Write to ETHERNET MACHTHR */
		1691	(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
		1692
		1693	/* Write to ETHERNET MACHTLR */
		1694	(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
		1695	/----------------------- ETHERNET MACFCR Configuration -------------------/
		1696
		1697	/* Get the ETHERNET MACFCR value */
		1698	tmpreg = (heth->Instance)->MACFCR;
		1699	/* Clear xx bits */
		1700	tmpreg &= ETH_MACFCR_CLEAR_MASK;
		1701
		1702	/* Set the PT bit according to ETH PauseTime value */
		1703	/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
		1704	/* Set the PLT bit according to ETH PauseLowThreshold value */
		1705	/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
		1706	/* Set the RFE bit according to ETH ReceiveFlowControl value */
		1707	/* Set the TFE bit according to ETH TransmitFlowControl value */
		1708	tmpreg \|= (uint32_t)((macinit.PauseTime << 16) \|
		1709	macinit.ZeroQuantaPause \|
		1710	macinit.PauseLowThreshold \|
		1711	macinit.UnicastPauseFrameDetect \|
		1712	macinit.ReceiveFlowControl \|
		1713	macinit.TransmitFlowControl);
		1714
		1715	/* Write to ETHERNET MACFCR */
		1716	(heth->Instance)->MACFCR = (uint32_t)tmpreg;
		1717
		1718	/* Wait until the write operation will be taken into account:
		1719	at least four TX_CLK/RX_CLK clock cycles */
		1720	tmpreg = (heth->Instance)->MACFCR;
		1721	HAL_Delay(ETH_REG_WRITE_DELAY);
		1722	(heth->Instance)->MACFCR = tmpreg;
		1723
		1724	/----------------------- ETHERNET MACVLANTR Configuration ----------------/
		1725	/* Set the ETV bit according to ETH VLANTagComparison value */
		1726	/* Set the VL bit according to ETH VLANTagIdentifier value */
		1727	(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison \|
		1728	macinit.VLANTagIdentifier);
		1729
		1730	/* Wait until the write operation will be taken into account:
		1731	at least four TX_CLK/RX_CLK clock cycles */
		1732	tmpreg = (heth->Instance)->MACVLANTR;
		1733	HAL_Delay(ETH_REG_WRITE_DELAY);
		1734	(heth->Instance)->MACVLANTR = tmpreg;
		1735
		1736	/* Ethernet DMA default initialization ************************************/
		1737	dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
		1738	dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
		1739	dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
		1740	dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
		1741	dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
		1742	dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
		1743	dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
		1744	dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
		1745	dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
		1746	dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
		1747	dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
		1748	dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
		1749	dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
		1750	dmainit.DescriptorSkipLength = 0x0;
		1751	dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
		1752
		1753	/* Get the ETHERNET DMAOMR value */
		1754	tmpreg = (heth->Instance)->DMAOMR;
		1755	/* Clear xx bits */
		1756	tmpreg &= ETH_DMAOMR_CLEAR_MASK;
		1757
		1758	/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
		1759	/* Set the RSF bit according to ETH ReceiveStoreForward value */
		1760	/* Set the DFF bit according to ETH FlushReceivedFrame value */
		1761	/* Set the TSF bit according to ETH TransmitStoreForward value */
		1762	/* Set the TTC bit according to ETH TransmitThresholdControl value */
		1763	/* Set the FEF bit according to ETH ForwardErrorFrames value */
		1764	/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
		1765	/* Set the RTC bit according to ETH ReceiveThresholdControl value */
		1766	/* Set the OSF bit according to ETH SecondFrameOperate value */
		1767	tmpreg \|= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame \|
		1768	dmainit.ReceiveStoreForward \|
		1769	dmainit.FlushReceivedFrame \|
		1770	dmainit.TransmitStoreForward \|
		1771	dmainit.TransmitThresholdControl \|
		1772	dmainit.ForwardErrorFrames \|
		1773	dmainit.ForwardUndersizedGoodFrames \|
		1774	dmainit.ReceiveThresholdControl \|
		1775	dmainit.SecondFrameOperate);
		1776
		1777	/* Write to ETHERNET DMAOMR */
		1778	(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
		1779
		1780	/* Wait until the write operation will be taken into account:
		1781	at least four TX_CLK/RX_CLK clock cycles */
		1782	tmpreg = (heth->Instance)->DMAOMR;
		1783	HAL_Delay(ETH_REG_WRITE_DELAY);
		1784	(heth->Instance)->DMAOMR = tmpreg;
		1785
		1786	/----------------------- ETHERNET DMABMR Configuration ------------------/
		1787	/* Set the AAL bit according to ETH AddressAlignedBeats value */
		1788	/* Set the FB bit according to ETH FixedBurst value */
		1789	/* Set the RPBL and 4PBL bits according to ETH RxDMABurstLength value /
		1790	/* Set the PBL and 4PBL bits according to ETH TxDMABurstLength value /
		1791	/* Set the DSL bit according to ETH DesciptorSkipLength value */
		1792	/* Set the PR and DA bits according to ETH DMAArbitration value */
		1793	(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats \|
		1794	dmainit.FixedBurst \|
		1795	dmainit.RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
		1796	dmainit.TxDMABurstLength \|
		1797	(dmainit.DescriptorSkipLength << 2) \|
		1798	dmainit.DMAArbitration \|
		1799	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
		1800
		1801	/* Wait until the write operation will be taken into account:
		1802	at least four TX_CLK/RX_CLK clock cycles */
		1803	tmpreg = (heth->Instance)->DMABMR;
		1804	HAL_Delay(ETH_REG_WRITE_DELAY);
		1805	(heth->Instance)->DMABMR = tmpreg;
		1806
		1807	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
		1808	{
		1809	/* Enable the Ethernet Rx Interrupt */
		1810	__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS \| ETH_DMA_IT_R);
		1811	}
		1812
		1813	/* Initialize MAC address in ethernet MAC */
		1814	ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
		1815	}
		1816
		1817	/**
		1818	* @brief Configures the selected MAC address.
		1819	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1820	* the configuration information for ETHERNET module
		1821	* @param MacAddr: The MAC address to configure
		1822	* This parameter can be one of the following values:
		1823	* @arg ETH_MAC_Address0: MAC Address0
		1824	* @arg ETH_MAC_Address1: MAC Address1
		1825	* @arg ETH_MAC_Address2: MAC Address2
		1826	* @arg ETH_MAC_Address3: MAC Address3
		1827	* @param Addr: Pointer to MAC address buffer data (6 bytes)
		1828	* @retval HAL status
		1829	*/
		1830	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr)
		1831	{
		1832	uint32_t tmpreg;
		1833
		1834	/* Check the parameters */
		1835	assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
		1836
		1837	/* Calculate the selected MAC address high register */
		1838	tmpreg = ((uint32_t)Addr[5] << 8) \| (uint32_t)Addr[4];
		1839	/* Load the selected MAC address high register */
		1840	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
		1841	/* Calculate the selected MAC address low register */
		1842	tmpreg = ((uint32_t)Addr[3] << 24) \| ((uint32_t)Addr[2] << 16) \| ((uint32_t)Addr[1] << 8) \| Addr[0];
		1843
		1844	/* Load the selected MAC address low register */
		1845	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
		1846	}
		1847
		1848	/**
		1849	* @brief Enables the MAC transmission.
		1850	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1851	* the configuration information for ETHERNET module
		1852	* @retval None
		1853	*/
		1854	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
		1855	{
		1856	__IO uint32_t tmpreg = 0;
		1857
		1858	/* Enable the MAC transmission */
		1859	(heth->Instance)->MACCR \|= ETH_MACCR_TE;
		1860
		1861	/* Wait until the write operation will be taken into account:
		1862	at least four TX_CLK/RX_CLK clock cycles */
		1863	tmpreg = (heth->Instance)->MACCR;
		1864	HAL_Delay(ETH_REG_WRITE_DELAY);
		1865	(heth->Instance)->MACCR = tmpreg;
		1866	}
		1867
		1868	/**
		1869	* @brief Disables the MAC transmission.
		1870	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1871	* the configuration information for ETHERNET module
		1872	* @retval None
		1873	*/
		1874	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
		1875	{
		1876	__IO uint32_t tmpreg = 0;
		1877
		1878	/* Disable the MAC transmission */
		1879	(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
		1880
		1881	/* Wait until the write operation will be taken into account:
		1882	at least four TX_CLK/RX_CLK clock cycles */
		1883	tmpreg = (heth->Instance)->MACCR;
		1884	HAL_Delay(ETH_REG_WRITE_DELAY);
		1885	(heth->Instance)->MACCR = tmpreg;
		1886	}
		1887
		1888	/**
		1889	* @brief Enables the MAC reception.
		1890	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1891	* the configuration information for ETHERNET module
		1892	* @retval None
		1893	*/
		1894	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
		1895	{
		1896	__IO uint32_t tmpreg = 0;
		1897
		1898	/* Enable the MAC reception */
		1899	(heth->Instance)->MACCR \|= ETH_MACCR_RE;
		1900
		1901	/* Wait until the write operation will be taken into account:
		1902	at least four TX_CLK/RX_CLK clock cycles */
		1903	tmpreg = (heth->Instance)->MACCR;
		1904	HAL_Delay(ETH_REG_WRITE_DELAY);
		1905	(heth->Instance)->MACCR = tmpreg;
		1906	}
		1907
		1908	/**
		1909	* @brief Disables the MAC reception.
		1910	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1911	* the configuration information for ETHERNET module
		1912	* @retval None
		1913	*/
		1914	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
		1915	{
		1916	__IO uint32_t tmpreg = 0;
		1917
		1918	/* Disable the MAC reception */
		1919	(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
		1920
		1921	/* Wait until the write operation will be taken into account:
		1922	at least four TX_CLK/RX_CLK clock cycles */
		1923	tmpreg = (heth->Instance)->MACCR;
		1924	HAL_Delay(ETH_REG_WRITE_DELAY);
		1925	(heth->Instance)->MACCR = tmpreg;
		1926	}
		1927
		1928	/**
		1929	* @brief Enables the DMA transmission.
		1930	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1931	* the configuration information for ETHERNET module
		1932	* @retval None
		1933	*/
		1934	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
		1935	{
		1936	/* Enable the DMA transmission */
		1937	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_ST;
		1938	}
		1939
		1940	/**
		1941	* @brief Disables the DMA transmission.
		1942	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1943	* the configuration information for ETHERNET module
		1944	* @retval None
		1945	*/
		1946	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
		1947	{
		1948	/* Disable the DMA transmission */
		1949	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
		1950	}
		1951
		1952	/**
		1953	* @brief Enables the DMA reception.
		1954	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1955	* the configuration information for ETHERNET module
		1956	* @retval None
		1957	*/
		1958	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
		1959	{
		1960	/* Enable the DMA reception */
		1961	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_SR;
		1962	}
		1963
		1964	/**
		1965	* @brief Disables the DMA reception.
		1966	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1967	* the configuration information for ETHERNET module
		1968	* @retval None
		1969	*/
		1970	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
		1971	{
		1972	/* Disable the DMA reception */
		1973	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
		1974	}
		1975
		1976	/**
		1977	* @brief Clears the ETHERNET transmit FIFO.
		1978	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
		1979	* the configuration information for ETHERNET module
		1980	* @retval None
		1981	*/
		1982	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
		1983	{
		1984	__IO uint32_t tmpreg = 0;
		1985
		1986	/* Set the Flush Transmit FIFO bit */
		1987	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_FTF;
		1988
		1989	/* Wait until the write operation will be taken into account:
		1990	at least four TX_CLK/RX_CLK clock cycles */
		1991	tmpreg = (heth->Instance)->DMAOMR;
		1992	HAL_Delay(ETH_REG_WRITE_DELAY);
		1993	(heth->Instance)->DMAOMR = tmpreg;
		1994	}
		1995
		1996	/**
		1997	* @}
		1998	*/
		1999
		2000	#endif /* HAL_ETH_MODULE_ENABLED */
		2001	/**
		2002	* @}
		2003	*/
		2004
		2005	#endif /* STM32F107xC */
		2006	/**
		2007	* @}
		2008	*/
		2009
		2010	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c – Rev 5