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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 18 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_dma.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief DMA HAL module driver. |
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| 6 | * This file provides firmware functions to manage the following |
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| 7 | * functionalities of the Direct Memory Access (DMA) peripheral: |
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| 8 | * + Initialization and de-initialization functions |
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| 9 | * + IO operation functions |
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| 10 | * + Peripheral State and errors functions |
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| 11 | @verbatim |
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| 12 | ============================================================================== |
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| 13 | ##### How to use this driver ##### |
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| 14 | ============================================================================== |
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| 15 | [..] |
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| 16 | (#) Enable and configure the peripheral to be connected to the DMA Channel |
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| 17 | (except for internal SRAM / FLASH memories: no initialization is |
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| 18 | necessary). Please refer to the Reference manual for connection between peripherals |
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| 19 | and DMA requests. |
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| 20 | |||
| 21 | (#) For a given Channel, program the required configuration through the following parameters: |
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| 22 | Channel request, Transfer Direction, Source and Destination data formats, |
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| 23 | Circular or Normal mode, Channel Priority level, Source and Destination Increment mode |
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| 24 | using HAL_DMA_Init() function. |
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| 25 | |||
| 26 | (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error |
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| 27 | detection. |
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| 28 | |||
| 29 | (#) Use HAL_DMA_Abort() function to abort the current transfer |
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| 30 | |||
| 31 | -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. |
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| 32 | *** Polling mode IO operation *** |
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| 33 | ================================= |
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| 34 | [..] |
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| 35 | (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source |
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| 36 | address and destination address and the Length of data to be transferred |
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| 37 | (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this |
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| 38 | case a fixed Timeout can be configured by User depending from his application. |
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| 39 | |||
| 40 | *** Interrupt mode IO operation *** |
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| 41 | =================================== |
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| 42 | [..] |
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| 43 | (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() |
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| 44 | (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() |
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| 45 | (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of |
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| 46 | Source address and destination address and the Length of data to be transferred. |
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| 47 | In this case the DMA interrupt is configured |
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| 48 | (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine |
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| 49 | (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can |
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| 50 | add his own function by customization of function pointer XferCpltCallback and |
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| 51 | XferErrorCallback (i.e. a member of DMA handle structure). |
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| 52 | |||
| 53 | *** DMA HAL driver macros list *** |
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| 54 | ============================================= |
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| 55 | [..] |
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| 56 | Below the list of most used macros in DMA HAL driver. |
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| 57 | |||
| 58 | (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. |
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| 59 | (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. |
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| 60 | (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. |
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| 61 | (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. |
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| 62 | (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. |
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| 63 | (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. |
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| 64 | (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. |
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| 65 | |||
| 66 | [..] |
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| 67 | (@) You can refer to the DMA HAL driver header file for more useful macros |
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| 68 | |||
| 69 | @endverbatim |
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| 70 | ****************************************************************************** |
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| 71 | * @attention |
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| 72 | * |
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| 73 | * Copyright (c) 2016 STMicroelectronics. |
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| 74 | * All rights reserved. |
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| 75 | * |
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| 76 | * This software is licensed under terms that can be found in the LICENSE file in |
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| 77 | * the root directory of this software component. |
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| 78 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 79 | * |
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| 80 | ****************************************************************************** |
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| 81 | */ |
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| 82 | |||
| 83 | /* Includes ------------------------------------------------------------------*/ |
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| 84 | #include "stm32f1xx_hal.h" |
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| 85 | |||
| 86 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 87 | * @{ |
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| 88 | */ |
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| 89 | |||
| 90 | /** @defgroup DMA DMA |
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| 91 | * @brief DMA HAL module driver |
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| 92 | * @{ |
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| 93 | */ |
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| 94 | |||
| 95 | #ifdef HAL_DMA_MODULE_ENABLED |
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| 96 | |||
| 97 | /* Private typedef -----------------------------------------------------------*/ |
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| 98 | /* Private define ------------------------------------------------------------*/ |
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| 99 | /* Private macro -------------------------------------------------------------*/ |
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| 100 | /* Private variables ---------------------------------------------------------*/ |
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| 101 | /* Private function prototypes -----------------------------------------------*/ |
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| 102 | /** @defgroup DMA_Private_Functions DMA Private Functions |
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| 103 | * @{ |
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| 104 | */ |
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| 105 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
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| 106 | /** |
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| 107 | * @} |
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| 108 | */ |
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| 109 | |||
| 110 | /* Exported functions ---------------------------------------------------------*/ |
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| 111 | |||
| 112 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
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| 113 | * @{ |
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| 114 | */ |
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| 115 | |||
| 116 | /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 117 | * @brief Initialization and de-initialization functions |
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| 118 | * |
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| 119 | @verbatim |
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| 120 | =============================================================================== |
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| 121 | ##### Initialization and de-initialization functions ##### |
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| 122 | =============================================================================== |
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| 123 | [..] |
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| 124 | This section provides functions allowing to initialize the DMA Channel source |
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| 125 | and destination addresses, incrementation and data sizes, transfer direction, |
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| 126 | circular/normal mode selection, memory-to-memory mode selection and Channel priority value. |
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| 127 | [..] |
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| 128 | The HAL_DMA_Init() function follows the DMA configuration procedures as described in |
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| 129 | reference manual. |
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| 130 | |||
| 131 | @endverbatim |
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| 132 | * @{ |
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| 133 | */ |
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| 134 | |||
| 135 | /** |
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| 136 | * @brief Initialize the DMA according to the specified |
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| 137 | * parameters in the DMA_InitTypeDef and initialize the associated handle. |
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| 138 | * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains |
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| 139 | * the configuration information for the specified DMA Channel. |
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| 140 | * @retval HAL status |
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| 141 | */ |
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| 142 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) |
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| 143 | { |
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| 144 | uint32_t tmp = 0U; |
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| 145 | |||
| 146 | /* Check the DMA handle allocation */ |
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| 147 | if(hdma == NULL) |
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| 148 | { |
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| 149 | return HAL_ERROR; |
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| 150 | } |
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| 151 | |||
| 152 | /* Check the parameters */ |
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| 153 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
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| 154 | assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); |
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| 155 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); |
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| 156 | assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); |
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| 157 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
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| 158 | assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
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| 159 | assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
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| 160 | assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
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| 161 | |||
| 162 | #if defined (DMA2) |
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| 163 | /* calculation of the channel index */ |
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| 164 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
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| 165 | { |
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| 166 | /* DMA1 */ |
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| 167 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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| 168 | hdma->DmaBaseAddress = DMA1; |
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| 169 | } |
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| 170 | else |
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| 171 | { |
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| 172 | /* DMA2 */ |
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| 173 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
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| 174 | hdma->DmaBaseAddress = DMA2; |
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| 175 | } |
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| 176 | #else |
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| 177 | /* DMA1 */ |
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| 178 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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| 179 | hdma->DmaBaseAddress = DMA1; |
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| 180 | #endif /* DMA2 */ |
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| 181 | |||
| 182 | /* Change DMA peripheral state */ |
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| 183 | hdma->State = HAL_DMA_STATE_BUSY; |
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| 184 | |||
| 185 | /* Get the CR register value */ |
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| 186 | tmp = hdma->Instance->CCR; |
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| 187 | |||
| 188 | /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ |
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| 189 | tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ |
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| 190 | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ |
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| 191 | DMA_CCR_DIR)); |
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| 192 | |||
| 193 | /* Prepare the DMA Channel configuration */ |
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| 194 | tmp |= hdma->Init.Direction | |
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| 195 | hdma->Init.PeriphInc | hdma->Init.MemInc | |
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| 196 | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | |
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| 197 | hdma->Init.Mode | hdma->Init.Priority; |
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| 198 | |||
| 199 | /* Write to DMA Channel CR register */ |
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| 200 | hdma->Instance->CCR = tmp; |
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| 201 | |||
| 202 | /* Initialise the error code */ |
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| 203 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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| 204 | |||
| 205 | /* Initialize the DMA state*/ |
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| 206 | hdma->State = HAL_DMA_STATE_READY; |
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| 207 | /* Allocate lock resource and initialize it */ |
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| 208 | hdma->Lock = HAL_UNLOCKED; |
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| 209 | |||
| 210 | return HAL_OK; |
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| 211 | } |
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| 212 | |||
| 213 | /** |
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| 214 | * @brief DeInitialize the DMA peripheral. |
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| 215 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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| 216 | * the configuration information for the specified DMA Channel. |
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| 217 | * @retval HAL status |
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| 218 | */ |
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| 219 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) |
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| 220 | { |
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| 221 | /* Check the DMA handle allocation */ |
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| 222 | if(hdma == NULL) |
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| 223 | { |
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| 224 | return HAL_ERROR; |
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| 225 | } |
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| 226 | |||
| 227 | /* Check the parameters */ |
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| 228 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
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| 229 | |||
| 230 | /* Disable the selected DMA Channelx */ |
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| 231 | __HAL_DMA_DISABLE(hdma); |
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| 232 | |||
| 233 | /* Reset DMA Channel control register */ |
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| 234 | hdma->Instance->CCR = 0U; |
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| 235 | |||
| 236 | /* Reset DMA Channel Number of Data to Transfer register */ |
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| 237 | hdma->Instance->CNDTR = 0U; |
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| 238 | |||
| 239 | /* Reset DMA Channel peripheral address register */ |
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| 240 | hdma->Instance->CPAR = 0U; |
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| 241 | |||
| 242 | /* Reset DMA Channel memory address register */ |
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| 243 | hdma->Instance->CMAR = 0U; |
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| 244 | |||
| 245 | #if defined (DMA2) |
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| 246 | /* calculation of the channel index */ |
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| 247 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
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| 248 | { |
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| 249 | /* DMA1 */ |
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| 250 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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| 251 | hdma->DmaBaseAddress = DMA1; |
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| 252 | } |
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| 253 | else |
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| 254 | { |
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| 255 | /* DMA2 */ |
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| 256 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
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| 257 | hdma->DmaBaseAddress = DMA2; |
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| 258 | } |
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| 259 | #else |
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| 260 | /* DMA1 */ |
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| 261 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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| 262 | hdma->DmaBaseAddress = DMA1; |
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| 263 | #endif /* DMA2 */ |
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| 264 | |||
| 265 | /* Clear all flags */ |
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| 266 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); |
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| 267 | |||
| 268 | /* Clean all callbacks */ |
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| 269 | hdma->XferCpltCallback = NULL; |
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| 270 | hdma->XferHalfCpltCallback = NULL; |
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| 271 | hdma->XferErrorCallback = NULL; |
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| 272 | hdma->XferAbortCallback = NULL; |
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| 273 | |||
| 274 | /* Reset the error code */ |
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| 275 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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| 276 | |||
| 277 | /* Reset the DMA state */ |
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| 278 | hdma->State = HAL_DMA_STATE_RESET; |
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| 279 | |||
| 280 | /* Release Lock */ |
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| 281 | __HAL_UNLOCK(hdma); |
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| 282 | |||
| 283 | return HAL_OK; |
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| 284 | } |
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| 285 | |||
| 286 | /** |
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| 287 | * @} |
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| 288 | */ |
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| 289 | |||
| 290 | /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions |
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| 291 | * @brief Input and Output operation functions |
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| 292 | * |
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| 293 | @verbatim |
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| 294 | =============================================================================== |
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| 295 | ##### IO operation functions ##### |
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| 296 | =============================================================================== |
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| 297 | [..] This section provides functions allowing to: |
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| 298 | (+) Configure the source, destination address and data length and Start DMA transfer |
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| 299 | (+) Configure the source, destination address and data length and |
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| 300 | Start DMA transfer with interrupt |
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| 301 | (+) Abort DMA transfer |
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| 302 | (+) Poll for transfer complete |
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| 303 | (+) Handle DMA interrupt request |
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| 304 | |||
| 305 | @endverbatim |
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| 306 | * @{ |
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| 307 | */ |
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| 308 | |||
| 309 | /** |
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| 310 | * @brief Start the DMA Transfer. |
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| 311 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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| 312 | * the configuration information for the specified DMA Channel. |
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| 313 | * @param SrcAddress: The source memory Buffer address |
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| 314 | * @param DstAddress: The destination memory Buffer address |
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| 315 | * @param DataLength: The length of data to be transferred from source to destination |
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| 316 | * @retval HAL status |
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| 317 | */ |
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| 318 | HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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| 319 | { |
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| 320 | HAL_StatusTypeDef status = HAL_OK; |
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| 321 | |||
| 322 | /* Check the parameters */ |
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| 323 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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| 324 | |||
| 325 | /* Process locked */ |
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| 326 | __HAL_LOCK(hdma); |
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| 327 | |||
| 328 | if(HAL_DMA_STATE_READY == hdma->State) |
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| 329 | { |
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| 330 | /* Change DMA peripheral state */ |
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| 331 | hdma->State = HAL_DMA_STATE_BUSY; |
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| 332 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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| 333 | |||
| 334 | /* Disable the peripheral */ |
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| 335 | __HAL_DMA_DISABLE(hdma); |
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| 336 | |||
| 337 | /* Configure the source, destination address and the data length & clear flags*/ |
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| 338 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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| 339 | |||
| 340 | /* Enable the Peripheral */ |
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| 341 | __HAL_DMA_ENABLE(hdma); |
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| 342 | } |
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| 343 | else |
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| 344 | { |
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| 345 | /* Process Unlocked */ |
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| 346 | __HAL_UNLOCK(hdma); |
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| 347 | status = HAL_BUSY; |
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| 348 | } |
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| 349 | return status; |
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| 350 | } |
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| 351 | |||
| 352 | /** |
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| 353 | * @brief Start the DMA Transfer with interrupt enabled. |
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| 354 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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| 355 | * the configuration information for the specified DMA Channel. |
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| 356 | * @param SrcAddress: The source memory Buffer address |
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| 357 | * @param DstAddress: The destination memory Buffer address |
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| 358 | * @param DataLength: The length of data to be transferred from source to destination |
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| 359 | * @retval HAL status |
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| 360 | */ |
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| 361 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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| 362 | { |
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| 363 | HAL_StatusTypeDef status = HAL_OK; |
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| 364 | |||
| 365 | /* Check the parameters */ |
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| 366 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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| 367 | |||
| 368 | /* Process locked */ |
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| 369 | __HAL_LOCK(hdma); |
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| 370 | |||
| 371 | if(HAL_DMA_STATE_READY == hdma->State) |
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| 372 | { |
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| 373 | /* Change DMA peripheral state */ |
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| 374 | hdma->State = HAL_DMA_STATE_BUSY; |
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| 375 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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| 376 | |||
| 377 | /* Disable the peripheral */ |
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| 378 | __HAL_DMA_DISABLE(hdma); |
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| 379 | |||
| 380 | /* Configure the source, destination address and the data length & clear flags*/ |
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| 381 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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| 382 | |||
| 383 | /* Enable the transfer complete interrupt */ |
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| 384 | /* Enable the transfer Error interrupt */ |
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| 385 | if(NULL != hdma->XferHalfCpltCallback) |
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| 386 | { |
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| 387 | /* Enable the Half transfer complete interrupt as well */ |
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| 388 | __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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| 389 | } |
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| 390 | else |
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| 391 | { |
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| 392 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
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| 393 | __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); |
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| 394 | } |
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| 395 | /* Enable the Peripheral */ |
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| 396 | __HAL_DMA_ENABLE(hdma); |
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| 397 | } |
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| 398 | else |
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| 399 | { |
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| 400 | /* Process Unlocked */ |
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| 401 | __HAL_UNLOCK(hdma); |
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| 402 | |||
| 403 | /* Remain BUSY */ |
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| 404 | status = HAL_BUSY; |
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| 405 | } |
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| 406 | return status; |
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| 407 | } |
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| 408 | |||
| 409 | /** |
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| 410 | * @brief Abort the DMA Transfer. |
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| 411 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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| 412 | * the configuration information for the specified DMA Channel. |
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| 413 | * @retval HAL status |
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| 414 | */ |
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| 415 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
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| 416 | { |
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| 417 | HAL_StatusTypeDef status = HAL_OK; |
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| 418 | |||
| 419 | if(hdma->State != HAL_DMA_STATE_BUSY) |
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| 420 | { |
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| 421 | /* no transfer ongoing */ |
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| 422 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
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| 423 | |||
| 424 | /* Process Unlocked */ |
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| 425 | __HAL_UNLOCK(hdma); |
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| 426 | |||
| 427 | return HAL_ERROR; |
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| 428 | } |
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| 429 | else |
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| 430 | |||
| 431 | { |
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| 432 | /* Disable DMA IT */ |
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| 433 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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| 434 | |||
| 435 | /* Disable the channel */ |
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| 436 | __HAL_DMA_DISABLE(hdma); |
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| 437 | |||
| 438 | /* Clear all flags */ |
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| 439 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
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| 440 | } |
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| 441 | /* Change the DMA state */ |
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| 442 | hdma->State = HAL_DMA_STATE_READY; |
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| 443 | |||
| 444 | /* Process Unlocked */ |
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| 445 | __HAL_UNLOCK(hdma); |
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| 446 | |||
| 447 | return status; |
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| 448 | } |
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| 449 | |||
| 450 | /** |
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| 451 | * @brief Aborts the DMA Transfer in Interrupt mode. |
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| 452 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
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| 453 | * the configuration information for the specified DMA Channel. |
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| 454 | * @retval HAL status |
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| 455 | */ |
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| 456 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) |
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| 457 | { |
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| 458 | HAL_StatusTypeDef status = HAL_OK; |
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| 459 | |||
| 460 | if(HAL_DMA_STATE_BUSY != hdma->State) |
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| 461 | { |
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| 462 | /* no transfer ongoing */ |
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| 463 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
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| 464 | |||
| 465 | status = HAL_ERROR; |
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| 466 | } |
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| 467 | else |
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| 468 | { |
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| 469 | /* Disable DMA IT */ |
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| 470 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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| 471 | |||
| 472 | /* Disable the channel */ |
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| 473 | __HAL_DMA_DISABLE(hdma); |
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| 474 | |||
| 475 | /* Clear all flags */ |
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| 476 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); |
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| 477 | |||
| 478 | /* Change the DMA state */ |
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| 479 | hdma->State = HAL_DMA_STATE_READY; |
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| 480 | |||
| 481 | /* Process Unlocked */ |
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| 482 | __HAL_UNLOCK(hdma); |
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| 483 | |||
| 484 | /* Call User Abort callback */ |
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| 485 | if(hdma->XferAbortCallback != NULL) |
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| 486 | { |
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| 487 | hdma->XferAbortCallback(hdma); |
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| 488 | } |
||
| 489 | } |
||
| 490 | return status; |
||
| 491 | } |
||
| 492 | |||
| 493 | /** |
||
| 494 | * @brief Polling for transfer complete. |
||
| 495 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
| 496 | * the configuration information for the specified DMA Channel. |
||
| 497 | * @param CompleteLevel: Specifies the DMA level complete. |
||
| 498 | * @param Timeout: Timeout duration. |
||
| 499 | * @retval HAL status |
||
| 500 | */ |
||
| 501 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) |
||
| 502 | { |
||
| 503 | uint32_t temp; |
||
| 504 | uint32_t tickstart = 0U; |
||
| 505 | |||
| 506 | if(HAL_DMA_STATE_BUSY != hdma->State) |
||
| 507 | { |
||
| 508 | /* no transfer ongoing */ |
||
| 509 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
||
| 510 | __HAL_UNLOCK(hdma); |
||
| 511 | return HAL_ERROR; |
||
| 512 | } |
||
| 513 | |||
| 514 | /* Polling mode not supported in circular mode */ |
||
| 515 | if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) |
||
| 516 | { |
||
| 517 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; |
||
| 518 | return HAL_ERROR; |
||
| 519 | } |
||
| 520 | |||
| 521 | /* Get the level transfer complete flag */ |
||
| 522 | if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
||
| 523 | { |
||
| 524 | /* Transfer Complete flag */ |
||
| 525 | temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); |
||
| 526 | } |
||
| 527 | else |
||
| 528 | { |
||
| 529 | /* Half Transfer Complete flag */ |
||
| 530 | temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); |
||
| 531 | } |
||
| 532 | |||
| 533 | /* Get tick */ |
||
| 534 | tickstart = HAL_GetTick(); |
||
| 535 | |||
| 536 | while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) |
||
| 537 | { |
||
| 538 | if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) |
||
| 539 | { |
||
| 540 | /* When a DMA transfer error occurs */ |
||
| 541 | /* A hardware clear of its EN bits is performed */ |
||
| 542 | /* Clear all flags */ |
||
| 543 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||
| 544 | |||
| 545 | /* Update error code */ |
||
| 546 | SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); |
||
| 547 | |||
| 548 | /* Change the DMA state */ |
||
| 549 | hdma->State= HAL_DMA_STATE_READY; |
||
| 550 | |||
| 551 | /* Process Unlocked */ |
||
| 552 | __HAL_UNLOCK(hdma); |
||
| 553 | |||
| 554 | return HAL_ERROR; |
||
| 555 | } |
||
| 556 | /* Check for the Timeout */ |
||
| 557 | if(Timeout != HAL_MAX_DELAY) |
||
| 558 | { |
||
| 559 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) |
||
| 560 | { |
||
| 561 | /* Update error code */ |
||
| 562 | SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); |
||
| 563 | |||
| 564 | /* Change the DMA state */ |
||
| 565 | hdma->State = HAL_DMA_STATE_READY; |
||
| 566 | |||
| 567 | /* Process Unlocked */ |
||
| 568 | __HAL_UNLOCK(hdma); |
||
| 569 | |||
| 570 | return HAL_ERROR; |
||
| 571 | } |
||
| 572 | } |
||
| 573 | } |
||
| 574 | |||
| 575 | if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
||
| 576 | { |
||
| 577 | /* Clear the transfer complete flag */ |
||
| 578 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
||
| 579 | |||
| 580 | /* The selected Channelx EN bit is cleared (DMA is disabled and |
||
| 581 | all transfers are complete) */ |
||
| 582 | hdma->State = HAL_DMA_STATE_READY; |
||
| 583 | } |
||
| 584 | else |
||
| 585 | { |
||
| 586 | /* Clear the half transfer complete flag */ |
||
| 587 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
||
| 588 | } |
||
| 589 | |||
| 590 | /* Process unlocked */ |
||
| 591 | __HAL_UNLOCK(hdma); |
||
| 592 | |||
| 593 | return HAL_OK; |
||
| 594 | } |
||
| 595 | |||
| 596 | /** |
||
| 597 | * @brief Handles DMA interrupt request. |
||
| 598 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
| 599 | * the configuration information for the specified DMA Channel. |
||
| 600 | * @retval None |
||
| 601 | */ |
||
| 602 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) |
||
| 603 | { |
||
| 604 | uint32_t flag_it = hdma->DmaBaseAddress->ISR; |
||
| 605 | uint32_t source_it = hdma->Instance->CCR; |
||
| 606 | |||
| 607 | /* Half Transfer Complete Interrupt management ******************************/ |
||
| 608 | if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) |
||
| 609 | { |
||
| 610 | /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ |
||
| 611 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||
| 612 | { |
||
| 613 | /* Disable the half transfer interrupt */ |
||
| 614 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
||
| 615 | } |
||
| 616 | /* Clear the half transfer complete flag */ |
||
| 617 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
||
| 618 | |||
| 619 | /* DMA peripheral state is not updated in Half Transfer */ |
||
| 620 | /* but in Transfer Complete case */ |
||
| 621 | |||
| 622 | if(hdma->XferHalfCpltCallback != NULL) |
||
| 623 | { |
||
| 624 | /* Half transfer callback */ |
||
| 625 | hdma->XferHalfCpltCallback(hdma); |
||
| 626 | } |
||
| 627 | } |
||
| 628 | |||
| 629 | /* Transfer Complete Interrupt management ***********************************/ |
||
| 630 | else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) |
||
| 631 | { |
||
| 632 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||
| 633 | { |
||
| 634 | /* Disable the transfer complete and error interrupt */ |
||
| 635 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); |
||
| 636 | |||
| 637 | /* Change the DMA state */ |
||
| 638 | hdma->State = HAL_DMA_STATE_READY; |
||
| 639 | } |
||
| 640 | /* Clear the transfer complete flag */ |
||
| 641 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
||
| 642 | |||
| 643 | /* Process Unlocked */ |
||
| 644 | __HAL_UNLOCK(hdma); |
||
| 645 | |||
| 646 | if(hdma->XferCpltCallback != NULL) |
||
| 647 | { |
||
| 648 | /* Transfer complete callback */ |
||
| 649 | hdma->XferCpltCallback(hdma); |
||
| 650 | } |
||
| 651 | } |
||
| 652 | |||
| 653 | /* Transfer Error Interrupt management **************************************/ |
||
| 654 | else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) |
||
| 655 | { |
||
| 656 | /* When a DMA transfer error occurs */ |
||
| 657 | /* A hardware clear of its EN bits is performed */ |
||
| 658 | /* Disable ALL DMA IT */ |
||
| 659 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
||
| 660 | |||
| 661 | /* Clear all flags */ |
||
| 662 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||
| 663 | |||
| 664 | /* Update error code */ |
||
| 665 | hdma->ErrorCode = HAL_DMA_ERROR_TE; |
||
| 666 | |||
| 667 | /* Change the DMA state */ |
||
| 668 | hdma->State = HAL_DMA_STATE_READY; |
||
| 669 | |||
| 670 | /* Process Unlocked */ |
||
| 671 | __HAL_UNLOCK(hdma); |
||
| 672 | |||
| 673 | if (hdma->XferErrorCallback != NULL) |
||
| 674 | { |
||
| 675 | /* Transfer error callback */ |
||
| 676 | hdma->XferErrorCallback(hdma); |
||
| 677 | } |
||
| 678 | } |
||
| 679 | return; |
||
| 680 | } |
||
| 681 | |||
| 682 | /** |
||
| 683 | * @brief Register callbacks |
||
| 684 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
| 685 | * the configuration information for the specified DMA Channel. |
||
| 686 | * @param CallbackID: User Callback identifier |
||
| 687 | * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||
| 688 | * @param pCallback: pointer to private callback function which has pointer to |
||
| 689 | * a DMA_HandleTypeDef structure as parameter. |
||
| 690 | * @retval HAL status |
||
| 691 | */ |
||
| 692 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) |
||
| 693 | { |
||
| 694 | HAL_StatusTypeDef status = HAL_OK; |
||
| 695 | |||
| 696 | /* Process locked */ |
||
| 697 | __HAL_LOCK(hdma); |
||
| 698 | |||
| 699 | if(HAL_DMA_STATE_READY == hdma->State) |
||
| 700 | { |
||
| 701 | switch (CallbackID) |
||
| 702 | { |
||
| 703 | case HAL_DMA_XFER_CPLT_CB_ID: |
||
| 704 | hdma->XferCpltCallback = pCallback; |
||
| 705 | break; |
||
| 706 | |||
| 707 | case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||
| 708 | hdma->XferHalfCpltCallback = pCallback; |
||
| 709 | break; |
||
| 710 | |||
| 711 | case HAL_DMA_XFER_ERROR_CB_ID: |
||
| 712 | hdma->XferErrorCallback = pCallback; |
||
| 713 | break; |
||
| 714 | |||
| 715 | case HAL_DMA_XFER_ABORT_CB_ID: |
||
| 716 | hdma->XferAbortCallback = pCallback; |
||
| 717 | break; |
||
| 718 | |||
| 719 | default: |
||
| 720 | status = HAL_ERROR; |
||
| 721 | break; |
||
| 722 | } |
||
| 723 | } |
||
| 724 | else |
||
| 725 | { |
||
| 726 | status = HAL_ERROR; |
||
| 727 | } |
||
| 728 | |||
| 729 | /* Release Lock */ |
||
| 730 | __HAL_UNLOCK(hdma); |
||
| 731 | |||
| 732 | return status; |
||
| 733 | } |
||
| 734 | |||
| 735 | /** |
||
| 736 | * @brief UnRegister callbacks |
||
| 737 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
| 738 | * the configuration information for the specified DMA Channel. |
||
| 739 | * @param CallbackID: User Callback identifier |
||
| 740 | * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||
| 741 | * @retval HAL status |
||
| 742 | */ |
||
| 743 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) |
||
| 744 | { |
||
| 745 | HAL_StatusTypeDef status = HAL_OK; |
||
| 746 | |||
| 747 | /* Process locked */ |
||
| 748 | __HAL_LOCK(hdma); |
||
| 749 | |||
| 750 | if(HAL_DMA_STATE_READY == hdma->State) |
||
| 751 | { |
||
| 752 | switch (CallbackID) |
||
| 753 | { |
||
| 754 | case HAL_DMA_XFER_CPLT_CB_ID: |
||
| 755 | hdma->XferCpltCallback = NULL; |
||
| 756 | break; |
||
| 757 | |||
| 758 | case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||
| 759 | hdma->XferHalfCpltCallback = NULL; |
||
| 760 | break; |
||
| 761 | |||
| 762 | case HAL_DMA_XFER_ERROR_CB_ID: |
||
| 763 | hdma->XferErrorCallback = NULL; |
||
| 764 | break; |
||
| 765 | |||
| 766 | case HAL_DMA_XFER_ABORT_CB_ID: |
||
| 767 | hdma->XferAbortCallback = NULL; |
||
| 768 | break; |
||
| 769 | |||
| 770 | case HAL_DMA_XFER_ALL_CB_ID: |
||
| 771 | hdma->XferCpltCallback = NULL; |
||
| 772 | hdma->XferHalfCpltCallback = NULL; |
||
| 773 | hdma->XferErrorCallback = NULL; |
||
| 774 | hdma->XferAbortCallback = NULL; |
||
| 775 | break; |
||
| 776 | |||
| 777 | default: |
||
| 778 | status = HAL_ERROR; |
||
| 779 | break; |
||
| 780 | } |
||
| 781 | } |
||
| 782 | else |
||
| 783 | { |
||
| 784 | status = HAL_ERROR; |
||
| 785 | } |
||
| 786 | |||
| 787 | /* Release Lock */ |
||
| 788 | __HAL_UNLOCK(hdma); |
||
| 789 | |||
| 790 | return status; |
||
| 791 | } |
||
| 792 | |||
| 793 | /** |
||
| 794 | * @} |
||
| 795 | */ |
||
| 796 | |||
| 797 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions |
||
| 798 | * @brief Peripheral State and Errors functions |
||
| 799 | * |
||
| 800 | @verbatim |
||
| 801 | =============================================================================== |
||
| 802 | ##### Peripheral State and Errors functions ##### |
||
| 803 | =============================================================================== |
||
| 804 | [..] |
||
| 805 | This subsection provides functions allowing to |
||
| 806 | (+) Check the DMA state |
||
| 807 | (+) Get error code |
||
| 808 | |||
| 809 | @endverbatim |
||
| 810 | * @{ |
||
| 811 | */ |
||
| 812 | |||
| 813 | /** |
||
| 814 | * @brief Return the DMA handle state. |
||
| 815 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
| 816 | * the configuration information for the specified DMA Channel. |
||
| 817 | * @retval HAL state |
||
| 818 | */ |
||
| 819 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) |
||
| 820 | { |
||
| 821 | /* Return DMA handle state */ |
||
| 822 | return hdma->State; |
||
| 823 | } |
||
| 824 | |||
| 825 | /** |
||
| 826 | * @brief Return the DMA error code. |
||
| 827 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
||
| 828 | * the configuration information for the specified DMA Channel. |
||
| 829 | * @retval DMA Error Code |
||
| 830 | */ |
||
| 831 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) |
||
| 832 | { |
||
| 833 | return hdma->ErrorCode; |
||
| 834 | } |
||
| 835 | |||
| 836 | /** |
||
| 837 | * @} |
||
| 838 | */ |
||
| 839 | |||
| 840 | /** |
||
| 841 | * @} |
||
| 842 | */ |
||
| 843 | |||
| 844 | /** @addtogroup DMA_Private_Functions |
||
| 845 | * @{ |
||
| 846 | */ |
||
| 847 | |||
| 848 | /** |
||
| 849 | * @brief Sets the DMA Transfer parameter. |
||
| 850 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
| 851 | * the configuration information for the specified DMA Channel. |
||
| 852 | * @param SrcAddress: The source memory Buffer address |
||
| 853 | * @param DstAddress: The destination memory Buffer address |
||
| 854 | * @param DataLength: The length of data to be transferred from source to destination |
||
| 855 | * @retval HAL status |
||
| 856 | */ |
||
| 857 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||
| 858 | { |
||
| 859 | /* Clear all flags */ |
||
| 860 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||
| 861 | |||
| 862 | /* Configure DMA Channel data length */ |
||
| 863 | hdma->Instance->CNDTR = DataLength; |
||
| 864 | |||
| 865 | /* Memory to Peripheral */ |
||
| 866 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) |
||
| 867 | { |
||
| 868 | /* Configure DMA Channel destination address */ |
||
| 869 | hdma->Instance->CPAR = DstAddress; |
||
| 870 | |||
| 871 | /* Configure DMA Channel source address */ |
||
| 872 | hdma->Instance->CMAR = SrcAddress; |
||
| 873 | } |
||
| 874 | /* Peripheral to Memory */ |
||
| 875 | else |
||
| 876 | { |
||
| 877 | /* Configure DMA Channel source address */ |
||
| 878 | hdma->Instance->CPAR = SrcAddress; |
||
| 879 | |||
| 880 | /* Configure DMA Channel destination address */ |
||
| 881 | hdma->Instance->CMAR = DstAddress; |
||
| 882 | } |
||
| 883 | } |
||
| 884 | |||
| 885 | /** |
||
| 886 | * @} |
||
| 887 | */ |
||
| 888 | |||
| 889 | #endif /* HAL_DMA_MODULE_ENABLED */ |
||
| 890 | /** |
||
| 891 | * @} |
||
| 892 | */ |
||
| 893 | |||
| 894 | /** |
||
| 895 | * @} |
||
| 896 | */ |
||
| 897 |