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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_cec.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V1.0.1 |
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| 6 | * @date 31-July-2015 |
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| 7 | * @brief CEC HAL module driver. |
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| 8 | * This file provides firmware functions to manage the following |
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| 9 | * functionalities of the High Definition Multimedia Interface |
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| 10 | * Consumer Electronics Control Peripheral (CEC). |
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| 11 | * + Initialization and de-initialization functions |
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| 12 | * + IO operation functions |
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| 13 | * + Peripheral Control functions |
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| 14 | * |
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| 15 | * @verbatim |
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| 16 | ============================================================================== |
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| 17 | ##### How to use this driver ##### |
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| 18 | ============================================================================== |
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| 19 | [..] |
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| 20 | The CEC HAL driver can be used as follows: |
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| 21 | (#) Declare a CEC_HandleTypeDef handle structure. |
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| 22 | (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API: |
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| 23 | (##) Enable the CEC interface clock. |
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| 24 | (##) Enable the clock for the CEC GPIOs. |
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| 25 | (##) Configure these CEC pins as alternate function pull-up. |
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| 26 | (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT() |
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| 27 | and HAL_CEC_Receive_IT() APIs): |
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| 28 | (##) Configure the CEC interrupt priority. |
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| 29 | (##) Enable the NVIC CEC IRQ handle. |
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| 30 | (##) The CEC interrupt is activated/deactivated by the HAL driver |
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| 31 | |||
| 32 | (#) Program the Bit Timing Error Mode and the Bit Period Error Mode in the hcec Init structure. |
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| 33 | |||
| 34 | (#) Initialize the CEC registers by calling the HAL_CEC_Init() API. |
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| 35 | |||
| 36 | (#) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) |
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| 37 | by calling the customized HAL_CEC_MspInit() API. |
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| 38 | |||
| 39 | @endverbatim |
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| 40 | ****************************************************************************** |
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| 41 | * @attention |
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| 42 | * |
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| 43 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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| 44 | * |
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| 45 | * Redistribution and use in source and binary forms, with or without modification, |
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| 46 | * are permitted provided that the following conditions are met: |
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| 47 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 48 | * this list of conditions and the following disclaimer. |
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| 49 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 50 | * this list of conditions and the following disclaimer in the documentation |
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| 51 | * and/or other materials provided with the distribution. |
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| 52 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 53 | * may be used to endorse or promote products derived from this software |
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| 54 | * without specific prior written permission. |
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| 55 | * |
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| 56 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 57 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 58 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 59 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 60 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 61 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 62 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 63 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 64 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 65 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 66 | * |
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| 67 | ****************************************************************************** |
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| 68 | */ |
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| 69 | |||
| 70 | /* Includes ------------------------------------------------------------------*/ |
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| 71 | #include "stm32f1xx_hal.h" |
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| 72 | |||
| 73 | #ifdef HAL_CEC_MODULE_ENABLED |
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| 74 | |||
| 75 | #if defined(STM32F100xB) || defined(STM32F100xE) |
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| 76 | |||
| 77 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 78 | * @{ |
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| 79 | */ |
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| 80 | |||
| 81 | /** @defgroup CEC CEC |
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| 82 | * @brief HAL CEC module driver |
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| 83 | * @{ |
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| 84 | */ |
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| 85 | |||
| 86 | /* Private typedef -----------------------------------------------------------*/ |
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| 87 | /* Private define ------------------------------------------------------------*/ |
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| 88 | /** @defgroup CEC_Private_Constants CEC Private Constants |
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| 89 | * @{ |
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| 90 | */ |
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| 91 | #define CEC_CFGR_FIELDS (CEC_CFGR_BTEM | CEC_CFGR_BPEM ) |
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| 92 | #define CEC_FLAG_TRANSMIT_MASK (CEC_FLAG_TSOM|CEC_FLAG_TEOM|CEC_FLAG_TBTRF) |
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| 93 | #define CEC_FLAG_RECEIVE_MASK (CEC_FLAG_RSOM|CEC_FLAG_REOM|CEC_FLAG_RBTF) |
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| 94 | #define CEC_ESR_ALL_ERROR (CEC_ESR_BTE|CEC_ESR_BPE|CEC_ESR_RBTFE|CEC_ESR_SBE|CEC_ESR_ACKE|CEC_ESR_LINE|CEC_ESR_TBTFE) |
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| 95 | #define CEC_RXXFERSIZE_INITIALIZE 0xFFFF /*!< Value used to initialise the RxXferSize of the handle */ |
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| 96 | /** |
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| 97 | * @} |
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| 98 | */ |
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| 99 | |||
| 100 | /* Private macro -------------------------------------------------------------*/ |
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| 101 | /* Private variables ---------------------------------------------------------*/ |
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| 102 | /* Private function prototypes -----------------------------------------------*/ |
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| 103 | /** @defgroup CEC_Private_Functions CEC Private Functions |
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| 104 | * @{ |
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| 105 | */ |
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| 106 | static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec); |
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| 107 | static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); |
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| 108 | /** |
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| 109 | * @} |
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| 110 | */ |
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| 111 | |||
| 112 | /* Exported functions ---------------------------------------------------------*/ |
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| 113 | |||
| 114 | /** @defgroup CEC_Exported_Functions CEC Exported Functions |
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| 115 | * @{ |
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| 116 | */ |
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| 117 | |||
| 118 | /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 119 | * @brief Initialization and Configuration functions |
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| 120 | * |
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| 121 | @verbatim |
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| 122 | =============================================================================== |
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| 123 | ##### Initialization and Configuration functions ##### |
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| 124 | =============================================================================== |
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| 125 | [..] |
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| 126 | This subsection provides a set of functions allowing to initialize the CEC |
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| 127 | (+) The following parameters need to be configured: |
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| 128 | (++) TimingErrorFree |
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| 129 | (++) PeriodErrorFree |
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| 130 | (++) InitiatorAddress |
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| 131 | |||
| 132 | @endverbatim |
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| 133 | * @{ |
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| 134 | */ |
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| 135 | |||
| 136 | /** |
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| 137 | * @brief Initializes the CEC mode according to the specified |
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| 138 | * parameters in the CEC_InitTypeDef and creates the associated handle . |
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| 139 | * @param hcec: CEC handle |
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| 140 | * @retval HAL status |
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| 141 | */ |
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| 142 | HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) |
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| 143 | { |
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| 144 | /* Check the CEC handle allocation */ |
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| 145 | if(hcec == NULL) |
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| 146 | { |
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| 147 | return HAL_ERROR; |
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| 148 | } |
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| 149 | |||
| 150 | /* Check the parameters */ |
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| 151 | assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); |
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| 152 | assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(hcec->Init.TimingErrorFree)); |
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| 153 | assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(hcec->Init.PeriodErrorFree)); |
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| 154 | assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress)); |
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| 155 | |||
| 156 | if(hcec->State == HAL_CEC_STATE_RESET) |
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| 157 | { |
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| 158 | /* Allocate lock resource and initialize it */ |
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| 159 | hcec->Lock = HAL_UNLOCKED; |
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| 160 | /* Init the low level hardware : GPIO, CLOCK */ |
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| 161 | HAL_CEC_MspInit(hcec); |
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| 162 | } |
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| 163 | |||
| 164 | hcec->State = HAL_CEC_STATE_BUSY; |
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| 165 | |||
| 166 | /* Disable the Peripheral */ |
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| 167 | __HAL_CEC_DISABLE(hcec); |
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| 168 | |||
| 169 | /* Write to CEC Control Register */ |
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| 170 | MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree|hcec->Init.PeriodErrorFree); |
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| 171 | |||
| 172 | /* Write to CEC Own Address Register */ |
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| 173 | MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.InitiatorAddress); |
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| 174 | |||
| 175 | /* Configure the prescaler to generate the required 50 microseconds time base.*/ |
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| 176 | MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50*(HAL_RCC_GetPCLK1Freq()/1000000)-1); |
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| 177 | |||
| 178 | /* Enable the Peripheral */ |
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| 179 | __HAL_CEC_ENABLE(hcec); |
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| 180 | |||
| 181 | hcec->State = HAL_CEC_STATE_READY; |
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| 182 | |||
| 183 | return HAL_OK; |
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| 184 | } |
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| 185 | |||
| 186 | |||
| 187 | |||
| 188 | /** |
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| 189 | * @brief DeInitializes the CEC peripheral |
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| 190 | * @param hcec: CEC handle |
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| 191 | * @retval HAL status |
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| 192 | */ |
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| 193 | HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) |
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| 194 | { |
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| 195 | /* Check the CEC handle allocation */ |
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| 196 | if(hcec == NULL) |
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| 197 | { |
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| 198 | return HAL_ERROR; |
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| 199 | } |
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| 200 | |||
| 201 | /* Check the parameters */ |
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| 202 | assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); |
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| 203 | |||
| 204 | hcec->State = HAL_CEC_STATE_BUSY; |
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| 205 | |||
| 206 | /* Set peripheral to reset state */ |
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| 207 | hcec->Instance->CFGR = 0x0; |
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| 208 | hcec->Instance->OAR = 0x0; |
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| 209 | hcec->Instance->PRES = 0x0; |
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| 210 | hcec->Instance->CFGR = 0x0; |
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| 211 | hcec->Instance->ESR = 0x0; |
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| 212 | hcec->Instance->CSR = 0x0; |
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| 213 | hcec->Instance->TXD = 0x0; |
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| 214 | hcec->Instance->RXD = 0x0; |
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| 215 | |||
| 216 | /* Disable the Peripheral */ |
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| 217 | __HAL_CEC_DISABLE(hcec); |
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| 218 | |||
| 219 | /* DeInit the low level hardware */ |
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| 220 | HAL_CEC_MspDeInit(hcec); |
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| 221 | |||
| 222 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
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| 223 | hcec->State = HAL_CEC_STATE_RESET; |
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| 224 | |||
| 225 | /* Process Unlock */ |
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| 226 | __HAL_UNLOCK(hcec); |
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| 227 | |||
| 228 | return HAL_OK; |
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| 229 | } |
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| 230 | |||
| 231 | /** |
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| 232 | * @brief CEC MSP Init |
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| 233 | * @param hcec: CEC handle |
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| 234 | * @retval None |
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| 235 | */ |
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| 236 | __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) |
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| 237 | { |
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| 238 | /* NOTE : This function should not be modified, when the callback is needed, |
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| 239 | the HAL_CEC_MspInit can be implemented in the user file |
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| 240 | */ |
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| 241 | } |
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| 242 | |||
| 243 | /** |
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| 244 | * @brief CEC MSP DeInit |
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| 245 | * @param hcec: CEC handle |
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| 246 | * @retval None |
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| 247 | */ |
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| 248 | __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) |
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| 249 | { |
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| 250 | /* NOTE : This function should not be modified, when the callback is needed, |
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| 251 | the HAL_CEC_MspDeInit can be implemented in the user file |
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| 252 | */ |
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| 253 | } |
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| 254 | |||
| 255 | /** |
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| 256 | * @} |
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| 257 | */ |
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| 258 | |||
| 259 | /** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions |
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| 260 | * @brief CEC Transmit/Receive functions |
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| 261 | * |
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| 262 | @verbatim |
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| 263 | =============================================================================== |
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| 264 | ##### IO operation functions ##### |
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| 265 | =============================================================================== |
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| 266 | [..] |
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| 267 | This subsection provides a set of functions allowing to manage the CEC data transfers. |
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| 268 | |||
| 269 | (#) There are two modes of transfer: |
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| 270 | (##) Blocking mode: The communication is performed in polling mode. |
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| 271 | The HAL status of all data processing is returned by the same function |
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| 272 | after finishing transfer. |
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| 273 | (##) No-Blocking mode: The communication is performed using Interrupts. |
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| 274 | These API's return the HAL status. |
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| 275 | The end of the data processing will be indicated through the |
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| 276 | dedicated CEC IRQ when using Interrupt mode. |
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| 277 | The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks |
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| 278 | will be executed respectivelly at the end of the Transmit or Receive process. |
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| 279 | The HAL_CEC_ErrorCallback()user callback will be executed when a communication |
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| 280 | error is detected |
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| 281 | (#) Blocking mode API's are : |
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| 282 | (##) HAL_CEC_Transmit() |
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| 283 | (##) HAL_CEC_Receive() |
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| 284 | (#) Non-Blocking mode API's with Interrupt are : |
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| 285 | (##) HAL_CEC_Transmit_IT() |
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| 286 | (##) HAL_CEC_Receive_IT() |
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| 287 | (##) HAL_CEC_IRQHandler() |
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| 288 | (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: |
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| 289 | (##) HAL_CEC_TxCpltCallback() |
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| 290 | (##) HAL_CEC_RxCpltCallback() |
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| 291 | (##) HAL_CEC_ErrorCallback() |
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| 292 | |||
| 293 | @endverbatim |
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| 294 | * @{ |
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| 295 | */ |
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| 296 | |||
| 297 | /** |
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| 298 | * @brief Send data in blocking mode |
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| 299 | * @param hcec: CEC handle |
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| 300 | * @param DestinationAddress: destination logical address |
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| 301 | * @param pData: pointer to input byte data buffer |
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| 302 | * @param Size: amount of data to be sent in bytes (without counting the header). |
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| 303 | * 0 means only the header is sent (ping operation). |
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| 304 | * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). |
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| 305 | * @param Timeout: Timeout duration. |
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| 306 | * @retval HAL status |
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| 307 | */ |
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| 308 | HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout) |
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| 309 | { |
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| 310 | uint8_t temp = 0; |
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| 311 | uint32_t tickstart = 0; |
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| 312 | |||
| 313 | /* If the IP is ready */ |
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| 314 | if((hcec->State == HAL_CEC_STATE_READY) |
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| 315 | && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) |
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| 316 | { |
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| 317 | /* Basic check on pData pointer */ |
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| 318 | if(((pData == NULL) && (Size > 0)) || (! IS_CEC_MSGSIZE(Size))) |
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| 319 | { |
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| 320 | return HAL_ERROR; |
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| 321 | } |
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| 322 | |||
| 323 | assert_param(IS_CEC_ADDRESS(DestinationAddress)); |
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| 324 | |||
| 325 | /* Process Locked */ |
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| 326 | __HAL_LOCK(hcec); |
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| 327 | |||
| 328 | /* Enter the transmit mode */ |
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| 329 | hcec->State = HAL_CEC_STATE_BUSY_TX; |
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| 330 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
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| 331 | |||
| 332 | /* Initialize the number of bytes to send, |
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| 333 | * 0 means only one header is sent (ping operation) */ |
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| 334 | hcec->TxXferCount = Size; |
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| 335 | |||
| 336 | /* Send header block */ |
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| 337 | temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress; |
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| 338 | hcec->Instance->TXD = temp; |
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| 339 | |||
| 340 | /* In case no data to be sent, sender is only pinging the system */ |
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| 341 | if (Size != 0) |
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| 342 | { |
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| 343 | /* Set TX Start of Message (TXSOM) bit */ |
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| 344 | hcec->Instance->CSR = CEC_FLAG_TSOM; |
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| 345 | } |
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| 346 | else |
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| 347 | { |
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| 348 | /* Send a ping command */ |
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| 349 | hcec->Instance->CSR = CEC_FLAG_TEOM|CEC_FLAG_TSOM; |
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| 350 | } |
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| 351 | |||
| 352 | /* Polling TBTRF bit with timeout handling*/ |
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| 353 | while (hcec->TxXferCount > 0) |
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| 354 | { |
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| 355 | /* Decreasing of the number of remaining data to receive */ |
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| 356 | hcec->TxXferCount--; |
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| 357 | |||
| 358 | /* Timeout handling */ |
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| 359 | tickstart = HAL_GetTick(); |
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| 360 | |||
| 361 | /* Waiting for the next data transmission */ |
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| 362 | while(HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF)) |
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| 363 | { |
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| 364 | /* Timeout handling */ |
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| 365 | if(Timeout != HAL_MAX_DELAY) |
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| 366 | { |
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| 367 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
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| 368 | { |
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| 369 | hcec->State = HAL_CEC_STATE_READY; |
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| 370 | /* Process Unlocked */ |
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| 371 | __HAL_UNLOCK(hcec); |
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| 372 | return HAL_TIMEOUT; |
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| 373 | } |
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| 374 | } |
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| 375 | |||
| 376 | /* Check if an error occured */ |
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| 377 | if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) |
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| 378 | { |
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| 379 | /* Copy ESR for error handling purposes */ |
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| 380 | hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); |
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| 381 | |||
| 382 | /* Acknowledgement of the error */ |
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| 383 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); |
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| 384 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); |
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| 385 | |||
| 386 | hcec->State = HAL_CEC_STATE_READY; |
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| 387 | __HAL_UNLOCK(hcec); |
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| 388 | return HAL_ERROR; |
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| 389 | } |
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| 390 | } |
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| 391 | |||
| 392 | /* Write the next data to TX buffer */ |
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| 393 | hcec->Instance->TXD = *pData++; |
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| 394 | |||
| 395 | /* If this is the last byte of the ongoing transmission */ |
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| 396 | if (hcec->TxXferCount == 0) |
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| 397 | { |
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| 398 | /* Acknowledge byte request and signal end of message */ |
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| 399 | MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM); |
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| 400 | } |
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| 401 | else |
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| 402 | { |
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| 403 | /* Acknowledge byte request by writing 0x00 */ |
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| 404 | MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); |
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| 405 | } |
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| 406 | } |
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| 407 | |||
| 408 | /* Timeout handling */ |
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| 409 | tickstart = HAL_GetTick(); |
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| 410 | |||
| 411 | /* Wait for message transmission completion (TBTRF is set) */ |
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| 412 | while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF)) |
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| 413 | { |
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| 414 | /* Timeout handling */ |
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| 415 | if(Timeout != HAL_MAX_DELAY) |
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| 416 | { |
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| 417 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
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| 418 | { |
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| 419 | hcec->State = HAL_CEC_STATE_READY; |
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| 420 | __HAL_UNLOCK(hcec); |
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| 421 | return HAL_TIMEOUT; |
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| 422 | } |
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| 423 | } |
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| 424 | |||
| 425 | /* Check of error during transmission of the last byte */ |
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| 426 | if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) |
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| 427 | { |
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| 428 | /* Copy ESR for error handling purposes */ |
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| 429 | hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); |
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| 430 | |||
| 431 | /* Acknowledgement of the error */ |
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| 432 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); |
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| 433 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); |
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| 434 | |||
| 435 | hcec->State = HAL_CEC_STATE_READY; |
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| 436 | __HAL_UNLOCK(hcec); |
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| 437 | return HAL_ERROR; |
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| 438 | } |
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| 439 | } |
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| 440 | |||
| 441 | /* Check of error after the last byte transmission */ |
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| 442 | if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) |
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| 443 | { |
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| 444 | /* Copy ESR for error handling purposes */ |
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| 445 | hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); |
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| 446 | |||
| 447 | /* Acknowledgement of the error */ |
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| 448 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); |
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| 449 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); |
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| 450 | |||
| 451 | hcec->State = HAL_CEC_STATE_READY; |
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| 452 | __HAL_UNLOCK(hcec); |
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| 453 | return HAL_ERROR; |
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| 454 | } |
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| 455 | |||
| 456 | /* Acknowledge successful completion by writing 0x00 */ |
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| 457 | MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); |
||
| 458 | |||
| 459 | hcec->State = HAL_CEC_STATE_READY; |
||
| 460 | __HAL_UNLOCK(hcec); |
||
| 461 | |||
| 462 | return HAL_OK; |
||
| 463 | } |
||
| 464 | else |
||
| 465 | { |
||
| 466 | return HAL_BUSY; |
||
| 467 | } |
||
| 468 | } |
||
| 469 | |||
| 470 | /** |
||
| 471 | * @brief Receive data in blocking mode. |
||
| 472 | * @param hcec: CEC handle |
||
| 473 | * @param pData: pointer to received data buffer. |
||
| 474 | * @param Timeout: Timeout duration. |
||
| 475 | * @note The received data size is not known beforehand, the latter is known |
||
| 476 | * when the reception is complete and is stored in hcec->RxXferSize. |
||
| 477 | * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). |
||
| 478 | * If only a header is received, hcec->RxXferSize = 0 |
||
| 479 | * @retval HAL status |
||
| 480 | */ |
||
| 481 | HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout) |
||
| 482 | { |
||
| 483 | uint32_t temp = 0; |
||
| 484 | uint32_t tickstart = 0; |
||
| 485 | |||
| 486 | if(hcec->State == HAL_CEC_STATE_READY) |
||
| 487 | { |
||
| 488 | if(pData == NULL) |
||
| 489 | { |
||
| 490 | return HAL_ERROR; |
||
| 491 | } |
||
| 492 | |||
| 493 | /* When a ping is received, RxXferSize is 0*/ |
||
| 494 | /* When a message is received, RxXferSize contains the number of received bytes */ |
||
| 495 | hcec->RxXferSize = CEC_RXXFERSIZE_INITIALIZE; |
||
| 496 | |||
| 497 | /* Process Locked */ |
||
| 498 | __HAL_LOCK(hcec); |
||
| 499 | |||
| 500 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
||
| 501 | |||
| 502 | /* Continue the reception until the End Of Message is received (CEC_FLAG_REOM) */ |
||
| 503 | do |
||
| 504 | { |
||
| 505 | /* Timeout handling */ |
||
| 506 | tickstart = HAL_GetTick(); |
||
| 507 | |||
| 508 | /* Wait for next byte to be received */ |
||
| 509 | while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_RBTF)) |
||
| 510 | { |
||
| 511 | /* Timeout handling */ |
||
| 512 | if(Timeout != HAL_MAX_DELAY) |
||
| 513 | { |
||
| 514 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
||
| 515 | { |
||
| 516 | hcec->State = HAL_CEC_STATE_READY; |
||
| 517 | __HAL_UNLOCK(hcec); |
||
| 518 | return HAL_TIMEOUT; |
||
| 519 | } |
||
| 520 | } |
||
| 521 | |||
| 522 | /* Check if an error occured during the reception */ |
||
| 523 | if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) |
||
| 524 | { |
||
| 525 | /* Copy ESR for error handling purposes */ |
||
| 526 | hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); |
||
| 527 | |||
| 528 | /* Acknowledgement of the error */ |
||
| 529 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); |
||
| 530 | |||
| 531 | hcec->State = HAL_CEC_STATE_READY; |
||
| 532 | __HAL_UNLOCK(hcec); |
||
| 533 | return HAL_ERROR; |
||
| 534 | } |
||
| 535 | } |
||
| 536 | |||
| 537 | /* Keep the value of CSR register as the register is cleared during reception process */ |
||
| 538 | temp = hcec->Instance->CSR; |
||
| 539 | |||
| 540 | /* Read received data */ |
||
| 541 | *pData++ = hcec->Instance->RXD; |
||
| 542 | |||
| 543 | /* Acknowledge received byte by writing 0x00 */ |
||
| 544 | CLEAR_BIT(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK); |
||
| 545 | |||
| 546 | /* Increment the number of received data */ |
||
| 547 | if(hcec->RxXferSize == CEC_RXXFERSIZE_INITIALIZE) |
||
| 548 | { |
||
| 549 | hcec->RxXferSize = 0; |
||
| 550 | } |
||
| 551 | else |
||
| 552 | { |
||
| 553 | hcec->RxXferSize++; |
||
| 554 | } |
||
| 555 | |||
| 556 | }while (HAL_IS_BIT_CLR(temp, CEC_FLAG_REOM)); |
||
| 557 | |||
| 558 | hcec->State = HAL_CEC_STATE_READY; |
||
| 559 | __HAL_UNLOCK(hcec); |
||
| 560 | |||
| 561 | if(IS_CEC_MSGSIZE(hcec->RxXferSize)) |
||
| 562 | { |
||
| 563 | return HAL_OK; |
||
| 564 | } |
||
| 565 | else |
||
| 566 | { |
||
| 567 | return HAL_ERROR; |
||
| 568 | } |
||
| 569 | } |
||
| 570 | else |
||
| 571 | { |
||
| 572 | return HAL_BUSY; |
||
| 573 | } |
||
| 574 | } |
||
| 575 | |||
| 576 | |||
| 577 | /** |
||
| 578 | * @brief Send data in interrupt mode |
||
| 579 | * @param hcec: CEC handle |
||
| 580 | * @param DestinationAddress: destination logical address |
||
| 581 | * @param pData: pointer to input byte data buffer |
||
| 582 | * @param Size: amount of data to be sent in bytes (without counting the header). |
||
| 583 | * 0 means only the header is sent (ping operation). |
||
| 584 | * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). |
||
| 585 | * @retval HAL status |
||
| 586 | */ |
||
| 587 | HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) |
||
| 588 | { |
||
| 589 | uint8_t temp = 0; |
||
| 590 | uint32_t tmp_state = 0; |
||
| 591 | |||
| 592 | tmp_state = hcec->State; |
||
| 593 | if(((tmp_state == HAL_CEC_STATE_READY) || (tmp_state == HAL_CEC_STATE_BUSY_RX)) |
||
| 594 | && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) |
||
| 595 | { |
||
| 596 | |||
| 597 | /* Basic check on pData pointer */ |
||
| 598 | if(((pData == NULL) && (Size > 0)) || (! IS_CEC_MSGSIZE(Size))) |
||
| 599 | { |
||
| 600 | return HAL_ERROR; |
||
| 601 | } |
||
| 602 | |||
| 603 | assert_param(IS_CEC_ADDRESS(DestinationAddress)); |
||
| 604 | |||
| 605 | /* Process Locked */ |
||
| 606 | __HAL_LOCK(hcec); |
||
| 607 | hcec->pTxBuffPtr = pData; |
||
| 608 | |||
| 609 | /* Check if a receive process is ongoing or not */ |
||
| 610 | if(hcec->State == HAL_CEC_STATE_BUSY_RX) |
||
| 611 | { |
||
| 612 | hcec->State = HAL_CEC_STATE_BUSY_TX_RX; |
||
| 613 | |||
| 614 | /* Interrupt are not enabled here because they are already enabled in the Reception process */ |
||
| 615 | } |
||
| 616 | else |
||
| 617 | { |
||
| 618 | hcec->State = HAL_CEC_STATE_BUSY_TX; |
||
| 619 | |||
| 620 | /* Enable the CEC interrupt */ |
||
| 621 | __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE); |
||
| 622 | } |
||
| 623 | |||
| 624 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
||
| 625 | |||
| 626 | /* initialize the number of bytes to send, |
||
| 627 | * 0 means only one header is sent (ping operation) */ |
||
| 628 | hcec->TxXferCount = Size; |
||
| 629 | |||
| 630 | /* send header block */ |
||
| 631 | temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress; |
||
| 632 | hcec->Instance->TXD = temp; |
||
| 633 | |||
| 634 | /* Process Unlocked */ |
||
| 635 | __HAL_UNLOCK(hcec); |
||
| 636 | |||
| 637 | /* case no data to be sent, sender is only pinging the system */ |
||
| 638 | if (Size != 0) |
||
| 639 | { |
||
| 640 | /* Set TX Start of Message (TXSOM) bit */ |
||
| 641 | MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TSOM); |
||
| 642 | } |
||
| 643 | else |
||
| 644 | { |
||
| 645 | /* Send a ping command */ |
||
| 646 | MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM|CEC_FLAG_TSOM); |
||
| 647 | } |
||
| 648 | return HAL_OK; |
||
| 649 | } |
||
| 650 | else |
||
| 651 | { |
||
| 652 | return HAL_BUSY; |
||
| 653 | } |
||
| 654 | } |
||
| 655 | |||
| 656 | |||
| 657 | /** |
||
| 658 | * @brief Receive data in interrupt mode. |
||
| 659 | * @param hcec: CEC handle |
||
| 660 | * @param pData: pointer to received data buffer. |
||
| 661 | * @note The received data size is not known beforehand, the latter is known |
||
| 662 | * when the reception is complete and is stored in hcec->RxXferSize. |
||
| 663 | * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). |
||
| 664 | * If only a header is received, hcec->RxXferSize = 0 |
||
| 665 | * @retval HAL status |
||
| 666 | */ |
||
| 667 | HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) |
||
| 668 | { |
||
| 669 | uint32_t tmp_state = 0; |
||
| 670 | tmp_state = hcec->State; |
||
| 671 | if((tmp_state == HAL_CEC_STATE_READY) || (tmp_state == HAL_CEC_STATE_BUSY_TX)) |
||
| 672 | { |
||
| 673 | if(pData == NULL) |
||
| 674 | { |
||
| 675 | return HAL_ERROR; |
||
| 676 | } |
||
| 677 | |||
| 678 | /* When a ping is received, RxXferSize is 0 */ |
||
| 679 | /* When a message is received, RxXferSize contains the number of received bytes */ |
||
| 680 | hcec->RxXferSize = CEC_RXXFERSIZE_INITIALIZE; |
||
| 681 | |||
| 682 | /* Process Locked */ |
||
| 683 | __HAL_LOCK(hcec); |
||
| 684 | |||
| 685 | hcec->pRxBuffPtr = pData; |
||
| 686 | hcec->ErrorCode = HAL_CEC_ERROR_NONE; |
||
| 687 | |||
| 688 | /* Process Unlocked */ |
||
| 689 | __HAL_UNLOCK(hcec); |
||
| 690 | |||
| 691 | /* Check if a transmit process is ongoing or not */ |
||
| 692 | if(hcec->State == HAL_CEC_STATE_BUSY_TX) |
||
| 693 | { |
||
| 694 | hcec->State = HAL_CEC_STATE_BUSY_TX_RX; |
||
| 695 | } |
||
| 696 | else |
||
| 697 | { |
||
| 698 | hcec->State = HAL_CEC_STATE_BUSY_RX; |
||
| 699 | |||
| 700 | /* Enable CEC interrupt */ |
||
| 701 | __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE); |
||
| 702 | } |
||
| 703 | |||
| 704 | return HAL_OK; |
||
| 705 | } |
||
| 706 | else |
||
| 707 | { |
||
| 708 | return HAL_BUSY; |
||
| 709 | } |
||
| 710 | } |
||
| 711 | |||
| 712 | /** |
||
| 713 | * @brief Get size of the received frame. |
||
| 714 | * @param hcec: CEC handle |
||
| 715 | * @retval Frame size |
||
| 716 | */ |
||
| 717 | uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec) |
||
| 718 | { |
||
| 719 | return hcec->RxXferSize; |
||
| 720 | } |
||
| 721 | |||
| 722 | /** |
||
| 723 | * @brief This function handles CEC interrupt requests. |
||
| 724 | * @param hcec: CEC handle |
||
| 725 | * @retval None |
||
| 726 | */ |
||
| 727 | void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) |
||
| 728 | { |
||
| 729 | /* Save error status register for further error handling purposes */ |
||
| 730 | hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); |
||
| 731 | |||
| 732 | /* Transmit error */ |
||
| 733 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TERR) != RESET)) |
||
| 734 | { |
||
| 735 | /* Acknowledgement of the error */ |
||
| 736 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); |
||
| 737 | |||
| 738 | /* Check if a receive process is ongoing or not */ |
||
| 739 | if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX) |
||
| 740 | { |
||
| 741 | /* Interrupts are not disabled due to reception still ongoing */ |
||
| 742 | |||
| 743 | hcec->State = HAL_CEC_STATE_BUSY_RX; |
||
| 744 | } |
||
| 745 | else |
||
| 746 | { |
||
| 747 | /* Disable the CEC Transmission Interrupts */ |
||
| 748 | __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE); |
||
| 749 | |||
| 750 | hcec->State = HAL_CEC_STATE_READY; |
||
| 751 | } |
||
| 752 | } |
||
| 753 | |||
| 754 | /* Receive error */ |
||
| 755 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RERR) != RESET)) |
||
| 756 | { |
||
| 757 | /* Acknowledgement of the error */ |
||
| 758 | __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); |
||
| 759 | |||
| 760 | /* Check if a transmit process is ongoing or not */ |
||
| 761 | if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX) |
||
| 762 | { |
||
| 763 | /* Interrupts are not disabled due to reception still ongoing */ |
||
| 764 | |||
| 765 | hcec->State = HAL_CEC_STATE_BUSY_TX; |
||
| 766 | } |
||
| 767 | else |
||
| 768 | { |
||
| 769 | /* Disable the CEC Transmission Interrupts */ |
||
| 770 | __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE); |
||
| 771 | |||
| 772 | hcec->State = HAL_CEC_STATE_READY; |
||
| 773 | } |
||
| 774 | } |
||
| 775 | |||
| 776 | if ((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0) |
||
| 777 | { |
||
| 778 | HAL_CEC_ErrorCallback(hcec); |
||
| 779 | } |
||
| 780 | |||
| 781 | /* Transmit byte request or block transfer finished */ |
||
| 782 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TBTRF) != RESET)) |
||
| 783 | { |
||
| 784 | CEC_Transmit_IT(hcec); |
||
| 785 | } |
||
| 786 | |||
| 787 | /* Receive byte or block transfer finished */ |
||
| 788 | if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RBTF) != RESET)) |
||
| 789 | { |
||
| 790 | CEC_Receive_IT(hcec); |
||
| 791 | } |
||
| 792 | } |
||
| 793 | |||
| 794 | |||
| 795 | /** |
||
| 796 | * @brief Tx Transfer completed callback |
||
| 797 | * @param hcec: CEC handle |
||
| 798 | * @retval None |
||
| 799 | */ |
||
| 800 | __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) |
||
| 801 | { |
||
| 802 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 803 | the HAL_CEC_TxCpltCallback can be implemented in the user file |
||
| 804 | */ |
||
| 805 | } |
||
| 806 | |||
| 807 | /** |
||
| 808 | * @brief Rx Transfer completed callback |
||
| 809 | * @param hcec: CEC handle |
||
| 810 | * @retval None |
||
| 811 | */ |
||
| 812 | __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) |
||
| 813 | { |
||
| 814 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 815 | the HAL_CEC_RxCpltCallback can be implemented in the user file |
||
| 816 | */ |
||
| 817 | } |
||
| 818 | |||
| 819 | /** |
||
| 820 | * @brief CEC error callbacks |
||
| 821 | * @param hcec: CEC handle |
||
| 822 | * @retval None |
||
| 823 | */ |
||
| 824 | __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) |
||
| 825 | { |
||
| 826 | /* NOTE : This function should not be modified, when the callback is needed, |
||
| 827 | the HAL_CEC_ErrorCallback can be implemented in the user file |
||
| 828 | */ |
||
| 829 | } |
||
| 830 | |||
| 831 | /** |
||
| 832 | * @} |
||
| 833 | */ |
||
| 834 | |||
| 835 | /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions |
||
| 836 | * @brief CEC control functions |
||
| 837 | * |
||
| 838 | @verbatim |
||
| 839 | =============================================================================== |
||
| 840 | ##### Peripheral Control functions ##### |
||
| 841 | =============================================================================== |
||
| 842 | [..] |
||
| 843 | This subsection provides a set of functions allowing to control the CEC. |
||
| 844 | (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. |
||
| 845 | (+) HAL_CEC_GetError() API can be helpful to get the error code of a failed transmission or reception. |
||
| 846 | @endverbatim |
||
| 847 | * @{ |
||
| 848 | */ |
||
| 849 | |||
| 850 | /** |
||
| 851 | * @brief return the CEC state |
||
| 852 | * @param hcec: CEC handle |
||
| 853 | * @retval HAL state |
||
| 854 | */ |
||
| 855 | HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) |
||
| 856 | { |
||
| 857 | return hcec->State; |
||
| 858 | } |
||
| 859 | |||
| 860 | /** |
||
| 861 | * @brief Return the CEC error code |
||
| 862 | * @param hcec : pointer to a CEC_HandleTypeDef structure that contains |
||
| 863 | * the configuration information for the specified CEC. |
||
| 864 | * @retval CEC Error Code |
||
| 865 | */ |
||
| 866 | uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) |
||
| 867 | { |
||
| 868 | return hcec->ErrorCode; |
||
| 869 | } |
||
| 870 | |||
| 871 | /** |
||
| 872 | * @} |
||
| 873 | */ |
||
| 874 | |||
| 875 | /** |
||
| 876 | * @} |
||
| 877 | */ |
||
| 878 | |||
| 879 | /** @addtogroup CEC_Private_Functions |
||
| 880 | * @{ |
||
| 881 | */ |
||
| 882 | |||
| 883 | /** |
||
| 884 | * @brief Send data in interrupt mode |
||
| 885 | * @param hcec: CEC handle. |
||
| 886 | * Function called under interruption only, once |
||
| 887 | * interruptions have been enabled by HAL_CEC_Transmit_IT() |
||
| 888 | * @retval HAL status |
||
| 889 | */ |
||
| 890 | static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) |
||
| 891 | { |
||
| 892 | uint32_t tmp_state = 0; |
||
| 893 | |||
| 894 | tmp_state = hcec->State; |
||
| 895 | /* if the IP is already busy or if there is a previous transmission |
||
| 896 | already pending due to arbitration loss */ |
||
| 897 | if(((tmp_state == HAL_CEC_STATE_BUSY_TX) || (tmp_state == HAL_CEC_STATE_BUSY_TX_RX)) |
||
| 898 | || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) |
||
| 899 | { |
||
| 900 | /* if all data have been sent */ |
||
| 901 | if(hcec->TxXferCount == 0) |
||
| 902 | { |
||
| 903 | /* Acknowledge successful completion by writing 0x00 */ |
||
| 904 | MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); |
||
| 905 | |||
| 906 | /* Check if a receive process is ongoing or not */ |
||
| 907 | if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX) |
||
| 908 | { |
||
| 909 | /* Interrupts are not disabled due to reception still ongoing */ |
||
| 910 | |||
| 911 | hcec->State = HAL_CEC_STATE_BUSY_RX; |
||
| 912 | } |
||
| 913 | else |
||
| 914 | { |
||
| 915 | /* Disable the CEC Transmission Interrupts */ |
||
| 916 | __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE); |
||
| 917 | |||
| 918 | hcec->State = HAL_CEC_STATE_READY; |
||
| 919 | } |
||
| 920 | |||
| 921 | HAL_CEC_TxCpltCallback(hcec); |
||
| 922 | |||
| 923 | return HAL_OK; |
||
| 924 | } |
||
| 925 | else |
||
| 926 | { |
||
| 927 | /* Reduce the number of bytes to transfer by one */ |
||
| 928 | hcec->TxXferCount--; |
||
| 929 | |||
| 930 | /* Write data to TX buffer*/ |
||
| 931 | hcec->Instance->TXD = *hcec->pTxBuffPtr++; |
||
| 932 | |||
| 933 | /* If this is the last byte of the ongoing transmission */ |
||
| 934 | if (hcec->TxXferCount == 0) |
||
| 935 | { |
||
| 936 | /* Acknowledge byte request and signal end of message */ |
||
| 937 | MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM); |
||
| 938 | } |
||
| 939 | else |
||
| 940 | { |
||
| 941 | /* Acknowledge byte request by writing 0x00 */ |
||
| 942 | MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); |
||
| 943 | } |
||
| 944 | |||
| 945 | return HAL_OK; |
||
| 946 | } |
||
| 947 | } |
||
| 948 | else |
||
| 949 | { |
||
| 950 | return HAL_BUSY; |
||
| 951 | } |
||
| 952 | } |
||
| 953 | |||
| 954 | /** |
||
| 955 | * @brief Receive data in interrupt mode. |
||
| 956 | * @param hcec: CEC handle. |
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| 957 | * Function called under interruption only, once |
||
| 958 | * interruptions have been enabled by HAL_CEC_Receive_IT() |
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| 959 | * @retval HAL status |
||
| 960 | */ |
||
| 961 | static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec) |
||
| 962 | { |
||
| 963 | static uint32_t temp; |
||
| 964 | uint32_t tmp_state = 0; |
||
| 965 | |||
| 966 | tmp_state = hcec->State; |
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| 967 | if((tmp_state == HAL_CEC_STATE_BUSY_RX) || (tmp_state == HAL_CEC_STATE_BUSY_TX_RX)) |
||
| 968 | { |
||
| 969 | temp = hcec->Instance->CSR; |
||
| 970 | |||
| 971 | /* Store received data */ |
||
| 972 | *hcec->pRxBuffPtr++ = hcec->Instance->RXD; |
||
| 973 | |||
| 974 | /* Acknowledge received byte by writing 0x00 */ |
||
| 975 | MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00); |
||
| 976 | |||
| 977 | /* Increment the number of received data */ |
||
| 978 | if(hcec->RxXferSize == CEC_RXXFERSIZE_INITIALIZE) |
||
| 979 | { |
||
| 980 | hcec->RxXferSize = 0; |
||
| 981 | } |
||
| 982 | else |
||
| 983 | { |
||
| 984 | hcec->RxXferSize++; |
||
| 985 | } |
||
| 986 | |||
| 987 | /* If the End Of Message is reached */ |
||
| 988 | if(HAL_IS_BIT_SET(temp, CEC_FLAG_REOM)) |
||
| 989 | { |
||
| 990 | if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX) |
||
| 991 | { |
||
| 992 | /* Interrupts are not disabled due to transmission still ongoing */ |
||
| 993 | |||
| 994 | hcec->State = HAL_CEC_STATE_BUSY_TX; |
||
| 995 | } |
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| 996 | else |
||
| 997 | { |
||
| 998 | /* Disable the CEC Transmission Interrupts */ |
||
| 999 | __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE); |
||
| 1000 | |||
| 1001 | hcec->State = HAL_CEC_STATE_READY; |
||
| 1002 | } |
||
| 1003 | |||
| 1004 | HAL_CEC_RxCpltCallback(hcec); |
||
| 1005 | |||
| 1006 | return HAL_OK; |
||
| 1007 | } |
||
| 1008 | else |
||
| 1009 | { |
||
| 1010 | return HAL_BUSY; |
||
| 1011 | } |
||
| 1012 | } |
||
| 1013 | else |
||
| 1014 | { |
||
| 1015 | return HAL_BUSY; |
||
| 1016 | } |
||
| 1017 | } |
||
| 1018 | |||
| 1019 | /** |
||
| 1020 | * @} |
||
| 1021 | */ |
||
| 1022 | |||
| 1023 | /** |
||
| 1024 | * @} |
||
| 1025 | */ |
||
| 1026 | |||
| 1027 | #endif /* defined(STM32F100xB) || defined(STM32F100xE) */ |
||
| 1028 | |||
| 1029 | #endif /* HAL_CEC_MODULE_ENABLED */ |
||
| 1030 | /** |
||
| 1031 | * @} |
||
| 1032 | */ |
||
| 1033 | |||
| 1034 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |