WebSVN – canSerial – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_adc.c
		4	* @author MCD Application Team
		5	* @brief This file provides firmware functions to manage the following
		6	* functionalities of the Analog to Digital Convertor (ADC)
		7	* peripheral:
		8	* + Initialization and de-initialization functions
		9	* ++ Initialization and Configuration of ADC
		10	* + Operation functions
		11	* ++ Start, stop, get result of conversions of regular
		12	* group, using 3 possible modes: polling, interruption or DMA.
		13	* + Control functions
		14	* ++ Channels configuration on regular group
		15	* ++ Channels configuration on injected group
		16	* ++ Analog Watchdog configuration
		17	* + State functions
		18	* ++ ADC state machine management
		19	* ++ Interrupts and flags management
		20	* Other functions (extended functions) are available in file
		21	* "stm32f1xx_hal_adc_ex.c".
		22	*
		23	@verbatim
		24	==============================================================================
		25	##### ADC peripheral features #####
		26	==============================================================================
		27	[..]
		28	(+) 12-bit resolution
		29
		30	(+) Interrupt generation at the end of regular conversion, end of injected
		31	conversion, and in case of analog watchdog or overrun events.
		32
		33	(+) Single and continuous conversion modes.
		34
		35	(+) Scan mode for conversion of several channels sequentially.
		36
		37	(+) Data alignment with in-built data coherency.
		38
		39	(+) Programmable sampling time (channel wise)
		40
		41	(+) ADC conversion of regular group and injected group.
		42
		43	(+) External trigger (timer or EXTI)
		44	for both regular and injected groups.
		45
		46	(+) DMA request generation for transfer of conversions data of regular group.
		47
		48	(+) Multimode Dual mode (available on devices with 2 ADCs or more).
		49
		50	(+) Configurable DMA data storage in Multimode Dual mode (available on devices
		51	with 2 DCs or more).
		52
		53	(+) Configurable delay between conversions in Dual interleaved mode (available
		54	on devices with 2 DCs or more).
		55
		56	(+) ADC calibration
		57
		58	(+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
		59	slower speed.
		60
		61	(+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
		62	Vdda or to an external voltage reference).
		63
		64
		65	##### How to use this driver #####
		66	==============================================================================
		67	[..]
		68
		69	* Configuration of top level parameters related to ADC *
		70	============================================================
		71	[..]
		72
		73	(#) Enable the ADC interface
		74	(++) As prerequisite, ADC clock must be configured at RCC top level.
		75	Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
		76	to device datasheet).
		77	Therefore, ADC clock prescaler must be configured in
		78	function of ADC clock source frequency to remain below
		79	this maximum frequency.
		80	(++) One clock setting is mandatory:
		81	ADC clock (core clock, also possibly conversion clock).
		82	(+++) Example:
		83	Into HAL_ADC_MspInit() (recommended code location) or with
		84	other device clock parameters configuration:
		85	(+++) RCC_PeriphCLKInitTypeDef PeriphClkInit;
		86	(+++) __ADC1_CLK_ENABLE();
		87	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
		88	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
		89	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
		90
		91	(#) ADC pins configuration
		92	(++) Enable the clock for the ADC GPIOs
		93	using macro __HAL_RCC_GPIOx_CLK_ENABLE()
		94	(++) Configure these ADC pins in analog mode
		95	using function HAL_GPIO_Init()
		96
		97	(#) Optionally, in case of usage of ADC with interruptions:
		98	(++) Configure the NVIC for ADC
		99	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
		100	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
		101	into the function of corresponding ADC interruption vector
		102	ADCx_IRQHandler().
		103
		104	(#) Optionally, in case of usage of DMA:
		105	(++) Configure the DMA (DMA channel, mode normal or circular, ...)
		106	using function HAL_DMA_Init().
		107	(++) Configure the NVIC for DMA
		108	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
		109	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
		110	into the function of corresponding DMA interruption vector
		111	DMAx_Channelx_IRQHandler().
		112
		113	* Configuration of ADC, groups regular/injected, channels parameters *
		114	==========================================================================
		115	[..]
		116
		117	(#) Configure the ADC parameters (resolution, data alignment, ...)
		118	and regular group parameters (conversion trigger, sequencer, ...)
		119	using function HAL_ADC_Init().
		120
		121	(#) Configure the channels for regular group parameters (channel number,
		122	channel rank into sequencer, ..., into regular group)
		123	using function HAL_ADC_ConfigChannel().
		124
		125	(#) Optionally, configure the injected group parameters (conversion trigger,
		126	sequencer, ..., of injected group)
		127	and the channels for injected group parameters (channel number,
		128	channel rank into sequencer, ..., into injected group)
		129	using function HAL_ADCEx_InjectedConfigChannel().
		130
		131	(#) Optionally, configure the analog watchdog parameters (channels
		132	monitored, thresholds, ...)
		133	using function HAL_ADC_AnalogWDGConfig().
		134
		135	(#) Optionally, for devices with several ADC instances: configure the
		136	multimode parameters
		137	using function HAL_ADCEx_MultiModeConfigChannel().
		138
		139	* Execution of ADC conversions *
		140	====================================
		141	[..]
		142
		143	(#) Optionally, perform an automatic ADC calibration to improve the
		144	conversion accuracy
		145	using function HAL_ADCEx_Calibration_Start().
		146
		147	(#) ADC driver can be used among three modes: polling, interruption,
		148	transfer by DMA.
		149
		150	(++) ADC conversion by polling:
		151	(+++) Activate the ADC peripheral and start conversions
		152	using function HAL_ADC_Start()
		153	(+++) Wait for ADC conversion completion
		154	using function HAL_ADC_PollForConversion()
		155	(or for injected group: HAL_ADCEx_InjectedPollForConversion() )
		156	(+++) Retrieve conversion results
		157	using function HAL_ADC_GetValue()
		158	(or for injected group: HAL_ADCEx_InjectedGetValue() )
		159	(+++) Stop conversion and disable the ADC peripheral
		160	using function HAL_ADC_Stop()
		161
		162	(++) ADC conversion by interruption:
		163	(+++) Activate the ADC peripheral and start conversions
		164	using function HAL_ADC_Start_IT()
		165	(+++) Wait for ADC conversion completion by call of function
		166	HAL_ADC_ConvCpltCallback()
		167	(this function must be implemented in user program)
		168	(or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
		169	(+++) Retrieve conversion results
		170	using function HAL_ADC_GetValue()
		171	(or for injected group: HAL_ADCEx_InjectedGetValue() )
		172	(+++) Stop conversion and disable the ADC peripheral
		173	using function HAL_ADC_Stop_IT()
		174
		175	(++) ADC conversion with transfer by DMA:
		176	(+++) Activate the ADC peripheral and start conversions
		177	using function HAL_ADC_Start_DMA()
		178	(+++) Wait for ADC conversion completion by call of function
		179	HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
		180	(these functions must be implemented in user program)
		181	(+++) Conversion results are automatically transferred by DMA into
		182	destination variable address.
		183	(+++) Stop conversion and disable the ADC peripheral
		184	using function HAL_ADC_Stop_DMA()
		185
		186	(++) For devices with several ADCs: ADC multimode conversion
		187	with transfer by DMA:
		188	(+++) Activate the ADC peripheral (slave) and start conversions
		189	using function HAL_ADC_Start()
		190	(+++) Activate the ADC peripheral (master) and start conversions
		191	using function HAL_ADCEx_MultiModeStart_DMA()
		192	(+++) Wait for ADC conversion completion by call of function
		193	HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
		194	(these functions must be implemented in user program)
		195	(+++) Conversion results are automatically transferred by DMA into
		196	destination variable address.
		197	(+++) Stop conversion and disable the ADC peripheral (master)
		198	using function HAL_ADCEx_MultiModeStop_DMA()
		199	(+++) Stop conversion and disable the ADC peripheral (slave)
		200	using function HAL_ADC_Stop_IT()
		201
		202	[..]
		203
		204	(@) Callback functions must be implemented in user program:
		205	(+@) HAL_ADC_ErrorCallback()
		206	(+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
		207	(+@) HAL_ADC_ConvCpltCallback()
		208	(+@) HAL_ADC_ConvHalfCpltCallback
		209	(+@) HAL_ADCEx_InjectedConvCpltCallback()
		210
		211	* Deinitialization of ADC *
		212	============================================================
		213	[..]
		214
		215	(#) Disable the ADC interface
		216	(++) ADC clock can be hard reset and disabled at RCC top level.
		217	(++) Hard reset of ADC peripherals
		218	using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
		219	(++) ADC clock disable
		220	using the equivalent macro/functions as configuration step.
		221	(+++) Example:
		222	Into HAL_ADC_MspDeInit() (recommended code location) or with
		223	other device clock parameters configuration:
		224	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
		225	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
		226	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
		227
		228	(#) ADC pins configuration
		229	(++) Disable the clock for the ADC GPIOs
		230	using macro __HAL_RCC_GPIOx_CLK_DISABLE()
		231
		232	(#) Optionally, in case of usage of ADC with interruptions:
		233	(++) Disable the NVIC for ADC
		234	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
		235
		236	(#) Optionally, in case of usage of DMA:
		237	(++) Deinitialize the DMA
		238	using function HAL_DMA_Init().
		239	(++) Disable the NVIC for DMA
		240	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
		241
		242	[..]
		243
		244	* Callback registration *
		245	=============================================
		246	[..]
		247
		248	The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
		249	allows the user to configure dynamically the driver callbacks.
		250	Use Functions @ref HAL_ADC_RegisterCallback()
		251	to register an interrupt callback.
		252	[..]
		253
		254	Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
		255	(+) ConvCpltCallback : ADC conversion complete callback
		256	(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
		257	(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
		258	(+) ErrorCallback : ADC error callback
		259	(+) InjectedConvCpltCallback : ADC group injected conversion complete callback
		260	(+) MspInitCallback : ADC Msp Init callback
		261	(+) MspDeInitCallback : ADC Msp DeInit callback
		262	This function takes as parameters the HAL peripheral handle, the Callback ID
		263	and a pointer to the user callback function.
		264	[..]
		265
		266	Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
		267	weak function.
		268	[..]
		269
		270	@ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
		271	and the Callback ID.
		272	This function allows to reset following callbacks:
		273	(+) ConvCpltCallback : ADC conversion complete callback
		274	(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
		275	(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
		276	(+) ErrorCallback : ADC error callback
		277	(+) InjectedConvCpltCallback : ADC group injected conversion complete callback
		278	(+) MspInitCallback : ADC Msp Init callback
		279	(+) MspDeInitCallback : ADC Msp DeInit callback
		280	[..]
		281
		282	By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
		283	all callbacks are set to the corresponding weak functions:
		284	examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
		285	Exception done for MspInit and MspDeInit functions that are
		286	reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
		287	these callbacks are null (not registered beforehand).
		288	[..]
		289
		290	If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
		291	keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
		292	[..]
		293
		294	Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
		295	Exception done MspInit/MspDeInit functions that can be registered/unregistered
		296	in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
		297	thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
		298	[..]
		299
		300	Then, the user first registers the MspInit/MspDeInit user callbacks
		301	using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
		302	or @ref HAL_ADC_Init() function.
		303	[..]
		304
		305	When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
		306	not defined, the callback registration feature is not available and all callbacks
		307	are set to the corresponding weak functions.
		308
		309	@endverbatim
		310	******************************************************************************
		311	* @attention
		312	*
		313	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		314	* All rights reserved.</center></h2>
		315	*
		316	* This software component is licensed by ST under BSD 3-Clause license,
		317	* the "License"; You may not use this file except in compliance with the
		318	* License. You may obtain a copy of the License at:
		319	* opensource.org/licenses/BSD-3-Clause
		320	*
		321	******************************************************************************
		322	*/
		323
		324	/* Includes ------------------------------------------------------------------*/
		325	#include "stm32f1xx_hal.h"
		326
		327	/** @addtogroup STM32F1xx_HAL_Driver
		328	* @{
		329	*/
		330
		331	/** @defgroup ADC ADC
		332	* @brief ADC HAL module driver
		333	* @{
		334	*/
		335
		336	#ifdef HAL_ADC_MODULE_ENABLED
		337
		338	/* Private typedef -----------------------------------------------------------*/
		339	/* Private define ------------------------------------------------------------*/
		340	/** @defgroup ADC_Private_Constants ADC Private Constants
		341	* @{
		342	*/
		343
		344	/* Timeout values for ADC enable and disable settling time. */
		345	/* Values defined to be higher than worst cases: low clocks freq, */
		346	/* maximum prescaler. */
		347	/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
		348	/* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
		349	/* Unit: ms */
		350	#define ADC_ENABLE_TIMEOUT 2U
		351	#define ADC_DISABLE_TIMEOUT 2U
		352
		353	/* Delay for ADC stabilization time. */
		354	/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
		355	/* Unit: us */
		356	#define ADC_STAB_DELAY_US 1U
		357
		358	/* Delay for temperature sensor stabilization time. */
		359	/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
		360	/* Unit: us */
		361	#define ADC_TEMPSENSOR_DELAY_US 10U
		362
		363	/**
		364	* @}
		365	*/
		366
		367	/* Private macro -------------------------------------------------------------*/
		368	/* Private variables ---------------------------------------------------------*/
		369	/* Private function prototypes -----------------------------------------------*/
		370	/** @defgroup ADC_Private_Functions ADC Private Functions
		371	* @{
		372	*/
		373	/**
		374	* @}
		375	*/
		376
		377	/* Exported functions --------------------------------------------------------*/
		378
		379	/** @defgroup ADC_Exported_Functions ADC Exported Functions
		380	* @{
		381	*/
		382
		383	/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
		384	* @brief Initialization and Configuration functions
		385	*
		386	@verbatim
		387	===============================================================================
		388	##### Initialization and de-initialization functions #####
		389	===============================================================================
		390	[..] This section provides functions allowing to:
		391	(+) Initialize and configure the ADC.
		392	(+) De-initialize the ADC.
		393
		394	@endverbatim
		395	* @{
		396	*/
		397
		398	/**
		399	* @brief Initializes the ADC peripheral and regular group according to
		400	* parameters specified in structure "ADC_InitTypeDef".
		401	* @note As prerequisite, ADC clock must be configured at RCC top level
		402	* (clock source APB2).
		403	* See commented example code below that can be copied and uncommented
		404	* into HAL_ADC_MspInit().
		405	* @note Possibility to update parameters on the fly:
		406	* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
		407	* coming from ADC state reset. Following calls to this function can
		408	* be used to reconfigure some parameters of ADC_InitTypeDef
		409	* structure on the fly, without modifying MSP configuration. If ADC
		410	* MSP has to be modified again, HAL_ADC_DeInit() must be called
		411	* before HAL_ADC_Init().
		412	* The setting of these parameters is conditioned to ADC state.
		413	* For parameters constraints, see comments of structure
		414	* "ADC_InitTypeDef".
		415	* @note This function configures the ADC within 2 scopes: scope of entire
		416	* ADC and scope of regular group. For parameters details, see comments
		417	* of structure "ADC_InitTypeDef".
		418	* @param hadc: ADC handle
		419	* @retval HAL status
		420	*/
		421	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
		422	{
		423	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
		424	uint32_t tmp_cr1 = 0U;
		425	uint32_t tmp_cr2 = 0U;
		426	uint32_t tmp_sqr1 = 0U;
		427
		428	/* Check ADC handle */
		429	if(hadc == NULL)
		430	{
		431	return HAL_ERROR;
		432	}
		433
		434	/* Check the parameters */
		435	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		436	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
		437	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
		438	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
		439	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
		440
		441	if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
		442	{
		443	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
		444	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
		445	if(hadc->Init.DiscontinuousConvMode != DISABLE)
		446	{
		447	assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
		448	}
		449	}
		450
		451	/* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
		452	/* at RCC top level. */
		453	/* Refer to header of this file for more details on clock enabling */
		454	/* procedure. */
		455
		456	/* Actions performed only if ADC is coming from state reset: */
		457	/* - Initialization of ADC MSP */
		458	if (hadc->State == HAL_ADC_STATE_RESET)
		459	{
		460	/* Initialize ADC error code */
		461	ADC_CLEAR_ERRORCODE(hadc);
		462
		463	/* Allocate lock resource and initialize it */
		464	hadc->Lock = HAL_UNLOCKED;
		465
		466	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		467	/* Init the ADC Callback settings */
		468	hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
		469	hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
		470	hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
		471	hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
		472	hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
		473
		474	if (hadc->MspInitCallback == NULL)
		475	{
		476	hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
		477	}
		478
		479	/* Init the low level hardware */
		480	hadc->MspInitCallback(hadc);
		481	#else
		482	/* Init the low level hardware */
		483	HAL_ADC_MspInit(hadc);
		484	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		485	}
		486
		487	/* Stop potential conversion on going, on regular and injected groups */
		488	/* Disable ADC peripheral */
		489	/* Note: In case of ADC already enabled, precaution to not launch an */
		490	/* unwanted conversion while modifying register CR2 by writing 1 to */
		491	/* bit ADON. */
		492	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
		493
		494
		495	/* Configuration of ADC parameters if previous preliminary actions are */
		496	/* correctly completed. */
		497	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
		498	(tmp_hal_status == HAL_OK) )
		499	{
		500	/* Set ADC state */
		501	ADC_STATE_CLR_SET(hadc->State,
		502	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
		503	HAL_ADC_STATE_BUSY_INTERNAL);
		504
		505	/* Set ADC parameters */
		506
		507	/* Configuration of ADC: */
		508	/* - data alignment */
		509	/* - external trigger to start conversion */
		510	/* - external trigger polarity (always set to 1, because needed for all */
		511	/* triggers: external trigger of SW start) */
		512	/* - continuous conversion mode */
		513	/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
		514	/* HAL_ADC_Start_xxx functions because if set in this function, */
		515	/* a conversion on injected group would start a conversion also on */
		516	/* regular group after ADC enabling. */
		517	tmp_cr2 \|= (hadc->Init.DataAlign \|
		518	ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) \|
		519	ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
		520
		521	/* Configuration of ADC: */
		522	/* - scan mode */
		523	/* - discontinuous mode disable/enable */
		524	/* - discontinuous mode number of conversions */
		525	tmp_cr1 \|= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
		526
		527	/* Enable discontinuous mode only if continuous mode is disabled */
		528	/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
		529	/* discontinuous is set anyway, but will have no effect on ADC HW. */
		530	if (hadc->Init.DiscontinuousConvMode == ENABLE)
		531	{
		532	if (hadc->Init.ContinuousConvMode == DISABLE)
		533	{
		534	/* Enable the selected ADC regular discontinuous mode */
		535	/* Set the number of channels to be converted in discontinuous mode */
		536	SET_BIT(tmp_cr1, ADC_CR1_DISCEN \|
		537	ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
		538	}
		539	else
		540	{
		541	/* ADC regular group settings continuous and sequencer discontinuous*/
		542	/* cannot be enabled simultaneously. */
		543
		544	/* Update ADC state machine to error */
		545	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
		546
		547	/* Set ADC error code to ADC IP internal error */
		548	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
		549	}
		550	}
		551
		552	/* Update ADC configuration register CR1 with previous settings */
		553	MODIFY_REG(hadc->Instance->CR1,
		554	ADC_CR1_SCAN \|
		555	ADC_CR1_DISCEN \|
		556	ADC_CR1_DISCNUM ,
		557	tmp_cr1 );
		558
		559	/* Update ADC configuration register CR2 with previous settings */
		560	MODIFY_REG(hadc->Instance->CR2,
		561	ADC_CR2_ALIGN \|
		562	ADC_CR2_EXTSEL \|
		563	ADC_CR2_EXTTRIG \|
		564	ADC_CR2_CONT ,
		565	tmp_cr2 );
		566
		567	/* Configuration of regular group sequencer: */
		568	/* - if scan mode is disabled, regular channels sequence length is set to */
		569	/* 0x00: 1 channel converted (channel on regular rank 1) */
		570	/* Parameter "NbrOfConversion" is discarded. */
		571	/* Note: Scan mode is present by hardware on this device and, if */
		572	/* disabled, discards automatically nb of conversions. Anyway, nb of */
		573	/* conversions is forced to 0x00 for alignment over all STM32 devices. */
		574	/* - if scan mode is enabled, regular channels sequence length is set to */
		575	/* parameter "NbrOfConversion" */
		576	if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
		577	{
		578	tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
		579	}
		580
		581	MODIFY_REG(hadc->Instance->SQR1,
		582	ADC_SQR1_L ,
		583	tmp_sqr1 );
		584
		585	/* Check back that ADC registers have effectively been configured to */
		586	/* ensure of no potential problem of ADC core IP clocking. */
		587	/* Check through register CR2 (excluding bits set in other functions: */
		588	/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
		589	/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
		590	/* measurement path bit (TSVREFE). */
		591	if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON \| ADC_CR2_DMA \|
		592	ADC_CR2_SWSTART \| ADC_CR2_JSWSTART \|
		593	ADC_CR2_JEXTTRIG \| ADC_CR2_JEXTSEL \|
		594	ADC_CR2_TSVREFE ))
		595	== tmp_cr2)
		596	{
		597	/* Set ADC error code to none */
		598	ADC_CLEAR_ERRORCODE(hadc);
		599
		600	/* Set the ADC state */
		601	ADC_STATE_CLR_SET(hadc->State,
		602	HAL_ADC_STATE_BUSY_INTERNAL,
		603	HAL_ADC_STATE_READY);
		604	}
		605	else
		606	{
		607	/* Update ADC state machine to error */
		608	ADC_STATE_CLR_SET(hadc->State,
		609	HAL_ADC_STATE_BUSY_INTERNAL,
		610	HAL_ADC_STATE_ERROR_INTERNAL);
		611
		612	/* Set ADC error code to ADC IP internal error */
		613	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
		614
		615	tmp_hal_status = HAL_ERROR;
		616	}
		617
		618	}
		619	else
		620	{
		621	/* Update ADC state machine to error */
		622	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
		623
		624	tmp_hal_status = HAL_ERROR;
		625	}
		626
		627	/* Return function status */
		628	return tmp_hal_status;
		629	}
		630
		631	/**
		632	* @brief Deinitialize the ADC peripheral registers to their default reset
		633	* values, with deinitialization of the ADC MSP.
		634	* If needed, the example code can be copied and uncommented into
		635	* function HAL_ADC_MspDeInit().
		636	* @param hadc: ADC handle
		637	* @retval HAL status
		638	*/
		639	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
		640	{
		641	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
		642
		643	/* Check ADC handle */
		644	if(hadc == NULL)
		645	{
		646	return HAL_ERROR;
		647	}
		648
		649	/* Check the parameters */
		650	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		651
		652	/* Set ADC state */
		653	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
		654
		655	/* Stop potential conversion on going, on regular and injected groups */
		656	/* Disable ADC peripheral */
		657	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
		658
		659
		660	/* Configuration of ADC parameters if previous preliminary actions are */
		661	/* correctly completed. */
		662	if (tmp_hal_status == HAL_OK)
		663	{
		664	/* ========== Reset ADC registers ========== */
		665
		666
		667
		668
		669	/* Reset register SR */
		670	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD \| ADC_FLAG_JEOC \| ADC_FLAG_EOC \|
		671	ADC_FLAG_JSTRT \| ADC_FLAG_STRT));
		672
		673	/* Reset register CR1 */
		674	CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_DISCNUM \|
		675	ADC_CR1_JDISCEN \| ADC_CR1_DISCEN \| ADC_CR1_JAUTO \|
		676	ADC_CR1_AWDSGL \| ADC_CR1_SCAN \| ADC_CR1_JEOCIE \|
		677	ADC_CR1_AWDIE \| ADC_CR1_EOCIE \| ADC_CR1_AWDCH ));
		678
		679	/* Reset register CR2 */
		680	CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE \| ADC_CR2_SWSTART \| ADC_CR2_JSWSTART \|
		681	ADC_CR2_EXTTRIG \| ADC_CR2_EXTSEL \| ADC_CR2_JEXTTRIG \|
		682	ADC_CR2_JEXTSEL \| ADC_CR2_ALIGN \| ADC_CR2_DMA \|
		683	ADC_CR2_RSTCAL \| ADC_CR2_CAL \| ADC_CR2_CONT \|
		684	ADC_CR2_ADON ));
		685
		686	/* Reset register SMPR1 */
		687	CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 \| ADC_SMPR1_SMP16 \| ADC_SMPR1_SMP15 \|
		688	ADC_SMPR1_SMP14 \| ADC_SMPR1_SMP13 \| ADC_SMPR1_SMP12 \|
		689	ADC_SMPR1_SMP11 \| ADC_SMPR1_SMP10 ));
		690
		691	/* Reset register SMPR2 */
		692	CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 \| ADC_SMPR2_SMP8 \| ADC_SMPR2_SMP7 \|
		693	ADC_SMPR2_SMP6 \| ADC_SMPR2_SMP5 \| ADC_SMPR2_SMP4 \|
		694	ADC_SMPR2_SMP3 \| ADC_SMPR2_SMP2 \| ADC_SMPR2_SMP1 \|
		695	ADC_SMPR2_SMP0 ));
		696
		697	/* Reset register JOFR1 */
		698	CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
		699	/* Reset register JOFR2 */
		700	CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
		701	/* Reset register JOFR3 */
		702	CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
		703	/* Reset register JOFR4 */
		704	CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
		705
		706	/* Reset register HTR */
		707	CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
		708	/* Reset register LTR */
		709	CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
		710
		711	/* Reset register SQR1 */
		712	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L \|
		713	ADC_SQR1_SQ16 \| ADC_SQR1_SQ15 \|
		714	ADC_SQR1_SQ14 \| ADC_SQR1_SQ13 );
		715
		716	/* Reset register SQR1 */
		717	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L \|
		718	ADC_SQR1_SQ16 \| ADC_SQR1_SQ15 \|
		719	ADC_SQR1_SQ14 \| ADC_SQR1_SQ13 );
		720
		721	/* Reset register SQR2 */
		722	CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 \| ADC_SQR2_SQ11 \| ADC_SQR2_SQ10 \|
		723	ADC_SQR2_SQ9 \| ADC_SQR2_SQ8 \| ADC_SQR2_SQ7 );
		724
		725	/* Reset register SQR3 */
		726	CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 \| ADC_SQR3_SQ5 \| ADC_SQR3_SQ4 \|
		727	ADC_SQR3_SQ3 \| ADC_SQR3_SQ2 \| ADC_SQR3_SQ1 );
		728
		729	/* Reset register JSQR */
		730	CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL \|
		731	ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3 \|
		732	ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 );
		733
		734	/* Reset register JSQR */
		735	CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL \|
		736	ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3 \|
		737	ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 );
		738
		739	/* Reset register DR */
		740	/* bits in access mode read only, no direct reset applicable*/
		741
		742	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
		743	/* bits in access mode read only, no direct reset applicable*/
		744
		745	/* ========== Hard reset ADC peripheral ========== */
		746	/* Performs a global reset of the entire ADC peripheral: ADC state is */
		747	/* forced to a similar state after device power-on. */
		748	/* If needed, copy-paste and uncomment the following reset code into */
		749	/* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
		750	/* */
		751	/* __HAL_RCC_ADC1_FORCE_RESET() */
		752	/* __HAL_RCC_ADC1_RELEASE_RESET() */
		753
		754	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		755	if (hadc->MspDeInitCallback == NULL)
		756	{
		757	hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
		758	}
		759
		760	/* DeInit the low level hardware */
		761	hadc->MspDeInitCallback(hadc);
		762	#else
		763	/* DeInit the low level hardware */
		764	HAL_ADC_MspDeInit(hadc);
		765	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		766
		767	/* Set ADC error code to none */
		768	ADC_CLEAR_ERRORCODE(hadc);
		769
		770	/* Set ADC state */
		771	hadc->State = HAL_ADC_STATE_RESET;
		772
		773	}
		774
		775	/* Process unlocked */
		776	__HAL_UNLOCK(hadc);
		777
		778	/* Return function status */
		779	return tmp_hal_status;
		780	}
		781
		782	/**
		783	* @brief Initializes the ADC MSP.
		784	* @param hadc: ADC handle
		785	* @retval None
		786	*/
		787	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
		788	{
		789	/* Prevent unused argument(s) compilation warning */
		790	UNUSED(hadc);
		791	/* NOTE : This function should not be modified. When the callback is needed,
		792	function HAL_ADC_MspInit must be implemented in the user file.
		793	*/
		794	}
		795
		796	/**
		797	* @brief DeInitializes the ADC MSP.
		798	* @param hadc: ADC handle
		799	* @retval None
		800	*/
		801	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
		802	{
		803	/* Prevent unused argument(s) compilation warning */
		804	UNUSED(hadc);
		805	/* NOTE : This function should not be modified. When the callback is needed,
		806	function HAL_ADC_MspDeInit must be implemented in the user file.
		807	*/
		808	}
		809
		810	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		811	/**
		812	* @brief Register a User ADC Callback
		813	* To be used instead of the weak predefined callback
		814	* @param hadc Pointer to a ADC_HandleTypeDef structure that contains
		815	* the configuration information for the specified ADC.
		816	* @param CallbackID ID of the callback to be registered
		817	* This parameter can be one of the following values:
		818	* @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
		819	* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
		820	* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
		821	* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
		822	* @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
		823	* @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
		824	* @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
		825	* @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
		826	* @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
		827	* @param pCallback pointer to the Callback function
		828	* @retval HAL status
		829	*/
		830	HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
		831	{
		832	HAL_StatusTypeDef status = HAL_OK;
		833
		834	if (pCallback == NULL)
		835	{
		836	/* Update the error code */
		837	hadc->ErrorCode \|= HAL_ADC_ERROR_INVALID_CALLBACK;
		838
		839	return HAL_ERROR;
		840	}
		841
		842	if ((hadc->State & HAL_ADC_STATE_READY) != 0)
		843	{
		844	switch (CallbackID)
		845	{
		846	case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
		847	hadc->ConvCpltCallback = pCallback;
		848	break;
		849
		850	case HAL_ADC_CONVERSION_HALF_CB_ID :
		851	hadc->ConvHalfCpltCallback = pCallback;
		852	break;
		853
		854	case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
		855	hadc->LevelOutOfWindowCallback = pCallback;
		856	break;
		857
		858	case HAL_ADC_ERROR_CB_ID :
		859	hadc->ErrorCallback = pCallback;
		860	break;
		861
		862	case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
		863	hadc->InjectedConvCpltCallback = pCallback;
		864	break;
		865
		866	case HAL_ADC_MSPINIT_CB_ID :
		867	hadc->MspInitCallback = pCallback;
		868	break;
		869
		870	case HAL_ADC_MSPDEINIT_CB_ID :
		871	hadc->MspDeInitCallback = pCallback;
		872	break;
		873
		874	default :
		875	/* Update the error code */
		876	hadc->ErrorCode \|= HAL_ADC_ERROR_INVALID_CALLBACK;
		877
		878	/* Return error status */
		879	status = HAL_ERROR;
		880	break;
		881	}
		882	}
		883	else if (HAL_ADC_STATE_RESET == hadc->State)
		884	{
		885	switch (CallbackID)
		886	{
		887	case HAL_ADC_MSPINIT_CB_ID :
		888	hadc->MspInitCallback = pCallback;
		889	break;
		890
		891	case HAL_ADC_MSPDEINIT_CB_ID :
		892	hadc->MspDeInitCallback = pCallback;
		893	break;
		894
		895	default :
		896	/* Update the error code */
		897	hadc->ErrorCode \|= HAL_ADC_ERROR_INVALID_CALLBACK;
		898
		899	/* Return error status */
		900	status = HAL_ERROR;
		901	break;
		902	}
		903	}
		904	else
		905	{
		906	/* Update the error code */
		907	hadc->ErrorCode \|= HAL_ADC_ERROR_INVALID_CALLBACK;
		908
		909	/* Return error status */
		910	status = HAL_ERROR;
		911	}
		912
		913	return status;
		914	}
		915
		916	/**
		917	* @brief Unregister a ADC Callback
		918	* ADC callback is redirected to the weak predefined callback
		919	* @param hadc Pointer to a ADC_HandleTypeDef structure that contains
		920	* the configuration information for the specified ADC.
		921	* @param CallbackID ID of the callback to be unregistered
		922	* This parameter can be one of the following values:
		923	* @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
		924	* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
		925	* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
		926	* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
		927	* @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
		928	* @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
		929	* @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
		930	* @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
		931	* @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
		932	* @retval HAL status
		933	*/
		934	HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
		935	{
		936	HAL_StatusTypeDef status = HAL_OK;
		937
		938	if ((hadc->State & HAL_ADC_STATE_READY) != 0)
		939	{
		940	switch (CallbackID)
		941	{
		942	case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
		943	hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
		944	break;
		945
		946	case HAL_ADC_CONVERSION_HALF_CB_ID :
		947	hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
		948	break;
		949
		950	case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
		951	hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
		952	break;
		953
		954	case HAL_ADC_ERROR_CB_ID :
		955	hadc->ErrorCallback = HAL_ADC_ErrorCallback;
		956	break;
		957
		958	case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
		959	hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
		960	break;
		961
		962	case HAL_ADC_MSPINIT_CB_ID :
		963	hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
		964	break;
		965
		966	case HAL_ADC_MSPDEINIT_CB_ID :
		967	hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
		968	break;
		969
		970	default :
		971	/* Update the error code */
		972	hadc->ErrorCode \|= HAL_ADC_ERROR_INVALID_CALLBACK;
		973
		974	/* Return error status */
		975	status = HAL_ERROR;
		976	break;
		977	}
		978	}
		979	else if (HAL_ADC_STATE_RESET == hadc->State)
		980	{
		981	switch (CallbackID)
		982	{
		983	case HAL_ADC_MSPINIT_CB_ID :
		984	hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
		985	break;
		986
		987	case HAL_ADC_MSPDEINIT_CB_ID :
		988	hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
		989	break;
		990
		991	default :
		992	/* Update the error code */
		993	hadc->ErrorCode \|= HAL_ADC_ERROR_INVALID_CALLBACK;
		994
		995	/* Return error status */
		996	status = HAL_ERROR;
		997	break;
		998	}
		999	}
		1000	else
		1001	{
		1002	/* Update the error code */
		1003	hadc->ErrorCode \|= HAL_ADC_ERROR_INVALID_CALLBACK;
		1004
		1005	/* Return error status */
		1006	status = HAL_ERROR;
		1007	}
		1008
		1009	return status;
		1010	}
		1011
		1012	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		1013
		1014	/**
		1015	* @}
		1016	*/
		1017
		1018	/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
		1019	* @brief Input and Output operation functions
		1020	*
		1021	@verbatim
		1022	===============================================================================
		1023	##### IO operation functions #####
		1024	===============================================================================
		1025	[..] This section provides functions allowing to:
		1026	(+) Start conversion of regular group.
		1027	(+) Stop conversion of regular group.
		1028	(+) Poll for conversion complete on regular group.
		1029	(+) Poll for conversion event.
		1030	(+) Get result of regular channel conversion.
		1031	(+) Start conversion of regular group and enable interruptions.
		1032	(+) Stop conversion of regular group and disable interruptions.
		1033	(+) Handle ADC interrupt request
		1034	(+) Start conversion of regular group and enable DMA transfer.
		1035	(+) Stop conversion of regular group and disable ADC DMA transfer.
		1036	@endverbatim
		1037	* @{
		1038	*/
		1039
		1040	/**
		1041	* @brief Enables ADC, starts conversion of regular group.
		1042	* Interruptions enabled in this function: None.
		1043	* @param hadc: ADC handle
		1044	* @retval HAL status
		1045	*/
		1046	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
		1047	{
		1048	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
		1049
		1050	/* Check the parameters */
		1051	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		1052
		1053	/* Process locked */
		1054	__HAL_LOCK(hadc);
		1055
		1056	/* Enable the ADC peripheral */
		1057	tmp_hal_status = ADC_Enable(hadc);
		1058
		1059	/* Start conversion if ADC is effectively enabled */
		1060	if (tmp_hal_status == HAL_OK)
		1061	{
		1062	/* Set ADC state */
		1063	/* - Clear state bitfield related to regular group conversion results */
		1064	/* - Set state bitfield related to regular operation */
		1065	ADC_STATE_CLR_SET(hadc->State,
		1066	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC,
		1067	HAL_ADC_STATE_REG_BUSY);
		1068
		1069	/* Set group injected state (from auto-injection) and multimode state */
		1070	/* for all cases of multimode: independent mode, multimode ADC master */
		1071	/* or multimode ADC slave (for devices with several ADCs): */
		1072	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
		1073	{
		1074	/* Set ADC state (ADC independent or master) */
		1075	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
		1076
		1077	/* If conversions on group regular are also triggering group injected, */
		1078	/* update ADC state. */
		1079	if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
		1080	{
		1081	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
		1082	}
		1083	}
		1084	else
		1085	{
		1086	/* Set ADC state (ADC slave) */
		1087	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
		1088
		1089	/* If conversions on group regular are also triggering group injected, */
		1090	/* update ADC state. */
		1091	if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
		1092	{
		1093	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
		1094	}
		1095	}
		1096
		1097	/* State machine update: Check if an injected conversion is ongoing */
		1098	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
		1099	{
		1100	/* Reset ADC error code fields related to conversions on group regular */
		1101	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
		1102	}
		1103	else
		1104	{
		1105	/* Reset ADC all error code fields */
		1106	ADC_CLEAR_ERRORCODE(hadc);
		1107	}
		1108
		1109	/* Process unlocked */
		1110	/* Unlock before starting ADC conversions: in case of potential */
		1111	/* interruption, to let the process to ADC IRQ Handler. */
		1112	__HAL_UNLOCK(hadc);
		1113
		1114	/* Clear regular group conversion flag */
		1115	/* (To ensure of no unknown state from potential previous ADC operations) */
		1116	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
		1117
		1118	/* Enable conversion of regular group. */
		1119	/* If software start has been selected, conversion starts immediately. */
		1120	/* If external trigger has been selected, conversion will start at next */
		1121	/* trigger event. */
		1122	/* Case of multimode enabled: */
		1123	/* - if ADC is slave, ADC is enabled only (conversion is not started). */
		1124	/* - if ADC is master, ADC is enabled and conversion is started. */
		1125	/* If ADC is master, ADC is enabled and conversion is started. */
		1126	/* Note: Alternate trigger for single conversion could be to force an */
		1127	/* additional set of bit ADON "hadc->Instance->CR2 \|= ADC_CR2_ADON;"*/
		1128	if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
		1129	ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
		1130	{
		1131	/* Start ADC conversion on regular group with SW start */
		1132	SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
		1133	}
		1134	else
		1135	{
		1136	/* Start ADC conversion on regular group with external trigger */
		1137	SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
		1138	}
		1139	}
		1140	else
		1141	{
		1142	/* Process unlocked */
		1143	__HAL_UNLOCK(hadc);
		1144	}
		1145
		1146	/* Return function status */
		1147	return tmp_hal_status;
		1148	}
		1149
		1150	/**
		1151	* @brief Stop ADC conversion of regular group (and injected channels in
		1152	* case of auto_injection mode), disable ADC peripheral.
		1153	* @note: ADC peripheral disable is forcing stop of potential
		1154	* conversion on injected group. If injected group is under use, it
		1155	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
		1156	* @param hadc: ADC handle
		1157	* @retval HAL status.
		1158	*/
		1159	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
		1160	{
		1161	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
		1162
		1163	/* Check the parameters */
		1164	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		1165
		1166	/* Process locked */
		1167	__HAL_LOCK(hadc);
		1168
		1169	/* Stop potential conversion on going, on regular and injected groups */
		1170	/* Disable ADC peripheral */
		1171	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
		1172
		1173	/* Check if ADC is effectively disabled */
		1174	if (tmp_hal_status == HAL_OK)
		1175	{
		1176	/* Set ADC state */
		1177	ADC_STATE_CLR_SET(hadc->State,
		1178	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
		1179	HAL_ADC_STATE_READY);
		1180	}
		1181
		1182	/* Process unlocked */
		1183	__HAL_UNLOCK(hadc);
		1184
		1185	/* Return function status */
		1186	return tmp_hal_status;
		1187	}
		1188
		1189	/**
		1190	* @brief Wait for regular group conversion to be completed.
		1191	* @note This function cannot be used in a particular setup: ADC configured
		1192	* in DMA mode.
		1193	* In this case, DMA resets the flag EOC and polling cannot be
		1194	* performed on each conversion.
		1195	* @note On STM32F1 devices, limitation in case of sequencer enabled
		1196	* (several ranks selected): polling cannot be done on each
		1197	* conversion inside the sequence. In this case, polling is replaced by
		1198	* wait for maximum conversion time.
		1199	* @param hadc: ADC handle
		1200	* @param Timeout: Timeout value in millisecond.
		1201	* @retval HAL status
		1202	*/
		1203	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
		1204	{
		1205	uint32_t tickstart = 0U;
		1206
		1207	/* Variables for polling in case of scan mode enabled and polling for each */
		1208	/* conversion. */
		1209	__IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
		1210	uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
		1211
		1212	/* Check the parameters */
		1213	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		1214
		1215	/* Get tick count */
		1216	tickstart = HAL_GetTick();
		1217
		1218	/* Verification that ADC configuration is compliant with polling for */
		1219	/* each conversion: */
		1220	/* Particular case is ADC configured in DMA mode */
		1221	if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
		1222	{
		1223	/* Update ADC state machine to error */
		1224	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
		1225
		1226	/* Process unlocked */
		1227	__HAL_UNLOCK(hadc);
		1228
		1229	return HAL_ERROR;
		1230	}
		1231
		1232	/* Polling for end of conversion: differentiation if single/sequence */
		1233	/* conversion. */
		1234	/* - If single conversion for regular group (Scan mode disabled or enabled */
		1235	/* with NbrOfConversion =1), flag EOC is used to determine the */
		1236	/* conversion completion. */
		1237	/* - If sequence conversion for regular group (scan mode enabled and */
		1238	/* NbrOfConversion >=2), flag EOC is set only at the end of the */
		1239	/* sequence. */
		1240	/* To poll for each conversion, the maximum conversion time is computed */
		1241	/* from ADC conversion time (selected sampling time + conversion time of */
		1242	/* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
		1243	/* settings, conversion time range can be from 28 to 32256 CPU cycles). */
		1244	/* As flag EOC is not set after each conversion, no timeout status can */
		1245	/* be set. */
		1246	if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
		1247	HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
		1248	{
		1249	/* Wait until End of Conversion flag is raised */
		1250	while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
		1251	{
		1252	/* Check if timeout is disabled (set to infinite wait) */
		1253	if(Timeout != HAL_MAX_DELAY)
		1254	{
		1255	if((Timeout == 0U) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
		1256	{
		1257	/* New check to avoid false timeout detection in case of preemption */
		1258	if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
		1259	{
		1260	/* Update ADC state machine to timeout */
		1261	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
		1262
		1263	/* Process unlocked */
		1264	__HAL_UNLOCK(hadc);
		1265
		1266	return HAL_TIMEOUT;
		1267	}
		1268	}
		1269	}
		1270	}
		1271	}
		1272	else
		1273	{
		1274	/* Replace polling by wait for maximum conversion time */
		1275	/* - Computation of CPU clock cycles corresponding to ADC clock cycles */
		1276	/* and ADC maximum conversion cycles on all channels. */
		1277	/* - Wait for the expected ADC clock cycles delay */
		1278	Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
		1279	/ HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
		1280	* ADC_CONVCYCLES_MAX_RANGE(hadc) );
		1281
		1282	while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
		1283	{
		1284	/* Check if timeout is disabled (set to infinite wait) */
		1285	if(Timeout != HAL_MAX_DELAY)
		1286	{
		1287	if((Timeout == 0U) \|\| ((HAL_GetTick() - tickstart) > Timeout))
		1288	{
		1289	/* New check to avoid false timeout detection in case of preemption */
		1290	if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
		1291	{
		1292	/* Update ADC state machine to timeout */
		1293	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
		1294
		1295	/* Process unlocked */
		1296	__HAL_UNLOCK(hadc);
		1297
		1298	return HAL_TIMEOUT;
		1299	}
		1300	}
		1301	}
		1302	Conversion_Timeout_CPU_cycles ++;
		1303	}
		1304	}
		1305
		1306	/* Clear regular group conversion flag */
		1307	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
		1308
		1309	/* Update ADC state machine */
		1310	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
		1311
		1312	/* Determine whether any further conversion upcoming on group regular */
		1313	/* by external trigger, continuous mode or scan sequence on going. */
		1314	/* Note: On STM32F1 devices, in case of sequencer enabled */
		1315	/* (several ranks selected), end of conversion flag is raised */
		1316	/* at the end of the sequence. */
		1317	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
		1318	(hadc->Init.ContinuousConvMode == DISABLE) )
		1319	{
		1320	/* Set ADC state */
		1321	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
		1322
		1323	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
		1324	{
		1325	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
		1326	}
		1327	}
		1328
		1329	/* Return ADC state */
		1330	return HAL_OK;
		1331	}
		1332
		1333	/**
		1334	* @brief Poll for conversion event.
		1335	* @param hadc: ADC handle
		1336	* @param EventType: the ADC event type.
		1337	* This parameter can be one of the following values:
		1338	* @arg ADC_AWD_EVENT: ADC Analog watchdog event.
		1339	* @param Timeout: Timeout value in millisecond.
		1340	* @retval HAL status
		1341	*/
		1342	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
		1343	{
		1344	uint32_t tickstart = 0U;
		1345
		1346	/* Check the parameters */
		1347	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		1348	assert_param(IS_ADC_EVENT_TYPE(EventType));
		1349
		1350	/* Get tick count */
		1351	tickstart = HAL_GetTick();
		1352
		1353	/* Check selected event flag */
		1354	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
		1355	{
		1356	/* Check if timeout is disabled (set to infinite wait) */
		1357	if(Timeout != HAL_MAX_DELAY)
		1358	{
		1359	if((Timeout == 0U) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
		1360	{
		1361	/* New check to avoid false timeout detection in case of preemption */
		1362	if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
		1363	{
		1364	/* Update ADC state machine to timeout */
		1365	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
		1366
		1367	/* Process unlocked */
		1368	__HAL_UNLOCK(hadc);
		1369
		1370	return HAL_TIMEOUT;
		1371	}
		1372	}
		1373	}
		1374	}
		1375
		1376	/* Analog watchdog (level out of window) event */
		1377	/* Set ADC state */
		1378	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
		1379
		1380	/* Clear ADC analog watchdog flag */
		1381	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
		1382
		1383	/* Return ADC state */
		1384	return HAL_OK;
		1385	}
		1386
		1387	/**
		1388	* @brief Enables ADC, starts conversion of regular group with interruption.
		1389	* Interruptions enabled in this function:
		1390	* - EOC (end of conversion of regular group)
		1391	* Each of these interruptions has its dedicated callback function.
		1392	* @param hadc: ADC handle
		1393	* @retval HAL status
		1394	*/
		1395	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
		1396	{
		1397	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
		1398
		1399	/* Check the parameters */
		1400	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		1401
		1402	/* Process locked */
		1403	__HAL_LOCK(hadc);
		1404
		1405	/* Enable the ADC peripheral */
		1406	tmp_hal_status = ADC_Enable(hadc);
		1407
		1408	/* Start conversion if ADC is effectively enabled */
		1409	if (tmp_hal_status == HAL_OK)
		1410	{
		1411	/* Set ADC state */
		1412	/* - Clear state bitfield related to regular group conversion results */
		1413	/* - Set state bitfield related to regular operation */
		1414	ADC_STATE_CLR_SET(hadc->State,
		1415	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
		1416	HAL_ADC_STATE_REG_BUSY);
		1417
		1418	/* Set group injected state (from auto-injection) and multimode state */
		1419	/* for all cases of multimode: independent mode, multimode ADC master */
		1420	/* or multimode ADC slave (for devices with several ADCs): */
		1421	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
		1422	{
		1423	/* Set ADC state (ADC independent or master) */
		1424	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
		1425
		1426	/* If conversions on group regular are also triggering group injected, */
		1427	/* update ADC state. */
		1428	if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
		1429	{
		1430	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
		1431	}
		1432	}
		1433	else
		1434	{
		1435	/* Set ADC state (ADC slave) */
		1436	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
		1437
		1438	/* If conversions on group regular are also triggering group injected, */
		1439	/* update ADC state. */
		1440	if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
		1441	{
		1442	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
		1443	}
		1444	}
		1445
		1446	/* State machine update: Check if an injected conversion is ongoing */
		1447	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
		1448	{
		1449	/* Reset ADC error code fields related to conversions on group regular */
		1450	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
		1451	}
		1452	else
		1453	{
		1454	/* Reset ADC all error code fields */
		1455	ADC_CLEAR_ERRORCODE(hadc);
		1456	}
		1457
		1458	/* Process unlocked */
		1459	/* Unlock before starting ADC conversions: in case of potential */
		1460	/* interruption, to let the process to ADC IRQ Handler. */
		1461	__HAL_UNLOCK(hadc);
		1462
		1463	/* Clear regular group conversion flag and overrun flag */
		1464	/* (To ensure of no unknown state from potential previous ADC operations) */
		1465	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
		1466
		1467	/* Enable end of conversion interrupt for regular group */
		1468	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
		1469
		1470	/* Enable conversion of regular group. */
		1471	/* If software start has been selected, conversion starts immediately. */
		1472	/* If external trigger has been selected, conversion will start at next */
		1473	/* trigger event. */
		1474	/* Case of multimode enabled: */
		1475	/* - if ADC is slave, ADC is enabled only (conversion is not started). */
		1476	/* - if ADC is master, ADC is enabled and conversion is started. */
		1477	if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
		1478	ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
		1479	{
		1480	/* Start ADC conversion on regular group with SW start */
		1481	SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
		1482	}
		1483	else
		1484	{
		1485	/* Start ADC conversion on regular group with external trigger */
		1486	SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
		1487	}
		1488	}
		1489	else
		1490	{
		1491	/* Process unlocked */
		1492	__HAL_UNLOCK(hadc);
		1493	}
		1494
		1495	/* Return function status */
		1496	return tmp_hal_status;
		1497	}
		1498
		1499	/**
		1500	* @brief Stop ADC conversion of regular group (and injected group in
		1501	* case of auto_injection mode), disable interrution of
		1502	* end-of-conversion, disable ADC peripheral.
		1503	* @param hadc: ADC handle
		1504	* @retval None
		1505	*/
		1506	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
		1507	{
		1508	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
		1509
		1510	/* Check the parameters */
		1511	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		1512
		1513	/* Process locked */
		1514	__HAL_LOCK(hadc);
		1515
		1516	/* Stop potential conversion on going, on regular and injected groups */
		1517	/* Disable ADC peripheral */
		1518	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
		1519
		1520	/* Check if ADC is effectively disabled */
		1521	if (tmp_hal_status == HAL_OK)
		1522	{
		1523	/* Disable ADC end of conversion interrupt for regular group */
		1524	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
		1525
		1526	/* Set ADC state */
		1527	ADC_STATE_CLR_SET(hadc->State,
		1528	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
		1529	HAL_ADC_STATE_READY);
		1530	}
		1531
		1532	/* Process unlocked */
		1533	__HAL_UNLOCK(hadc);
		1534
		1535	/* Return function status */
		1536	return tmp_hal_status;
		1537	}
		1538
		1539	/**
		1540	* @brief Enables ADC, starts conversion of regular group and transfers result
		1541	* through DMA.
		1542	* Interruptions enabled in this function:
		1543	* - DMA transfer complete
		1544	* - DMA half transfer
		1545	* Each of these interruptions has its dedicated callback function.
		1546	* @note For devices with several ADCs: This function is for single-ADC mode
		1547	* only. For multimode, use the dedicated MultimodeStart function.
		1548	* @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
		1549	* on devices) have DMA capability.
		1550	* ADC2 converted data can be transferred in dual ADC mode using DMA
		1551	* of ADC1 (ADC master in multimode).
		1552	* In case of using ADC1 with DMA on a device featuring 2 ADC
		1553	* instances: ADC1 conversion register DR contains ADC1 conversion
		1554	* result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
		1555	* conversion result (ADC1 register DR bits 16 to 27). Therefore, to
		1556	* have DMA transferring the conversion results of ADC1 only, DMA must
		1557	* be configured to transfer size: half word.
		1558	* @param hadc: ADC handle
		1559	* @param pData: The destination Buffer address.
		1560	* @param Length: The length of data to be transferred from ADC peripheral to memory.
		1561	* @retval None
		1562	*/
		1563	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
		1564	{
		1565	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
		1566
		1567	/* Check the parameters */
		1568	assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
		1569
		1570	/* Verification if multimode is disabled (for devices with several ADC) */
		1571	/* If multimode is enabled, dedicated function multimode conversion */
		1572	/* start DMA must be used. */
		1573	if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
		1574	{
		1575	/* Process locked */
		1576	__HAL_LOCK(hadc);
		1577
		1578	/* Enable the ADC peripheral */
		1579	tmp_hal_status = ADC_Enable(hadc);
		1580
		1581	/* Start conversion if ADC is effectively enabled */
		1582	if (tmp_hal_status == HAL_OK)
		1583	{
		1584	/* Set ADC state */
		1585	/* - Clear state bitfield related to regular group conversion results */
		1586	/* - Set state bitfield related to regular operation */
		1587	ADC_STATE_CLR_SET(hadc->State,
		1588	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
		1589	HAL_ADC_STATE_REG_BUSY);
		1590
		1591	/* Set group injected state (from auto-injection) and multimode state */
		1592	/* for all cases of multimode: independent mode, multimode ADC master */
		1593	/* or multimode ADC slave (for devices with several ADCs): */
		1594	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
		1595	{
		1596	/* Set ADC state (ADC independent or master) */
		1597	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
		1598
		1599	/* If conversions on group regular are also triggering group injected, */
		1600	/* update ADC state. */
		1601	if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
		1602	{
		1603	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
		1604	}
		1605	}
		1606	else
		1607	{
		1608	/* Set ADC state (ADC slave) */
		1609	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
		1610
		1611	/* If conversions on group regular are also triggering group injected, */
		1612	/* update ADC state. */
		1613	if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
		1614	{
		1615	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
		1616	}
		1617	}
		1618
		1619	/* State machine update: Check if an injected conversion is ongoing */
		1620	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
		1621	{
		1622	/* Reset ADC error code fields related to conversions on group regular */
		1623	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
		1624	}
		1625	else
		1626	{
		1627	/* Reset ADC all error code fields */
		1628	ADC_CLEAR_ERRORCODE(hadc);
		1629	}
		1630
		1631	/* Process unlocked */
		1632	/* Unlock before starting ADC conversions: in case of potential */
		1633	/* interruption, to let the process to ADC IRQ Handler. */
		1634	__HAL_UNLOCK(hadc);
		1635
		1636	/* Set the DMA transfer complete callback */
		1637	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
		1638
		1639	/* Set the DMA half transfer complete callback */
		1640	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
		1641
		1642	/* Set the DMA error callback */
		1643	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
		1644
		1645
		1646	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
		1647	/* start (in case of SW start): */
		1648
		1649	/* Clear regular group conversion flag and overrun flag */
		1650	/* (To ensure of no unknown state from potential previous ADC */
		1651	/* operations) */
		1652	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
		1653
		1654	/* Enable ADC DMA mode */
		1655	SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
		1656
		1657	/* Start the DMA channel */
		1658	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
		1659
		1660	/* Enable conversion of regular group. */
		1661	/* If software start has been selected, conversion starts immediately. */
		1662	/* If external trigger has been selected, conversion will start at next */
		1663	/* trigger event. */
		1664	if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
		1665	{
		1666	/* Start ADC conversion on regular group with SW start */
		1667	SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
		1668	}
		1669	else
		1670	{
		1671	/* Start ADC conversion on regular group with external trigger */
		1672	SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
		1673	}
		1674	}
		1675	else
		1676	{
		1677	/* Process unlocked */
		1678	__HAL_UNLOCK(hadc);
		1679	}
		1680	}
		1681	else
		1682	{
		1683	tmp_hal_status = HAL_ERROR;
		1684	}
		1685
		1686	/* Return function status */
		1687	return tmp_hal_status;
		1688	}
		1689
		1690	/**
		1691	* @brief Stop ADC conversion of regular group (and injected group in
		1692	* case of auto_injection mode), disable ADC DMA transfer, disable
		1693	* ADC peripheral.
		1694	* @note: ADC peripheral disable is forcing stop of potential
		1695	* conversion on injected group. If injected group is under use, it
		1696	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
		1697	* @note For devices with several ADCs: This function is for single-ADC mode
		1698	* only. For multimode, use the dedicated MultimodeStop function.
		1699	* @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
		1700	* on devices) have DMA capability.
		1701	* @param hadc: ADC handle
		1702	* @retval HAL status.
		1703	*/
		1704	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
		1705	{
		1706	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
		1707
		1708	/* Check the parameters */
		1709	assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
		1710
		1711	/* Process locked */
		1712	__HAL_LOCK(hadc);
		1713
		1714	/* Stop potential conversion on going, on regular and injected groups */
		1715	/* Disable ADC peripheral */
		1716	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
		1717
		1718	/* Check if ADC is effectively disabled */
		1719	if (tmp_hal_status == HAL_OK)
		1720	{
		1721	/* Disable ADC DMA mode */
		1722	CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
		1723
		1724	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
		1725	/* DMA transfer is on going) */
		1726	if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
		1727	{
		1728	tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
		1729
		1730	/* Check if DMA channel effectively disabled */
		1731	if (tmp_hal_status == HAL_OK)
		1732	{
		1733	/* Set ADC state */
		1734	ADC_STATE_CLR_SET(hadc->State,
		1735	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
		1736	HAL_ADC_STATE_READY);
		1737	}
		1738	else
		1739	{
		1740	/* Update ADC state machine to error */
		1741	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
		1742	}
		1743	}
		1744	}
		1745
		1746	/* Process unlocked */
		1747	__HAL_UNLOCK(hadc);
		1748
		1749	/* Return function status */
		1750	return tmp_hal_status;
		1751	}
		1752
		1753	/**
		1754	* @brief Get ADC regular group conversion result.
		1755	* @note Reading register DR automatically clears ADC flag EOC
		1756	* (ADC group regular end of unitary conversion).
		1757	* @note This function does not clear ADC flag EOS
		1758	* (ADC group regular end of sequence conversion).
		1759	* Occurrence of flag EOS rising:
		1760	* - If sequencer is composed of 1 rank, flag EOS is equivalent
		1761	* to flag EOC.
		1762	* - If sequencer is composed of several ranks, during the scan
		1763	* sequence flag EOC only is raised, at the end of the scan sequence
		1764	* both flags EOC and EOS are raised.
		1765	* To clear this flag, either use function:
		1766	* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
		1767	* model polling: @ref HAL_ADC_PollForConversion()
		1768	* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
		1769	* @param hadc: ADC handle
		1770	* @retval ADC group regular conversion data
		1771	*/
		1772	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
		1773	{
		1774	/* Check the parameters */
		1775	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		1776
		1777	/* Note: EOC flag is not cleared here by software because automatically */
		1778	/* cleared by hardware when reading register DR. */
		1779
		1780	/* Return ADC converted value */
		1781	return hadc->Instance->DR;
		1782	}
		1783
		1784	/**
		1785	* @brief Handles ADC interrupt request
		1786	* @param hadc: ADC handle
		1787	* @retval None
		1788	*/
		1789	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
		1790	{
		1791	/* Check the parameters */
		1792	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		1793	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
		1794	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
		1795
		1796
		1797	/* ========== Check End of Conversion flag for regular group ========== */
		1798	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
		1799	{
		1800	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
		1801	{
		1802	/* Update state machine on conversion status if not in error state */
		1803	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
		1804	{
		1805	/* Set ADC state */
		1806	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
		1807	}
		1808
		1809	/* Determine whether any further conversion upcoming on group regular */
		1810	/* by external trigger, continuous mode or scan sequence on going. */
		1811	/* Note: On STM32F1 devices, in case of sequencer enabled */
		1812	/* (several ranks selected), end of conversion flag is raised */
		1813	/* at the end of the sequence. */
		1814	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
		1815	(hadc->Init.ContinuousConvMode == DISABLE) )
		1816	{
		1817	/* Disable ADC end of conversion interrupt on group regular */
		1818	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
		1819
		1820	/* Set ADC state */
		1821	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
		1822
		1823	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
		1824	{
		1825	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
		1826	}
		1827	}
		1828
		1829	/* Conversion complete callback */
		1830	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		1831	hadc->ConvCpltCallback(hadc);
		1832	#else
		1833	HAL_ADC_ConvCpltCallback(hadc);
		1834	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		1835
		1836	/* Clear regular group conversion flag */
		1837	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
		1838	}
		1839	}
		1840
		1841	/* ========== Check End of Conversion flag for injected group ========== */
		1842	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
		1843	{
		1844	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
		1845	{
		1846	/* Update state machine on conversion status if not in error state */
		1847	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
		1848	{
		1849	/* Set ADC state */
		1850	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
		1851	}
		1852
		1853	/* Determine whether any further conversion upcoming on group injected */
		1854	/* by external trigger, scan sequence on going or by automatic injected */
		1855	/* conversion from group regular (same conditions as group regular */
		1856	/* interruption disabling above). */
		1857	/* Note: On STM32F1 devices, in case of sequencer enabled */
		1858	/* (several ranks selected), end of conversion flag is raised */
		1859	/* at the end of the sequence. */
		1860	if(ADC_IS_SOFTWARE_START_INJECTED(hadc) \|\|
		1861	(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
		1862	(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
		1863	(hadc->Init.ContinuousConvMode == DISABLE) ) ) )
		1864	{
		1865	/* Disable ADC end of conversion interrupt on group injected */
		1866	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
		1867
		1868	/* Set ADC state */
		1869	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
		1870
		1871	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
		1872	{
		1873	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
		1874	}
		1875	}
		1876
		1877	/* Conversion complete callback */
		1878	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		1879	hadc->InjectedConvCpltCallback(hadc);
		1880	#else
		1881	HAL_ADCEx_InjectedConvCpltCallback(hadc);
		1882	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		1883
		1884	/* Clear injected group conversion flag */
		1885	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT \| ADC_FLAG_JEOC));
		1886	}
		1887	}
		1888
		1889	/* ========== Check Analog watchdog flags ========== */
		1890	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
		1891	{
		1892	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
		1893	{
		1894	/* Set ADC state */
		1895	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
		1896
		1897	/* Level out of window callback */
		1898	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		1899	hadc->LevelOutOfWindowCallback(hadc);
		1900	#else
		1901	HAL_ADC_LevelOutOfWindowCallback(hadc);
		1902	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		1903
		1904	/* Clear the ADC analog watchdog flag */
		1905	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
		1906	}
		1907	}
		1908
		1909	}
		1910
		1911	/**
		1912	* @brief Conversion complete callback in non blocking mode
		1913	* @param hadc: ADC handle
		1914	* @retval None
		1915	*/
		1916	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
		1917	{
		1918	/* Prevent unused argument(s) compilation warning */
		1919	UNUSED(hadc);
		1920	/* NOTE : This function should not be modified. When the callback is needed,
		1921	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
		1922	*/
		1923	}
		1924
		1925	/**
		1926	* @brief Conversion DMA half-transfer callback in non blocking mode
		1927	* @param hadc: ADC handle
		1928	* @retval None
		1929	*/
		1930	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
		1931	{
		1932	/* Prevent unused argument(s) compilation warning */
		1933	UNUSED(hadc);
		1934	/* NOTE : This function should not be modified. When the callback is needed,
		1935	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
		1936	*/
		1937	}
		1938
		1939	/**
		1940	* @brief Analog watchdog callback in non blocking mode.
		1941	* @param hadc: ADC handle
		1942	* @retval None
		1943	*/
		1944	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
		1945	{
		1946	/* Prevent unused argument(s) compilation warning */
		1947	UNUSED(hadc);
		1948	/* NOTE : This function should not be modified. When the callback is needed,
		1949	function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
		1950	*/
		1951	}
		1952
		1953	/**
		1954	* @brief ADC error callback in non blocking mode
		1955	* (ADC conversion with interruption or transfer by DMA)
		1956	* @param hadc: ADC handle
		1957	* @retval None
		1958	*/
		1959	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
		1960	{
		1961	/* Prevent unused argument(s) compilation warning */
		1962	UNUSED(hadc);
		1963	/* NOTE : This function should not be modified. When the callback is needed,
		1964	function HAL_ADC_ErrorCallback must be implemented in the user file.
		1965	*/
		1966	}
		1967
		1968
		1969	/**
		1970	* @}
		1971	*/
		1972
		1973	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
		1974	* @brief Peripheral Control functions
		1975	*
		1976	@verbatim
		1977	===============================================================================
		1978	##### Peripheral Control functions #####
		1979	===============================================================================
		1980	[..] This section provides functions allowing to:
		1981	(+) Configure channels on regular group
		1982	(+) Configure the analog watchdog
		1983
		1984	@endverbatim
		1985	* @{
		1986	*/
		1987
		1988	/**
		1989	* @brief Configures the the selected channel to be linked to the regular
		1990	* group.
		1991	* @note In case of usage of internal measurement channels:
		1992	* Vbat/VrefInt/TempSensor.
		1993	* These internal paths can be be disabled using function
		1994	* HAL_ADC_DeInit().
		1995	* @note Possibility to update parameters on the fly:
		1996	* This function initializes channel into regular group, following
		1997	* calls to this function can be used to reconfigure some parameters
		1998	* of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
		1999	* the ADC.
		2000	* The setting of these parameters is conditioned to ADC state.
		2001	* For parameters constraints, see comments of structure
		2002	* "ADC_ChannelConfTypeDef".
		2003	* @param hadc: ADC handle
		2004	* @param sConfig: Structure of ADC channel for regular group.
		2005	* @retval HAL status
		2006	*/
		2007	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
		2008	{
		2009	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
		2010	__IO uint32_t wait_loop_index = 0U;
		2011
		2012	/* Check the parameters */
		2013	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		2014	assert_param(IS_ADC_CHANNEL(sConfig->Channel));
		2015	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
		2016	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
		2017
		2018	/* Process locked */
		2019	__HAL_LOCK(hadc);
		2020
		2021
		2022	/* Regular sequence configuration */
		2023	/* For Rank 1 to 6 */
		2024	if (sConfig->Rank < 7U)
		2025	{
		2026	MODIFY_REG(hadc->Instance->SQR3 ,
		2027	ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
		2028	ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
		2029	}
		2030	/* For Rank 7 to 12 */
		2031	else if (sConfig->Rank < 13U)
		2032	{
		2033	MODIFY_REG(hadc->Instance->SQR2 ,
		2034	ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
		2035	ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
		2036	}
		2037	/* For Rank 13 to 16 */
		2038	else
		2039	{
		2040	MODIFY_REG(hadc->Instance->SQR1 ,
		2041	ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
		2042	ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
		2043	}
		2044
		2045
		2046	/* Channel sampling time configuration */
		2047	/* For channels 10 to 17 */
		2048	if (sConfig->Channel >= ADC_CHANNEL_10)
		2049	{
		2050	MODIFY_REG(hadc->Instance->SMPR1 ,
		2051	ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
		2052	ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
		2053	}
		2054	else /* For channels 0 to 9 */
		2055	{
		2056	MODIFY_REG(hadc->Instance->SMPR2 ,
		2057	ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
		2058	ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
		2059	}
		2060
		2061	/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
		2062	/* and VREFINT measurement path. */
		2063	if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) \|\|
		2064	(sConfig->Channel == ADC_CHANNEL_VREFINT) )
		2065	{
		2066	/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
		2067	/* measurement channels (VrefInt/TempSensor). If these channels are */
		2068	/* intended to be set on other ADC instances, an error is reported. */
		2069	if (hadc->Instance == ADC1)
		2070	{
		2071	if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
		2072	{
		2073	SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
		2074
		2075	if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
		2076	{
		2077	/* Delay for temperature sensor stabilization time */
		2078	/* Compute number of CPU cycles to wait for */
		2079	wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
		2080	while(wait_loop_index != 0U)
		2081	{
		2082	wait_loop_index--;
		2083	}
		2084	}
		2085	}
		2086	}
		2087	else
		2088	{
		2089	/* Update ADC state machine to error */
		2090	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
		2091
		2092	tmp_hal_status = HAL_ERROR;
		2093	}
		2094	}
		2095
		2096	/* Process unlocked */
		2097	__HAL_UNLOCK(hadc);
		2098
		2099	/* Return function status */
		2100	return tmp_hal_status;
		2101	}
		2102
		2103	/**
		2104	* @brief Configures the analog watchdog.
		2105	* @note Analog watchdog thresholds can be modified while ADC conversion
		2106	* is on going.
		2107	* In this case, some constraints must be taken into account:
		2108	* the programmed threshold values are effective from the next
		2109	* ADC EOC (end of unitary conversion).
		2110	* Considering that registers write delay may happen due to
		2111	* bus activity, this might cause an uncertainty on the
		2112	* effective timing of the new programmed threshold values.
		2113	* @param hadc: ADC handle
		2114	* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
		2115	* @retval HAL status
		2116	*/
		2117	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
		2118	{
		2119	/* Check the parameters */
		2120	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
		2121	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
		2122	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
		2123	assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
		2124	assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
		2125
		2126	if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\|
		2127	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\|
		2128	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
		2129	{
		2130	assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
		2131	}
		2132
		2133	/* Process locked */
		2134	__HAL_LOCK(hadc);
		2135
		2136	/* Analog watchdog configuration */
		2137
		2138	/* Configure ADC Analog watchdog interrupt */
		2139	if(AnalogWDGConfig->ITMode == ENABLE)
		2140	{
		2141	/* Enable the ADC Analog watchdog interrupt */
		2142	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
		2143	}
		2144	else
		2145	{
		2146	/* Disable the ADC Analog watchdog interrupt */
		2147	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
		2148	}
		2149
		2150	/* Configuration of analog watchdog: */
		2151	/* - Set the analog watchdog enable mode: regular and/or injected groups, */
		2152	/* one or all channels. */
		2153	/* - Set the Analog watchdog channel (is not used if watchdog */
		2154	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
		2155	MODIFY_REG(hadc->Instance->CR1 ,
		2156	ADC_CR1_AWDSGL \|
		2157	ADC_CR1_JAWDEN \|
		2158	ADC_CR1_AWDEN \|
		2159	ADC_CR1_AWDCH ,
		2160	AnalogWDGConfig->WatchdogMode \|
		2161	AnalogWDGConfig->Channel );
		2162
		2163	/* Set the high threshold */
		2164	WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
		2165
		2166	/* Set the low threshold */
		2167	WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
		2168
		2169	/* Process unlocked */
		2170	__HAL_UNLOCK(hadc);
		2171
		2172	/* Return function status */
		2173	return HAL_OK;
		2174	}
		2175
		2176
		2177	/**
		2178	* @}
		2179	*/
		2180
		2181
		2182	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
		2183	* @brief Peripheral State functions
		2184	*
		2185	@verbatim
		2186	===============================================================================
		2187	##### Peripheral State and Errors functions #####
		2188	===============================================================================
		2189	[..]
		2190	This subsection provides functions to get in run-time the status of the
		2191	peripheral.
		2192	(+) Check the ADC state
		2193	(+) Check the ADC error code
		2194
		2195	@endverbatim
		2196	* @{
		2197	*/
		2198
		2199	/**
		2200	* @brief return the ADC state
		2201	* @param hadc: ADC handle
		2202	* @retval HAL state
		2203	*/
		2204	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
		2205	{
		2206	/* Return ADC state */
		2207	return hadc->State;
		2208	}
		2209
		2210	/**
		2211	* @brief Return the ADC error code
		2212	* @param hadc: ADC handle
		2213	* @retval ADC Error Code
		2214	*/
		2215	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
		2216	{
		2217	return hadc->ErrorCode;
		2218	}
		2219
		2220	/**
		2221	* @}
		2222	*/
		2223
		2224	/**
		2225	* @}
		2226	*/
		2227
		2228	/** @defgroup ADC_Private_Functions ADC Private Functions
		2229	* @{
		2230	*/
		2231
		2232	/**
		2233	* @brief Enable the selected ADC.
		2234	* @note Prerequisite condition to use this function: ADC must be disabled
		2235	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
		2236	* @param hadc: ADC handle
		2237	* @retval HAL status.
		2238	*/
		2239	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
		2240	{
		2241	uint32_t tickstart = 0U;
		2242	__IO uint32_t wait_loop_index = 0U;
		2243
		2244	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
		2245	/* enabling phase not yet completed: flag ADC ready not yet set). */
		2246	/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
		2247	/* causes: ADC clock not running, ...). */
		2248	if (ADC_IS_ENABLE(hadc) == RESET)
		2249	{
		2250	/* Enable the Peripheral */
		2251	__HAL_ADC_ENABLE(hadc);
		2252
		2253	/* Delay for ADC stabilization time */
		2254	/* Compute number of CPU cycles to wait for */
		2255	wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
		2256	while(wait_loop_index != 0U)
		2257	{
		2258	wait_loop_index--;
		2259	}
		2260
		2261	/* Get tick count */
		2262	tickstart = HAL_GetTick();
		2263
		2264	/* Wait for ADC effectively enabled */
		2265	while(ADC_IS_ENABLE(hadc) == RESET)
		2266	{
		2267	if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
		2268	{
		2269	/* New check to avoid false timeout detection in case of preemption */
		2270	if(ADC_IS_ENABLE(hadc) == RESET)
		2271	{
		2272	/* Update ADC state machine to error */
		2273	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
		2274
		2275	/* Set ADC error code to ADC IP internal error */
		2276	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
		2277
		2278	/* Process unlocked */
		2279	__HAL_UNLOCK(hadc);
		2280
		2281	return HAL_ERROR;
		2282	}
		2283	}
		2284	}
		2285	}
		2286
		2287	/* Return HAL status */
		2288	return HAL_OK;
		2289	}
		2290
		2291	/**
		2292	* @brief Stop ADC conversion and disable the selected ADC
		2293	* @note Prerequisite condition to use this function: ADC conversions must be
		2294	* stopped to disable the ADC.
		2295	* @param hadc: ADC handle
		2296	* @retval HAL status.
		2297	*/
		2298	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
		2299	{
		2300	uint32_t tickstart = 0U;
		2301
		2302	/* Verification if ADC is not already disabled */
		2303	if (ADC_IS_ENABLE(hadc) != RESET)
		2304	{
		2305	/* Disable the ADC peripheral */
		2306	__HAL_ADC_DISABLE(hadc);
		2307
		2308	/* Get tick count */
		2309	tickstart = HAL_GetTick();
		2310
		2311	/* Wait for ADC effectively disabled */
		2312	while(ADC_IS_ENABLE(hadc) != RESET)
		2313	{
		2314	if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
		2315	{
		2316	/* New check to avoid false timeout detection in case of preemption */
		2317	if(ADC_IS_ENABLE(hadc) != RESET)
		2318	{
		2319	/* Update ADC state machine to error */
		2320	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
		2321
		2322	/* Set ADC error code to ADC IP internal error */
		2323	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
		2324
		2325	return HAL_ERROR;
		2326	}
		2327	}
		2328	}
		2329	}
		2330
		2331	/* Return HAL status */
		2332	return HAL_OK;
		2333	}
		2334
		2335	/**
		2336	* @brief DMA transfer complete callback.
		2337	* @param hdma: pointer to DMA handle.
		2338	* @retval None
		2339	*/
		2340	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
		2341	{
		2342	/* Retrieve ADC handle corresponding to current DMA handle */
		2343	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2344
		2345	/* Update state machine on conversion status if not in error state */
		2346	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL \| HAL_ADC_STATE_ERROR_DMA))
		2347	{
		2348	/* Update ADC state machine */
		2349	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
		2350
		2351	/* Determine whether any further conversion upcoming on group regular */
		2352	/* by external trigger, continuous mode or scan sequence on going. */
		2353	/* Note: On STM32F1 devices, in case of sequencer enabled */
		2354	/* (several ranks selected), end of conversion flag is raised */
		2355	/* at the end of the sequence. */
		2356	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
		2357	(hadc->Init.ContinuousConvMode == DISABLE) )
		2358	{
		2359	/* Set ADC state */
		2360	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
		2361
		2362	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
		2363	{
		2364	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
		2365	}
		2366	}
		2367
		2368	/* Conversion complete callback */
		2369	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		2370	hadc->ConvCpltCallback(hadc);
		2371	#else
		2372	HAL_ADC_ConvCpltCallback(hadc);
		2373	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		2374	}
		2375	else
		2376	{
		2377	/* Call DMA error callback */
		2378	hadc->DMA_Handle->XferErrorCallback(hdma);
		2379	}
		2380	}
		2381
		2382	/**
		2383	* @brief DMA half transfer complete callback.
		2384	* @param hdma: pointer to DMA handle.
		2385	* @retval None
		2386	*/
		2387	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
		2388	{
		2389	/* Retrieve ADC handle corresponding to current DMA handle */
		2390	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2391
		2392	/* Half conversion callback */
		2393	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		2394	hadc->ConvHalfCpltCallback(hadc);
		2395	#else
		2396	HAL_ADC_ConvHalfCpltCallback(hadc);
		2397	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		2398	}
		2399
		2400	/**
		2401	* @brief DMA error callback
		2402	* @param hdma: pointer to DMA handle.
		2403	* @retval None
		2404	*/
		2405	void ADC_DMAError(DMA_HandleTypeDef *hdma)
		2406	{
		2407	/* Retrieve ADC handle corresponding to current DMA handle */
		2408	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
		2409
		2410	/* Set ADC state */
		2411	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
		2412
		2413	/* Set ADC error code to DMA error */
		2414	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
		2415
		2416	/* Error callback */
		2417	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		2418	hadc->ErrorCallback(hadc);
		2419	#else
		2420	HAL_ADC_ErrorCallback(hadc);
		2421	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		2422	}
		2423
		2424	/**
		2425	* @}
		2426	*/
		2427
		2428	#endif /* HAL_ADC_MODULE_ENABLED */
		2429	/**
		2430	* @}
		2431	*/
		2432
		2433	/**
		2434	* @}
		2435	*/
		2436
		2437	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c – Rev 2