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/**
2
  ******************************************************************************
3
  * @file    stm32f1xx_hal_adc.c
4
  * @author  MCD Application Team
5
  * @brief   This file provides firmware functions to manage the following
6
  *          functionalities of the Analog to Digital Convertor (ADC)
7
  *          peripheral:
8
  *           + Initialization and de-initialization functions
9
  *           + Peripheral Control functions
10
  *           + Peripheral State functions
11
  *          Other functions (extended functions) are available in file
12
  *          "stm32f1xx_hal_adc_ex.c".
13
  *
14
  ******************************************************************************
15
  * @attention
16
  *
17
  * Copyright (c) 2016 STMicroelectronics.
18
  * All rights reserved.
19
  *
20
  * This software is licensed under terms that can be found in the LICENSE file
21
  * in the root directory of this software component.
22
  * If no LICENSE file comes with this software, it is provided AS-IS.
23
  *
24
  ******************************************************************************
25
  @verbatim
26
  ==============================================================================
27
                     ##### ADC peripheral features #####
28
  ==============================================================================
29
  [..]
30
  (+) 12-bit resolution
31
 
32
  (+) Interrupt generation at the end of regular conversion, end of injected
33
      conversion, and in case of analog watchdog or overrun events.
34
 
35
  (+) Single and continuous conversion modes.
36
 
37
  (+) Scan mode for conversion of several channels sequentially.
38
 
39
  (+) Data alignment with in-built data coherency.
40
 
41
  (+) Programmable sampling time (channel wise)
42
 
43
  (+) ADC conversion of regular group and injected group.
44
 
45
  (+) External trigger (timer or EXTI)
46
      for both regular and injected groups.
47
 
48
  (+) DMA request generation for transfer of conversions data of regular group.
49
 
50
  (+) Multimode Dual mode (available on devices with 2 ADCs or more).
51
 
52
  (+) Configurable DMA data storage in Multimode Dual mode (available on devices
53
      with 2 DCs or more).
54
 
55
  (+) Configurable delay between conversions in Dual interleaved mode (available
56
      on devices with 2 DCs or more).
57
 
58
  (+) ADC calibration
59
 
60
  (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
61
      slower speed.
62
 
63
  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
64
      Vdda or to an external voltage reference).
65
 
66
 
67
                     ##### How to use this driver #####
68
  ==============================================================================
69
    [..]
70
 
71
     *** Configuration of top level parameters related to ADC ***
72
     ============================================================
73
     [..]
74
 
75
    (#) Enable the ADC interface
76
      (++) As prerequisite, ADC clock must be configured at RCC top level.
77
           Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
78
                    to device datasheet).
79
                    Therefore, ADC clock prescaler must be configured in
80
                    function of ADC clock source frequency to remain below
81
                    this maximum frequency.
82
        (++) One clock setting is mandatory:
83
             ADC clock (core clock, also possibly conversion clock).
84
             (+++) Example:
85
                   Into HAL_ADC_MspInit() (recommended code location) or with
86
                   other device clock parameters configuration:
87
               (+++) RCC_PeriphCLKInitTypeDef  PeriphClkInit;
88
               (+++) __ADC1_CLK_ENABLE();
89
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
90
               (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
91
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
92
 
93
    (#) ADC pins configuration
94
         (++) Enable the clock for the ADC GPIOs
95
              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
96
         (++) Configure these ADC pins in analog mode
97
              using function HAL_GPIO_Init()
98
 
99
    (#) Optionally, in case of usage of ADC with interruptions:
100
         (++) Configure the NVIC for ADC
101
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
102
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
103
              into the function of corresponding ADC interruption vector
104
              ADCx_IRQHandler().
105
 
106
    (#) Optionally, in case of usage of DMA:
107
         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
108
              using function HAL_DMA_Init().
109
         (++) Configure the NVIC for DMA
110
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
111
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
112
              into the function of corresponding DMA interruption vector
113
              DMAx_Channelx_IRQHandler().
114
 
115
     *** Configuration of ADC, groups regular/injected, channels parameters ***
116
     ==========================================================================
117
     [..]
118
 
119
    (#) Configure the ADC parameters (resolution, data alignment, ...)
120
        and regular group parameters (conversion trigger, sequencer, ...)
121
        using function HAL_ADC_Init().
122
 
123
    (#) Configure the channels for regular group parameters (channel number,
124
        channel rank into sequencer, ..., into regular group)
125
        using function HAL_ADC_ConfigChannel().
126
 
127
    (#) Optionally, configure the injected group parameters (conversion trigger,
128
        sequencer, ..., of injected group)
129
        and the channels for injected group parameters (channel number,
130
        channel rank into sequencer, ..., into injected group)
131
        using function HAL_ADCEx_InjectedConfigChannel().
132
 
133
    (#) Optionally, configure the analog watchdog parameters (channels
134
        monitored, thresholds, ...)
135
        using function HAL_ADC_AnalogWDGConfig().
136
 
137
    (#) Optionally, for devices with several ADC instances: configure the
138
        multimode parameters
139
        using function HAL_ADCEx_MultiModeConfigChannel().
140
 
141
     *** Execution of ADC conversions ***
142
     ====================================
143
     [..]
144
 
145
    (#) Optionally, perform an automatic ADC calibration to improve the
146
        conversion accuracy
147
        using function HAL_ADCEx_Calibration_Start().
148
 
149
    (#) ADC driver can be used among three modes: polling, interruption,
150
        transfer by DMA.
151
 
152
        (++) ADC conversion by polling:
153
          (+++) Activate the ADC peripheral and start conversions
154
                using function HAL_ADC_Start()
155
          (+++) Wait for ADC conversion completion
156
                using function HAL_ADC_PollForConversion()
157
                (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
158
          (+++) Retrieve conversion results
159
                using function HAL_ADC_GetValue()
160
                (or for injected group: HAL_ADCEx_InjectedGetValue() )
161
          (+++) Stop conversion and disable the ADC peripheral
162
                using function HAL_ADC_Stop()
163
 
164
        (++) ADC conversion by interruption:
165
          (+++) Activate the ADC peripheral and start conversions
166
                using function HAL_ADC_Start_IT()
167
          (+++) Wait for ADC conversion completion by call of function
168
                HAL_ADC_ConvCpltCallback()
169
                (this function must be implemented in user program)
170
                (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
171
          (+++) Retrieve conversion results
172
                using function HAL_ADC_GetValue()
173
                (or for injected group: HAL_ADCEx_InjectedGetValue() )
174
          (+++) Stop conversion and disable the ADC peripheral
175
                using function HAL_ADC_Stop_IT()
176
 
177
        (++) ADC conversion with transfer by DMA:
178
          (+++) Activate the ADC peripheral and start conversions
179
                using function HAL_ADC_Start_DMA()
180
          (+++) Wait for ADC conversion completion by call of function
181
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
182
                (these functions must be implemented in user program)
183
          (+++) Conversion results are automatically transferred by DMA into
184
                destination variable address.
185
          (+++) Stop conversion and disable the ADC peripheral
186
                using function HAL_ADC_Stop_DMA()
187
 
188
        (++) For devices with several ADCs: ADC multimode conversion
189
             with transfer by DMA:
190
          (+++) Activate the ADC peripheral (slave) and start conversions
191
                using function HAL_ADC_Start()
192
          (+++) Activate the ADC peripheral (master) and start conversions
193
                using function HAL_ADCEx_MultiModeStart_DMA()
194
          (+++) Wait for ADC conversion completion by call of function
195
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
196
                (these functions must be implemented in user program)
197
          (+++) Conversion results are automatically transferred by DMA into
198
                destination variable address.
199
          (+++) Stop conversion and disable the ADC peripheral (master)
200
                using function HAL_ADCEx_MultiModeStop_DMA()
201
          (+++) Stop conversion and disable the ADC peripheral (slave)
202
                using function HAL_ADC_Stop_IT()
203
 
204
     [..]
205
 
206
    (@) Callback functions must be implemented in user program:
207
      (+@) HAL_ADC_ErrorCallback()
208
      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
209
      (+@) HAL_ADC_ConvCpltCallback()
210
      (+@) HAL_ADC_ConvHalfCpltCallback
211
      (+@) HAL_ADCEx_InjectedConvCpltCallback()
212
 
213
     *** Deinitialization of ADC ***
214
     ============================================================
215
     [..]
216
 
217
    (#) Disable the ADC interface
218
      (++) ADC clock can be hard reset and disabled at RCC top level.
219
        (++) Hard reset of ADC peripherals
220
             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
221
        (++) ADC clock disable
222
             using the equivalent macro/functions as configuration step.
223
             (+++) Example:
224
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
225
                   other device clock parameters configuration:
226
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
227
               (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
228
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
229
 
230
    (#) ADC pins configuration
231
         (++) Disable the clock for the ADC GPIOs
232
              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
233
 
234
    (#) Optionally, in case of usage of ADC with interruptions:
235
         (++) Disable the NVIC for ADC
236
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
237
 
238
    (#) Optionally, in case of usage of DMA:
239
         (++) Deinitialize the DMA
240
              using function HAL_DMA_Init().
241
         (++) Disable the NVIC for DMA
242
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
243
 
244
    [..]
245
 
246
    *** Callback registration ***
247
    =============================================
248
    [..]
249
 
250
     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
251
     allows the user to configure dynamically the driver callbacks.
252
     Use Functions HAL_ADC_RegisterCallback()
253
     to register an interrupt callback.
254
    [..]
255
 
256
     Function HAL_ADC_RegisterCallback() allows to register following callbacks:
257
       (+) ConvCpltCallback               : ADC conversion complete callback
258
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
259
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
260
       (+) ErrorCallback                  : ADC error callback
261
       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
262
       (+) MspInitCallback                : ADC Msp Init callback
263
       (+) MspDeInitCallback              : ADC Msp DeInit callback
264
     This function takes as parameters the HAL peripheral handle, the Callback ID
265
     and a pointer to the user callback function.
266
    [..]
267
 
268
     Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
269
     weak function.
270
    [..]
271
 
272
     HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
273
     and the Callback ID.
274
     This function allows to reset following callbacks:
275
       (+) ConvCpltCallback               : ADC conversion complete callback
276
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
277
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
278
       (+) ErrorCallback                  : ADC error callback
279
       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
280
       (+) MspInitCallback                : ADC Msp Init callback
281
       (+) MspDeInitCallback              : ADC Msp DeInit callback
282
     [..]
283
 
284
     By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
285
     all callbacks are set to the corresponding weak functions:
286
     examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
287
     Exception done for MspInit and MspDeInit functions that are
288
     reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
289
     these callbacks are null (not registered beforehand).
290
    [..]
291
 
292
     If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
293
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
294
     [..]
295
 
296
     Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
297
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
298
     in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
299
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
300
    [..]
301
 
302
     Then, the user first registers the MspInit/MspDeInit user callbacks
303
     using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
304
     or HAL_ADC_Init() function.
305
     [..]
306
 
307
     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
308
     not defined, the callback registration feature is not available and all callbacks
309
     are set to the corresponding weak functions.
310
 
311
  @endverbatim
312
  */
313
 
314
/* Includes ------------------------------------------------------------------*/
315
#include "stm32f1xx_hal.h"
316
 
317
/** @addtogroup STM32F1xx_HAL_Driver
318
  * @{
319
  */
320
 
321
/** @defgroup ADC ADC
322
  * @brief ADC HAL module driver
323
  * @{
324
  */
325
 
326
#ifdef HAL_ADC_MODULE_ENABLED
327
 
328
/* Private typedef -----------------------------------------------------------*/
329
/* Private define ------------------------------------------------------------*/
330
/** @defgroup ADC_Private_Constants ADC Private Constants
331
  * @{
332
  */
333
 
334
  /* Timeout values for ADC enable and disable settling time.                 */
335
  /* Values defined to be higher than worst cases: low clocks freq,           */
336
  /* maximum prescaler.                                                       */
337
  /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
338
  /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits.    */
339
  /* Unit: ms                                                                 */
340
  #define ADC_ENABLE_TIMEOUT              2U
341
  #define ADC_DISABLE_TIMEOUT             2U
342
 
343
  /* Delay for ADC stabilization time.                                        */
344
  /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
345
  /* Unit: us                                                                 */
346
  #define ADC_STAB_DELAY_US               1U
347
 
348
  /* Delay for temperature sensor stabilization time.                         */
349
  /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
350
  /* Unit: us                                                                 */
351
  #define ADC_TEMPSENSOR_DELAY_US         10U
352
 
353
/**
354
  * @}
355
  */
356
 
357
/* Private macro -------------------------------------------------------------*/
358
/* Private variables ---------------------------------------------------------*/
359
/* Private function prototypes -----------------------------------------------*/
360
/** @defgroup ADC_Private_Functions ADC Private Functions
361
  * @{
362
  */
363
/**
364
  * @}
365
  */
366
 
367
/* Exported functions --------------------------------------------------------*/
368
 
369
/** @defgroup ADC_Exported_Functions ADC Exported Functions
370
  * @{
371
  */
372
 
373
/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
374
  * @brief    Initialization and Configuration functions
375
  *
376
@verbatim    
377
 ===============================================================================
378
              ##### Initialization and de-initialization functions #####
379
 ===============================================================================
380
    [..]  This section provides functions allowing to:
381
      (+) Initialize and configure the ADC.
382
      (+) De-initialize the ADC.
383
 
384
@endverbatim
385
  * @{
386
  */
387
 
388
/**
389
  * @brief  Initializes the ADC peripheral and regular group according to  
390
  *         parameters specified in structure "ADC_InitTypeDef".
391
  * @note   As prerequisite, ADC clock must be configured at RCC top level
392
  *         (clock source APB2).
393
  *         See commented example code below that can be copied and uncommented
394
  *         into HAL_ADC_MspInit().
395
  * @note   Possibility to update parameters on the fly:
396
  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
397
  *         coming from ADC state reset. Following calls to this function can
398
  *         be used to reconfigure some parameters of ADC_InitTypeDef  
399
  *         structure on the fly, without modifying MSP configuration. If ADC  
400
  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
401
  *         before HAL_ADC_Init().
402
  *         The setting of these parameters is conditioned to ADC state.
403
  *         For parameters constraints, see comments of structure
404
  *         "ADC_InitTypeDef".
405
  * @note   This function configures the ADC within 2 scopes: scope of entire
406
  *         ADC and scope of regular group. For parameters details, see comments
407
  *         of structure "ADC_InitTypeDef".
408
  * @param  hadc: ADC handle
409
  * @retval HAL status
410
  */
411
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
412
{
413
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
414
  uint32_t tmp_cr1 = 0U;
415
  uint32_t tmp_cr2 = 0U;
416
  uint32_t tmp_sqr1 = 0U;
417
 
418
  /* Check ADC handle */
419
  if(hadc == NULL)
420
  {
421
    return HAL_ERROR;
422
  }
423
 
424
  /* Check the parameters */
425
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
426
  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
427
  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
428
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
429
  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
430
 
431
  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
432
  {
433
    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
434
    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
435
    if(hadc->Init.DiscontinuousConvMode != DISABLE)
436
    {
437
      assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
438
    }
439
  }
440
 
441
  /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured    */
442
  /* at RCC top level.                                                        */
443
  /* Refer to header of this file for more details on clock enabling          */
444
  /* procedure.                                                               */
445
 
446
  /* Actions performed only if ADC is coming from state reset:                */
447
  /* - Initialization of ADC MSP                                              */
448
  if (hadc->State == HAL_ADC_STATE_RESET)
449
  {
450
    /* Initialize ADC error code */
451
    ADC_CLEAR_ERRORCODE(hadc);
452
 
453
    /* Allocate lock resource and initialize it */
454
    hadc->Lock = HAL_UNLOCKED;
455
 
456
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
457
    /* Init the ADC Callback settings */
458
    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
459
    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
460
    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
461
    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
462
    hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
463
 
464
    if (hadc->MspInitCallback == NULL)
465
    {
466
      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
467
    }
468
 
469
    /* Init the low level hardware */
470
    hadc->MspInitCallback(hadc);
471
#else
472
    /* Init the low level hardware */
473
    HAL_ADC_MspInit(hadc);
474
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
475
  }
476
 
477
  /* Stop potential conversion on going, on regular and injected groups */
478
  /* Disable ADC peripheral */
479
  /* Note: In case of ADC already enabled, precaution to not launch an        */
480
  /*       unwanted conversion while modifying register CR2 by writing 1 to   */
481
  /*       bit ADON.                                                          */
482
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
483
 
484
 
485
  /* Configuration of ADC parameters if previous preliminary actions are      */
486
  /* correctly completed.                                                     */
487
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
488
      (tmp_hal_status == HAL_OK)                                  )
489
  {
490
    /* Set ADC state */
491
    ADC_STATE_CLR_SET(hadc->State,
492
                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
493
                      HAL_ADC_STATE_BUSY_INTERNAL);
494
 
495
    /* Set ADC parameters */
496
 
497
    /* Configuration of ADC:                                                  */
498
    /*  - data alignment                                                      */
499
    /*  - external trigger to start conversion                                */
500
    /*  - external trigger polarity (always set to 1, because needed for all  */
501
    /*    triggers: external trigger of SW start)                             */
502
    /*  - continuous conversion mode                                          */
503
    /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into          */
504
    /*       HAL_ADC_Start_xxx functions because if set in this function,     */
505
    /*       a conversion on injected group would start a conversion also on  */
506
    /*       regular group after ADC enabling.                                */
507
    tmp_cr2 |= (hadc->Init.DataAlign                                          |
508
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
509
                ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)   );
510
 
511
    /* Configuration of ADC:                                                  */
512
    /*  - scan mode                                                           */
513
    /*  - discontinuous mode disable/enable                                   */
514
    /*  - discontinuous mode number of conversions                            */
515
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
516
 
517
    /* Enable discontinuous mode only if continuous mode is disabled */
518
    /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter    */
519
    /*       discontinuous is set anyway, but will have no effect on ADC HW.  */
520
    if (hadc->Init.DiscontinuousConvMode == ENABLE)
521
    {
522
      if (hadc->Init.ContinuousConvMode == DISABLE)
523
      {
524
        /* Enable the selected ADC regular discontinuous mode */
525
        /* Set the number of channels to be converted in discontinuous mode */
526
        SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
527
                         ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion)  );
528
      }
529
      else
530
      {
531
        /* ADC regular group settings continuous and sequencer discontinuous*/
532
        /* cannot be enabled simultaneously.                                */
533
 
534
        /* Update ADC state machine to error */
535
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
536
 
537
        /* Set ADC error code to ADC IP internal error */
538
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
539
      }
540
    }
541
 
542
    /* Update ADC configuration register CR1 with previous settings */
543
      MODIFY_REG(hadc->Instance->CR1,
544
                 ADC_CR1_SCAN    |
545
                 ADC_CR1_DISCEN  |
546
                 ADC_CR1_DISCNUM    ,
547
                 tmp_cr1             );
548
 
549
    /* Update ADC configuration register CR2 with previous settings */
550
      MODIFY_REG(hadc->Instance->CR2,
551
                 ADC_CR2_ALIGN   |
552
                 ADC_CR2_EXTSEL  |
553
                 ADC_CR2_EXTTRIG |
554
                 ADC_CR2_CONT       ,
555
                 tmp_cr2             );
556
 
557
    /* Configuration of regular group sequencer:                              */
558
    /* - if scan mode is disabled, regular channels sequence length is set to */
559
    /*   0x00: 1 channel converted (channel on regular rank 1)                */
560
    /*   Parameter "NbrOfConversion" is discarded.                            */
561
    /*   Note: Scan mode is present by hardware on this device and, if        */
562
    /*   disabled, discards automatically nb of conversions. Anyway, nb of    */
563
    /*   conversions is forced to 0x00 for alignment over all STM32 devices.  */
564
    /* - if scan mode is enabled, regular channels sequence length is set to  */
565
    /*   parameter "NbrOfConversion"                                          */
566
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
567
    {
568
      tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
569
    }
570
 
571
    MODIFY_REG(hadc->Instance->SQR1,
572
               ADC_SQR1_L          ,
573
               tmp_sqr1             );
574
 
575
    /* Check back that ADC registers have effectively been configured to      */
576
    /* ensure of no potential problem of ADC core IP clocking.                */
577
    /* Check through register CR2 (excluding bits set in other functions:     */
578
    /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits   */
579
    /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal    */
580
    /* measurement path bit (TSVREFE).                                        */
581
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
582
                                        ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
583
                                        ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
584
                                        ADC_CR2_TSVREFE                     ))
585
         == tmp_cr2)
586
    {
587
      /* Set ADC error code to none */
588
      ADC_CLEAR_ERRORCODE(hadc);
589
 
590
      /* Set the ADC state */
591
      ADC_STATE_CLR_SET(hadc->State,
592
                        HAL_ADC_STATE_BUSY_INTERNAL,
593
                        HAL_ADC_STATE_READY);
594
    }
595
    else
596
    {
597
      /* Update ADC state machine to error */
598
      ADC_STATE_CLR_SET(hadc->State,
599
                        HAL_ADC_STATE_BUSY_INTERNAL,
600
                        HAL_ADC_STATE_ERROR_INTERNAL);
601
 
602
      /* Set ADC error code to ADC IP internal error */
603
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
604
 
605
      tmp_hal_status = HAL_ERROR;
606
    }
607
 
608
  }
609
  else
610
  {
611
    /* Update ADC state machine to error */
612
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
613
 
614
    tmp_hal_status = HAL_ERROR;
615
  }
616
 
617
  /* Return function status */
618
  return tmp_hal_status;
619
}
620
 
621
/**
622
  * @brief  Deinitialize the ADC peripheral registers to their default reset
623
  *         values, with deinitialization of the ADC MSP.
624
  *         If needed, the example code can be copied and uncommented into
625
  *         function HAL_ADC_MspDeInit().
626
  * @param  hadc: ADC handle
627
  * @retval HAL status
628
  */
629
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
630
{
631
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
632
 
633
  /* Check ADC handle */
634
  if(hadc == NULL)
635
  {
636
     return HAL_ERROR;
637
  }
638
 
639
  /* Check the parameters */
640
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
641
 
642
  /* Set ADC state */
643
  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
644
 
645
  /* Stop potential conversion on going, on regular and injected groups */
646
  /* Disable ADC peripheral */
647
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
648
 
649
 
650
  /* Configuration of ADC parameters if previous preliminary actions are      */
651
  /* correctly completed.                                                     */
652
  if (tmp_hal_status == HAL_OK)
653
  {
654
    /* ========== Reset ADC registers ========== */
655
 
656
 
657
 
658
 
659
    /* Reset register SR */
660
    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
661
                                ADC_FLAG_JSTRT | ADC_FLAG_STRT));
662
 
663
    /* Reset register CR1 */
664
    CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN   | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
665
                                    ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO   |
666
                                    ADC_CR1_AWDSGL  | ADC_CR1_SCAN   | ADC_CR1_JEOCIE  |  
667
                                    ADC_CR1_AWDIE   | ADC_CR1_EOCIE  | ADC_CR1_AWDCH    ));
668
 
669
    /* Reset register CR2 */
670
    CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
671
                                    ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL  | ADC_CR2_JEXTTRIG |  
672
                                    ADC_CR2_JEXTSEL | ADC_CR2_ALIGN   | ADC_CR2_DMA      |        
673
                                    ADC_CR2_RSTCAL  | ADC_CR2_CAL     | ADC_CR2_CONT     |          
674
                                    ADC_CR2_ADON                                          ));
675
 
676
    /* Reset register SMPR1 */
677
    CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 |
678
                                      ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 |
679
                                      ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10                    ));
680
 
681
    /* Reset register SMPR2 */
682
    CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
683
                                      ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
684
                                      ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
685
                                      ADC_SMPR2_SMP0                                    ));
686
 
687
    /* Reset register JOFR1 */
688
    CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
689
    /* Reset register JOFR2 */
690
    CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
691
    /* Reset register JOFR3 */
692
    CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
693
    /* Reset register JOFR4 */
694
    CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
695
 
696
    /* Reset register HTR */
697
    CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
698
    /* Reset register LTR */
699
    CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
700
 
701
    /* Reset register SQR1 */
702
    CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L    |
703
                                    ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
704
                                    ADC_SQR1_SQ14 | ADC_SQR1_SQ13  );
705
 
706
    /* Reset register SQR1 */
707
    CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L    |
708
                                    ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
709
                                    ADC_SQR1_SQ14 | ADC_SQR1_SQ13  );
710
 
711
    /* Reset register SQR2 */
712
    CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
713
                                    ADC_SQR2_SQ9  | ADC_SQR2_SQ8  | ADC_SQR2_SQ7   );
714
 
715
    /* Reset register SQR3 */
716
    CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
717
                                    ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1  );
718
 
719
    /* Reset register JSQR */
720
    CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
721
                                    ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
722
                                    ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  );
723
 
724
    /* Reset register JSQR */
725
    CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
726
                                    ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
727
                                    ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  );
728
 
729
    /* Reset register DR */
730
    /* bits in access mode read only, no direct reset applicable*/
731
 
732
    /* Reset registers JDR1, JDR2, JDR3, JDR4 */
733
    /* bits in access mode read only, no direct reset applicable*/
734
 
735
    /* ========== Hard reset ADC peripheral ========== */
736
    /* Performs a global reset of the entire ADC peripheral: ADC state is     */
737
    /* forced to a similar state after device power-on.                       */
738
    /* If needed, copy-paste and uncomment the following reset code into      */
739
    /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)":              */
740
    /*                                                                        */
741
    /*  __HAL_RCC_ADC1_FORCE_RESET()                                          */
742
    /*  __HAL_RCC_ADC1_RELEASE_RESET()                                        */
743
 
744
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
745
    if (hadc->MspDeInitCallback == NULL)
746
    {
747
      hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
748
    }
749
 
750
    /* DeInit the low level hardware */
751
    hadc->MspDeInitCallback(hadc);
752
#else
753
    /* DeInit the low level hardware */
754
    HAL_ADC_MspDeInit(hadc);
755
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
756
 
757
    /* Set ADC error code to none */
758
    ADC_CLEAR_ERRORCODE(hadc);
759
 
760
    /* Set ADC state */
761
    hadc->State = HAL_ADC_STATE_RESET;
762
 
763
  }
764
 
765
  /* Process unlocked */
766
  __HAL_UNLOCK(hadc);
767
 
768
  /* Return function status */
769
  return tmp_hal_status;
770
}
771
 
772
/**
773
  * @brief  Initializes the ADC MSP.
774
  * @param  hadc: ADC handle
775
  * @retval None
776
  */
777
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
778
{
779
  /* Prevent unused argument(s) compilation warning */
780
  UNUSED(hadc);
781
  /* NOTE : This function should not be modified. When the callback is needed,
782
            function HAL_ADC_MspInit must be implemented in the user file.
783
   */
784
}
785
 
786
/**
787
  * @brief  DeInitializes the ADC MSP.
788
  * @param  hadc: ADC handle
789
  * @retval None
790
  */
791
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
792
{
793
  /* Prevent unused argument(s) compilation warning */
794
  UNUSED(hadc);
795
  /* NOTE : This function should not be modified. When the callback is needed,
796
            function HAL_ADC_MspDeInit must be implemented in the user file.
797
   */
798
}
799
 
800
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
801
/**
802
  * @brief  Register a User ADC Callback
803
  *         To be used instead of the weak predefined callback
804
  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
805
  *                the configuration information for the specified ADC.
806
  * @param  CallbackID ID of the callback to be registered
807
  *         This parameter can be one of the following values:
808
  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
809
  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion complete callback ID
810
  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
811
  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
812
  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
813
  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
814
  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
815
  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
816
  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
817
  * @param  pCallback pointer to the Callback function
818
  * @retval HAL status
819
  */
820
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
821
{
822
  HAL_StatusTypeDef status = HAL_OK;
823
 
824
  if (pCallback == NULL)
825
  {
826
    /* Update the error code */
827
    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
828
 
829
    return HAL_ERROR;
830
  }
831
 
832
  if ((hadc->State & HAL_ADC_STATE_READY) != 0)
833
  {
834
    switch (CallbackID)
835
    {
836
      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
837
        hadc->ConvCpltCallback = pCallback;
838
        break;
839
 
840
      case HAL_ADC_CONVERSION_HALF_CB_ID :
841
        hadc->ConvHalfCpltCallback = pCallback;
842
        break;
843
 
844
      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
845
        hadc->LevelOutOfWindowCallback = pCallback;
846
        break;
847
 
848
      case HAL_ADC_ERROR_CB_ID :
849
        hadc->ErrorCallback = pCallback;
850
        break;
851
 
852
      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
853
        hadc->InjectedConvCpltCallback = pCallback;
854
        break;
855
 
856
      case HAL_ADC_MSPINIT_CB_ID :
857
        hadc->MspInitCallback = pCallback;
858
        break;
859
 
860
      case HAL_ADC_MSPDEINIT_CB_ID :
861
        hadc->MspDeInitCallback = pCallback;
862
        break;
863
 
864
      default :
865
        /* Update the error code */
866
        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
867
 
868
        /* Return error status */
869
        status = HAL_ERROR;
870
        break;
871
    }
872
  }
873
  else if (HAL_ADC_STATE_RESET == hadc->State)
874
  {
875
    switch (CallbackID)
876
    {
877
      case HAL_ADC_MSPINIT_CB_ID :
878
        hadc->MspInitCallback = pCallback;
879
        break;
880
 
881
      case HAL_ADC_MSPDEINIT_CB_ID :
882
        hadc->MspDeInitCallback = pCallback;
883
        break;
884
 
885
      default :
886
        /* Update the error code */
887
        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
888
 
889
        /* Return error status */
890
        status = HAL_ERROR;
891
        break;
892
    }
893
  }
894
  else
895
  {
896
    /* Update the error code */
897
    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
898
 
899
    /* Return error status */
900
    status =  HAL_ERROR;
901
  }
902
 
903
  return status;
904
}
905
 
906
/**
907
  * @brief  Unregister a ADC Callback
908
  *         ADC callback is redirected to the weak predefined callback
909
  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
910
  *                the configuration information for the specified ADC.
911
  * @param  CallbackID ID of the callback to be unregistered
912
  *         This parameter can be one of the following values:
913
  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
914
  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion complete callback ID
915
  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
916
  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
917
  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
918
  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
919
  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
920
  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
921
  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
922
  * @retval HAL status
923
  */
924
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
925
{
926
  HAL_StatusTypeDef status = HAL_OK;
927
 
928
  if ((hadc->State & HAL_ADC_STATE_READY) != 0)
929
  {
930
    switch (CallbackID)
931
    {
932
      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
933
        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
934
        break;
935
 
936
      case HAL_ADC_CONVERSION_HALF_CB_ID :
937
        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
938
        break;
939
 
940
      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
941
        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
942
        break;
943
 
944
      case HAL_ADC_ERROR_CB_ID :
945
        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
946
        break;
947
 
948
      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
949
        hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
950
        break;
951
 
952
      case HAL_ADC_MSPINIT_CB_ID :
953
        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
954
        break;
955
 
956
      case HAL_ADC_MSPDEINIT_CB_ID :
957
        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
958
        break;
959
 
960
      default :
961
        /* Update the error code */
962
        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
963
 
964
        /* Return error status */
965
        status =  HAL_ERROR;
966
        break;
967
    }
968
  }
969
  else if (HAL_ADC_STATE_RESET == hadc->State)
970
  {
971
    switch (CallbackID)
972
    {
973
      case HAL_ADC_MSPINIT_CB_ID :
974
        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
975
        break;
976
 
977
      case HAL_ADC_MSPDEINIT_CB_ID :
978
        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
979
        break;
980
 
981
      default :
982
        /* Update the error code */
983
        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
984
 
985
        /* Return error status */
986
        status =  HAL_ERROR;
987
        break;
988
    }
989
  }
990
  else
991
  {
992
    /* Update the error code */
993
    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
994
 
995
    /* Return error status */
996
    status =  HAL_ERROR;
997
  }
998
 
999
  return status;
1000
}
1001
 
1002
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1003
 
1004
/**
1005
  * @}
1006
  */
1007
 
1008
/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
1009
 *  @brief    Input and Output operation functions
1010
 *
1011
@verbatim  
1012
 ===============================================================================
1013
                      ##### IO operation functions #####
1014
 ===============================================================================
1015
    [..]  This section provides functions allowing to:
1016
      (+) Start conversion of regular group.
1017
      (+) Stop conversion of regular group.
1018
      (+) Poll for conversion complete on regular group.
1019
      (+) Poll for conversion event.
1020
      (+) Get result of regular channel conversion.
1021
      (+) Start conversion of regular group and enable interruptions.
1022
      (+) Stop conversion of regular group and disable interruptions.
1023
      (+) Handle ADC interrupt request
1024
      (+) Start conversion of regular group and enable DMA transfer.
1025
      (+) Stop conversion of regular group and disable ADC DMA transfer.
1026
@endverbatim
1027
  * @{
1028
  */
1029
 
1030
/**
1031
  * @brief  Enables ADC, starts conversion of regular group.
1032
  *         Interruptions enabled in this function: None.
1033
  * @param  hadc: ADC handle
1034
  * @retval HAL status
1035
  */
1036
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
1037
{
1038
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1039
 
1040
  /* Check the parameters */
1041
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1042
 
1043
  /* Process locked */
1044
  __HAL_LOCK(hadc);
1045
 
1046
  /* Enable the ADC peripheral */
1047
  tmp_hal_status = ADC_Enable(hadc);
1048
 
1049
  /* Start conversion if ADC is effectively enabled */
1050
  if (tmp_hal_status == HAL_OK)
1051
  {
1052
    /* Set ADC state                                                          */
1053
    /* - Clear state bitfield related to regular group conversion results     */
1054
    /* - Set state bitfield related to regular operation                      */
1055
    ADC_STATE_CLR_SET(hadc->State,
1056
                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
1057
                      HAL_ADC_STATE_REG_BUSY);
1058
 
1059
    /* Set group injected state (from auto-injection) and multimode state     */
1060
    /* for all cases of multimode: independent mode, multimode ADC master     */
1061
    /* or multimode ADC slave (for devices with several ADCs):                */
1062
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
1063
    {
1064
      /* Set ADC state (ADC independent or master) */
1065
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1066
 
1067
      /* If conversions on group regular are also triggering group injected,  */
1068
      /* update ADC state.                                                    */
1069
      if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1070
      {
1071
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
1072
      }
1073
    }
1074
    else
1075
    {
1076
      /* Set ADC state (ADC slave) */
1077
      SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1078
 
1079
      /* If conversions on group regular are also triggering group injected,  */
1080
      /* update ADC state.                                                    */
1081
      if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
1082
      {
1083
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1084
      }
1085
    }
1086
 
1087
    /* State machine update: Check if an injected conversion is ongoing */
1088
    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1089
    {
1090
      /* Reset ADC error code fields related to conversions on group regular */
1091
      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));        
1092
    }
1093
    else
1094
    {
1095
      /* Reset ADC all error code fields */
1096
      ADC_CLEAR_ERRORCODE(hadc);
1097
    }
1098
 
1099
    /* Process unlocked */
1100
    /* Unlock before starting ADC conversions: in case of potential           */
1101
    /* interruption, to let the process to ADC IRQ Handler.                   */
1102
    __HAL_UNLOCK(hadc);
1103
 
1104
    /* Clear regular group conversion flag */
1105
    /* (To ensure of no unknown state from potential previous ADC operations) */
1106
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
1107
 
1108
    /* Enable conversion of regular group.                                    */
1109
    /* If software start has been selected, conversion starts immediately.    */
1110
    /* If external trigger has been selected, conversion will start at next   */
1111
    /* trigger event.                                                         */
1112
    /* Case of multimode enabled:                                             */
1113
    /*  - if ADC is slave, ADC is enabled only (conversion is not started).   */
1114
    /*  - if ADC is master, ADC is enabled and conversion is started.         */
1115
    /* If ADC is master, ADC is enabled and conversion is started.            */
1116
    /* Note: Alternate trigger for single conversion could be to force an     */
1117
    /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
1118
    if (ADC_IS_SOFTWARE_START_REGULAR(hadc)      &&
1119
        ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
1120
    {
1121
      /* Start ADC conversion on regular group with SW start */
1122
      SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
1123
    }
1124
    else
1125
    {
1126
      /* Start ADC conversion on regular group with external trigger */
1127
      SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
1128
    }
1129
  }
1130
  else
1131
  {
1132
    /* Process unlocked */
1133
    __HAL_UNLOCK(hadc);
1134
  }
1135
 
1136
  /* Return function status */
1137
  return tmp_hal_status;
1138
}
1139
 
1140
/**
1141
  * @brief  Stop ADC conversion of regular group (and injected channels in
1142
  *         case of auto_injection mode), disable ADC peripheral.
1143
  * @note:  ADC peripheral disable is forcing stop of potential
1144
  *         conversion on injected group. If injected group is under use, it
1145
  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1146
  * @param  hadc: ADC handle
1147
  * @retval HAL status.
1148
  */
1149
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
1150
{
1151
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1152
 
1153
  /* Check the parameters */
1154
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1155
 
1156
  /* Process locked */
1157
  __HAL_LOCK(hadc);
1158
 
1159
  /* Stop potential conversion on going, on regular and injected groups */
1160
  /* Disable ADC peripheral */
1161
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
1162
 
1163
  /* Check if ADC is effectively disabled */
1164
  if (tmp_hal_status == HAL_OK)
1165
  {
1166
    /* Set ADC state */
1167
    ADC_STATE_CLR_SET(hadc->State,
1168
                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1169
                      HAL_ADC_STATE_READY);
1170
  }
1171
 
1172
  /* Process unlocked */
1173
  __HAL_UNLOCK(hadc);
1174
 
1175
  /* Return function status */
1176
  return tmp_hal_status;
1177
}
1178
 
1179
/**
1180
  * @brief  Wait for regular group conversion to be completed.
1181
  * @note   This function cannot be used in a particular setup: ADC configured
1182
  *         in DMA mode.
1183
  *         In this case, DMA resets the flag EOC and polling cannot be
1184
  *         performed on each conversion.
1185
  * @note   On STM32F1 devices, limitation in case of sequencer enabled
1186
  *         (several ranks selected): polling cannot be done on each
1187
  *         conversion inside the sequence. In this case, polling is replaced by
1188
  *         wait for maximum conversion time.
1189
  * @param  hadc: ADC handle
1190
  * @param  Timeout: Timeout value in millisecond.
1191
  * @retval HAL status
1192
  */
1193
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
1194
{
1195
  uint32_t tickstart = 0U;
1196
 
1197
  /* Variables for polling in case of scan mode enabled and polling for each  */
1198
  /* conversion.                                                              */
1199
  __IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
1200
  uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
1201
 
1202
  /* Check the parameters */
1203
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1204
 
1205
  /* Get tick count */
1206
  tickstart = HAL_GetTick();
1207
 
1208
  /* Verification that ADC configuration is compliant with polling for        */
1209
  /* each conversion:                                                         */
1210
  /* Particular case is ADC configured in DMA mode                            */
1211
  if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
1212
  {
1213
    /* Update ADC state machine to error */
1214
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1215
 
1216
    /* Process unlocked */
1217
    __HAL_UNLOCK(hadc);
1218
 
1219
    return HAL_ERROR;
1220
  }
1221
 
1222
  /* Polling for end of conversion: differentiation if single/sequence        */
1223
  /* conversion.                                                              */
1224
  /*  - If single conversion for regular group (Scan mode disabled or enabled */
1225
  /*    with NbrOfConversion =1), flag EOC is used to determine the           */
1226
  /*    conversion completion.                                                */
1227
  /*  - If sequence conversion for regular group (scan mode enabled and       */
1228
  /*    NbrOfConversion >=2), flag EOC is set only at the end of the          */
1229
  /*    sequence.                                                             */
1230
  /*    To poll for each conversion, the maximum conversion time is computed  */
1231
  /*    from ADC conversion time (selected sampling time + conversion time of */
1232
  /*    12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on    */
1233
  /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
1234
  /*    As flag EOC is not set after each conversion, no timeout status can   */
1235
  /*    be set.                                                               */
1236
  if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
1237
      HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L)    )
1238
  {
1239
    /* Wait until End of Conversion flag is raised */
1240
    while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
1241
    {
1242
      /* Check if timeout is disabled (set to infinite wait) */
1243
      if(Timeout != HAL_MAX_DELAY)
1244
      {
1245
        if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
1246
        {
1247
          /* New check to avoid false timeout detection in case of preemption */
1248
          if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
1249
          {
1250
            /* Update ADC state machine to timeout */
1251
            SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1252
 
1253
            /* Process unlocked */
1254
            __HAL_UNLOCK(hadc);
1255
 
1256
            return HAL_TIMEOUT;
1257
          }
1258
        }
1259
      }
1260
    }
1261
  }
1262
  else
1263
  {
1264
    /* Replace polling by wait for maximum conversion time */
1265
    /*  - Computation of CPU clock cycles corresponding to ADC clock cycles   */
1266
    /*    and ADC maximum conversion cycles on all channels.                  */
1267
    /*  - Wait for the expected ADC clock cycles delay                        */
1268
    Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
1269
                                          / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
1270
                                         * ADC_CONVCYCLES_MAX_RANGE(hadc)                 );
1271
 
1272
    while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
1273
    {
1274
      /* Check if timeout is disabled (set to infinite wait) */
1275
      if(Timeout != HAL_MAX_DELAY)
1276
      {
1277
        if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
1278
        {
1279
          /* New check to avoid false timeout detection in case of preemption */
1280
          if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
1281
          {
1282
            /* Update ADC state machine to timeout */
1283
            SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1284
 
1285
            /* Process unlocked */
1286
            __HAL_UNLOCK(hadc);
1287
 
1288
            return HAL_TIMEOUT;
1289
          }
1290
        }
1291
      }
1292
      Conversion_Timeout_CPU_cycles ++;
1293
    }
1294
  }
1295
 
1296
  /* Clear regular group conversion flag */
1297
  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1298
 
1299
  /* Update ADC state machine */
1300
  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1301
 
1302
  /* Determine whether any further conversion upcoming on group regular       */
1303
  /* by external trigger, continuous mode or scan sequence on going.          */
1304
  /* Note: On STM32F1 devices, in case of sequencer enabled                   */
1305
  /*       (several ranks selected), end of conversion flag is raised         */
1306
  /*       at the end of the sequence.                                        */
1307
  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
1308
     (hadc->Init.ContinuousConvMode == DISABLE)   )
1309
  {  
1310
    /* Set ADC state */
1311
    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);  
1312
 
1313
    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1314
    {
1315
      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1316
    }
1317
  }
1318
 
1319
  /* Return ADC state */
1320
  return HAL_OK;
1321
}
1322
 
1323
/**
1324
  * @brief  Poll for conversion event.
1325
  * @param  hadc: ADC handle
1326
  * @param  EventType: the ADC event type.
1327
  *          This parameter can be one of the following values:
1328
  *            @arg ADC_AWD_EVENT: ADC Analog watchdog event.
1329
  * @param  Timeout: Timeout value in millisecond.
1330
  * @retval HAL status
1331
  */
1332
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
1333
{
1334
  uint32_t tickstart = 0U;
1335
 
1336
  /* Check the parameters */
1337
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1338
  assert_param(IS_ADC_EVENT_TYPE(EventType));
1339
 
1340
  /* Get tick count */
1341
  tickstart = HAL_GetTick();
1342
 
1343
  /* Check selected event flag */
1344
  while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
1345
  {
1346
    /* Check if timeout is disabled (set to infinite wait) */
1347
    if(Timeout != HAL_MAX_DELAY)
1348
    {
1349
      if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
1350
      {
1351
        /* New check to avoid false timeout detection in case of preemption */
1352
        if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
1353
        {
1354
          /* Update ADC state machine to timeout */
1355
          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1356
 
1357
          /* Process unlocked */
1358
          __HAL_UNLOCK(hadc);
1359
 
1360
          return HAL_TIMEOUT;
1361
        }
1362
      }
1363
    }
1364
  }
1365
 
1366
  /* Analog watchdog (level out of window) event */
1367
  /* Set ADC state */
1368
  SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1369
 
1370
  /* Clear ADC analog watchdog flag */
1371
  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1372
 
1373
  /* Return ADC state */
1374
  return HAL_OK;
1375
}
1376
 
1377
/**
1378
  * @brief  Enables ADC, starts conversion of regular group with interruption.
1379
  *         Interruptions enabled in this function:
1380
  *          - EOC (end of conversion of regular group)
1381
  *         Each of these interruptions has its dedicated callback function.
1382
  * @param  hadc: ADC handle
1383
  * @retval HAL status
1384
  */
1385
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1386
{
1387
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1388
 
1389
  /* Check the parameters */
1390
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1391
 
1392
  /* Process locked */
1393
  __HAL_LOCK(hadc);
1394
 
1395
  /* Enable the ADC peripheral */
1396
  tmp_hal_status = ADC_Enable(hadc);
1397
 
1398
  /* Start conversion if ADC is effectively enabled */
1399
  if (tmp_hal_status == HAL_OK)
1400
  {
1401
    /* Set ADC state                                                          */
1402
    /* - Clear state bitfield related to regular group conversion results     */
1403
    /* - Set state bitfield related to regular operation                      */
1404
    ADC_STATE_CLR_SET(hadc->State,
1405
                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1406
                      HAL_ADC_STATE_REG_BUSY);
1407
 
1408
    /* Set group injected state (from auto-injection) and multimode state     */
1409
    /* for all cases of multimode: independent mode, multimode ADC master     */
1410
    /* or multimode ADC slave (for devices with several ADCs):                */
1411
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
1412
    {
1413
      /* Set ADC state (ADC independent or master) */
1414
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1415
 
1416
      /* If conversions on group regular are also triggering group injected,  */
1417
      /* update ADC state.                                                    */
1418
      if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1419
      {
1420
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
1421
      }
1422
    }
1423
    else
1424
    {
1425
      /* Set ADC state (ADC slave) */
1426
      SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1427
 
1428
      /* If conversions on group regular are also triggering group injected,  */
1429
      /* update ADC state.                                                    */
1430
      if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
1431
      {
1432
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1433
      }
1434
    }
1435
 
1436
    /* State machine update: Check if an injected conversion is ongoing */
1437
    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1438
    {
1439
      /* Reset ADC error code fields related to conversions on group regular */
1440
      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));        
1441
    }
1442
    else
1443
    {
1444
      /* Reset ADC all error code fields */
1445
      ADC_CLEAR_ERRORCODE(hadc);
1446
    }
1447
 
1448
    /* Process unlocked */
1449
    /* Unlock before starting ADC conversions: in case of potential           */
1450
    /* interruption, to let the process to ADC IRQ Handler.                   */
1451
    __HAL_UNLOCK(hadc);
1452
 
1453
    /* Clear regular group conversion flag and overrun flag */
1454
    /* (To ensure of no unknown state from potential previous ADC operations) */
1455
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
1456
 
1457
    /* Enable end of conversion interrupt for regular group */
1458
    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1459
 
1460
    /* Enable conversion of regular group.                                    */
1461
    /* If software start has been selected, conversion starts immediately.    */
1462
    /* If external trigger has been selected, conversion will start at next   */
1463
    /* trigger event.                                                         */
1464
    /* Case of multimode enabled:                                             */
1465
    /*  - if ADC is slave, ADC is enabled only (conversion is not started).   */
1466
    /*  - if ADC is master, ADC is enabled and conversion is started.         */
1467
    if (ADC_IS_SOFTWARE_START_REGULAR(hadc)      &&
1468
        ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
1469
    {
1470
      /* Start ADC conversion on regular group with SW start */
1471
      SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
1472
    }
1473
    else
1474
    {
1475
      /* Start ADC conversion on regular group with external trigger */
1476
      SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
1477
    }
1478
  }
1479
  else
1480
  {
1481
    /* Process unlocked */
1482
    __HAL_UNLOCK(hadc);
1483
  }
1484
 
1485
  /* Return function status */
1486
  return tmp_hal_status;
1487
}
1488
 
1489
/**
1490
  * @brief  Stop ADC conversion of regular group (and injected group in
1491
  *         case of auto_injection mode), disable interrution of
1492
  *         end-of-conversion, disable ADC peripheral.
1493
  * @param  hadc: ADC handle
1494
  * @retval None
1495
  */
1496
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
1497
{
1498
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1499
 
1500
  /* Check the parameters */
1501
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1502
 
1503
  /* Process locked */
1504
  __HAL_LOCK(hadc);
1505
 
1506
  /* Stop potential conversion on going, on regular and injected groups */
1507
  /* Disable ADC peripheral */
1508
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
1509
 
1510
  /* Check if ADC is effectively disabled */
1511
  if (tmp_hal_status == HAL_OK)
1512
  {
1513
    /* Disable ADC end of conversion interrupt for regular group */
1514
    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1515
 
1516
    /* Set ADC state */
1517
    ADC_STATE_CLR_SET(hadc->State,
1518
                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1519
                      HAL_ADC_STATE_READY);
1520
  }
1521
 
1522
  /* Process unlocked */
1523
  __HAL_UNLOCK(hadc);
1524
 
1525
  /* Return function status */
1526
  return tmp_hal_status;
1527
}
1528
 
1529
/**
1530
  * @brief  Enables ADC, starts conversion of regular group and transfers result
1531
  *         through DMA.
1532
  *         Interruptions enabled in this function:
1533
  *          - DMA transfer complete
1534
  *          - DMA half transfer
1535
  *         Each of these interruptions has its dedicated callback function.
1536
  * @note   For devices with several ADCs: This function is for single-ADC mode
1537
  *         only. For multimode, use the dedicated MultimodeStart function.
1538
  * @note   On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
1539
  *         on devices) have DMA capability.
1540
  *         ADC2 converted data can be transferred in dual ADC mode using DMA
1541
  *         of ADC1 (ADC master in multimode).
1542
  *         In case of using ADC1 with DMA on a device featuring 2 ADC
1543
  *         instances: ADC1 conversion register DR contains ADC1 conversion
1544
  *         result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
1545
  *         conversion result (ADC1 register DR bits 16 to 27). Therefore, to
1546
  *         have DMA transferring the conversion results of ADC1 only, DMA must
1547
  *         be configured to transfer size: half word.
1548
  * @param  hadc: ADC handle
1549
  * @param  pData: The destination Buffer address.
1550
  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
1551
  * @retval None
1552
  */
1553
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
1554
{
1555
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1556
 
1557
  /* Check the parameters */
1558
  assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
1559
 
1560
  /* Verification if multimode is disabled (for devices with several ADC)     */
1561
  /* If multimode is enabled, dedicated function multimode conversion         */
1562
  /* start DMA must be used.                                                  */
1563
  if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
1564
  {
1565
    /* Process locked */
1566
    __HAL_LOCK(hadc);
1567
 
1568
    /* Enable the ADC peripheral */
1569
    tmp_hal_status = ADC_Enable(hadc);
1570
 
1571
    /* Start conversion if ADC is effectively enabled */
1572
    if (tmp_hal_status == HAL_OK)
1573
    {
1574
      /* Set ADC state                                                        */
1575
      /* - Clear state bitfield related to regular group conversion results   */
1576
      /* - Set state bitfield related to regular operation                    */
1577
      ADC_STATE_CLR_SET(hadc->State,
1578
                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1579
                        HAL_ADC_STATE_REG_BUSY);
1580
 
1581
    /* Set group injected state (from auto-injection) and multimode state     */
1582
    /* for all cases of multimode: independent mode, multimode ADC master     */
1583
    /* or multimode ADC slave (for devices with several ADCs):                */
1584
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
1585
    {
1586
      /* Set ADC state (ADC independent or master) */
1587
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1588
 
1589
      /* If conversions on group regular are also triggering group injected,  */
1590
      /* update ADC state.                                                    */
1591
      if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1592
      {
1593
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
1594
      }
1595
    }
1596
    else
1597
    {
1598
      /* Set ADC state (ADC slave) */
1599
      SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1600
 
1601
      /* If conversions on group regular are also triggering group injected,  */
1602
      /* update ADC state.                                                    */
1603
      if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
1604
      {
1605
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1606
      }
1607
    }
1608
 
1609
      /* State machine update: Check if an injected conversion is ongoing */
1610
      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1611
      {
1612
        /* Reset ADC error code fields related to conversions on group regular */
1613
        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));        
1614
      }
1615
      else
1616
      {
1617
        /* Reset ADC all error code fields */
1618
        ADC_CLEAR_ERRORCODE(hadc);
1619
      }
1620
 
1621
      /* Process unlocked */
1622
      /* Unlock before starting ADC conversions: in case of potential         */
1623
      /* interruption, to let the process to ADC IRQ Handler.                 */
1624
      __HAL_UNLOCK(hadc);
1625
 
1626
      /* Set the DMA transfer complete callback */
1627
      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1628
 
1629
      /* Set the DMA half transfer complete callback */
1630
      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1631
 
1632
      /* Set the DMA error callback */
1633
      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1634
 
1635
 
1636
      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC   */
1637
      /* start (in case of SW start):                                         */
1638
 
1639
      /* Clear regular group conversion flag and overrun flag */
1640
      /* (To ensure of no unknown state from potential previous ADC           */
1641
      /* operations)                                                          */
1642
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
1643
 
1644
      /* Enable ADC DMA mode */
1645
      SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
1646
 
1647
      /* Start the DMA channel */
1648
      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1649
 
1650
      /* Enable conversion of regular group.                                  */
1651
      /* If software start has been selected, conversion starts immediately.  */
1652
      /* If external trigger has been selected, conversion will start at next */
1653
      /* trigger event.                                                       */
1654
      if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
1655
      {
1656
        /* Start ADC conversion on regular group with SW start */
1657
        SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
1658
      }
1659
      else
1660
      {
1661
        /* Start ADC conversion on regular group with external trigger */
1662
        SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
1663
      }
1664
    }
1665
    else
1666
    {
1667
      /* Process unlocked */
1668
      __HAL_UNLOCK(hadc);
1669
    }
1670
  }
1671
  else
1672
  {
1673
    tmp_hal_status = HAL_ERROR;
1674
  }
1675
 
1676
  /* Return function status */
1677
  return tmp_hal_status;
1678
}
1679
 
1680
/**
1681
  * @brief  Stop ADC conversion of regular group (and injected group in
1682
  *         case of auto_injection mode), disable ADC DMA transfer, disable
1683
  *         ADC peripheral.
1684
  * @note:  ADC peripheral disable is forcing stop of potential
1685
  *         conversion on injected group. If injected group is under use, it
1686
  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1687
  * @note   For devices with several ADCs: This function is for single-ADC mode
1688
  *         only. For multimode, use the dedicated MultimodeStop function.
1689
  * @note   On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
1690
  *         on devices) have DMA capability.
1691
  * @param  hadc: ADC handle
1692
  * @retval HAL status.
1693
  */
1694
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
1695
{
1696
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1697
 
1698
  /* Check the parameters */
1699
  assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
1700
 
1701
  /* Process locked */
1702
  __HAL_LOCK(hadc);
1703
 
1704
  /* Stop potential conversion on going, on regular and injected groups */
1705
  /* Disable ADC peripheral */
1706
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
1707
 
1708
  /* Check if ADC is effectively disabled */
1709
  if (tmp_hal_status == HAL_OK)
1710
  {
1711
    /* Disable ADC DMA mode */
1712
    CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
1713
 
1714
    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1715
    /* DMA transfer is on going)                                              */
1716
    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
1717
    {
1718
      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1719
 
1720
      /* Check if DMA channel effectively disabled */
1721
      if (tmp_hal_status == HAL_OK)
1722
      {
1723
        /* Set ADC state */
1724
        ADC_STATE_CLR_SET(hadc->State,
1725
                          HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1726
                          HAL_ADC_STATE_READY);
1727
      }
1728
      else
1729
      {
1730
        /* Update ADC state machine to error */
1731
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1732
      }
1733
    }
1734
  }
1735
 
1736
  /* Process unlocked */
1737
  __HAL_UNLOCK(hadc);
1738
 
1739
  /* Return function status */
1740
  return tmp_hal_status;
1741
}
1742
 
1743
/**
1744
  * @brief  Get ADC regular group conversion result.
1745
  * @note   Reading register DR automatically clears ADC flag EOC
1746
  *         (ADC group regular end of unitary conversion).
1747
  * @note   This function does not clear ADC flag EOS
1748
  *         (ADC group regular end of sequence conversion).
1749
  *         Occurrence of flag EOS rising:
1750
  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
1751
  *            to flag EOC.
1752
  *          - If sequencer is composed of several ranks, during the scan
1753
  *            sequence flag EOC only is raised, at the end of the scan sequence
1754
  *            both flags EOC and EOS are raised.
1755
  *         To clear this flag, either use function:
1756
  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1757
  *         model polling: @ref HAL_ADC_PollForConversion()
1758
  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
1759
  * @param  hadc: ADC handle
1760
  * @retval ADC group regular conversion data
1761
  */
1762
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
1763
{
1764
  /* Check the parameters */
1765
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1766
 
1767
  /* Note: EOC flag is not cleared here by software because automatically     */
1768
  /*       cleared by hardware when reading register DR.                      */
1769
 
1770
  /* Return ADC converted value */
1771
  return hadc->Instance->DR;
1772
}
1773
 
1774
/**
1775
  * @brief  Handles ADC interrupt request  
1776
  * @param  hadc: ADC handle
1777
  * @retval None
1778
  */
1779
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
1780
{
1781
  uint32_t tmp_sr = hadc->Instance->SR;
1782
  uint32_t tmp_cr1 = hadc->Instance->CR1;
1783
 
1784
  /* Check the parameters */
1785
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1786
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1787
  assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
1788
 
1789
 
1790
  /* ========== Check End of Conversion flag for regular group ========== */
1791
  if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC)
1792
  {
1793
    if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC)
1794
    {
1795
      /* Update state machine on conversion status if not in error state */
1796
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1797
      {
1798
        /* Set ADC state */
1799
        SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1800
      }
1801
 
1802
      /* Determine whether any further conversion upcoming on group regular   */
1803
      /* by external trigger, continuous mode or scan sequence on going.      */
1804
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
1805
      /*       (several ranks selected), end of conversion flag is raised     */
1806
      /*       at the end of the sequence.                                    */
1807
      if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
1808
         (hadc->Init.ContinuousConvMode == DISABLE)   )
1809
      {
1810
        /* Disable ADC end of conversion interrupt on group regular */
1811
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1812
 
1813
        /* Set ADC state */
1814
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);  
1815
 
1816
        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1817
        {
1818
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1819
        }
1820
      }
1821
 
1822
      /* Conversion complete callback */
1823
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1824
      hadc->ConvCpltCallback(hadc);
1825
#else
1826
      HAL_ADC_ConvCpltCallback(hadc);
1827
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1828
 
1829
      /* Clear regular group conversion flag */
1830
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1831
    }
1832
  }
1833
 
1834
  /* ========== Check End of Conversion flag for injected group ========== */
1835
  if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC)
1836
  {
1837
    if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC)
1838
    {
1839
      /* Update state machine on conversion status if not in error state */
1840
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1841
      {
1842
        /* Set ADC state */
1843
        SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
1844
      }
1845
 
1846
      /* Determine whether any further conversion upcoming on group injected  */
1847
      /* by external trigger, scan sequence on going or by automatic injected */
1848
      /* conversion from group regular (same conditions as group regular      */
1849
      /* interruption disabling above).                                       */
1850
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
1851
      /*       (several ranks selected), end of conversion flag is raised     */
1852
      /*       at the end of the sequence.                                    */
1853
      if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     ||
1854
         (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&    
1855
         (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
1856
          (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
1857
      {
1858
        /* Disable ADC end of conversion interrupt on group injected */
1859
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1860
 
1861
        /* Set ADC state */
1862
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);  
1863
 
1864
        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
1865
        {
1866
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1867
        }
1868
      }
1869
 
1870
      /* Conversion complete callback */
1871
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1872
      hadc->InjectedConvCpltCallback(hadc);
1873
#else
1874
      HAL_ADCEx_InjectedConvCpltCallback(hadc);
1875
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1876
 
1877
      /* Clear injected group conversion flag */
1878
      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
1879
    }
1880
  }
1881
 
1882
  /* ========== Check Analog watchdog flags ========== */
1883
  if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD)
1884
  {
1885
    if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD)
1886
    {
1887
      /* Set ADC state */
1888
      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1889
 
1890
      /* Level out of window callback */
1891
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1892
      hadc->LevelOutOfWindowCallback(hadc);
1893
#else
1894
      HAL_ADC_LevelOutOfWindowCallback(hadc);
1895
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1896
 
1897
      /* Clear the ADC analog watchdog flag */
1898
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1899
    }
1900
  }
1901
 
1902
}
1903
 
1904
/**
1905
  * @brief  Conversion complete callback in non blocking mode
1906
  * @param  hadc: ADC handle
1907
  * @retval None
1908
  */
1909
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
1910
{
1911
  /* Prevent unused argument(s) compilation warning */
1912
  UNUSED(hadc);
1913
  /* NOTE : This function should not be modified. When the callback is needed,
1914
            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
1915
   */
1916
}
1917
 
1918
/**
1919
  * @brief  Conversion DMA half-transfer callback in non blocking mode
1920
  * @param  hadc: ADC handle
1921
  * @retval None
1922
  */
1923
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
1924
{
1925
  /* Prevent unused argument(s) compilation warning */
1926
  UNUSED(hadc);
1927
  /* NOTE : This function should not be modified. When the callback is needed,
1928
            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
1929
  */
1930
}
1931
 
1932
/**
1933
  * @brief  Analog watchdog callback in non blocking mode.
1934
  * @param  hadc: ADC handle
1935
  * @retval None
1936
  */
1937
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
1938
{
1939
  /* Prevent unused argument(s) compilation warning */
1940
  UNUSED(hadc);
1941
  /* NOTE : This function should not be modified. When the callback is needed,
1942
            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
1943
  */
1944
}
1945
 
1946
/**
1947
  * @brief  ADC error callback in non blocking mode
1948
  *        (ADC conversion with interruption or transfer by DMA)
1949
  * @param  hadc: ADC handle
1950
  * @retval None
1951
  */
1952
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
1953
{
1954
  /* Prevent unused argument(s) compilation warning */
1955
  UNUSED(hadc);
1956
  /* NOTE : This function should not be modified. When the callback is needed,
1957
            function HAL_ADC_ErrorCallback must be implemented in the user file.
1958
  */
1959
}
1960
 
1961
 
1962
/**
1963
  * @}
1964
  */
1965
 
1966
/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
1967
 *  @brief    Peripheral Control functions
1968
 *
1969
@verbatim  
1970
 ===============================================================================
1971
             ##### Peripheral Control functions #####
1972
 ===============================================================================  
1973
    [..]  This section provides functions allowing to:
1974
      (+) Configure channels on regular group
1975
      (+) Configure the analog watchdog
1976
 
1977
@endverbatim
1978
  * @{
1979
  */
1980
 
1981
/**
1982
  * @brief  Configures the the selected channel to be linked to the regular
1983
  *         group.
1984
  * @note   In case of usage of internal measurement channels:
1985
  *         Vbat/VrefInt/TempSensor.
1986
  *         These internal paths can be be disabled using function
1987
  *         HAL_ADC_DeInit().
1988
  * @note   Possibility to update parameters on the fly:
1989
  *         This function initializes channel into regular group, following  
1990
  *         calls to this function can be used to reconfigure some parameters
1991
  *         of structure "ADC_ChannelConfTypeDef" on the fly, without resetting
1992
  *         the ADC.
1993
  *         The setting of these parameters is conditioned to ADC state.
1994
  *         For parameters constraints, see comments of structure
1995
  *         "ADC_ChannelConfTypeDef".
1996
  * @param  hadc: ADC handle
1997
  * @param  sConfig: Structure of ADC channel for regular group.
1998
  * @retval HAL status
1999
  */
2000
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
2001
{
2002
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2003
  __IO uint32_t wait_loop_index = 0U;
2004
 
2005
  /* Check the parameters */
2006
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2007
  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
2008
  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
2009
  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
2010
 
2011
  /* Process locked */
2012
  __HAL_LOCK(hadc);
2013
 
2014
 
2015
  /* Regular sequence configuration */
2016
  /* For Rank 1 to 6 */
2017
  if (sConfig->Rank < 7U)
2018
  {
2019
    MODIFY_REG(hadc->Instance->SQR3                        ,
2020
               ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank)    ,
2021
               ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
2022
  }
2023
  /* For Rank 7 to 12 */
2024
  else if (sConfig->Rank < 13U)
2025
  {
2026
    MODIFY_REG(hadc->Instance->SQR2                        ,
2027
               ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank)    ,
2028
               ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
2029
  }
2030
  /* For Rank 13 to 16 */
2031
  else
2032
  {
2033
    MODIFY_REG(hadc->Instance->SQR1                        ,
2034
               ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank)   ,
2035
               ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
2036
  }
2037
 
2038
 
2039
  /* Channel sampling time configuration */
2040
  /* For channels 10 to 17 */
2041
  if (sConfig->Channel >= ADC_CHANNEL_10)
2042
  {
2043
    MODIFY_REG(hadc->Instance->SMPR1                             ,
2044
               ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel)      ,
2045
               ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
2046
  }
2047
  else /* For channels 0 to 9 */
2048
  {
2049
    MODIFY_REG(hadc->Instance->SMPR2                             ,
2050
               ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel)       ,
2051
               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
2052
  }
2053
 
2054
  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
2055
  /* and VREFINT measurement path.                                            */
2056
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
2057
      (sConfig->Channel == ADC_CHANNEL_VREFINT)      )
2058
  {
2059
    /* For STM32F1 devices with several ADC: Only ADC1 can access internal    */
2060
    /* measurement channels (VrefInt/TempSensor). If these channels are       */
2061
    /* intended to be set on other ADC instances, an error is reported.       */
2062
    if (hadc->Instance == ADC1)
2063
    {
2064
      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
2065
      {
2066
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
2067
 
2068
        if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
2069
        {
2070
          /* Delay for temperature sensor stabilization time */
2071
          /* Compute number of CPU cycles to wait for */
2072
          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
2073
          while(wait_loop_index != 0U)
2074
          {
2075
            wait_loop_index--;
2076
          }
2077
        }
2078
      }
2079
    }
2080
    else
2081
    {
2082
      /* Update ADC state machine to error */
2083
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2084
 
2085
      tmp_hal_status = HAL_ERROR;
2086
    }
2087
  }
2088
 
2089
  /* Process unlocked */
2090
  __HAL_UNLOCK(hadc);
2091
 
2092
  /* Return function status */
2093
  return tmp_hal_status;
2094
}
2095
 
2096
/**
2097
  * @brief  Configures the analog watchdog.
2098
  * @note   Analog watchdog thresholds can be modified while ADC conversion
2099
  *         is on going.
2100
  *         In this case, some constraints must be taken into account:
2101
  *         the programmed threshold values are effective from the next
2102
  *         ADC EOC (end of unitary conversion).
2103
  *         Considering that registers write delay may happen due to
2104
  *         bus activity, this might cause an uncertainty on the
2105
  *         effective timing of the new programmed threshold values.
2106
  * @param  hadc: ADC handle
2107
  * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
2108
  * @retval HAL status
2109
  */
2110
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
2111
{
2112
  /* Check the parameters */
2113
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2114
  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
2115
  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
2116
  assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
2117
  assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
2118
 
2119
  if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
2120
     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
2121
     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
2122
  {
2123
    assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
2124
  }
2125
 
2126
  /* Process locked */
2127
  __HAL_LOCK(hadc);
2128
 
2129
  /* Analog watchdog configuration */
2130
 
2131
  /* Configure ADC Analog watchdog interrupt */
2132
  if(AnalogWDGConfig->ITMode == ENABLE)
2133
  {
2134
    /* Enable the ADC Analog watchdog interrupt */
2135
    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
2136
  }
2137
  else
2138
  {
2139
    /* Disable the ADC Analog watchdog interrupt */
2140
    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
2141
  }
2142
 
2143
  /* Configuration of analog watchdog:                                        */
2144
  /*  - Set the analog watchdog enable mode: regular and/or injected groups,  */
2145
  /*    one or all channels.                                                  */
2146
  /*  - Set the Analog watchdog channel (is not used if watchdog              */
2147
  /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                             */
2148
  MODIFY_REG(hadc->Instance->CR1            ,
2149
             ADC_CR1_AWDSGL |
2150
             ADC_CR1_JAWDEN |
2151
             ADC_CR1_AWDEN  |
2152
             ADC_CR1_AWDCH                  ,
2153
             AnalogWDGConfig->WatchdogMode |
2154
             AnalogWDGConfig->Channel        );
2155
 
2156
  /* Set the high threshold */
2157
  WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
2158
 
2159
  /* Set the low threshold */
2160
  WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
2161
 
2162
  /* Process unlocked */
2163
  __HAL_UNLOCK(hadc);
2164
 
2165
  /* Return function status */
2166
  return HAL_OK;
2167
}
2168
 
2169
 
2170
/**
2171
  * @}
2172
  */
2173
 
2174
 
2175
/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
2176
 *  @brief    Peripheral State functions
2177
 *
2178
@verbatim
2179
 ===============================================================================
2180
            ##### Peripheral State and Errors functions #####
2181
 ===============================================================================  
2182
    [..]
2183
    This subsection provides functions to get in run-time the status of the  
2184
    peripheral.
2185
      (+) Check the ADC state
2186
      (+) Check the ADC error code
2187
 
2188
@endverbatim
2189
  * @{
2190
  */
2191
 
2192
/**
2193
  * @brief  return the ADC state
2194
  * @param  hadc: ADC handle
2195
  * @retval HAL state
2196
  */
2197
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
2198
{
2199
  /* Return ADC state */
2200
  return hadc->State;
2201
}
2202
 
2203
/**
2204
  * @brief  Return the ADC error code
2205
  * @param  hadc: ADC handle
2206
  * @retval ADC Error Code
2207
  */
2208
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
2209
{
2210
  return hadc->ErrorCode;
2211
}
2212
 
2213
/**
2214
  * @}
2215
  */
2216
 
2217
/**
2218
  * @}
2219
  */
2220
 
2221
/** @defgroup ADC_Private_Functions ADC Private Functions
2222
  * @{
2223
  */
2224
 
2225
/**
2226
  * @brief  Enable the selected ADC.
2227
  * @note   Prerequisite condition to use this function: ADC must be disabled
2228
  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
2229
  * @param  hadc: ADC handle
2230
  * @retval HAL status.
2231
  */
2232
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
2233
{
2234
  uint32_t tickstart = 0U;
2235
  __IO uint32_t wait_loop_index = 0U;
2236
 
2237
  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
2238
  /* enabling phase not yet completed: flag ADC ready not yet set).           */
2239
  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
2240
  /* causes: ADC clock not running, ...).                                     */
2241
  if (ADC_IS_ENABLE(hadc) == RESET)
2242
  {
2243
    /* Enable the Peripheral */
2244
    __HAL_ADC_ENABLE(hadc);
2245
 
2246
    /* Delay for ADC stabilization time */
2247
    /* Compute number of CPU cycles to wait for */
2248
    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
2249
    while(wait_loop_index != 0U)
2250
    {
2251
      wait_loop_index--;
2252
    }
2253
 
2254
    /* Get tick count */
2255
    tickstart = HAL_GetTick();
2256
 
2257
    /* Wait for ADC effectively enabled */
2258
    while(ADC_IS_ENABLE(hadc) == RESET)
2259
    {
2260
      if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
2261
      {
2262
        /* New check to avoid false timeout detection in case of preemption */
2263
        if(ADC_IS_ENABLE(hadc) == RESET)
2264
        {
2265
          /* Update ADC state machine to error */
2266
          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2267
 
2268
          /* Set ADC error code to ADC IP internal error */
2269
          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2270
 
2271
          /* Process unlocked */
2272
          __HAL_UNLOCK(hadc);
2273
 
2274
          return HAL_ERROR;
2275
        }
2276
      }
2277
    }
2278
  }
2279
 
2280
  /* Return HAL status */
2281
  return HAL_OK;
2282
}
2283
 
2284
/**
2285
  * @brief  Stop ADC conversion and disable the selected ADC
2286
  * @note   Prerequisite condition to use this function: ADC conversions must be
2287
  *         stopped to disable the ADC.
2288
  * @param  hadc: ADC handle
2289
  * @retval HAL status.
2290
  */
2291
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
2292
{
2293
  uint32_t tickstart = 0U;
2294
 
2295
  /* Verification if ADC is not already disabled */
2296
  if (ADC_IS_ENABLE(hadc) != RESET)
2297
  {
2298
    /* Disable the ADC peripheral */
2299
    __HAL_ADC_DISABLE(hadc);
2300
 
2301
    /* Get tick count */
2302
    tickstart = HAL_GetTick();
2303
 
2304
    /* Wait for ADC effectively disabled */
2305
    while(ADC_IS_ENABLE(hadc) != RESET)
2306
    {
2307
      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
2308
      {
2309
        /* New check to avoid false timeout detection in case of preemption */
2310
        if(ADC_IS_ENABLE(hadc) != RESET)
2311
        {
2312
          /* Update ADC state machine to error */
2313
          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2314
 
2315
          /* Set ADC error code to ADC IP internal error */
2316
          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2317
 
2318
          return HAL_ERROR;
2319
        }
2320
      }
2321
    }
2322
  }
2323
 
2324
  /* Return HAL status */
2325
  return HAL_OK;
2326
}
2327
 
2328
/**
2329
  * @brief  DMA transfer complete callback.
2330
  * @param  hdma: pointer to DMA handle.
2331
  * @retval None
2332
  */
2333
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
2334
{
2335
  /* Retrieve ADC handle corresponding to current DMA handle */
2336
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2337
 
2338
  /* Update state machine on conversion status if not in error state */
2339
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
2340
  {
2341
    /* Update ADC state machine */
2342
    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2343
 
2344
    /* Determine whether any further conversion upcoming on group regular     */
2345
    /* by external trigger, continuous mode or scan sequence on going.        */
2346
    /* Note: On STM32F1 devices, in case of sequencer enabled                 */
2347
    /*       (several ranks selected), end of conversion flag is raised       */
2348
    /*       at the end of the sequence.                                      */
2349
    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
2350
       (hadc->Init.ContinuousConvMode == DISABLE)   )
2351
    {
2352
      /* Set ADC state */
2353
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);  
2354
 
2355
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2356
      {
2357
        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2358
      }
2359
    }
2360
 
2361
    /* Conversion complete callback */
2362
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2363
    hadc->ConvCpltCallback(hadc);
2364
#else
2365
    HAL_ADC_ConvCpltCallback(hadc);
2366
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2367
  }
2368
  else
2369
  {
2370
    /* Call DMA error callback */
2371
    hadc->DMA_Handle->XferErrorCallback(hdma);
2372
  }
2373
}
2374
 
2375
/**
2376
  * @brief  DMA half transfer complete callback.
2377
  * @param  hdma: pointer to DMA handle.
2378
  * @retval None
2379
  */
2380
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)  
2381
{
2382
  /* Retrieve ADC handle corresponding to current DMA handle */
2383
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2384
 
2385
  /* Half conversion callback */
2386
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2387
    hadc->ConvHalfCpltCallback(hadc);
2388
#else
2389
  HAL_ADC_ConvHalfCpltCallback(hadc);
2390
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2391
}
2392
 
2393
/**
2394
  * @brief  DMA error callback
2395
  * @param  hdma: pointer to DMA handle.
2396
  * @retval None
2397
  */
2398
void ADC_DMAError(DMA_HandleTypeDef *hdma)  
2399
{
2400
  /* Retrieve ADC handle corresponding to current DMA handle */
2401
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2402
 
2403
  /* Set ADC state */
2404
  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2405
 
2406
  /* Set ADC error code to DMA error */
2407
  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
2408
 
2409
  /* Error callback */
2410
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2411
  hadc->ErrorCallback(hadc);
2412
#else
2413
  HAL_ADC_ErrorCallback(hadc);
2414
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2415
}
2416
 
2417
/**
2418
  * @}
2419
  */
2420
 
2421
#endif /* HAL_ADC_MODULE_ENABLED */
2422
/**
2423
  * @}
2424
  */
2425
 
2426
/**
2427
  * @}
2428
  */