WebSVN – testOled – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef __STM32F1xx_LL_TIM_H
		22	#define __STM32F1xx_LL_TIM_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f1xx.h"
		30
		31	/** @addtogroup STM32F1xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17)
		36
		37	/** @defgroup TIM_LL TIM
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
		44	* @{
		45	*/
		46	static const uint8_t OFFSET_TAB_CCMRx[] =
		47	{
		48	0x00U, /* 0: TIMx_CH1 */
		49	0x00U, /* 1: TIMx_CH1N */
		50	0x00U, /* 2: TIMx_CH2 */
		51	0x00U, /* 3: TIMx_CH2N */
		52	0x04U, /* 4: TIMx_CH3 */
		53	0x04U, /* 5: TIMx_CH3N */
		54	0x04U /* 6: TIMx_CH4 */
		55	};
		56
		57	static const uint8_t SHIFT_TAB_OCxx[] =
		58	{
		59	0U, /* 0: OC1M, OC1FE, OC1PE */
		60	0U, /* 1: - NA */
		61	8U, /* 2: OC2M, OC2FE, OC2PE */
		62	0U, /* 3: - NA */
		63	0U, /* 4: OC3M, OC3FE, OC3PE */
		64	0U, /* 5: - NA */
		65	8U /* 6: OC4M, OC4FE, OC4PE */
		66	};
		67
		68	static const uint8_t SHIFT_TAB_ICxx[] =
		69	{
		70	0U, /* 0: CC1S, IC1PSC, IC1F */
		71	0U, /* 1: - NA */
		72	8U, /* 2: CC2S, IC2PSC, IC2F */
		73	0U, /* 3: - NA */
		74	0U, /* 4: CC3S, IC3PSC, IC3F */
		75	0U, /* 5: - NA */
		76	8U /* 6: CC4S, IC4PSC, IC4F */
		77	};
		78
		79	static const uint8_t SHIFT_TAB_CCxP[] =
		80	{
		81	0U, /* 0: CC1P */
		82	2U, /* 1: CC1NP */
		83	4U, /* 2: CC2P */
		84	6U, /* 3: CC2NP */
		85	8U, /* 4: CC3P */
		86	10U, /* 5: CC3NP */
		87	12U /* 6: CC4P */
		88	};
		89
		90	static const uint8_t SHIFT_TAB_OISx[] =
		91	{
		92	0U, /* 0: OIS1 */
		93	1U, /* 1: OIS1N */
		94	2U, /* 2: OIS2 */
		95	3U, /* 3: OIS2N */
		96	4U, /* 4: OIS3 */
		97	5U, /* 5: OIS3N */
		98	6U /* 6: OIS4 */
		99	};
		100	/**
		101	* @}
		102	*/
		103
		104	/* Private constants ---------------------------------------------------------*/
		105	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
		106	* @{
		107	*/
		108
		109
		110
		111	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
		112	#define DT_DELAY_1 ((uint8_t)0x7F)
		113	#define DT_DELAY_2 ((uint8_t)0x3F)
		114	#define DT_DELAY_3 ((uint8_t)0x1F)
		115	#define DT_DELAY_4 ((uint8_t)0x1F)
		116
		117	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
		118	#define DT_RANGE_1 ((uint8_t)0x00)
		119	#define DT_RANGE_2 ((uint8_t)0x80)
		120	#define DT_RANGE_3 ((uint8_t)0xC0)
		121	#define DT_RANGE_4 ((uint8_t)0xE0)
		122
		123
		124	/**
		125	* @}
		126	*/
		127
		128	/* Private macros ------------------------------------------------------------*/
		129	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
		130	* @{
		131	*/
		132	/** @brief Convert channel id into channel index.
		133	* @param __CHANNEL__ This parameter can be one of the following values:
		134	* @arg @ref LL_TIM_CHANNEL_CH1
		135	* @arg @ref LL_TIM_CHANNEL_CH1N
		136	* @arg @ref LL_TIM_CHANNEL_CH2
		137	* @arg @ref LL_TIM_CHANNEL_CH2N
		138	* @arg @ref LL_TIM_CHANNEL_CH3
		139	* @arg @ref LL_TIM_CHANNEL_CH3N
		140	* @arg @ref LL_TIM_CHANNEL_CH4
		141	* @retval none
		142	*/
		143	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
		144	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
		145	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
		146	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
		147	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
		148	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
		149	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
		150
		151	/** @brief Calculate the deadtime sampling period(in ps).
		152	* @param __TIMCLK__ timer input clock frequency (in Hz).
		153	* @param __CKD__ This parameter can be one of the following values:
		154	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		155	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		156	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		157	* @retval none
		158	*/
		159	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
		160	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
		161	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
		162	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
		163	/**
		164	* @}
		165	*/
		166
		167
		168	/* Exported types ------------------------------------------------------------*/
		169	#if defined(USE_FULL_LL_DRIVER)
		170	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
		171	* @{
		172	*/
		173
		174	/**
		175	* @brief TIM Time Base configuration structure definition.
		176	*/
		177	typedef struct
		178	{
		179	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		180	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		181
		182	This feature can be modified afterwards using unitary function
		183	@ref LL_TIM_SetPrescaler().*/
		184
		185	uint32_t CounterMode; /*!< Specifies the counter mode.
		186	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
		187
		188	This feature can be modified afterwards using unitary function
		189	@ref LL_TIM_SetCounterMode().*/
		190
		191	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
		192	Auto-Reload Register at the next update event.
		193	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		194	Some timer instances may support 32 bits counters. In that case this parameter must
		195	be a number between 0x0000 and 0xFFFFFFFF.
		196
		197	This feature can be modified afterwards using unitary function
		198	@ref LL_TIM_SetAutoReload().*/
		199
		200	uint32_t ClockDivision; /*!< Specifies the clock division.
		201	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
		202
		203	This feature can be modified afterwards using unitary function
		204	@ref LL_TIM_SetClockDivision().*/
		205
		206	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
		207	reaches zero, an update event is generated and counting restarts
		208	from the RCR value (N).
		209	This means in PWM mode that (N+1) corresponds to:
		210	- the number of PWM periods in edge-aligned mode
		211	- the number of half PWM period in center-aligned mode
		212	GP timers: this parameter must be a number between Min_Data = 0x00 and
		213	Max_Data = 0xFF.
		214	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
		215	Max_Data = 0xFFFF.
		216
		217	This feature can be modified afterwards using unitary function
		218	@ref LL_TIM_SetRepetitionCounter().*/
		219	} LL_TIM_InitTypeDef;
		220
		221	/**
		222	* @brief TIM Output Compare configuration structure definition.
		223	*/
		224	typedef struct
		225	{
		226	uint32_t OCMode; /*!< Specifies the output mode.
		227	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
		228
		229	This feature can be modified afterwards using unitary function
		230	@ref LL_TIM_OC_SetMode().*/
		231
		232	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
		233	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		234
		235	This feature can be modified afterwards using unitary functions
		236	@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
		237
		238	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
		239	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		240
		241	This feature can be modified afterwards using unitary functions
		242	@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
		243
		244	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
		245	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		246
		247	This feature can be modified afterwards using unitary function
		248	LL_TIM_OC_SetCompareCHx (x=1..6).*/
		249
		250	uint32_t OCPolarity; /*!< Specifies the output polarity.
		251	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		252
		253	This feature can be modified afterwards using unitary function
		254	@ref LL_TIM_OC_SetPolarity().*/
		255
		256	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		257	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		258
		259	This feature can be modified afterwards using unitary function
		260	@ref LL_TIM_OC_SetPolarity().*/
		261
		262
		263	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		264	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		265
		266	This feature can be modified afterwards using unitary function
		267	@ref LL_TIM_OC_SetIdleState().*/
		268
		269	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		270	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		271
		272	This feature can be modified afterwards using unitary function
		273	@ref LL_TIM_OC_SetIdleState().*/
		274	} LL_TIM_OC_InitTypeDef;
		275
		276	/**
		277	* @brief TIM Input Capture configuration structure definition.
		278	*/
		279
		280	typedef struct
		281	{
		282
		283	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		284	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		285
		286	This feature can be modified afterwards using unitary function
		287	@ref LL_TIM_IC_SetPolarity().*/
		288
		289	uint32_t ICActiveInput; /*!< Specifies the input.
		290	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		291
		292	This feature can be modified afterwards using unitary function
		293	@ref LL_TIM_IC_SetActiveInput().*/
		294
		295	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		296	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		297
		298	This feature can be modified afterwards using unitary function
		299	@ref LL_TIM_IC_SetPrescaler().*/
		300
		301	uint32_t ICFilter; /*!< Specifies the input capture filter.
		302	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		303
		304	This feature can be modified afterwards using unitary function
		305	@ref LL_TIM_IC_SetFilter().*/
		306	} LL_TIM_IC_InitTypeDef;
		307
		308
		309	/**
		310	* @brief TIM Encoder interface configuration structure definition.
		311	*/
		312	typedef struct
		313	{
		314	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
		315	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
		316
		317	This feature can be modified afterwards using unitary function
		318	@ref LL_TIM_SetEncoderMode().*/
		319
		320	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		321	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		322
		323	This feature can be modified afterwards using unitary function
		324	@ref LL_TIM_IC_SetPolarity().*/
		325
		326	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
		327	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		328
		329	This feature can be modified afterwards using unitary function
		330	@ref LL_TIM_IC_SetActiveInput().*/
		331
		332	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		333	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		334
		335	This feature can be modified afterwards using unitary function
		336	@ref LL_TIM_IC_SetPrescaler().*/
		337
		338	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		339	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		340
		341	This feature can be modified afterwards using unitary function
		342	@ref LL_TIM_IC_SetFilter().*/
		343
		344	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
		345	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		346
		347	This feature can be modified afterwards using unitary function
		348	@ref LL_TIM_IC_SetPolarity().*/
		349
		350	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
		351	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		352
		353	This feature can be modified afterwards using unitary function
		354	@ref LL_TIM_IC_SetActiveInput().*/
		355
		356	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
		357	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		358
		359	This feature can be modified afterwards using unitary function
		360	@ref LL_TIM_IC_SetPrescaler().*/
		361
		362	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
		363	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		364
		365	This feature can be modified afterwards using unitary function
		366	@ref LL_TIM_IC_SetFilter().*/
		367
		368	} LL_TIM_ENCODER_InitTypeDef;
		369
		370	/**
		371	* @brief TIM Hall sensor interface configuration structure definition.
		372	*/
		373	typedef struct
		374	{
		375
		376	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		377	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		378
		379	This feature can be modified afterwards using unitary function
		380	@ref LL_TIM_IC_SetPolarity().*/
		381
		382	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		383	Prescaler must be set to get a maximum counter period longer than the
		384	time interval between 2 consecutive changes on the Hall inputs.
		385	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		386
		387	This feature can be modified afterwards using unitary function
		388	@ref LL_TIM_IC_SetPrescaler().*/
		389
		390	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		391	This parameter can be a value of
		392	@ref TIM_LL_EC_IC_FILTER.
		393
		394	This feature can be modified afterwards using unitary function
		395	@ref LL_TIM_IC_SetFilter().*/
		396
		397	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
		398	A positive pulse (TRGO event) is generated with a programmable delay every time
		399	a change occurs on the Hall inputs.
		400	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
		401
		402	This feature can be modified afterwards using unitary function
		403	@ref LL_TIM_OC_SetCompareCH2().*/
		404	} LL_TIM_HALLSENSOR_InitTypeDef;
		405
		406	/**
		407	* @brief BDTR (Break and Dead Time) structure definition
		408	*/
		409	typedef struct
		410	{
		411	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
		412	This parameter can be a value of @ref TIM_LL_EC_OSSR
		413
		414	This feature can be modified afterwards using unitary function
		415	@ref LL_TIM_SetOffStates()
		416
		417	@note This bit-field cannot be modified as long as LOCK level 2 has been
		418	programmed. */
		419
		420	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
		421	This parameter can be a value of @ref TIM_LL_EC_OSSI
		422
		423	This feature can be modified afterwards using unitary function
		424	@ref LL_TIM_SetOffStates()
		425
		426	@note This bit-field cannot be modified as long as LOCK level 2 has been
		427	programmed. */
		428
		429	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
		430	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
		431
		432	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
		433	register has been written, their content is frozen until the next reset.*/
		434
		435	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
		436	switching-on of the outputs.
		437	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
		438
		439	This feature can be modified afterwards using unitary function
		440	@ref LL_TIM_OC_SetDeadTime()
		441
		442	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
		443	programmed. */
		444
		445	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
		446	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
		447
		448	This feature can be modified afterwards using unitary functions
		449	@ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
		450
		451	@note This bit-field can not be modified as long as LOCK level 1 has been
		452	programmed. */
		453
		454	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
		455	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
		456
		457	This feature can be modified afterwards using unitary function
		458	@ref LL_TIM_ConfigBRK()
		459
		460	@note This bit-field can not be modified as long as LOCK level 1 has been
		461	programmed. */
		462
		463	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
		464	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
		465
		466	This feature can be modified afterwards using unitary functions
		467	@ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
		468
		469	@note This bit-field can not be modified as long as LOCK level 1 has been
		470	programmed. */
		471	} LL_TIM_BDTR_InitTypeDef;
		472
		473	/**
		474	* @}
		475	*/
		476	#endif /* USE_FULL_LL_DRIVER */
		477
		478	/* Exported constants --------------------------------------------------------*/
		479	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
		480	* @{
		481	*/
		482
		483	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
		484	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
		485	* @{
		486	*/
		487	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
		488	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
		489	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
		490	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
		491	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
		492	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
		493	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
		494	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
		495	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
		496	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
		497	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
		498	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
		499	/**
		500	* @}
		501	*/
		502
		503	#if defined(USE_FULL_LL_DRIVER)
		504	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
		505	* @{
		506	*/
		507	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
		508	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
		509	/**
		510	* @}
		511	*/
		512
		513	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
		514	* @{
		515	*/
		516	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
		517	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
		518	/**
		519	* @}
		520	*/
		521	#endif /* USE_FULL_LL_DRIVER */
		522
		523	/** @defgroup TIM_LL_EC_IT IT Defines
		524	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
		525	* @{
		526	*/
		527	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
		528	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
		529	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
		530	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
		531	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
		532	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
		533	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
		534	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
		535	/**
		536	* @}
		537	*/
		538
		539	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
		540	* @{
		541	*/
		542	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
		543	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
		544	/**
		545	* @}
		546	*/
		547
		548	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
		549	* @{
		550	*/
		551	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
		552	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
		553	/**
		554	* @}
		555	*/
		556
		557	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
		558	* @{
		559	*/
		560	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
		561	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
		562	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
		563	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
		564	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
		565	/**
		566	* @}
		567	*/
		568
		569	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
		570	* @{
		571	*/
		572	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
		573	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
		574	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
		575	/**
		576	* @}
		577	*/
		578
		579	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
		580	* @{
		581	*/
		582	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
		583	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
		584	/**
		585	* @}
		586	*/
		587
		588	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
		589	* @{
		590	*/
		591	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
		592	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
		593	/**
		594	* @}
		595	*/
		596
		597	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
		598	* @{
		599	*/
		600	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
		601	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
		602	/**
		603	* @}
		604	*/
		605
		606	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
		607	* @{
		608	*/
		609	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
		610	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
		611	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
		612	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
		613	/**
		614	* @}
		615	*/
		616
		617	/** @defgroup TIM_LL_EC_CHANNEL Channel
		618	* @{
		619	*/
		620	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
		621	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
		622	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
		623	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
		624	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
		625	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
		626	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
		627	/**
		628	* @}
		629	*/
		630
		631	#if defined(USE_FULL_LL_DRIVER)
		632	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
		633	* @{
		634	*/
		635	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
		636	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
		637	/**
		638	* @}
		639	*/
		640	#endif /* USE_FULL_LL_DRIVER */
		641
		642	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
		643	* @{
		644	*/
		645	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
		646	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
		647	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
		648	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
		649	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
		650	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
		651	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
		652	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
		653	/**
		654	* @}
		655	*/
		656
		657	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
		658	* @{
		659	*/
		660	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
		661	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
		662	/**
		663	* @}
		664	*/
		665
		666	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
		667	* @{
		668	*/
		669	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
		670	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
		671	/**
		672	* @}
		673	*/
		674
		675
		676	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
		677	* @{
		678	*/
		679	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
		680	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
		681	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
		682	/**
		683	* @}
		684	*/
		685
		686	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
		687	* @{
		688	*/
		689	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
		690	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
		691	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
		692	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
		693	/**
		694	* @}
		695	*/
		696
		697	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
		698	* @{
		699	*/
		700	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		701	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
		702	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
		703	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
		704	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
		705	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
		706	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
		707	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
		708	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
		709	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
		710	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
		711	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
		712	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
		713	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
		714	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
		715	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
		716	/**
		717	* @}
		718	*/
		719
		720	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
		721	* @{
		722	*/
		723	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
		724	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
		725	/**
		726	* @}
		727	*/
		728
		729	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
		730	* @{
		731	*/
		732	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
		733	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
		734	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
		735	/**
		736	* @}
		737	*/
		738
		739	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
		740	* @{
		741	*/
		742	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
		743	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
		744	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
		745	/**
		746	* @}
		747	*/
		748
		749	/** @defgroup TIM_LL_EC_TRGO Trigger Output
		750	* @{
		751	*/
		752	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
		753	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
		754	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
		755	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
		756	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
		757	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
		758	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
		759	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
		760	/**
		761	* @}
		762	*/
		763
		764
		765	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
		766	* @{
		767	*/
		768	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
		769	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
		770	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
		771	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
		772	/**
		773	* @}
		774	*/
		775
		776	/** @defgroup TIM_LL_EC_TS Trigger Selection
		777	* @{
		778	*/
		779	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
		780	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
		781	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
		782	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
		783	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
		784	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
		785	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
		786	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
		787	/**
		788	* @}
		789	*/
		790
		791	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
		792	* @{
		793	*/
		794	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
		795	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
		796	/**
		797	* @}
		798	*/
		799
		800	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
		801	* @{
		802	*/
		803	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
		804	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
		805	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
		806	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
		807	/**
		808	* @}
		809	*/
		810
		811	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
		812	* @{
		813	*/
		814	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		815	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
		816	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
		817	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
		818	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
		819	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
		820	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
		821	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
		822	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
		823	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
		824	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
		825	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
		826	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
		827	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
		828	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
		829	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
		830	/**
		831	* @}
		832	*/
		833
		834
		835	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
		836	* @{
		837	*/
		838	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
		839	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
		840	/**
		841	* @}
		842	*/
		843
		844
		845
		846
		847	/** @defgroup TIM_LL_EC_OSSI OSSI
		848	* @{
		849	*/
		850	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		851	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
		852	/**
		853	* @}
		854	*/
		855
		856	/** @defgroup TIM_LL_EC_OSSR OSSR
		857	* @{
		858	*/
		859	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		860	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
		861	/**
		862	* @}
		863	*/
		864
		865
		866	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
		867	* @{
		868	*/
		869	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
		870	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
		871	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
		872	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
		873	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
		874	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
		875	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
		876	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
		877	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
		878	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
		879	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
		880	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
		881	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
		882	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
		883	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
		884	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
		885	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
		886	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
		887	/**
		888	* @}
		889	*/
		890
		891	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
		892	* @{
		893	*/
		894	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
		895	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
		896	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
		897	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
		898	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
		899	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
		900	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
		901	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
		902	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
		903	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
		904	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
		905	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
		906	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
		907	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
		908	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
		909	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
		910	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
		911	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
		912	/**
		913	* @}
		914	*/
		915
		916
		917	/**
		918	* @}
		919	*/
		920
		921	/* Exported macro ------------------------------------------------------------*/
		922	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
		923	* @{
		924	*/
		925
		926	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
		927	* @{
		928	*/
		929	/**
		930	* @brief Write a value in TIM register.
		931	* @param __INSTANCE__ TIM Instance
		932	* @param __REG__ Register to be written
		933	* @param __VALUE__ Value to be written in the register
		934	* @retval None
		935	*/
		936	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
		937
		938	/**
		939	* @brief Read a value in TIM register.
		940	* @param __INSTANCE__ TIM Instance
		941	* @param __REG__ Register to be read
		942	* @retval Register value
		943	*/
		944	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
		945	/**
		946	* @}
		947	*/
		948
		949	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
		950	* @{
		951	*/
		952
		953	/**
		954	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
		955	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
		956	* @param __TIMCLK__ timer input clock frequency (in Hz)
		957	* @param __CKD__ This parameter can be one of the following values:
		958	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		959	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		960	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		961	* @param __DT__ deadtime duration (in ns)
		962	* @retval DTG[0:7]
		963	*/
		964	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
		965	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
		966	(uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
		967	(((uint64_t)((__DT__)1000U)) < ((64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
		968	(uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
		969	(__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
		970	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
		971	(uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
		972	(__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
		973	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
		974	(uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
		975	(__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
		976	0U)
		977
		978	/**
		979	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
		980	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
		981	* @param __TIMCLK__ timer input clock frequency (in Hz)
		982	* @param __CNTCLK__ counter clock frequency (in Hz)
		983	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
		984	*/
		985	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
		986	(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
		987
		988	/**
		989	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
		990	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
		991	* @param __TIMCLK__ timer input clock frequency (in Hz)
		992	* @param __PSC__ prescaler
		993	* @param __FREQ__ output signal frequency (in Hz)
		994	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		995	*/
		996	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
		997	((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
		998
		999	/**
		1000	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare
		1001	* active/inactive delay.
		1002	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
		1003	* @param __TIMCLK__ timer input clock frequency (in Hz)
		1004	* @param __PSC__ prescaler
		1005	* @param __DELAY__ timer output compare active/inactive delay (in us)
		1006	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
		1007	*/
		1008	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
		1009	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
		1010	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
		1011
		1012	/**
		1013	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
		1014	* (when the timer operates in one pulse mode).
		1015	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
		1016	* @param __TIMCLK__ timer input clock frequency (in Hz)
		1017	* @param __PSC__ prescaler
		1018	* @param __DELAY__ timer output compare active/inactive delay (in us)
		1019	* @param __PULSE__ pulse duration (in us)
		1020	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		1021	*/
		1022	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
		1023	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
		1024	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
		1025
		1026	/**
		1027	* @brief HELPER macro retrieving the ratio of the input capture prescaler
		1028	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
		1029	* @param __ICPSC__ This parameter can be one of the following values:
		1030	* @arg @ref LL_TIM_ICPSC_DIV1
		1031	* @arg @ref LL_TIM_ICPSC_DIV2
		1032	* @arg @ref LL_TIM_ICPSC_DIV4
		1033	* @arg @ref LL_TIM_ICPSC_DIV8
		1034	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
		1035	*/
		1036	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
		1037	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
		1038
		1039
		1040	/**
		1041	* @}
		1042	*/
		1043
		1044
		1045	/**
		1046	* @}
		1047	*/
		1048
		1049	/* Exported functions --------------------------------------------------------*/
		1050	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
		1051	* @{
		1052	*/
		1053
		1054	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
		1055	* @{
		1056	*/
		1057	/**
		1058	* @brief Enable timer counter.
		1059	* @rmtoll CR1 CEN LL_TIM_EnableCounter
		1060	* @param TIMx Timer instance
		1061	* @retval None
		1062	*/
		1063	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
		1064	{
		1065	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
		1066	}
		1067
		1068	/**
		1069	* @brief Disable timer counter.
		1070	* @rmtoll CR1 CEN LL_TIM_DisableCounter
		1071	* @param TIMx Timer instance
		1072	* @retval None
		1073	*/
		1074	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
		1075	{
		1076	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
		1077	}
		1078
		1079	/**
		1080	* @brief Indicates whether the timer counter is enabled.
		1081	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
		1082	* @param TIMx Timer instance
		1083	* @retval State of bit (1 or 0).
		1084	*/
		1085	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
		1086	{
		1087	return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
		1088	}
		1089
		1090	/**
		1091	* @brief Enable update event generation.
		1092	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
		1093	* @param TIMx Timer instance
		1094	* @retval None
		1095	*/
		1096	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
		1097	{
		1098	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1099	}
		1100
		1101	/**
		1102	* @brief Disable update event generation.
		1103	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
		1104	* @param TIMx Timer instance
		1105	* @retval None
		1106	*/
		1107	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
		1108	{
		1109	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1110	}
		1111
		1112	/**
		1113	* @brief Indicates whether update event generation is enabled.
		1114	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
		1115	* @param TIMx Timer instance
		1116	* @retval Inverted state of bit (0 or 1).
		1117	*/
		1118	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
		1119	{
		1120	return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
		1121	}
		1122
		1123	/**
		1124	* @brief Set update event source
		1125	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
		1126	* generate an update interrupt or DMA request if enabled:
		1127	* - Counter overflow/underflow
		1128	* - Setting the UG bit
		1129	* - Update generation through the slave mode controller
		1130	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
		1131	* overflow/underflow generates an update interrupt or DMA request if enabled.
		1132	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
		1133	* @param TIMx Timer instance
		1134	* @param UpdateSource This parameter can be one of the following values:
		1135	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1136	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1137	* @retval None
		1138	*/
		1139	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
		1140	{
		1141	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
		1142	}
		1143
		1144	/**
		1145	* @brief Get actual event update source
		1146	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
		1147	* @param TIMx Timer instance
		1148	* @retval Returned value can be one of the following values:
		1149	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1150	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1151	*/
		1152	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
		1153	{
		1154	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
		1155	}
		1156
		1157	/**
		1158	* @brief Set one pulse mode (one shot v.s. repetitive).
		1159	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
		1160	* @param TIMx Timer instance
		1161	* @param OnePulseMode This parameter can be one of the following values:
		1162	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1163	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1164	* @retval None
		1165	*/
		1166	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
		1167	{
		1168	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
		1169	}
		1170
		1171	/**
		1172	* @brief Get actual one pulse mode.
		1173	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
		1174	* @param TIMx Timer instance
		1175	* @retval Returned value can be one of the following values:
		1176	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1177	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1178	*/
		1179	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
		1180	{
		1181	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
		1182	}
		1183
		1184	/**
		1185	* @brief Set the timer counter counting mode.
		1186	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1187	* check whether or not the counter mode selection feature is supported
		1188	* by a timer instance.
		1189	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1190	* requires a timer reset to avoid unexpected direction
		1191	* due to DIR bit readonly in center aligned mode.
		1192	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
		1193	* CR1 CMS LL_TIM_SetCounterMode
		1194	* @param TIMx Timer instance
		1195	* @param CounterMode This parameter can be one of the following values:
		1196	* @arg @ref LL_TIM_COUNTERMODE_UP
		1197	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1198	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1199	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1200	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1201	* @retval None
		1202	*/
		1203	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
		1204	{
		1205	MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR \| TIM_CR1_CMS), CounterMode);
		1206	}
		1207
		1208	/**
		1209	* @brief Get actual counter mode.
		1210	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1211	* check whether or not the counter mode selection feature is supported
		1212	* by a timer instance.
		1213	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
		1214	* CR1 CMS LL_TIM_GetCounterMode
		1215	* @param TIMx Timer instance
		1216	* @retval Returned value can be one of the following values:
		1217	* @arg @ref LL_TIM_COUNTERMODE_UP
		1218	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1219	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1220	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1221	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1222	*/
		1223	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
		1224	{
		1225	uint32_t counter_mode;
		1226
		1227	counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
		1228
		1229	if (counter_mode == 0U)
		1230	{
		1231	counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1232	}
		1233
		1234	return counter_mode;
		1235	}
		1236
		1237	/**
		1238	* @brief Enable auto-reload (ARR) preload.
		1239	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
		1240	* @param TIMx Timer instance
		1241	* @retval None
		1242	*/
		1243	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
		1244	{
		1245	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1246	}
		1247
		1248	/**
		1249	* @brief Disable auto-reload (ARR) preload.
		1250	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
		1251	* @param TIMx Timer instance
		1252	* @retval None
		1253	*/
		1254	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
		1255	{
		1256	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1257	}
		1258
		1259	/**
		1260	* @brief Indicates whether auto-reload (ARR) preload is enabled.
		1261	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
		1262	* @param TIMx Timer instance
		1263	* @retval State of bit (1 or 0).
		1264	*/
		1265	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
		1266	{
		1267	return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
		1268	}
		1269
		1270	/**
		1271	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
		1272	* (when supported) and the digital filters.
		1273	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1274	* whether or not the clock division feature is supported by the timer
		1275	* instance.
		1276	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
		1277	* @param TIMx Timer instance
		1278	* @param ClockDivision This parameter can be one of the following values:
		1279	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1280	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1281	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1282	* @retval None
		1283	*/
		1284	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
		1285	{
		1286	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
		1287	}
		1288
		1289	/**
		1290	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
		1291	* generators (when supported) and the digital filters.
		1292	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1293	* whether or not the clock division feature is supported by the timer
		1294	* instance.
		1295	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
		1296	* @param TIMx Timer instance
		1297	* @retval Returned value can be one of the following values:
		1298	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1299	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1300	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1301	*/
		1302	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
		1303	{
		1304	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
		1305	}
		1306
		1307	/**
		1308	* @brief Set the counter value.
		1309	* @rmtoll CNT CNT LL_TIM_SetCounter
		1310	* @param TIMx Timer instance
		1311	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
		1312	* @retval None
		1313	*/
		1314	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
		1315	{
		1316	WRITE_REG(TIMx->CNT, Counter);
		1317	}
		1318
		1319	/**
		1320	* @brief Get the counter value.
		1321	* @rmtoll CNT CNT LL_TIM_GetCounter
		1322	* @param TIMx Timer instance
		1323	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
		1324	*/
		1325	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
		1326	{
		1327	return (uint32_t)(READ_REG(TIMx->CNT));
		1328	}
		1329
		1330	/**
		1331	* @brief Get the current direction of the counter
		1332	* @rmtoll CR1 DIR LL_TIM_GetDirection
		1333	* @param TIMx Timer instance
		1334	* @retval Returned value can be one of the following values:
		1335	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
		1336	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
		1337	*/
		1338	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
		1339	{
		1340	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1341	}
		1342
		1343	/**
		1344	* @brief Set the prescaler value.
		1345	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
		1346	* @note The prescaler can be changed on the fly as this control register is buffered. The new
		1347	* prescaler ratio is taken into account at the next update event.
		1348	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
		1349	* @rmtoll PSC PSC LL_TIM_SetPrescaler
		1350	* @param TIMx Timer instance
		1351	* @param Prescaler between Min_Data=0 and Max_Data=65535
		1352	* @retval None
		1353	*/
		1354	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
		1355	{
		1356	WRITE_REG(TIMx->PSC, Prescaler);
		1357	}
		1358
		1359	/**
		1360	* @brief Get the prescaler value.
		1361	* @rmtoll PSC PSC LL_TIM_GetPrescaler
		1362	* @param TIMx Timer instance
		1363	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
		1364	*/
		1365	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
		1366	{
		1367	return (uint32_t)(READ_REG(TIMx->PSC));
		1368	}
		1369
		1370	/**
		1371	* @brief Set the auto-reload value.
		1372	* @note The counter is blocked while the auto-reload value is null.
		1373	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
		1374	* @rmtoll ARR ARR LL_TIM_SetAutoReload
		1375	* @param TIMx Timer instance
		1376	* @param AutoReload between Min_Data=0 and Max_Data=65535
		1377	* @retval None
		1378	*/
		1379	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
		1380	{
		1381	WRITE_REG(TIMx->ARR, AutoReload);
		1382	}
		1383
		1384	/**
		1385	* @brief Get the auto-reload value.
		1386	* @rmtoll ARR ARR LL_TIM_GetAutoReload
		1387	* @param TIMx Timer instance
		1388	* @retval Auto-reload value
		1389	*/
		1390	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
		1391	{
		1392	return (uint32_t)(READ_REG(TIMx->ARR));
		1393	}
		1394
		1395	/**
		1396	* @brief Set the repetition counter value.
		1397	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
		1398	* whether or not a timer instance supports a repetition counter.
		1399	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
		1400	* @param TIMx Timer instance
		1401	* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
		1402	* @retval None
		1403	*/
		1404	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
		1405	{
		1406	WRITE_REG(TIMx->RCR, RepetitionCounter);
		1407	}
		1408
		1409	/**
		1410	* @brief Get the repetition counter value.
		1411	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
		1412	* whether or not a timer instance supports a repetition counter.
		1413	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
		1414	* @param TIMx Timer instance
		1415	* @retval Repetition counter value
		1416	*/
		1417	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
		1418	{
		1419	return (uint32_t)(READ_REG(TIMx->RCR));
		1420	}
		1421
		1422	/**
		1423	* @}
		1424	*/
		1425
		1426	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
		1427	* @{
		1428	*/
		1429	/**
		1430	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
		1431	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
		1432	* they are updated only when a commutation event (COM) occurs.
		1433	* @note Only on channels that have a complementary output.
		1434	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1435	* whether or not a timer instance is able to generate a commutation event.
		1436	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
		1437	* @param TIMx Timer instance
		1438	* @retval None
		1439	*/
		1440	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
		1441	{
		1442	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1443	}
		1444
		1445	/**
		1446	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
		1447	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1448	* whether or not a timer instance is able to generate a commutation event.
		1449	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
		1450	* @param TIMx Timer instance
		1451	* @retval None
		1452	*/
		1453	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
		1454	{
		1455	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1456	}
		1457
		1458	/**
		1459	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
		1460	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1461	* whether or not a timer instance is able to generate a commutation event.
		1462	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
		1463	* @param TIMx Timer instance
		1464	* @param CCUpdateSource This parameter can be one of the following values:
		1465	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
		1466	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
		1467	* @retval None
		1468	*/
		1469	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
		1470	{
		1471	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
		1472	}
		1473
		1474	/**
		1475	* @brief Set the trigger of the capture/compare DMA request.
		1476	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
		1477	* @param TIMx Timer instance
		1478	* @param DMAReqTrigger This parameter can be one of the following values:
		1479	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1480	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1481	* @retval None
		1482	*/
		1483	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
		1484	{
		1485	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
		1486	}
		1487
		1488	/**
		1489	* @brief Get actual trigger of the capture/compare DMA request.
		1490	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
		1491	* @param TIMx Timer instance
		1492	* @retval Returned value can be one of the following values:
		1493	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1494	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1495	*/
		1496	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
		1497	{
		1498	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
		1499	}
		1500
		1501	/**
		1502	* @brief Set the lock level to freeze the
		1503	* configuration of several capture/compare parameters.
		1504	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		1505	* the lock mechanism is supported by a timer instance.
		1506	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
		1507	* @param TIMx Timer instance
		1508	* @param LockLevel This parameter can be one of the following values:
		1509	* @arg @ref LL_TIM_LOCKLEVEL_OFF
		1510	* @arg @ref LL_TIM_LOCKLEVEL_1
		1511	* @arg @ref LL_TIM_LOCKLEVEL_2
		1512	* @arg @ref LL_TIM_LOCKLEVEL_3
		1513	* @retval None
		1514	*/
		1515	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
		1516	{
		1517	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
		1518	}
		1519
		1520	/**
		1521	* @brief Enable capture/compare channels.
		1522	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
		1523	* CCER CC1NE LL_TIM_CC_EnableChannel\n
		1524	* CCER CC2E LL_TIM_CC_EnableChannel\n
		1525	* CCER CC2NE LL_TIM_CC_EnableChannel\n
		1526	* CCER CC3E LL_TIM_CC_EnableChannel\n
		1527	* CCER CC3NE LL_TIM_CC_EnableChannel\n
		1528	* CCER CC4E LL_TIM_CC_EnableChannel
		1529	* @param TIMx Timer instance
		1530	* @param Channels This parameter can be a combination of the following values:
		1531	* @arg @ref LL_TIM_CHANNEL_CH1
		1532	* @arg @ref LL_TIM_CHANNEL_CH1N
		1533	* @arg @ref LL_TIM_CHANNEL_CH2
		1534	* @arg @ref LL_TIM_CHANNEL_CH2N
		1535	* @arg @ref LL_TIM_CHANNEL_CH3
		1536	* @arg @ref LL_TIM_CHANNEL_CH3N
		1537	* @arg @ref LL_TIM_CHANNEL_CH4
		1538	* @retval None
		1539	*/
		1540	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1541	{
		1542	SET_BIT(TIMx->CCER, Channels);
		1543	}
		1544
		1545	/**
		1546	* @brief Disable capture/compare channels.
		1547	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
		1548	* CCER CC1NE LL_TIM_CC_DisableChannel\n
		1549	* CCER CC2E LL_TIM_CC_DisableChannel\n
		1550	* CCER CC2NE LL_TIM_CC_DisableChannel\n
		1551	* CCER CC3E LL_TIM_CC_DisableChannel\n
		1552	* CCER CC3NE LL_TIM_CC_DisableChannel\n
		1553	* CCER CC4E LL_TIM_CC_DisableChannel
		1554	* @param TIMx Timer instance
		1555	* @param Channels This parameter can be a combination of the following values:
		1556	* @arg @ref LL_TIM_CHANNEL_CH1
		1557	* @arg @ref LL_TIM_CHANNEL_CH1N
		1558	* @arg @ref LL_TIM_CHANNEL_CH2
		1559	* @arg @ref LL_TIM_CHANNEL_CH2N
		1560	* @arg @ref LL_TIM_CHANNEL_CH3
		1561	* @arg @ref LL_TIM_CHANNEL_CH3N
		1562	* @arg @ref LL_TIM_CHANNEL_CH4
		1563	* @retval None
		1564	*/
		1565	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1566	{
		1567	CLEAR_BIT(TIMx->CCER, Channels);
		1568	}
		1569
		1570	/**
		1571	* @brief Indicate whether channel(s) is(are) enabled.
		1572	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
		1573	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
		1574	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
		1575	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
		1576	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
		1577	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
		1578	* CCER CC4E LL_TIM_CC_IsEnabledChannel
		1579	* @param TIMx Timer instance
		1580	* @param Channels This parameter can be a combination of the following values:
		1581	* @arg @ref LL_TIM_CHANNEL_CH1
		1582	* @arg @ref LL_TIM_CHANNEL_CH1N
		1583	* @arg @ref LL_TIM_CHANNEL_CH2
		1584	* @arg @ref LL_TIM_CHANNEL_CH2N
		1585	* @arg @ref LL_TIM_CHANNEL_CH3
		1586	* @arg @ref LL_TIM_CHANNEL_CH3N
		1587	* @arg @ref LL_TIM_CHANNEL_CH4
		1588	* @retval State of bit (1 or 0).
		1589	*/
		1590	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1591	{
		1592	return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
		1593	}
		1594
		1595	/**
		1596	* @}
		1597	*/
		1598
		1599	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
		1600	* @{
		1601	*/
		1602	/**
		1603	* @brief Configure an output channel.
		1604	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
		1605	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
		1606	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
		1607	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
		1608	* CCER CC1P LL_TIM_OC_ConfigOutput\n
		1609	* CCER CC2P LL_TIM_OC_ConfigOutput\n
		1610	* CCER CC3P LL_TIM_OC_ConfigOutput\n
		1611	* CCER CC4P LL_TIM_OC_ConfigOutput\n
		1612	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
		1613	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
		1614	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
		1615	* CR2 OIS4 LL_TIM_OC_ConfigOutput
		1616	* @param TIMx Timer instance
		1617	* @param Channel This parameter can be one of the following values:
		1618	* @arg @ref LL_TIM_CHANNEL_CH1
		1619	* @arg @ref LL_TIM_CHANNEL_CH2
		1620	* @arg @ref LL_TIM_CHANNEL_CH3
		1621	* @arg @ref LL_TIM_CHANNEL_CH4
		1622	* @param Configuration This parameter must be a combination of all the following values:
		1623	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
		1624	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
		1625	* @retval None
		1626	*/
		1627	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		1628	{
		1629	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1630	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1631	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
		1632	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
		1633	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
		1634	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
		1635	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
		1636	}
		1637
		1638	/**
		1639	* @brief Define the behavior of the output reference signal OCxREF from which
		1640	* OCx and OCxN (when relevant) are derived.
		1641	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
		1642	* CCMR1 OC2M LL_TIM_OC_SetMode\n
		1643	* CCMR2 OC3M LL_TIM_OC_SetMode\n
		1644	* CCMR2 OC4M LL_TIM_OC_SetMode
		1645	* @param TIMx Timer instance
		1646	* @param Channel This parameter can be one of the following values:
		1647	* @arg @ref LL_TIM_CHANNEL_CH1
		1648	* @arg @ref LL_TIM_CHANNEL_CH2
		1649	* @arg @ref LL_TIM_CHANNEL_CH3
		1650	* @arg @ref LL_TIM_CHANNEL_CH4
		1651	* @param Mode This parameter can be one of the following values:
		1652	* @arg @ref LL_TIM_OCMODE_FROZEN
		1653	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1654	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1655	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1656	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1657	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1658	* @arg @ref LL_TIM_OCMODE_PWM1
		1659	* @arg @ref LL_TIM_OCMODE_PWM2
		1660	* @retval None
		1661	*/
		1662	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
		1663	{
		1664	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1665	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1666	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
		1667	}
		1668
		1669	/**
		1670	* @brief Get the output compare mode of an output channel.
		1671	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
		1672	* CCMR1 OC2M LL_TIM_OC_GetMode\n
		1673	* CCMR2 OC3M LL_TIM_OC_GetMode\n
		1674	* CCMR2 OC4M LL_TIM_OC_GetMode
		1675	* @param TIMx Timer instance
		1676	* @param Channel This parameter can be one of the following values:
		1677	* @arg @ref LL_TIM_CHANNEL_CH1
		1678	* @arg @ref LL_TIM_CHANNEL_CH2
		1679	* @arg @ref LL_TIM_CHANNEL_CH3
		1680	* @arg @ref LL_TIM_CHANNEL_CH4
		1681	* @retval Returned value can be one of the following values:
		1682	* @arg @ref LL_TIM_OCMODE_FROZEN
		1683	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1684	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1685	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1686	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1687	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1688	* @arg @ref LL_TIM_OCMODE_PWM1
		1689	* @arg @ref LL_TIM_OCMODE_PWM2
		1690	*/
		1691	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
		1692	{
		1693	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1694	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1695	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
		1696	}
		1697
		1698	/**
		1699	* @brief Set the polarity of an output channel.
		1700	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
		1701	* CCER CC1NP LL_TIM_OC_SetPolarity\n
		1702	* CCER CC2P LL_TIM_OC_SetPolarity\n
		1703	* CCER CC2NP LL_TIM_OC_SetPolarity\n
		1704	* CCER CC3P LL_TIM_OC_SetPolarity\n
		1705	* CCER CC3NP LL_TIM_OC_SetPolarity\n
		1706	* CCER CC4P LL_TIM_OC_SetPolarity
		1707	* @param TIMx Timer instance
		1708	* @param Channel This parameter can be one of the following values:
		1709	* @arg @ref LL_TIM_CHANNEL_CH1
		1710	* @arg @ref LL_TIM_CHANNEL_CH1N
		1711	* @arg @ref LL_TIM_CHANNEL_CH2
		1712	* @arg @ref LL_TIM_CHANNEL_CH2N
		1713	* @arg @ref LL_TIM_CHANNEL_CH3
		1714	* @arg @ref LL_TIM_CHANNEL_CH3N
		1715	* @arg @ref LL_TIM_CHANNEL_CH4
		1716	* @param Polarity This parameter can be one of the following values:
		1717	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1718	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1719	* @retval None
		1720	*/
		1721	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
		1722	{
		1723	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1724	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
		1725	}
		1726
		1727	/**
		1728	* @brief Get the polarity of an output channel.
		1729	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
		1730	* CCER CC1NP LL_TIM_OC_GetPolarity\n
		1731	* CCER CC2P LL_TIM_OC_GetPolarity\n
		1732	* CCER CC2NP LL_TIM_OC_GetPolarity\n
		1733	* CCER CC3P LL_TIM_OC_GetPolarity\n
		1734	* CCER CC3NP LL_TIM_OC_GetPolarity\n
		1735	* CCER CC4P LL_TIM_OC_GetPolarity
		1736	* @param TIMx Timer instance
		1737	* @param Channel This parameter can be one of the following values:
		1738	* @arg @ref LL_TIM_CHANNEL_CH1
		1739	* @arg @ref LL_TIM_CHANNEL_CH1N
		1740	* @arg @ref LL_TIM_CHANNEL_CH2
		1741	* @arg @ref LL_TIM_CHANNEL_CH2N
		1742	* @arg @ref LL_TIM_CHANNEL_CH3
		1743	* @arg @ref LL_TIM_CHANNEL_CH3N
		1744	* @arg @ref LL_TIM_CHANNEL_CH4
		1745	* @retval Returned value can be one of the following values:
		1746	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1747	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1748	*/
		1749	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		1750	{
		1751	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1752	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
		1753	}
		1754
		1755	/**
		1756	* @brief Set the IDLE state of an output channel
		1757	* @note This function is significant only for the timer instances
		1758	* supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
		1759	* can be used to check whether or not a timer instance provides
		1760	* a break input.
		1761	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
		1762	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
		1763	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
		1764	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
		1765	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
		1766	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
		1767	* CR2 OIS4 LL_TIM_OC_SetIdleState
		1768	* @param TIMx Timer instance
		1769	* @param Channel This parameter can be one of the following values:
		1770	* @arg @ref LL_TIM_CHANNEL_CH1
		1771	* @arg @ref LL_TIM_CHANNEL_CH1N
		1772	* @arg @ref LL_TIM_CHANNEL_CH2
		1773	* @arg @ref LL_TIM_CHANNEL_CH2N
		1774	* @arg @ref LL_TIM_CHANNEL_CH3
		1775	* @arg @ref LL_TIM_CHANNEL_CH3N
		1776	* @arg @ref LL_TIM_CHANNEL_CH4
		1777	* @param IdleState This parameter can be one of the following values:
		1778	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1779	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1780	* @retval None
		1781	*/
		1782	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
		1783	{
		1784	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1785	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
		1786	}
		1787
		1788	/**
		1789	* @brief Get the IDLE state of an output channel
		1790	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
		1791	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
		1792	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
		1793	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
		1794	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
		1795	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
		1796	* CR2 OIS4 LL_TIM_OC_GetIdleState
		1797	* @param TIMx Timer instance
		1798	* @param Channel This parameter can be one of the following values:
		1799	* @arg @ref LL_TIM_CHANNEL_CH1
		1800	* @arg @ref LL_TIM_CHANNEL_CH1N
		1801	* @arg @ref LL_TIM_CHANNEL_CH2
		1802	* @arg @ref LL_TIM_CHANNEL_CH2N
		1803	* @arg @ref LL_TIM_CHANNEL_CH3
		1804	* @arg @ref LL_TIM_CHANNEL_CH3N
		1805	* @arg @ref LL_TIM_CHANNEL_CH4
		1806	* @retval Returned value can be one of the following values:
		1807	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1808	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1809	*/
		1810	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
		1811	{
		1812	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1813	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
		1814	}
		1815
		1816	/**
		1817	* @brief Enable fast mode for the output channel.
		1818	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
		1819	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
		1820	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
		1821	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
		1822	* CCMR2 OC4FE LL_TIM_OC_EnableFast
		1823	* @param TIMx Timer instance
		1824	* @param Channel This parameter can be one of the following values:
		1825	* @arg @ref LL_TIM_CHANNEL_CH1
		1826	* @arg @ref LL_TIM_CHANNEL_CH2
		1827	* @arg @ref LL_TIM_CHANNEL_CH3
		1828	* @arg @ref LL_TIM_CHANNEL_CH4
		1829	* @retval None
		1830	*/
		1831	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1832	{
		1833	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1834	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1835	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1836
		1837	}
		1838
		1839	/**
		1840	* @brief Disable fast mode for the output channel.
		1841	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
		1842	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
		1843	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
		1844	* CCMR2 OC4FE LL_TIM_OC_DisableFast
		1845	* @param TIMx Timer instance
		1846	* @param Channel This parameter can be one of the following values:
		1847	* @arg @ref LL_TIM_CHANNEL_CH1
		1848	* @arg @ref LL_TIM_CHANNEL_CH2
		1849	* @arg @ref LL_TIM_CHANNEL_CH3
		1850	* @arg @ref LL_TIM_CHANNEL_CH4
		1851	* @retval None
		1852	*/
		1853	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1854	{
		1855	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1856	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1857	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1858
		1859	}
		1860
		1861	/**
		1862	* @brief Indicates whether fast mode is enabled for the output channel.
		1863	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
		1864	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
		1865	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
		1866	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
		1867	* @param TIMx Timer instance
		1868	* @param Channel This parameter can be one of the following values:
		1869	* @arg @ref LL_TIM_CHANNEL_CH1
		1870	* @arg @ref LL_TIM_CHANNEL_CH2
		1871	* @arg @ref LL_TIM_CHANNEL_CH3
		1872	* @arg @ref LL_TIM_CHANNEL_CH4
		1873	* @retval State of bit (1 or 0).
		1874	*/
		1875	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1876	{
		1877	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1878	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1879	uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
		1880	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1881	}
		1882
		1883	/**
		1884	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
		1885	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
		1886	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
		1887	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
		1888	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
		1889	* @param TIMx Timer instance
		1890	* @param Channel This parameter can be one of the following values:
		1891	* @arg @ref LL_TIM_CHANNEL_CH1
		1892	* @arg @ref LL_TIM_CHANNEL_CH2
		1893	* @arg @ref LL_TIM_CHANNEL_CH3
		1894	* @arg @ref LL_TIM_CHANNEL_CH4
		1895	* @retval None
		1896	*/
		1897	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1898	{
		1899	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1900	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1901	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1902	}
		1903
		1904	/**
		1905	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
		1906	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
		1907	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
		1908	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
		1909	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
		1910	* @param TIMx Timer instance
		1911	* @param Channel This parameter can be one of the following values:
		1912	* @arg @ref LL_TIM_CHANNEL_CH1
		1913	* @arg @ref LL_TIM_CHANNEL_CH2
		1914	* @arg @ref LL_TIM_CHANNEL_CH3
		1915	* @arg @ref LL_TIM_CHANNEL_CH4
		1916	* @retval None
		1917	*/
		1918	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1919	{
		1920	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1921	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1922	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1923	}
		1924
		1925	/**
		1926	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
		1927	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
		1928	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
		1929	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
		1930	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
		1931	* @param TIMx Timer instance
		1932	* @param Channel This parameter can be one of the following values:
		1933	* @arg @ref LL_TIM_CHANNEL_CH1
		1934	* @arg @ref LL_TIM_CHANNEL_CH2
		1935	* @arg @ref LL_TIM_CHANNEL_CH3
		1936	* @arg @ref LL_TIM_CHANNEL_CH4
		1937	* @retval State of bit (1 or 0).
		1938	*/
		1939	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1940	{
		1941	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1942	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1943	uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
		1944	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1945	}
		1946
		1947	/**
		1948	* @brief Enable clearing the output channel on an external event.
		1949	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1950	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1951	* or not a timer instance can clear the OCxREF signal on an external event.
		1952	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
		1953	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
		1954	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
		1955	* CCMR2 OC4CE LL_TIM_OC_EnableClear
		1956	* @param TIMx Timer instance
		1957	* @param Channel This parameter can be one of the following values:
		1958	* @arg @ref LL_TIM_CHANNEL_CH1
		1959	* @arg @ref LL_TIM_CHANNEL_CH2
		1960	* @arg @ref LL_TIM_CHANNEL_CH3
		1961	* @arg @ref LL_TIM_CHANNEL_CH4
		1962	* @retval None
		1963	*/
		1964	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1965	{
		1966	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1967	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1968	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1969	}
		1970
		1971	/**
		1972	* @brief Disable clearing the output channel on an external event.
		1973	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1974	* or not a timer instance can clear the OCxREF signal on an external event.
		1975	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
		1976	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
		1977	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
		1978	* CCMR2 OC4CE LL_TIM_OC_DisableClear
		1979	* @param TIMx Timer instance
		1980	* @param Channel This parameter can be one of the following values:
		1981	* @arg @ref LL_TIM_CHANNEL_CH1
		1982	* @arg @ref LL_TIM_CHANNEL_CH2
		1983	* @arg @ref LL_TIM_CHANNEL_CH3
		1984	* @arg @ref LL_TIM_CHANNEL_CH4
		1985	* @retval None
		1986	*/
		1987	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1988	{
		1989	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1990	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1991	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1992	}
		1993
		1994	/**
		1995	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
		1996	* @note This function enables clearing the output channel on an external event.
		1997	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1998	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1999	* or not a timer instance can clear the OCxREF signal on an external event.
		2000	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
		2001	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
		2002	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
		2003	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
		2004	* @param TIMx Timer instance
		2005	* @param Channel This parameter can be one of the following values:
		2006	* @arg @ref LL_TIM_CHANNEL_CH1
		2007	* @arg @ref LL_TIM_CHANNEL_CH2
		2008	* @arg @ref LL_TIM_CHANNEL_CH3
		2009	* @arg @ref LL_TIM_CHANNEL_CH4
		2010	* @retval State of bit (1 or 0).
		2011	*/
		2012	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
		2013	{
		2014	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2015	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2016	uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
		2017	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		2018	}
		2019
		2020	/**
		2021	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
		2022	* the Ocx and OCxN signals).
		2023	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2024	* dead-time insertion feature is supported by a timer instance.
		2025	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
		2026	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
		2027	* @param TIMx Timer instance
		2028	* @param DeadTime between Min_Data=0 and Max_Data=255
		2029	* @retval None
		2030	*/
		2031	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
		2032	{
		2033	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
		2034	}
		2035
		2036	/**
		2037	* @brief Set compare value for output channel 1 (TIMx_CCR1).
		2038	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2039	* output channel 1 is supported by a timer instance.
		2040	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
		2041	* @param TIMx Timer instance
		2042	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2043	* @retval None
		2044	*/
		2045	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2046	{
		2047	WRITE_REG(TIMx->CCR1, CompareValue);
		2048	}
		2049
		2050	/**
		2051	* @brief Set compare value for output channel 2 (TIMx_CCR2).
		2052	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2053	* output channel 2 is supported by a timer instance.
		2054	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
		2055	* @param TIMx Timer instance
		2056	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2057	* @retval None
		2058	*/
		2059	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2060	{
		2061	WRITE_REG(TIMx->CCR2, CompareValue);
		2062	}
		2063
		2064	/**
		2065	* @brief Set compare value for output channel 3 (TIMx_CCR3).
		2066	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2067	* output channel is supported by a timer instance.
		2068	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
		2069	* @param TIMx Timer instance
		2070	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2071	* @retval None
		2072	*/
		2073	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2074	{
		2075	WRITE_REG(TIMx->CCR3, CompareValue);
		2076	}
		2077
		2078	/**
		2079	* @brief Set compare value for output channel 4 (TIMx_CCR4).
		2080	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2081	* output channel 4 is supported by a timer instance.
		2082	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
		2083	* @param TIMx Timer instance
		2084	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2085	* @retval None
		2086	*/
		2087	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2088	{
		2089	WRITE_REG(TIMx->CCR4, CompareValue);
		2090	}
		2091
		2092	/**
		2093	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
		2094	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2095	* output channel 1 is supported by a timer instance.
		2096	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
		2097	* @param TIMx Timer instance
		2098	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2099	*/
		2100	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
		2101	{
		2102	return (uint32_t)(READ_REG(TIMx->CCR1));
		2103	}
		2104
		2105	/**
		2106	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
		2107	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2108	* output channel 2 is supported by a timer instance.
		2109	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
		2110	* @param TIMx Timer instance
		2111	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2112	*/
		2113	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
		2114	{
		2115	return (uint32_t)(READ_REG(TIMx->CCR2));
		2116	}
		2117
		2118	/**
		2119	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
		2120	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2121	* output channel 3 is supported by a timer instance.
		2122	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
		2123	* @param TIMx Timer instance
		2124	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2125	*/
		2126	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
		2127	{
		2128	return (uint32_t)(READ_REG(TIMx->CCR3));
		2129	}
		2130
		2131	/**
		2132	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
		2133	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2134	* output channel 4 is supported by a timer instance.
		2135	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
		2136	* @param TIMx Timer instance
		2137	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2138	*/
		2139	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
		2140	{
		2141	return (uint32_t)(READ_REG(TIMx->CCR4));
		2142	}
		2143
		2144	/**
		2145	* @}
		2146	*/
		2147
		2148	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
		2149	* @{
		2150	*/
		2151	/**
		2152	* @brief Configure input channel.
		2153	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
		2154	* CCMR1 IC1PSC LL_TIM_IC_Config\n
		2155	* CCMR1 IC1F LL_TIM_IC_Config\n
		2156	* CCMR1 CC2S LL_TIM_IC_Config\n
		2157	* CCMR1 IC2PSC LL_TIM_IC_Config\n
		2158	* CCMR1 IC2F LL_TIM_IC_Config\n
		2159	* CCMR2 CC3S LL_TIM_IC_Config\n
		2160	* CCMR2 IC3PSC LL_TIM_IC_Config\n
		2161	* CCMR2 IC3F LL_TIM_IC_Config\n
		2162	* CCMR2 CC4S LL_TIM_IC_Config\n
		2163	* CCMR2 IC4PSC LL_TIM_IC_Config\n
		2164	* CCMR2 IC4F LL_TIM_IC_Config\n
		2165	* CCER CC1P LL_TIM_IC_Config\n
		2166	* CCER CC1NP LL_TIM_IC_Config\n
		2167	* CCER CC2P LL_TIM_IC_Config\n
		2168	* CCER CC2NP LL_TIM_IC_Config\n
		2169	* CCER CC3P LL_TIM_IC_Config\n
		2170	* CCER CC3NP LL_TIM_IC_Config\n
		2171	* CCER CC4P LL_TIM_IC_Config\n
		2172	* @param TIMx Timer instance
		2173	* @param Channel This parameter can be one of the following values:
		2174	* @arg @ref LL_TIM_CHANNEL_CH1
		2175	* @arg @ref LL_TIM_CHANNEL_CH2
		2176	* @arg @ref LL_TIM_CHANNEL_CH3
		2177	* @arg @ref LL_TIM_CHANNEL_CH4
		2178	* @param Configuration This parameter must be a combination of all the following values:
		2179	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
		2180	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
		2181	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
		2182	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
		2183	* @retval None
		2184	*/
		2185	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		2186	{
		2187	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2188	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2189	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
		2190	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) \
		2191	<< SHIFT_TAB_ICxx[iChannel]);
		2192	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2193	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
		2194	}
		2195
		2196	/**
		2197	* @brief Set the active input.
		2198	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
		2199	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
		2200	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
		2201	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
		2202	* @param TIMx Timer instance
		2203	* @param Channel This parameter can be one of the following values:
		2204	* @arg @ref LL_TIM_CHANNEL_CH1
		2205	* @arg @ref LL_TIM_CHANNEL_CH2
		2206	* @arg @ref LL_TIM_CHANNEL_CH3
		2207	* @arg @ref LL_TIM_CHANNEL_CH4
		2208	* @param ICActiveInput This parameter can be one of the following values:
		2209	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2210	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2211	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2212	* @retval None
		2213	*/
		2214	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
		2215	{
		2216	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2217	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2218	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2219	}
		2220
		2221	/**
		2222	* @brief Get the current active input.
		2223	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
		2224	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
		2225	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
		2226	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
		2227	* @param TIMx Timer instance
		2228	* @param Channel This parameter can be one of the following values:
		2229	* @arg @ref LL_TIM_CHANNEL_CH1
		2230	* @arg @ref LL_TIM_CHANNEL_CH2
		2231	* @arg @ref LL_TIM_CHANNEL_CH3
		2232	* @arg @ref LL_TIM_CHANNEL_CH4
		2233	* @retval Returned value can be one of the following values:
		2234	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2235	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2236	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2237	*/
		2238	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
		2239	{
		2240	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2241	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2242	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2243	}
		2244
		2245	/**
		2246	* @brief Set the prescaler of input channel.
		2247	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
		2248	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
		2249	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
		2250	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
		2251	* @param TIMx Timer instance
		2252	* @param Channel This parameter can be one of the following values:
		2253	* @arg @ref LL_TIM_CHANNEL_CH1
		2254	* @arg @ref LL_TIM_CHANNEL_CH2
		2255	* @arg @ref LL_TIM_CHANNEL_CH3
		2256	* @arg @ref LL_TIM_CHANNEL_CH4
		2257	* @param ICPrescaler This parameter can be one of the following values:
		2258	* @arg @ref LL_TIM_ICPSC_DIV1
		2259	* @arg @ref LL_TIM_ICPSC_DIV2
		2260	* @arg @ref LL_TIM_ICPSC_DIV4
		2261	* @arg @ref LL_TIM_ICPSC_DIV8
		2262	* @retval None
		2263	*/
		2264	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
		2265	{
		2266	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2267	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2268	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2269	}
		2270
		2271	/**
		2272	* @brief Get the current prescaler value acting on an input channel.
		2273	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
		2274	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
		2275	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
		2276	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
		2277	* @param TIMx Timer instance
		2278	* @param Channel This parameter can be one of the following values:
		2279	* @arg @ref LL_TIM_CHANNEL_CH1
		2280	* @arg @ref LL_TIM_CHANNEL_CH2
		2281	* @arg @ref LL_TIM_CHANNEL_CH3
		2282	* @arg @ref LL_TIM_CHANNEL_CH4
		2283	* @retval Returned value can be one of the following values:
		2284	* @arg @ref LL_TIM_ICPSC_DIV1
		2285	* @arg @ref LL_TIM_ICPSC_DIV2
		2286	* @arg @ref LL_TIM_ICPSC_DIV4
		2287	* @arg @ref LL_TIM_ICPSC_DIV8
		2288	*/
		2289	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
		2290	{
		2291	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2292	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2293	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2294	}
		2295
		2296	/**
		2297	* @brief Set the input filter duration.
		2298	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
		2299	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
		2300	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
		2301	* CCMR2 IC4F LL_TIM_IC_SetFilter
		2302	* @param TIMx Timer instance
		2303	* @param Channel This parameter can be one of the following values:
		2304	* @arg @ref LL_TIM_CHANNEL_CH1
		2305	* @arg @ref LL_TIM_CHANNEL_CH2
		2306	* @arg @ref LL_TIM_CHANNEL_CH3
		2307	* @arg @ref LL_TIM_CHANNEL_CH4
		2308	* @param ICFilter This parameter can be one of the following values:
		2309	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2310	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2311	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2312	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2313	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2314	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2315	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2316	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2317	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2318	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2319	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2320	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2321	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2322	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2323	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2324	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2325	* @retval None
		2326	*/
		2327	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
		2328	{
		2329	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2330	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2331	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2332	}
		2333
		2334	/**
		2335	* @brief Get the input filter duration.
		2336	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
		2337	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
		2338	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
		2339	* CCMR2 IC4F LL_TIM_IC_GetFilter
		2340	* @param TIMx Timer instance
		2341	* @param Channel This parameter can be one of the following values:
		2342	* @arg @ref LL_TIM_CHANNEL_CH1
		2343	* @arg @ref LL_TIM_CHANNEL_CH2
		2344	* @arg @ref LL_TIM_CHANNEL_CH3
		2345	* @arg @ref LL_TIM_CHANNEL_CH4
		2346	* @retval Returned value can be one of the following values:
		2347	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2348	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2349	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2350	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2351	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2352	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2353	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2354	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2355	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2356	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2357	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2358	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2359	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2360	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2361	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2362	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2363	*/
		2364	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
		2365	{
		2366	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2367	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2368	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2369	}
		2370
		2371	/**
		2372	* @brief Set the input channel polarity.
		2373	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
		2374	* CCER CC1NP LL_TIM_IC_SetPolarity\n
		2375	* CCER CC2P LL_TIM_IC_SetPolarity\n
		2376	* CCER CC2NP LL_TIM_IC_SetPolarity\n
		2377	* CCER CC3P LL_TIM_IC_SetPolarity\n
		2378	* CCER CC3NP LL_TIM_IC_SetPolarity\n
		2379	* CCER CC4P LL_TIM_IC_SetPolarity\n
		2380	* @param TIMx Timer instance
		2381	* @param Channel This parameter can be one of the following values:
		2382	* @arg @ref LL_TIM_CHANNEL_CH1
		2383	* @arg @ref LL_TIM_CHANNEL_CH2
		2384	* @arg @ref LL_TIM_CHANNEL_CH3
		2385	* @arg @ref LL_TIM_CHANNEL_CH4
		2386	* @param ICPolarity This parameter can be one of the following values:
		2387	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2388	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2389	* @retval None
		2390	*/
		2391	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
		2392	{
		2393	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2394	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2395	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
		2396	}
		2397
		2398	/**
		2399	* @brief Get the current input channel polarity.
		2400	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
		2401	* CCER CC1NP LL_TIM_IC_GetPolarity\n
		2402	* CCER CC2P LL_TIM_IC_GetPolarity\n
		2403	* CCER CC2NP LL_TIM_IC_GetPolarity\n
		2404	* CCER CC3P LL_TIM_IC_GetPolarity\n
		2405	* CCER CC3NP LL_TIM_IC_GetPolarity\n
		2406	* CCER CC4P LL_TIM_IC_GetPolarity\n
		2407	* @param TIMx Timer instance
		2408	* @param Channel This parameter can be one of the following values:
		2409	* @arg @ref LL_TIM_CHANNEL_CH1
		2410	* @arg @ref LL_TIM_CHANNEL_CH2
		2411	* @arg @ref LL_TIM_CHANNEL_CH3
		2412	* @arg @ref LL_TIM_CHANNEL_CH4
		2413	* @retval Returned value can be one of the following values:
		2414	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2415	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2416	*/
		2417	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		2418	{
		2419	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2420	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
		2421	SHIFT_TAB_CCxP[iChannel]);
		2422	}
		2423
		2424	/**
		2425	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
		2426	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2427	* a timer instance provides an XOR input.
		2428	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
		2429	* @param TIMx Timer instance
		2430	* @retval None
		2431	*/
		2432	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
		2433	{
		2434	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2435	}
		2436
		2437	/**
		2438	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
		2439	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2440	* a timer instance provides an XOR input.
		2441	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
		2442	* @param TIMx Timer instance
		2443	* @retval None
		2444	*/
		2445	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
		2446	{
		2447	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2448	}
		2449
		2450	/**
		2451	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
		2452	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2453	* a timer instance provides an XOR input.
		2454	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
		2455	* @param TIMx Timer instance
		2456	* @retval State of bit (1 or 0).
		2457	*/
		2458	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
		2459	{
		2460	return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
		2461	}
		2462
		2463	/**
		2464	* @brief Get captured value for input channel 1.
		2465	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2466	* input channel 1 is supported by a timer instance.
		2467	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
		2468	* @param TIMx Timer instance
		2469	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2470	*/
		2471	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
		2472	{
		2473	return (uint32_t)(READ_REG(TIMx->CCR1));
		2474	}
		2475
		2476	/**
		2477	* @brief Get captured value for input channel 2.
		2478	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2479	* input channel 2 is supported by a timer instance.
		2480	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
		2481	* @param TIMx Timer instance
		2482	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2483	*/
		2484	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
		2485	{
		2486	return (uint32_t)(READ_REG(TIMx->CCR2));
		2487	}
		2488
		2489	/**
		2490	* @brief Get captured value for input channel 3.
		2491	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2492	* input channel 3 is supported by a timer instance.
		2493	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
		2494	* @param TIMx Timer instance
		2495	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2496	*/
		2497	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
		2498	{
		2499	return (uint32_t)(READ_REG(TIMx->CCR3));
		2500	}
		2501
		2502	/**
		2503	* @brief Get captured value for input channel 4.
		2504	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2505	* input channel 4 is supported by a timer instance.
		2506	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
		2507	* @param TIMx Timer instance
		2508	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2509	*/
		2510	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
		2511	{
		2512	return (uint32_t)(READ_REG(TIMx->CCR4));
		2513	}
		2514
		2515	/**
		2516	* @}
		2517	*/
		2518
		2519	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
		2520	* @{
		2521	*/
		2522	/**
		2523	* @brief Enable external clock mode 2.
		2524	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
		2525	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2526	* whether or not a timer instance supports external clock mode2.
		2527	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
		2528	* @param TIMx Timer instance
		2529	* @retval None
		2530	*/
		2531	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
		2532	{
		2533	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2534	}
		2535
		2536	/**
		2537	* @brief Disable external clock mode 2.
		2538	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2539	* whether or not a timer instance supports external clock mode2.
		2540	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
		2541	* @param TIMx Timer instance
		2542	* @retval None
		2543	*/
		2544	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
		2545	{
		2546	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2547	}
		2548
		2549	/**
		2550	* @brief Indicate whether external clock mode 2 is enabled.
		2551	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2552	* whether or not a timer instance supports external clock mode2.
		2553	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
		2554	* @param TIMx Timer instance
		2555	* @retval State of bit (1 or 0).
		2556	*/
		2557	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
		2558	{
		2559	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
		2560	}
		2561
		2562	/**
		2563	* @brief Set the clock source of the counter clock.
		2564	* @note when selected clock source is external clock mode 1, the timer input
		2565	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
		2566	* function. This timer input must be configured by calling
		2567	* the @ref LL_TIM_IC_Config() function.
		2568	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
		2569	* whether or not a timer instance supports external clock mode1.
		2570	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2571	* whether or not a timer instance supports external clock mode2.
		2572	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
		2573	* SMCR ECE LL_TIM_SetClockSource
		2574	* @param TIMx Timer instance
		2575	* @param ClockSource This parameter can be one of the following values:
		2576	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
		2577	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
		2578	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
		2579	* @retval None
		2580	*/
		2581	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
		2582	{
		2583	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
		2584	}
		2585
		2586	/**
		2587	* @brief Set the encoder interface mode.
		2588	* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
		2589	* whether or not a timer instance supports the encoder mode.
		2590	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
		2591	* @param TIMx Timer instance
		2592	* @param EncoderMode This parameter can be one of the following values:
		2593	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
		2594	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
		2595	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
		2596	* @retval None
		2597	*/
		2598	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
		2599	{
		2600	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
		2601	}
		2602
		2603	/**
		2604	* @}
		2605	*/
		2606
		2607	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
		2608	* @{
		2609	*/
		2610	/**
		2611	* @brief Set the trigger output (TRGO) used for timer synchronization .
		2612	* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
		2613	* whether or not a timer instance can operate as a master timer.
		2614	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
		2615	* @param TIMx Timer instance
		2616	* @param TimerSynchronization This parameter can be one of the following values:
		2617	* @arg @ref LL_TIM_TRGO_RESET
		2618	* @arg @ref LL_TIM_TRGO_ENABLE
		2619	* @arg @ref LL_TIM_TRGO_UPDATE
		2620	* @arg @ref LL_TIM_TRGO_CC1IF
		2621	* @arg @ref LL_TIM_TRGO_OC1REF
		2622	* @arg @ref LL_TIM_TRGO_OC2REF
		2623	* @arg @ref LL_TIM_TRGO_OC3REF
		2624	* @arg @ref LL_TIM_TRGO_OC4REF
		2625	* @retval None
		2626	*/
		2627	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
		2628	{
		2629	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
		2630	}
		2631
		2632	/**
		2633	* @brief Set the synchronization mode of a slave timer.
		2634	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2635	* a timer instance can operate as a slave timer.
		2636	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
		2637	* @param TIMx Timer instance
		2638	* @param SlaveMode This parameter can be one of the following values:
		2639	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
		2640	* @arg @ref LL_TIM_SLAVEMODE_RESET
		2641	* @arg @ref LL_TIM_SLAVEMODE_GATED
		2642	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
		2643	* @retval None
		2644	*/
		2645	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
		2646	{
		2647	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
		2648	}
		2649
		2650	/**
		2651	* @brief Set the selects the trigger input to be used to synchronize the counter.
		2652	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2653	* a timer instance can operate as a slave timer.
		2654	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
		2655	* @param TIMx Timer instance
		2656	* @param TriggerInput This parameter can be one of the following values:
		2657	* @arg @ref LL_TIM_TS_ITR0
		2658	* @arg @ref LL_TIM_TS_ITR1
		2659	* @arg @ref LL_TIM_TS_ITR2
		2660	* @arg @ref LL_TIM_TS_ITR3
		2661	* @arg @ref LL_TIM_TS_TI1F_ED
		2662	* @arg @ref LL_TIM_TS_TI1FP1
		2663	* @arg @ref LL_TIM_TS_TI2FP2
		2664	* @arg @ref LL_TIM_TS_ETRF
		2665	* @retval None
		2666	*/
		2667	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
		2668	{
		2669	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
		2670	}
		2671
		2672	/**
		2673	* @brief Enable the Master/Slave mode.
		2674	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2675	* a timer instance can operate as a slave timer.
		2676	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
		2677	* @param TIMx Timer instance
		2678	* @retval None
		2679	*/
		2680	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
		2681	{
		2682	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2683	}
		2684
		2685	/**
		2686	* @brief Disable the Master/Slave mode.
		2687	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2688	* a timer instance can operate as a slave timer.
		2689	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
		2690	* @param TIMx Timer instance
		2691	* @retval None
		2692	*/
		2693	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
		2694	{
		2695	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2696	}
		2697
		2698	/**
		2699	* @brief Indicates whether the Master/Slave mode is enabled.
		2700	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2701	* a timer instance can operate as a slave timer.
		2702	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
		2703	* @param TIMx Timer instance
		2704	* @retval State of bit (1 or 0).
		2705	*/
		2706	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
		2707	{
		2708	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
		2709	}
		2710
		2711	/**
		2712	* @brief Configure the external trigger (ETR) input.
		2713	* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
		2714	* a timer instance provides an external trigger input.
		2715	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
		2716	* SMCR ETPS LL_TIM_ConfigETR\n
		2717	* SMCR ETF LL_TIM_ConfigETR
		2718	* @param TIMx Timer instance
		2719	* @param ETRPolarity This parameter can be one of the following values:
		2720	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
		2721	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
		2722	* @param ETRPrescaler This parameter can be one of the following values:
		2723	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
		2724	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
		2725	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
		2726	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
		2727	* @param ETRFilter This parameter can be one of the following values:
		2728	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
		2729	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
		2730	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
		2731	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
		2732	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
		2733	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
		2734	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
		2735	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
		2736	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
		2737	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
		2738	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
		2739	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
		2740	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
		2741	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
		2742	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
		2743	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
		2744	* @retval None
		2745	*/
		2746	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
		2747	uint32_t ETRFilter)
		2748	{
		2749	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
		2750	}
		2751
		2752	/**
		2753	* @}
		2754	*/
		2755
		2756	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
		2757	* @{
		2758	*/
		2759	/**
		2760	* @brief Enable the break function.
		2761	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2762	* a timer instance provides a break input.
		2763	* @rmtoll BDTR BKE LL_TIM_EnableBRK
		2764	* @param TIMx Timer instance
		2765	* @retval None
		2766	*/
		2767	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
		2768	{
		2769	__IO uint32_t tmpreg;
		2770	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
		2771	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
		2772	tmpreg = READ_REG(TIMx->BDTR);
		2773	(void)(tmpreg);
		2774	}
		2775
		2776	/**
		2777	* @brief Disable the break function.
		2778	* @rmtoll BDTR BKE LL_TIM_DisableBRK
		2779	* @param TIMx Timer instance
		2780	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2781	* a timer instance provides a break input.
		2782	* @retval None
		2783	*/
		2784	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
		2785	{
		2786	__IO uint32_t tmpreg;
		2787	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
		2788	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
		2789	tmpreg = READ_REG(TIMx->BDTR);
		2790	(void)(tmpreg);
		2791	}
		2792
		2793	/**
		2794	* @brief Configure the break input.
		2795	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2796	* a timer instance provides a break input.
		2797	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
		2798	* @param TIMx Timer instance
		2799	* @param BreakPolarity This parameter can be one of the following values:
		2800	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
		2801	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
		2802	* @retval None
		2803	*/
		2804	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
		2805	{
		2806	__IO uint32_t tmpreg;
		2807	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
		2808	/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
		2809	tmpreg = READ_REG(TIMx->BDTR);
		2810	(void)(tmpreg);
		2811	}
		2812
		2813	/**
		2814	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
		2815	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2816	* a timer instance provides a break input.
		2817	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
		2818	* BDTR OSSR LL_TIM_SetOffStates
		2819	* @param TIMx Timer instance
		2820	* @param OffStateIdle This parameter can be one of the following values:
		2821	* @arg @ref LL_TIM_OSSI_DISABLE
		2822	* @arg @ref LL_TIM_OSSI_ENABLE
		2823	* @param OffStateRun This parameter can be one of the following values:
		2824	* @arg @ref LL_TIM_OSSR_DISABLE
		2825	* @arg @ref LL_TIM_OSSR_ENABLE
		2826	* @retval None
		2827	*/
		2828	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
		2829	{
		2830	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
		2831	}
		2832
		2833	/**
		2834	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
		2835	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2836	* a timer instance provides a break input.
		2837	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
		2838	* @param TIMx Timer instance
		2839	* @retval None
		2840	*/
		2841	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
		2842	{
		2843	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2844	}
		2845
		2846	/**
		2847	* @brief Disable automatic output (MOE can be set only by software).
		2848	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2849	* a timer instance provides a break input.
		2850	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
		2851	* @param TIMx Timer instance
		2852	* @retval None
		2853	*/
		2854	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
		2855	{
		2856	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2857	}
		2858
		2859	/**
		2860	* @brief Indicate whether automatic output is enabled.
		2861	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2862	* a timer instance provides a break input.
		2863	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
		2864	* @param TIMx Timer instance
		2865	* @retval State of bit (1 or 0).
		2866	*/
		2867	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
		2868	{
		2869	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
		2870	}
		2871
		2872	/**
		2873	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
		2874	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2875	* software and is reset in case of break or break2 event
		2876	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2877	* a timer instance provides a break input.
		2878	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
		2879	* @param TIMx Timer instance
		2880	* @retval None
		2881	*/
		2882	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
		2883	{
		2884	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2885	}
		2886
		2887	/**
		2888	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
		2889	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2890	* software and is reset in case of break or break2 event.
		2891	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2892	* a timer instance provides a break input.
		2893	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
		2894	* @param TIMx Timer instance
		2895	* @retval None
		2896	*/
		2897	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
		2898	{
		2899	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2900	}
		2901
		2902	/**
		2903	* @brief Indicates whether outputs are enabled.
		2904	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2905	* a timer instance provides a break input.
		2906	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
		2907	* @param TIMx Timer instance
		2908	* @retval State of bit (1 or 0).
		2909	*/
		2910	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
		2911	{
		2912	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
		2913	}
		2914
		2915	/**
		2916	* @}
		2917	*/
		2918
		2919	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
		2920	* @{
		2921	*/
		2922	/**
		2923	* @brief Configures the timer DMA burst feature.
		2924	* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
		2925	* not a timer instance supports the DMA burst mode.
		2926	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
		2927	* DCR DBA LL_TIM_ConfigDMABurst
		2928	* @param TIMx Timer instance
		2929	* @param DMABurstBaseAddress This parameter can be one of the following values:
		2930	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
		2931	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
		2932	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
		2933	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
		2934	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
		2935	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
		2936	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
		2937	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
		2938	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
		2939	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
		2940	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
		2941	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
		2942	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
		2943	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
		2944	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
		2945	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
		2946	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
		2947	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
		2948	* @param DMABurstLength This parameter can be one of the following values:
		2949	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
		2950	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
		2951	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
		2952	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
		2953	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
		2954	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
		2955	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
		2956	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
		2957	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
		2958	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
		2959	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
		2960	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
		2961	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
		2962	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
		2963	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
		2964	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
		2965	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
		2966	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
		2967	* @retval None
		2968	*/
		2969	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
		2970	{
		2971	MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL \| TIM_DCR_DBA), (DMABurstBaseAddress \| DMABurstLength));
		2972	}
		2973
		2974	/**
		2975	* @}
		2976	*/
		2977
		2978
		2979	/**
		2980	* @}
		2981	*/
		2982
		2983	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
		2984	* @{
		2985	*/
		2986	/**
		2987	* @brief Clear the update interrupt flag (UIF).
		2988	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
		2989	* @param TIMx Timer instance
		2990	* @retval None
		2991	*/
		2992	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
		2993	{
		2994	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
		2995	}
		2996
		2997	/**
		2998	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
		2999	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
		3000	* @param TIMx Timer instance
		3001	* @retval State of bit (1 or 0).
		3002	*/
		3003	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
		3004	{
		3005	return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
		3006	}
		3007
		3008	/**
		3009	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
		3010	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
		3011	* @param TIMx Timer instance
		3012	* @retval None
		3013	*/
		3014	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
		3015	{
		3016	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
		3017	}
		3018
		3019	/**
		3020	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
		3021	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
		3022	* @param TIMx Timer instance
		3023	* @retval State of bit (1 or 0).
		3024	*/
		3025	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
		3026	{
		3027	return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
		3028	}
		3029
		3030	/**
		3031	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
		3032	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
		3033	* @param TIMx Timer instance
		3034	* @retval None
		3035	*/
		3036	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
		3037	{
		3038	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
		3039	}
		3040
		3041	/**
		3042	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
		3043	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
		3044	* @param TIMx Timer instance
		3045	* @retval State of bit (1 or 0).
		3046	*/
		3047	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
		3048	{
		3049	return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
		3050	}
		3051
		3052	/**
		3053	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
		3054	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
		3055	* @param TIMx Timer instance
		3056	* @retval None
		3057	*/
		3058	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
		3059	{
		3060	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
		3061	}
		3062
		3063	/**
		3064	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
		3065	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
		3066	* @param TIMx Timer instance
		3067	* @retval State of bit (1 or 0).
		3068	*/
		3069	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
		3070	{
		3071	return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
		3072	}
		3073
		3074	/**
		3075	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
		3076	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
		3077	* @param TIMx Timer instance
		3078	* @retval None
		3079	*/
		3080	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
		3081	{
		3082	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
		3083	}
		3084
		3085	/**
		3086	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
		3087	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
		3088	* @param TIMx Timer instance
		3089	* @retval State of bit (1 or 0).
		3090	*/
		3091	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
		3092	{
		3093	return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
		3094	}
		3095
		3096	/**
		3097	* @brief Clear the commutation interrupt flag (COMIF).
		3098	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
		3099	* @param TIMx Timer instance
		3100	* @retval None
		3101	*/
		3102	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
		3103	{
		3104	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
		3105	}
		3106
		3107	/**
		3108	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
		3109	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
		3110	* @param TIMx Timer instance
		3111	* @retval State of bit (1 or 0).
		3112	*/
		3113	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
		3114	{
		3115	return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
		3116	}
		3117
		3118	/**
		3119	* @brief Clear the trigger interrupt flag (TIF).
		3120	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
		3121	* @param TIMx Timer instance
		3122	* @retval None
		3123	*/
		3124	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
		3125	{
		3126	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
		3127	}
		3128
		3129	/**
		3130	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
		3131	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
		3132	* @param TIMx Timer instance
		3133	* @retval State of bit (1 or 0).
		3134	*/
		3135	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
		3136	{
		3137	return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
		3138	}
		3139
		3140	/**
		3141	* @brief Clear the break interrupt flag (BIF).
		3142	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
		3143	* @param TIMx Timer instance
		3144	* @retval None
		3145	*/
		3146	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
		3147	{
		3148	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
		3149	}
		3150
		3151	/**
		3152	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
		3153	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
		3154	* @param TIMx Timer instance
		3155	* @retval State of bit (1 or 0).
		3156	*/
		3157	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
		3158	{
		3159	return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
		3160	}
		3161
		3162	/**
		3163	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
		3164	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
		3165	* @param TIMx Timer instance
		3166	* @retval None
		3167	*/
		3168	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
		3169	{
		3170	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
		3171	}
		3172
		3173	/**
		3174	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
		3175	* (Capture/Compare 1 interrupt is pending).
		3176	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
		3177	* @param TIMx Timer instance
		3178	* @retval State of bit (1 or 0).
		3179	*/
		3180	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
		3181	{
		3182	return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
		3183	}
		3184
		3185	/**
		3186	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
		3187	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
		3188	* @param TIMx Timer instance
		3189	* @retval None
		3190	*/
		3191	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
		3192	{
		3193	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
		3194	}
		3195
		3196	/**
		3197	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
		3198	* (Capture/Compare 2 over-capture interrupt is pending).
		3199	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
		3200	* @param TIMx Timer instance
		3201	* @retval State of bit (1 or 0).
		3202	*/
		3203	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
		3204	{
		3205	return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
		3206	}
		3207
		3208	/**
		3209	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
		3210	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
		3211	* @param TIMx Timer instance
		3212	* @retval None
		3213	*/
		3214	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
		3215	{
		3216	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
		3217	}
		3218
		3219	/**
		3220	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
		3221	* (Capture/Compare 3 over-capture interrupt is pending).
		3222	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
		3223	* @param TIMx Timer instance
		3224	* @retval State of bit (1 or 0).
		3225	*/
		3226	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
		3227	{
		3228	return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
		3229	}
		3230
		3231	/**
		3232	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
		3233	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
		3234	* @param TIMx Timer instance
		3235	* @retval None
		3236	*/
		3237	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
		3238	{
		3239	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
		3240	}
		3241
		3242	/**
		3243	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
		3244	* (Capture/Compare 4 over-capture interrupt is pending).
		3245	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
		3246	* @param TIMx Timer instance
		3247	* @retval State of bit (1 or 0).
		3248	*/
		3249	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
		3250	{
		3251	return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
		3252	}
		3253
		3254	/**
		3255	* @}
		3256	*/
		3257
		3258	/** @defgroup TIM_LL_EF_IT_Management IT-Management
		3259	* @{
		3260	*/
		3261	/**
		3262	* @brief Enable update interrupt (UIE).
		3263	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
		3264	* @param TIMx Timer instance
		3265	* @retval None
		3266	*/
		3267	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
		3268	{
		3269	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
		3270	}
		3271
		3272	/**
		3273	* @brief Disable update interrupt (UIE).
		3274	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
		3275	* @param TIMx Timer instance
		3276	* @retval None
		3277	*/
		3278	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
		3279	{
		3280	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
		3281	}
		3282
		3283	/**
		3284	* @brief Indicates whether the update interrupt (UIE) is enabled.
		3285	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
		3286	* @param TIMx Timer instance
		3287	* @retval State of bit (1 or 0).
		3288	*/
		3289	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
		3290	{
		3291	return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
		3292	}
		3293
		3294	/**
		3295	* @brief Enable capture/compare 1 interrupt (CC1IE).
		3296	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
		3297	* @param TIMx Timer instance
		3298	* @retval None
		3299	*/
		3300	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
		3301	{
		3302	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3303	}
		3304
		3305	/**
		3306	* @brief Disable capture/compare 1 interrupt (CC1IE).
		3307	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
		3308	* @param TIMx Timer instance
		3309	* @retval None
		3310	*/
		3311	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
		3312	{
		3313	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3314	}
		3315
		3316	/**
		3317	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
		3318	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
		3319	* @param TIMx Timer instance
		3320	* @retval State of bit (1 or 0).
		3321	*/
		3322	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
		3323	{
		3324	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
		3325	}
		3326
		3327	/**
		3328	* @brief Enable capture/compare 2 interrupt (CC2IE).
		3329	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
		3330	* @param TIMx Timer instance
		3331	* @retval None
		3332	*/
		3333	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
		3334	{
		3335	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3336	}
		3337
		3338	/**
		3339	* @brief Disable capture/compare 2 interrupt (CC2IE).
		3340	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
		3341	* @param TIMx Timer instance
		3342	* @retval None
		3343	*/
		3344	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
		3345	{
		3346	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3347	}
		3348
		3349	/**
		3350	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
		3351	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
		3352	* @param TIMx Timer instance
		3353	* @retval State of bit (1 or 0).
		3354	*/
		3355	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
		3356	{
		3357	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
		3358	}
		3359
		3360	/**
		3361	* @brief Enable capture/compare 3 interrupt (CC3IE).
		3362	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
		3363	* @param TIMx Timer instance
		3364	* @retval None
		3365	*/
		3366	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
		3367	{
		3368	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3369	}
		3370
		3371	/**
		3372	* @brief Disable capture/compare 3 interrupt (CC3IE).
		3373	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
		3374	* @param TIMx Timer instance
		3375	* @retval None
		3376	*/
		3377	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
		3378	{
		3379	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3380	}
		3381
		3382	/**
		3383	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
		3384	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
		3385	* @param TIMx Timer instance
		3386	* @retval State of bit (1 or 0).
		3387	*/
		3388	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
		3389	{
		3390	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
		3391	}
		3392
		3393	/**
		3394	* @brief Enable capture/compare 4 interrupt (CC4IE).
		3395	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
		3396	* @param TIMx Timer instance
		3397	* @retval None
		3398	*/
		3399	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
		3400	{
		3401	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3402	}
		3403
		3404	/**
		3405	* @brief Disable capture/compare 4 interrupt (CC4IE).
		3406	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
		3407	* @param TIMx Timer instance
		3408	* @retval None
		3409	*/
		3410	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
		3411	{
		3412	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3413	}
		3414
		3415	/**
		3416	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
		3417	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
		3418	* @param TIMx Timer instance
		3419	* @retval State of bit (1 or 0).
		3420	*/
		3421	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
		3422	{
		3423	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
		3424	}
		3425
		3426	/**
		3427	* @brief Enable commutation interrupt (COMIE).
		3428	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
		3429	* @param TIMx Timer instance
		3430	* @retval None
		3431	*/
		3432	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
		3433	{
		3434	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3435	}
		3436
		3437	/**
		3438	* @brief Disable commutation interrupt (COMIE).
		3439	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
		3440	* @param TIMx Timer instance
		3441	* @retval None
		3442	*/
		3443	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
		3444	{
		3445	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3446	}
		3447
		3448	/**
		3449	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
		3450	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
		3451	* @param TIMx Timer instance
		3452	* @retval State of bit (1 or 0).
		3453	*/
		3454	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
		3455	{
		3456	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
		3457	}
		3458
		3459	/**
		3460	* @brief Enable trigger interrupt (TIE).
		3461	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
		3462	* @param TIMx Timer instance
		3463	* @retval None
		3464	*/
		3465	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
		3466	{
		3467	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
		3468	}
		3469
		3470	/**
		3471	* @brief Disable trigger interrupt (TIE).
		3472	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
		3473	* @param TIMx Timer instance
		3474	* @retval None
		3475	*/
		3476	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
		3477	{
		3478	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
		3479	}
		3480
		3481	/**
		3482	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
		3483	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
		3484	* @param TIMx Timer instance
		3485	* @retval State of bit (1 or 0).
		3486	*/
		3487	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
		3488	{
		3489	return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
		3490	}
		3491
		3492	/**
		3493	* @brief Enable break interrupt (BIE).
		3494	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
		3495	* @param TIMx Timer instance
		3496	* @retval None
		3497	*/
		3498	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
		3499	{
		3500	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
		3501	}
		3502
		3503	/**
		3504	* @brief Disable break interrupt (BIE).
		3505	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
		3506	* @param TIMx Timer instance
		3507	* @retval None
		3508	*/
		3509	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
		3510	{
		3511	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
		3512	}
		3513
		3514	/**
		3515	* @brief Indicates whether the break interrupt (BIE) is enabled.
		3516	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
		3517	* @param TIMx Timer instance
		3518	* @retval State of bit (1 or 0).
		3519	*/
		3520	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
		3521	{
		3522	return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
		3523	}
		3524
		3525	/**
		3526	* @}
		3527	*/
		3528
		3529	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
		3530	* @{
		3531	*/
		3532	/**
		3533	* @brief Enable update DMA request (UDE).
		3534	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
		3535	* @param TIMx Timer instance
		3536	* @retval None
		3537	*/
		3538	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3539	{
		3540	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
		3541	}
		3542
		3543	/**
		3544	* @brief Disable update DMA request (UDE).
		3545	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
		3546	* @param TIMx Timer instance
		3547	* @retval None
		3548	*/
		3549	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3550	{
		3551	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
		3552	}
		3553
		3554	/**
		3555	* @brief Indicates whether the update DMA request (UDE) is enabled.
		3556	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
		3557	* @param TIMx Timer instance
		3558	* @retval State of bit (1 or 0).
		3559	*/
		3560	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3561	{
		3562	return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
		3563	}
		3564
		3565	/**
		3566	* @brief Enable capture/compare 1 DMA request (CC1DE).
		3567	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
		3568	* @param TIMx Timer instance
		3569	* @retval None
		3570	*/
		3571	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
		3572	{
		3573	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3574	}
		3575
		3576	/**
		3577	* @brief Disable capture/compare 1 DMA request (CC1DE).
		3578	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
		3579	* @param TIMx Timer instance
		3580	* @retval None
		3581	*/
		3582	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
		3583	{
		3584	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3585	}
		3586
		3587	/**
		3588	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
		3589	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
		3590	* @param TIMx Timer instance
		3591	* @retval State of bit (1 or 0).
		3592	*/
		3593	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
		3594	{
		3595	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
		3596	}
		3597
		3598	/**
		3599	* @brief Enable capture/compare 2 DMA request (CC2DE).
		3600	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
		3601	* @param TIMx Timer instance
		3602	* @retval None
		3603	*/
		3604	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
		3605	{
		3606	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3607	}
		3608
		3609	/**
		3610	* @brief Disable capture/compare 2 DMA request (CC2DE).
		3611	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
		3612	* @param TIMx Timer instance
		3613	* @retval None
		3614	*/
		3615	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
		3616	{
		3617	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3618	}
		3619
		3620	/**
		3621	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
		3622	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
		3623	* @param TIMx Timer instance
		3624	* @retval State of bit (1 or 0).
		3625	*/
		3626	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
		3627	{
		3628	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
		3629	}
		3630
		3631	/**
		3632	* @brief Enable capture/compare 3 DMA request (CC3DE).
		3633	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
		3634	* @param TIMx Timer instance
		3635	* @retval None
		3636	*/
		3637	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
		3638	{
		3639	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3640	}
		3641
		3642	/**
		3643	* @brief Disable capture/compare 3 DMA request (CC3DE).
		3644	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
		3645	* @param TIMx Timer instance
		3646	* @retval None
		3647	*/
		3648	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
		3649	{
		3650	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3651	}
		3652
		3653	/**
		3654	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
		3655	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
		3656	* @param TIMx Timer instance
		3657	* @retval State of bit (1 or 0).
		3658	*/
		3659	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
		3660	{
		3661	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
		3662	}
		3663
		3664	/**
		3665	* @brief Enable capture/compare 4 DMA request (CC4DE).
		3666	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
		3667	* @param TIMx Timer instance
		3668	* @retval None
		3669	*/
		3670	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
		3671	{
		3672	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3673	}
		3674
		3675	/**
		3676	* @brief Disable capture/compare 4 DMA request (CC4DE).
		3677	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
		3678	* @param TIMx Timer instance
		3679	* @retval None
		3680	*/
		3681	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
		3682	{
		3683	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3684	}
		3685
		3686	/**
		3687	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
		3688	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
		3689	* @param TIMx Timer instance
		3690	* @retval State of bit (1 or 0).
		3691	*/
		3692	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
		3693	{
		3694	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
		3695	}
		3696
		3697	/**
		3698	* @brief Enable commutation DMA request (COMDE).
		3699	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
		3700	* @param TIMx Timer instance
		3701	* @retval None
		3702	*/
		3703	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
		3704	{
		3705	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3706	}
		3707
		3708	/**
		3709	* @brief Disable commutation DMA request (COMDE).
		3710	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
		3711	* @param TIMx Timer instance
		3712	* @retval None
		3713	*/
		3714	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
		3715	{
		3716	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3717	}
		3718
		3719	/**
		3720	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
		3721	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
		3722	* @param TIMx Timer instance
		3723	* @retval State of bit (1 or 0).
		3724	*/
		3725	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
		3726	{
		3727	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
		3728	}
		3729
		3730	/**
		3731	* @brief Enable trigger interrupt (TDE).
		3732	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
		3733	* @param TIMx Timer instance
		3734	* @retval None
		3735	*/
		3736	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3737	{
		3738	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
		3739	}
		3740
		3741	/**
		3742	* @brief Disable trigger interrupt (TDE).
		3743	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
		3744	* @param TIMx Timer instance
		3745	* @retval None
		3746	*/
		3747	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3748	{
		3749	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
		3750	}
		3751
		3752	/**
		3753	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
		3754	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
		3755	* @param TIMx Timer instance
		3756	* @retval State of bit (1 or 0).
		3757	*/
		3758	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
		3759	{
		3760	return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
		3761	}
		3762
		3763	/**
		3764	* @}
		3765	*/
		3766
		3767	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
		3768	* @{
		3769	*/
		3770	/**
		3771	* @brief Generate an update event.
		3772	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
		3773	* @param TIMx Timer instance
		3774	* @retval None
		3775	*/
		3776	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
		3777	{
		3778	SET_BIT(TIMx->EGR, TIM_EGR_UG);
		3779	}
		3780
		3781	/**
		3782	* @brief Generate Capture/Compare 1 event.
		3783	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
		3784	* @param TIMx Timer instance
		3785	* @retval None
		3786	*/
		3787	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
		3788	{
		3789	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
		3790	}
		3791
		3792	/**
		3793	* @brief Generate Capture/Compare 2 event.
		3794	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
		3795	* @param TIMx Timer instance
		3796	* @retval None
		3797	*/
		3798	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
		3799	{
		3800	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
		3801	}
		3802
		3803	/**
		3804	* @brief Generate Capture/Compare 3 event.
		3805	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
		3806	* @param TIMx Timer instance
		3807	* @retval None
		3808	*/
		3809	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
		3810	{
		3811	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
		3812	}
		3813
		3814	/**
		3815	* @brief Generate Capture/Compare 4 event.
		3816	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
		3817	* @param TIMx Timer instance
		3818	* @retval None
		3819	*/
		3820	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
		3821	{
		3822	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
		3823	}
		3824
		3825	/**
		3826	* @brief Generate commutation event.
		3827	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
		3828	* @param TIMx Timer instance
		3829	* @retval None
		3830	*/
		3831	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
		3832	{
		3833	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
		3834	}
		3835
		3836	/**
		3837	* @brief Generate trigger event.
		3838	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
		3839	* @param TIMx Timer instance
		3840	* @retval None
		3841	*/
		3842	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
		3843	{
		3844	SET_BIT(TIMx->EGR, TIM_EGR_TG);
		3845	}
		3846
		3847	/**
		3848	* @brief Generate break event.
		3849	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
		3850	* @param TIMx Timer instance
		3851	* @retval None
		3852	*/
		3853	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
		3854	{
		3855	SET_BIT(TIMx->EGR, TIM_EGR_BG);
		3856	}
		3857
		3858	/**
		3859	* @}
		3860	*/
		3861
		3862	#if defined(USE_FULL_LL_DRIVER)
		3863	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
		3864	* @{
		3865	*/
		3866
		3867	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
		3868	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
		3869	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
		3870	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
		3871	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
		3872	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
		3873	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
		3874	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
		3875	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
		3876	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
		3877	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
		3878	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
		3879	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
		3880	/**
		3881	* @}
		3882	*/
		3883	#endif /* USE_FULL_LL_DRIVER */
		3884
		3885	/**
		3886	* @}
		3887	*/
		3888
		3889	/**
		3890	* @}
		3891	*/
		3892
		3893	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 */
		3894
		3895	/**
		3896	* @}
		3897	*/
		3898
		3899	#ifdef __cplusplus
		3900	}
		3901	#endif
		3902
		3903	#endif /* __STM32F1xx_LL_TIM_H */
		3904	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h – Rev 2