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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
		10	*
		11	* Redistribution and use in source and binary forms, with or without modification,
		12	* are permitted provided that the following conditions are met:
		13	* 1. Redistributions of source code must retain the above copyright notice,
		14	* this list of conditions and the following disclaimer.
		15	* 2. Redistributions in binary form must reproduce the above copyright notice,
		16	* this list of conditions and the following disclaimer in the documentation
		17	* and/or other materials provided with the distribution.
		18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		19	* may be used to endorse or promote products derived from this software
		20	* without specific prior written permission.
		21	*
		22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		32	*
		33	******************************************************************************
		34	*/
		35
		36	/* Define to prevent recursive inclusion -------------------------------------*/
		37	#ifndef __STM32F1xx_LL_TIM_H
		38	#define __STM32F1xx_LL_TIM_H
		39
		40	#ifdef __cplusplus
		41	extern "C" {
		42	#endif
		43
		44	/* Includes ------------------------------------------------------------------*/
		45	#include "stm32f1xx.h"
		46
		47	/** @addtogroup STM32F1xx_LL_Driver
		48	* @{
		49	*/
		50
		51	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17)
		52
		53	/** @defgroup TIM_LL TIM
		54	* @{
		55	*/
		56
		57	/* Private types -------------------------------------------------------------*/
		58	/* Private variables ---------------------------------------------------------*/
		59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
		60	* @{
		61	*/
		62	static const uint8_t OFFSET_TAB_CCMRx[] =
		63	{
		64	0x00U, /* 0: TIMx_CH1 */
		65	0x00U, /* 1: TIMx_CH1N */
		66	0x00U, /* 2: TIMx_CH2 */
		67	0x00U, /* 3: TIMx_CH2N */
		68	0x04U, /* 4: TIMx_CH3 */
		69	0x04U, /* 5: TIMx_CH3N */
		70	0x04U /* 6: TIMx_CH4 */
		71	};
		72
		73	static const uint8_t SHIFT_TAB_OCxx[] =
		74	{
		75	0U, /* 0: OC1M, OC1FE, OC1PE */
		76	0U, /* 1: - NA */
		77	8U, /* 2: OC2M, OC2FE, OC2PE */
		78	0U, /* 3: - NA */
		79	0U, /* 4: OC3M, OC3FE, OC3PE */
		80	0U, /* 5: - NA */
		81	8U /* 6: OC4M, OC4FE, OC4PE */
		82	};
		83
		84	static const uint8_t SHIFT_TAB_ICxx[] =
		85	{
		86	0U, /* 0: CC1S, IC1PSC, IC1F */
		87	0U, /* 1: - NA */
		88	8U, /* 2: CC2S, IC2PSC, IC2F */
		89	0U, /* 3: - NA */
		90	0U, /* 4: CC3S, IC3PSC, IC3F */
		91	0U, /* 5: - NA */
		92	8U /* 6: CC4S, IC4PSC, IC4F */
		93	};
		94
		95	static const uint8_t SHIFT_TAB_CCxP[] =
		96	{
		97	0U, /* 0: CC1P */
		98	2U, /* 1: CC1NP */
		99	4U, /* 2: CC2P */
		100	6U, /* 3: CC2NP */
		101	8U, /* 4: CC3P */
		102	10U, /* 5: CC3NP */
		103	12U /* 6: CC4P */
		104	};
		105
		106	static const uint8_t SHIFT_TAB_OISx[] =
		107	{
		108	0U, /* 0: OIS1 */
		109	1U, /* 1: OIS1N */
		110	2U, /* 2: OIS2 */
		111	3U, /* 3: OIS2N */
		112	4U, /* 4: OIS3 */
		113	5U, /* 5: OIS3N */
		114	6U /* 6: OIS4 */
		115	};
		116	/**
		117	* @}
		118	*/
		119
		120
		121	/* Private constants ---------------------------------------------------------*/
		122	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
		123	* @{
		124	*/
		125
		126
		127
		128	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
		129	#define DT_DELAY_1 ((uint8_t)0x7F)
		130	#define DT_DELAY_2 ((uint8_t)0x3F)
		131	#define DT_DELAY_3 ((uint8_t)0x1F)
		132	#define DT_DELAY_4 ((uint8_t)0x1F)
		133
		134	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
		135	#define DT_RANGE_1 ((uint8_t)0x00)
		136	#define DT_RANGE_2 ((uint8_t)0x80)
		137	#define DT_RANGE_3 ((uint8_t)0xC0)
		138	#define DT_RANGE_4 ((uint8_t)0xE0)
		139
		140
		141	/**
		142	* @}
		143	*/
		144
		145	/* Private macros ------------------------------------------------------------*/
		146	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
		147	* @{
		148	*/
		149	/** @brief Convert channel id into channel index.
		150	* @param __CHANNEL__ This parameter can be one of the following values:
		151	* @arg @ref LL_TIM_CHANNEL_CH1
		152	* @arg @ref LL_TIM_CHANNEL_CH1N
		153	* @arg @ref LL_TIM_CHANNEL_CH2
		154	* @arg @ref LL_TIM_CHANNEL_CH2N
		155	* @arg @ref LL_TIM_CHANNEL_CH3
		156	* @arg @ref LL_TIM_CHANNEL_CH3N
		157	* @arg @ref LL_TIM_CHANNEL_CH4
		158	* @retval none
		159	*/
		160	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
		161	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
		162	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
		163	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
		164	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
		165	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
		166	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
		167
		168	/** @brief Calculate the deadtime sampling period(in ps).
		169	* @param __TIMCLK__ timer input clock frequency (in Hz).
		170	* @param __CKD__ This parameter can be one of the following values:
		171	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		172	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		173	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		174	* @retval none
		175	*/
		176	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
		177	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
		178	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
		179	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
		180	/**
		181	* @}
		182	*/
		183
		184
		185	/* Exported types ------------------------------------------------------------*/
		186	#if defined(USE_FULL_LL_DRIVER)
		187	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
		188	* @{
		189	*/
		190
		191	/**
		192	* @brief TIM Time Base configuration structure definition.
		193	*/
		194	typedef struct
		195	{
		196	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		197	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		198
		199	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
		200
		201	uint32_t CounterMode; /*!< Specifies the counter mode.
		202	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
		203
		204	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
		205
		206	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
		207	Auto-Reload Register at the next update event.
		208	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		209	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
		210
		211	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
		212
		213	uint32_t ClockDivision; /*!< Specifies the clock division.
		214	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
		215
		216	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
		217
		218	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
		219	reaches zero, an update event is generated and counting restarts
		220	from the RCR value (N).
		221	This means in PWM mode that (N+1) corresponds to:
		222	- the number of PWM periods in edge-aligned mode
		223	- the number of half PWM period in center-aligned mode
		224	This parameter must be a number between 0x00 and 0xFF.
		225
		226	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
		227	} LL_TIM_InitTypeDef;
		228
		229	/**
		230	* @brief TIM Output Compare configuration structure definition.
		231	*/
		232	typedef struct
		233	{
		234	uint32_t OCMode; /*!< Specifies the output mode.
		235	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
		236
		237	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
		238
		239	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
		240	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		241
		242	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
		243
		244	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
		245	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		246
		247	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
		248
		249	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
		250	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		251
		252	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
		253
		254	uint32_t OCPolarity; /*!< Specifies the output polarity.
		255	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		256
		257	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
		258
		259	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		260	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		261
		262	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
		263
		264
		265	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		266	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		267
		268	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
		269
		270	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		271	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		272
		273	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
		274	} LL_TIM_OC_InitTypeDef;
		275
		276	/**
		277	* @brief TIM Input Capture configuration structure definition.
		278	*/
		279
		280	typedef struct
		281	{
		282
		283	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		284	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		285
		286	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		287
		288	uint32_t ICActiveInput; /*!< Specifies the input.
		289	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		290
		291	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		292
		293	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		294	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		295
		296	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		297
		298	uint32_t ICFilter; /*!< Specifies the input capture filter.
		299	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		300
		301	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		302	} LL_TIM_IC_InitTypeDef;
		303
		304
		305	/**
		306	* @brief TIM Encoder interface configuration structure definition.
		307	*/
		308	typedef struct
		309	{
		310	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
		311	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
		312
		313	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
		314
		315	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		316	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		317
		318	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		319
		320	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
		321	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		322
		323	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		324
		325	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		326	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		327
		328	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		329
		330	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		331	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		332
		333	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		334
		335	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
		336	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		337
		338	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		339
		340	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
		341	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		342
		343	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		344
		345	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
		346	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		347
		348	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		349
		350	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
		351	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		352
		353	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		354
		355	} LL_TIM_ENCODER_InitTypeDef;
		356
		357	/**
		358	* @brief TIM Hall sensor interface configuration structure definition.
		359	*/
		360	typedef struct
		361	{
		362
		363	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		364	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		365
		366	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		367
		368	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		369	Prescaler must be set to get a maximum counter period longer than the
		370	time interval between 2 consecutive changes on the Hall inputs.
		371	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		372
		373	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		374
		375	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		376	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		377
		378	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		379
		380	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
		381	A positive pulse (TRGO event) is generated with a programmable delay every time
		382	a change occurs on the Hall inputs.
		383	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
		384
		385	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
		386	} LL_TIM_HALLSENSOR_InitTypeDef;
		387
		388	/**
		389	* @brief BDTR (Break and Dead Time) structure definition
		390	*/
		391	typedef struct
		392	{
		393	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
		394	This parameter can be a value of @ref TIM_LL_EC_OSSR
		395
		396	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
		397
		398	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
		399
		400	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
		401	This parameter can be a value of @ref TIM_LL_EC_OSSI
		402
		403	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
		404
		405	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
		406
		407	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
		408	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
		409
		410	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
		411	has been written, their content is frozen until the next reset.*/
		412
		413	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
		414	switching-on of the outputs.
		415	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
		416
		417	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
		418
		419	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
		420
		421	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
		422	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
		423
		424	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
		425
		426	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
		427
		428	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
		429	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
		430
		431	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
		432
		433	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
		434
		435	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
		436	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
		437
		438	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
		439
		440	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
		441	} LL_TIM_BDTR_InitTypeDef;
		442
		443	/**
		444	* @}
		445	*/
		446	#endif /* USE_FULL_LL_DRIVER */
		447
		448	/* Exported constants --------------------------------------------------------*/
		449	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
		450	* @{
		451	*/
		452
		453	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
		454	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
		455	* @{
		456	*/
		457	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
		458	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
		459	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
		460	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
		461	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
		462	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
		463	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
		464	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
		465	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
		466	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
		467	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
		468	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
		469	/**
		470	* @}
		471	*/
		472
		473	#if defined(USE_FULL_LL_DRIVER)
		474	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
		475	* @{
		476	*/
		477	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
		478	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
		479	/**
		480	* @}
		481	*/
		482
		483	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
		484	* @{
		485	*/
		486	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
		487	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
		488	/**
		489	* @}
		490	*/
		491	#endif /* USE_FULL_LL_DRIVER */
		492
		493	/** @defgroup TIM_LL_EC_IT IT Defines
		494	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
		495	* @{
		496	*/
		497	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
		498	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
		499	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
		500	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
		501	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
		502	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
		503	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
		504	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
		505	/**
		506	* @}
		507	*/
		508
		509	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
		510	* @{
		511	*/
		512	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
		513	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
		514	/**
		515	* @}
		516	*/
		517
		518	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
		519	* @{
		520	*/
		521	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
		522	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
		523	/**
		524	* @}
		525	*/
		526
		527	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
		528	* @{
		529	*/
		530	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
		531	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
		532	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
		533	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
		534	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
		535	/**
		536	* @}
		537	*/
		538
		539	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
		540	* @{
		541	*/
		542	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
		543	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
		544	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
		545	/**
		546	* @}
		547	*/
		548
		549	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
		550	* @{
		551	*/
		552	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
		553	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
		554	/**
		555	* @}
		556	*/
		557
		558	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
		559	* @{
		560	*/
		561	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
		562	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
		563	/**
		564	* @}
		565	*/
		566
		567	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
		568	* @{
		569	*/
		570	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
		571	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
		572	/**
		573	* @}
		574	*/
		575
		576	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
		577	* @{
		578	*/
		579	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
		580	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
		581	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
		582	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
		583	/**
		584	* @}
		585	*/
		586
		587	/** @defgroup TIM_LL_EC_CHANNEL Channel
		588	* @{
		589	*/
		590	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
		591	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
		592	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
		593	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
		594	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
		595	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
		596	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
		597	/**
		598	* @}
		599	*/
		600
		601	#if defined(USE_FULL_LL_DRIVER)
		602	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
		603	* @{
		604	*/
		605	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
		606	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
		607	/**
		608	* @}
		609	*/
		610	#endif /* USE_FULL_LL_DRIVER */
		611
		612	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
		613	* @{
		614	*/
		615	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
		616	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
		617	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
		618	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
		619	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
		620	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
		621	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
		622	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
		623	/**
		624	* @}
		625	*/
		626
		627	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
		628	* @{
		629	*/
		630	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
		631	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
		632	/**
		633	* @}
		634	*/
		635
		636	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
		637	* @{
		638	*/
		639	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
		640	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
		641	/**
		642	* @}
		643	*/
		644
		645
		646	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
		647	* @{
		648	*/
		649	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
		650	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
		651	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
		652	/**
		653	* @}
		654	*/
		655
		656	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
		657	* @{
		658	*/
		659	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
		660	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
		661	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
		662	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
		663	/**
		664	* @}
		665	*/
		666
		667	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
		668	* @{
		669	*/
		670	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		671	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
		672	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
		673	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
		674	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
		675	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
		676	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
		677	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
		678	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
		679	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
		680	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
		681	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
		682	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
		683	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
		684	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
		685	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
		686	/**
		687	* @}
		688	*/
		689
		690	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
		691	* @{
		692	*/
		693	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
		694	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
		695	/**
		696	* @}
		697	*/
		698
		699	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
		700	* @{
		701	*/
		702	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
		703	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
		704	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
		705	/**
		706	* @}
		707	*/
		708
		709	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
		710	* @{
		711	*/
		712	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
		713	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
		714	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
		715	/**
		716	* @}
		717	*/
		718
		719	/** @defgroup TIM_LL_EC_TRGO Trigger Output
		720	* @{
		721	*/
		722	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
		723	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
		724	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
		725	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
		726	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
		727	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
		728	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
		729	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
		730	/**
		731	* @}
		732	*/
		733
		734
		735	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
		736	* @{
		737	*/
		738	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
		739	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
		740	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
		741	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
		742	/**
		743	* @}
		744	*/
		745
		746	/** @defgroup TIM_LL_EC_TS Trigger Selection
		747	* @{
		748	*/
		749	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
		750	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
		751	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
		752	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
		753	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
		754	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
		755	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
		756	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
		757	/**
		758	* @}
		759	*/
		760
		761	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
		762	* @{
		763	*/
		764	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
		765	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
		766	/**
		767	* @}
		768	*/
		769
		770	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
		771	* @{
		772	*/
		773	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
		774	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
		775	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
		776	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
		777	/**
		778	* @}
		779	*/
		780
		781	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
		782	* @{
		783	*/
		784	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		785	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
		786	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
		787	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
		788	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
		789	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
		790	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
		791	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
		792	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
		793	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
		794	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
		795	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
		796	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
		797	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
		798	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
		799	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
		800	/**
		801	* @}
		802	*/
		803
		804
		805	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
		806	* @{
		807	*/
		808	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
		809	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
		810	/**
		811	* @}
		812	*/
		813
		814
		815
		816
		817	/** @defgroup TIM_LL_EC_OSSI OSSI
		818	* @{
		819	*/
		820	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		821	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
		822	/**
		823	* @}
		824	*/
		825
		826	/** @defgroup TIM_LL_EC_OSSR OSSR
		827	* @{
		828	*/
		829	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		830	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
		831	/**
		832	* @}
		833	*/
		834
		835
		836	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
		837	* @{
		838	*/
		839	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
		840	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
		841	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
		842	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
		843	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
		844	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
		845	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
		846	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
		847	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
		848	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
		849	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
		850	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
		851	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
		852	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
		853	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
		854	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
		855	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
		856	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
		857	/**
		858	* @}
		859	*/
		860
		861	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
		862	* @{
		863	*/
		864	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
		865	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
		866	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
		867	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
		868	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
		869	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
		870	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
		871	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
		872	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
		873	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
		874	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
		875	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
		876	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
		877	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
		878	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
		879	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
		880	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
		881	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
		882	/**
		883	* @}
		884	*/
		885
		886
		887
		888	/**
		889	* @}
		890	*/
		891
		892	/* Exported macro ------------------------------------------------------------*/
		893	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
		894	* @{
		895	*/
		896
		897	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
		898	* @{
		899	*/
		900	/**
		901	* @brief Write a value in TIM register.
		902	* @param __INSTANCE__ TIM Instance
		903	* @param __REG__ Register to be written
		904	* @param __VALUE__ Value to be written in the register
		905	* @retval None
		906	*/
		907	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		908
		909	/**
		910	* @brief Read a value in TIM register.
		911	* @param __INSTANCE__ TIM Instance
		912	* @param __REG__ Register to be read
		913	* @retval Register value
		914	*/
		915	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		916	/**
		917	* @}
		918	*/
		919
		920	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
		921	* @{
		922	*/
		923
		924	/**
		925	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
		926	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
		927	* @param __TIMCLK__ timer input clock frequency (in Hz)
		928	* @param __CKD__ This parameter can be one of the following values:
		929	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		930	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		931	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		932	* @param __DT__ deadtime duration (in ns)
		933	* @retval DTG[0:7]
		934	*/
		935	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
		936	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
		937	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
		938	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
		939	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
		940	0U)
		941
		942	/**
		943	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
		944	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
		945	* @param __TIMCLK__ timer input clock frequency (in Hz)
		946	* @param __CNTCLK__ counter clock frequency (in Hz)
		947	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
		948	*/
		949	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
		950	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
		951
		952	/**
		953	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
		954	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
		955	* @param __TIMCLK__ timer input clock frequency (in Hz)
		956	* @param __PSC__ prescaler
		957	* @param __FREQ__ output signal frequency (in Hz)
		958	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		959	*/
		960	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
		961	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
		962
		963	/**
		964	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
		965	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
		966	* @param __TIMCLK__ timer input clock frequency (in Hz)
		967	* @param __PSC__ prescaler
		968	* @param __DELAY__ timer output compare active/inactive delay (in us)
		969	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
		970	*/
		971	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
		972	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
		973	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
		974
		975	/**
		976	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
		977	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
		978	* @param __TIMCLK__ timer input clock frequency (in Hz)
		979	* @param __PSC__ prescaler
		980	* @param __DELAY__ timer output compare active/inactive delay (in us)
		981	* @param __PULSE__ pulse duration (in us)
		982	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		983	*/
		984	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
		985	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
		986	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
		987
		988	/**
		989	* @brief HELPER macro retrieving the ratio of the input capture prescaler
		990	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
		991	* @param __ICPSC__ This parameter can be one of the following values:
		992	* @arg @ref LL_TIM_ICPSC_DIV1
		993	* @arg @ref LL_TIM_ICPSC_DIV2
		994	* @arg @ref LL_TIM_ICPSC_DIV4
		995	* @arg @ref LL_TIM_ICPSC_DIV8
		996	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
		997	*/
		998	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
		999	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
		1000
		1001
		1002	/**
		1003	* @}
		1004	*/
		1005
		1006
		1007	/**
		1008	* @}
		1009	*/
		1010
		1011	/* Exported functions --------------------------------------------------------*/
		1012	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
		1013	* @{
		1014	*/
		1015
		1016	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
		1017	* @{
		1018	*/
		1019	/**
		1020	* @brief Enable timer counter.
		1021	* @rmtoll CR1 CEN LL_TIM_EnableCounter
		1022	* @param TIMx Timer instance
		1023	* @retval None
		1024	*/
		1025	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
		1026	{
		1027	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
		1028	}
		1029
		1030	/**
		1031	* @brief Disable timer counter.
		1032	* @rmtoll CR1 CEN LL_TIM_DisableCounter
		1033	* @param TIMx Timer instance
		1034	* @retval None
		1035	*/
		1036	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
		1037	{
		1038	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
		1039	}
		1040
		1041	/**
		1042	* @brief Indicates whether the timer counter is enabled.
		1043	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
		1044	* @param TIMx Timer instance
		1045	* @retval State of bit (1 or 0).
		1046	*/
		1047	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
		1048	{
		1049	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
		1050	}
		1051
		1052	/**
		1053	* @brief Enable update event generation.
		1054	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
		1055	* @param TIMx Timer instance
		1056	* @retval None
		1057	*/
		1058	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
		1059	{
		1060	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1061	}
		1062
		1063	/**
		1064	* @brief Disable update event generation.
		1065	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
		1066	* @param TIMx Timer instance
		1067	* @retval None
		1068	*/
		1069	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
		1070	{
		1071	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1072	}
		1073
		1074	/**
		1075	* @brief Indicates whether update event generation is enabled.
		1076	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
		1077	* @param TIMx Timer instance
		1078	* @retval State of bit (1 or 0).
		1079	*/
		1080	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
		1081	{
		1082	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
		1083	}
		1084
		1085	/**
		1086	* @brief Set update event source
		1087	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
		1088	* generate an update interrupt or DMA request if enabled:
		1089	* - Counter overflow/underflow
		1090	* - Setting the UG bit
		1091	* - Update generation through the slave mode controller
		1092	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
		1093	* overflow/underflow generates an update interrupt or DMA request if enabled.
		1094	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
		1095	* @param TIMx Timer instance
		1096	* @param UpdateSource This parameter can be one of the following values:
		1097	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1098	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1099	* @retval None
		1100	*/
		1101	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
		1102	{
		1103	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
		1104	}
		1105
		1106	/**
		1107	* @brief Get actual event update source
		1108	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
		1109	* @param TIMx Timer instance
		1110	* @retval Returned value can be one of the following values:
		1111	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1112	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1113	*/
		1114	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
		1115	{
		1116	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
		1117	}
		1118
		1119	/**
		1120	* @brief Set one pulse mode (one shot v.s. repetitive).
		1121	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
		1122	* @param TIMx Timer instance
		1123	* @param OnePulseMode This parameter can be one of the following values:
		1124	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1125	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1126	* @retval None
		1127	*/
		1128	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
		1129	{
		1130	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
		1131	}
		1132
		1133	/**
		1134	* @brief Get actual one pulse mode.
		1135	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
		1136	* @param TIMx Timer instance
		1137	* @retval Returned value can be one of the following values:
		1138	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1139	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1140	*/
		1141	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
		1142	{
		1143	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
		1144	}
		1145
		1146	/**
		1147	* @brief Set the timer counter counting mode.
		1148	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1149	* check whether or not the counter mode selection feature is supported
		1150	* by a timer instance.
		1151	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1152	* requires a timer reset to avoid unexpected direction
		1153	* due to DIR bit readonly in center aligned mode.
		1154	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
		1155	* CR1 CMS LL_TIM_SetCounterMode
		1156	* @param TIMx Timer instance
		1157	* @param CounterMode This parameter can be one of the following values:
		1158	* @arg @ref LL_TIM_COUNTERMODE_UP
		1159	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1160	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1161	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1162	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1163	* @retval None
		1164	*/
		1165	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
		1166	{
		1167	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
		1168	}
		1169
		1170	/**
		1171	* @brief Get actual counter mode.
		1172	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1173	* check whether or not the counter mode selection feature is supported
		1174	* by a timer instance.
		1175	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
		1176	* CR1 CMS LL_TIM_GetCounterMode
		1177	* @param TIMx Timer instance
		1178	* @retval Returned value can be one of the following values:
		1179	* @arg @ref LL_TIM_COUNTERMODE_UP
		1180	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1181	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1182	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1183	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1184	*/
		1185	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
		1186	{
		1187	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
		1188	}
		1189
		1190	/**
		1191	* @brief Enable auto-reload (ARR) preload.
		1192	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
		1193	* @param TIMx Timer instance
		1194	* @retval None
		1195	*/
		1196	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
		1197	{
		1198	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1199	}
		1200
		1201	/**
		1202	* @brief Disable auto-reload (ARR) preload.
		1203	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
		1204	* @param TIMx Timer instance
		1205	* @retval None
		1206	*/
		1207	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
		1208	{
		1209	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1210	}
		1211
		1212	/**
		1213	* @brief Indicates whether auto-reload (ARR) preload is enabled.
		1214	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
		1215	* @param TIMx Timer instance
		1216	* @retval State of bit (1 or 0).
		1217	*/
		1218	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
		1219	{
		1220	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
		1221	}
		1222
		1223	/**
		1224	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
		1225	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1226	* whether or not the clock division feature is supported by the timer
		1227	* instance.
		1228	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
		1229	* @param TIMx Timer instance
		1230	* @param ClockDivision This parameter can be one of the following values:
		1231	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1232	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1233	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1234	* @retval None
		1235	*/
		1236	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
		1237	{
		1238	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
		1239	}
		1240
		1241	/**
		1242	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
		1243	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1244	* whether or not the clock division feature is supported by the timer
		1245	* instance.
		1246	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
		1247	* @param TIMx Timer instance
		1248	* @retval Returned value can be one of the following values:
		1249	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1250	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1251	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1252	*/
		1253	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
		1254	{
		1255	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
		1256	}
		1257
		1258	/**
		1259	* @brief Set the counter value.
		1260	* @rmtoll CNT CNT LL_TIM_SetCounter
		1261	* @param TIMx Timer instance
		1262	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
		1263	* @retval None
		1264	*/
		1265	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
		1266	{
		1267	WRITE_REG(TIMx->CNT, Counter);
		1268	}
		1269
		1270	/**
		1271	* @brief Get the counter value.
		1272	* @rmtoll CNT CNT LL_TIM_GetCounter
		1273	* @param TIMx Timer instance
		1274	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
		1275	*/
		1276	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
		1277	{
		1278	return (uint32_t)(READ_REG(TIMx->CNT));
		1279	}
		1280
		1281	/**
		1282	* @brief Get the current direction of the counter
		1283	* @rmtoll CR1 DIR LL_TIM_GetDirection
		1284	* @param TIMx Timer instance
		1285	* @retval Returned value can be one of the following values:
		1286	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
		1287	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
		1288	*/
		1289	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
		1290	{
		1291	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1292	}
		1293
		1294	/**
		1295	* @brief Set the prescaler value.
		1296	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
		1297	* @note The prescaler can be changed on the fly as this control register is buffered. The new
		1298	* prescaler ratio is taken into account at the next update event.
		1299	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
		1300	* @rmtoll PSC PSC LL_TIM_SetPrescaler
		1301	* @param TIMx Timer instance
		1302	* @param Prescaler between Min_Data=0 and Max_Data=65535
		1303	* @retval None
		1304	*/
		1305	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
		1306	{
		1307	WRITE_REG(TIMx->PSC, Prescaler);
		1308	}
		1309
		1310	/**
		1311	* @brief Get the prescaler value.
		1312	* @rmtoll PSC PSC LL_TIM_GetPrescaler
		1313	* @param TIMx Timer instance
		1314	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
		1315	*/
		1316	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
		1317	{
		1318	return (uint32_t)(READ_REG(TIMx->PSC));
		1319	}
		1320
		1321	/**
		1322	* @brief Set the auto-reload value.
		1323	* @note The counter is blocked while the auto-reload value is null.
		1324	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
		1325	* @rmtoll ARR ARR LL_TIM_SetAutoReload
		1326	* @param TIMx Timer instance
		1327	* @param AutoReload between Min_Data=0 and Max_Data=65535
		1328	* @retval None
		1329	*/
		1330	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
		1331	{
		1332	WRITE_REG(TIMx->ARR, AutoReload);
		1333	}
		1334
		1335	/**
		1336	* @brief Get the auto-reload value.
		1337	* @rmtoll ARR ARR LL_TIM_GetAutoReload
		1338	* @param TIMx Timer instance
		1339	* @retval Auto-reload value
		1340	*/
		1341	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
		1342	{
		1343	return (uint32_t)(READ_REG(TIMx->ARR));
		1344	}
		1345
		1346	/**
		1347	* @brief Set the repetition counter value.
		1348	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
		1349	* whether or not a timer instance supports a repetition counter.
		1350	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
		1351	* @param TIMx Timer instance
		1352	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
		1353	* @retval None
		1354	*/
		1355	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
		1356	{
		1357	WRITE_REG(TIMx->RCR, RepetitionCounter);
		1358	}
		1359
		1360	/**
		1361	* @brief Get the repetition counter value.
		1362	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
		1363	* whether or not a timer instance supports a repetition counter.
		1364	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
		1365	* @param TIMx Timer instance
		1366	* @retval Repetition counter value
		1367	*/
		1368	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
		1369	{
		1370	return (uint32_t)(READ_REG(TIMx->RCR));
		1371	}
		1372
		1373	/**
		1374	* @}
		1375	*/
		1376
		1377	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
		1378	* @{
		1379	*/
		1380	/**
		1381	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
		1382	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
		1383	* they are updated only when a commutation event (COM) occurs.
		1384	* @note Only on channels that have a complementary output.
		1385	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1386	* whether or not a timer instance is able to generate a commutation event.
		1387	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
		1388	* @param TIMx Timer instance
		1389	* @retval None
		1390	*/
		1391	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
		1392	{
		1393	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1394	}
		1395
		1396	/**
		1397	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
		1398	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1399	* whether or not a timer instance is able to generate a commutation event.
		1400	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
		1401	* @param TIMx Timer instance
		1402	* @retval None
		1403	*/
		1404	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
		1405	{
		1406	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1407	}
		1408
		1409	/**
		1410	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
		1411	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1412	* whether or not a timer instance is able to generate a commutation event.
		1413	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
		1414	* @param TIMx Timer instance
		1415	* @param CCUpdateSource This parameter can be one of the following values:
		1416	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
		1417	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
		1418	* @retval None
		1419	*/
		1420	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
		1421	{
		1422	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
		1423	}
		1424
		1425	/**
		1426	* @brief Set the trigger of the capture/compare DMA request.
		1427	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
		1428	* @param TIMx Timer instance
		1429	* @param DMAReqTrigger This parameter can be one of the following values:
		1430	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1431	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1432	* @retval None
		1433	*/
		1434	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
		1435	{
		1436	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
		1437	}
		1438
		1439	/**
		1440	* @brief Get actual trigger of the capture/compare DMA request.
		1441	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
		1442	* @param TIMx Timer instance
		1443	* @retval Returned value can be one of the following values:
		1444	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1445	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1446	*/
		1447	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
		1448	{
		1449	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
		1450	}
		1451
		1452	/**
		1453	* @brief Set the lock level to freeze the
		1454	* configuration of several capture/compare parameters.
		1455	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		1456	* the lock mechanism is supported by a timer instance.
		1457	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
		1458	* @param TIMx Timer instance
		1459	* @param LockLevel This parameter can be one of the following values:
		1460	* @arg @ref LL_TIM_LOCKLEVEL_OFF
		1461	* @arg @ref LL_TIM_LOCKLEVEL_1
		1462	* @arg @ref LL_TIM_LOCKLEVEL_2
		1463	* @arg @ref LL_TIM_LOCKLEVEL_3
		1464	* @retval None
		1465	*/
		1466	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
		1467	{
		1468	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
		1469	}
		1470
		1471	/**
		1472	* @brief Enable capture/compare channels.
		1473	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
		1474	* CCER CC1NE LL_TIM_CC_EnableChannel\n
		1475	* CCER CC2E LL_TIM_CC_EnableChannel\n
		1476	* CCER CC2NE LL_TIM_CC_EnableChannel\n
		1477	* CCER CC3E LL_TIM_CC_EnableChannel\n
		1478	* CCER CC3NE LL_TIM_CC_EnableChannel\n
		1479	* CCER CC4E LL_TIM_CC_EnableChannel
		1480	* @param TIMx Timer instance
		1481	* @param Channels This parameter can be a combination of the following values:
		1482	* @arg @ref LL_TIM_CHANNEL_CH1
		1483	* @arg @ref LL_TIM_CHANNEL_CH1N
		1484	* @arg @ref LL_TIM_CHANNEL_CH2
		1485	* @arg @ref LL_TIM_CHANNEL_CH2N
		1486	* @arg @ref LL_TIM_CHANNEL_CH3
		1487	* @arg @ref LL_TIM_CHANNEL_CH3N
		1488	* @arg @ref LL_TIM_CHANNEL_CH4
		1489	* @retval None
		1490	*/
		1491	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1492	{
		1493	SET_BIT(TIMx->CCER, Channels);
		1494	}
		1495
		1496	/**
		1497	* @brief Disable capture/compare channels.
		1498	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
		1499	* CCER CC1NE LL_TIM_CC_DisableChannel\n
		1500	* CCER CC2E LL_TIM_CC_DisableChannel\n
		1501	* CCER CC2NE LL_TIM_CC_DisableChannel\n
		1502	* CCER CC3E LL_TIM_CC_DisableChannel\n
		1503	* CCER CC3NE LL_TIM_CC_DisableChannel\n
		1504	* CCER CC4E LL_TIM_CC_DisableChannel
		1505	* @param TIMx Timer instance
		1506	* @param Channels This parameter can be a combination of the following values:
		1507	* @arg @ref LL_TIM_CHANNEL_CH1
		1508	* @arg @ref LL_TIM_CHANNEL_CH1N
		1509	* @arg @ref LL_TIM_CHANNEL_CH2
		1510	* @arg @ref LL_TIM_CHANNEL_CH2N
		1511	* @arg @ref LL_TIM_CHANNEL_CH3
		1512	* @arg @ref LL_TIM_CHANNEL_CH3N
		1513	* @arg @ref LL_TIM_CHANNEL_CH4
		1514	* @retval None
		1515	*/
		1516	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1517	{
		1518	CLEAR_BIT(TIMx->CCER, Channels);
		1519	}
		1520
		1521	/**
		1522	* @brief Indicate whether channel(s) is(are) enabled.
		1523	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
		1524	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
		1525	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
		1526	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
		1527	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
		1528	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
		1529	* CCER CC4E LL_TIM_CC_IsEnabledChannel
		1530	* @param TIMx Timer instance
		1531	* @param Channels This parameter can be a combination of the following values:
		1532	* @arg @ref LL_TIM_CHANNEL_CH1
		1533	* @arg @ref LL_TIM_CHANNEL_CH1N
		1534	* @arg @ref LL_TIM_CHANNEL_CH2
		1535	* @arg @ref LL_TIM_CHANNEL_CH2N
		1536	* @arg @ref LL_TIM_CHANNEL_CH3
		1537	* @arg @ref LL_TIM_CHANNEL_CH3N
		1538	* @arg @ref LL_TIM_CHANNEL_CH4
		1539	* @retval State of bit (1 or 0).
		1540	*/
		1541	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1542	{
		1543	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
		1544	}
		1545
		1546	/**
		1547	* @}
		1548	*/
		1549
		1550	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
		1551	* @{
		1552	*/
		1553	/**
		1554	* @brief Configure an output channel.
		1555	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
		1556	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
		1557	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
		1558	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
		1559	* CCER CC1P LL_TIM_OC_ConfigOutput\n
		1560	* CCER CC2P LL_TIM_OC_ConfigOutput\n
		1561	* CCER CC3P LL_TIM_OC_ConfigOutput\n
		1562	* CCER CC4P LL_TIM_OC_ConfigOutput\n
		1563	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
		1564	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
		1565	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
		1566	* CR2 OIS4 LL_TIM_OC_ConfigOutput
		1567	* @param TIMx Timer instance
		1568	* @param Channel This parameter can be one of the following values:
		1569	* @arg @ref LL_TIM_CHANNEL_CH1
		1570	* @arg @ref LL_TIM_CHANNEL_CH2
		1571	* @arg @ref LL_TIM_CHANNEL_CH3
		1572	* @arg @ref LL_TIM_CHANNEL_CH4
		1573	* @param Configuration This parameter must be a combination of all the following values:
		1574	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
		1575	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
		1576	* @retval None
		1577	*/
		1578	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		1579	{
		1580	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1581	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1582	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
		1583	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
		1584	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
		1585	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
		1586	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
		1587	}
		1588
		1589	/**
		1590	* @brief Define the behavior of the output reference signal OCxREF from which
		1591	* OCx and OCxN (when relevant) are derived.
		1592	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
		1593	* CCMR1 OC2M LL_TIM_OC_SetMode\n
		1594	* CCMR2 OC3M LL_TIM_OC_SetMode\n
		1595	* CCMR2 OC4M LL_TIM_OC_SetMode
		1596	* @param TIMx Timer instance
		1597	* @param Channel This parameter can be one of the following values:
		1598	* @arg @ref LL_TIM_CHANNEL_CH1
		1599	* @arg @ref LL_TIM_CHANNEL_CH2
		1600	* @arg @ref LL_TIM_CHANNEL_CH3
		1601	* @arg @ref LL_TIM_CHANNEL_CH4
		1602	* @param Mode This parameter can be one of the following values:
		1603	* @arg @ref LL_TIM_OCMODE_FROZEN
		1604	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1605	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1606	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1607	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1608	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1609	* @arg @ref LL_TIM_OCMODE_PWM1
		1610	* @arg @ref LL_TIM_OCMODE_PWM2
		1611	* @retval None
		1612	*/
		1613	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
		1614	{
		1615	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1616	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1617	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
		1618	}
		1619
		1620	/**
		1621	* @brief Get the output compare mode of an output channel.
		1622	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
		1623	* CCMR1 OC2M LL_TIM_OC_GetMode\n
		1624	* CCMR2 OC3M LL_TIM_OC_GetMode\n
		1625	* CCMR2 OC4M LL_TIM_OC_GetMode
		1626	* @param TIMx Timer instance
		1627	* @param Channel This parameter can be one of the following values:
		1628	* @arg @ref LL_TIM_CHANNEL_CH1
		1629	* @arg @ref LL_TIM_CHANNEL_CH2
		1630	* @arg @ref LL_TIM_CHANNEL_CH3
		1631	* @arg @ref LL_TIM_CHANNEL_CH4
		1632	* @retval Returned value can be one of the following values:
		1633	* @arg @ref LL_TIM_OCMODE_FROZEN
		1634	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1635	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1636	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1637	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1638	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1639	* @arg @ref LL_TIM_OCMODE_PWM1
		1640	* @arg @ref LL_TIM_OCMODE_PWM2
		1641	*/
		1642	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
		1643	{
		1644	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1645	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1646	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
		1647	}
		1648
		1649	/**
		1650	* @brief Set the polarity of an output channel.
		1651	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
		1652	* CCER CC1NP LL_TIM_OC_SetPolarity\n
		1653	* CCER CC2P LL_TIM_OC_SetPolarity\n
		1654	* CCER CC2NP LL_TIM_OC_SetPolarity\n
		1655	* CCER CC3P LL_TIM_OC_SetPolarity\n
		1656	* CCER CC3NP LL_TIM_OC_SetPolarity\n
		1657	* CCER CC4P LL_TIM_OC_SetPolarity
		1658	* @param TIMx Timer instance
		1659	* @param Channel This parameter can be one of the following values:
		1660	* @arg @ref LL_TIM_CHANNEL_CH1
		1661	* @arg @ref LL_TIM_CHANNEL_CH1N
		1662	* @arg @ref LL_TIM_CHANNEL_CH2
		1663	* @arg @ref LL_TIM_CHANNEL_CH2N
		1664	* @arg @ref LL_TIM_CHANNEL_CH3
		1665	* @arg @ref LL_TIM_CHANNEL_CH3N
		1666	* @arg @ref LL_TIM_CHANNEL_CH4
		1667	* @param Polarity This parameter can be one of the following values:
		1668	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1669	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1670	* @retval None
		1671	*/
		1672	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
		1673	{
		1674	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1675	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
		1676	}
		1677
		1678	/**
		1679	* @brief Get the polarity of an output channel.
		1680	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
		1681	* CCER CC1NP LL_TIM_OC_GetPolarity\n
		1682	* CCER CC2P LL_TIM_OC_GetPolarity\n
		1683	* CCER CC2NP LL_TIM_OC_GetPolarity\n
		1684	* CCER CC3P LL_TIM_OC_GetPolarity\n
		1685	* CCER CC3NP LL_TIM_OC_GetPolarity\n
		1686	* CCER CC4P LL_TIM_OC_GetPolarity
		1687	* @param TIMx Timer instance
		1688	* @param Channel This parameter can be one of the following values:
		1689	* @arg @ref LL_TIM_CHANNEL_CH1
		1690	* @arg @ref LL_TIM_CHANNEL_CH1N
		1691	* @arg @ref LL_TIM_CHANNEL_CH2
		1692	* @arg @ref LL_TIM_CHANNEL_CH2N
		1693	* @arg @ref LL_TIM_CHANNEL_CH3
		1694	* @arg @ref LL_TIM_CHANNEL_CH3N
		1695	* @arg @ref LL_TIM_CHANNEL_CH4
		1696	* @retval Returned value can be one of the following values:
		1697	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1698	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1699	*/
		1700	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		1701	{
		1702	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1703	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
		1704	}
		1705
		1706	/**
		1707	* @brief Set the IDLE state of an output channel
		1708	* @note This function is significant only for the timer instances
		1709	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
		1710	* can be used to check whether or not a timer instance provides
		1711	* a break input.
		1712	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
		1713	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
		1714	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
		1715	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
		1716	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
		1717	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
		1718	* CR2 OIS4 LL_TIM_OC_SetIdleState
		1719	* @param TIMx Timer instance
		1720	* @param Channel This parameter can be one of the following values:
		1721	* @arg @ref LL_TIM_CHANNEL_CH1
		1722	* @arg @ref LL_TIM_CHANNEL_CH1N
		1723	* @arg @ref LL_TIM_CHANNEL_CH2
		1724	* @arg @ref LL_TIM_CHANNEL_CH2N
		1725	* @arg @ref LL_TIM_CHANNEL_CH3
		1726	* @arg @ref LL_TIM_CHANNEL_CH3N
		1727	* @arg @ref LL_TIM_CHANNEL_CH4
		1728	* @param IdleState This parameter can be one of the following values:
		1729	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1730	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1731	* @retval None
		1732	*/
		1733	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
		1734	{
		1735	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1736	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
		1737	}
		1738
		1739	/**
		1740	* @brief Get the IDLE state of an output channel
		1741	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
		1742	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
		1743	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
		1744	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
		1745	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
		1746	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
		1747	* CR2 OIS4 LL_TIM_OC_GetIdleState
		1748	* @param TIMx Timer instance
		1749	* @param Channel This parameter can be one of the following values:
		1750	* @arg @ref LL_TIM_CHANNEL_CH1
		1751	* @arg @ref LL_TIM_CHANNEL_CH1N
		1752	* @arg @ref LL_TIM_CHANNEL_CH2
		1753	* @arg @ref LL_TIM_CHANNEL_CH2N
		1754	* @arg @ref LL_TIM_CHANNEL_CH3
		1755	* @arg @ref LL_TIM_CHANNEL_CH3N
		1756	* @arg @ref LL_TIM_CHANNEL_CH4
		1757	* @retval Returned value can be one of the following values:
		1758	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1759	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1760	*/
		1761	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
		1762	{
		1763	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1764	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
		1765	}
		1766
		1767	/**
		1768	* @brief Enable fast mode for the output channel.
		1769	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
		1770	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
		1771	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
		1772	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
		1773	* CCMR2 OC4FE LL_TIM_OC_EnableFast
		1774	* @param TIMx Timer instance
		1775	* @param Channel This parameter can be one of the following values:
		1776	* @arg @ref LL_TIM_CHANNEL_CH1
		1777	* @arg @ref LL_TIM_CHANNEL_CH2
		1778	* @arg @ref LL_TIM_CHANNEL_CH3
		1779	* @arg @ref LL_TIM_CHANNEL_CH4
		1780	* @retval None
		1781	*/
		1782	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1783	{
		1784	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1785	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1786	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1787
		1788	}
		1789
		1790	/**
		1791	* @brief Disable fast mode for the output channel.
		1792	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
		1793	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
		1794	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
		1795	* CCMR2 OC4FE LL_TIM_OC_DisableFast
		1796	* @param TIMx Timer instance
		1797	* @param Channel This parameter can be one of the following values:
		1798	* @arg @ref LL_TIM_CHANNEL_CH1
		1799	* @arg @ref LL_TIM_CHANNEL_CH2
		1800	* @arg @ref LL_TIM_CHANNEL_CH3
		1801	* @arg @ref LL_TIM_CHANNEL_CH4
		1802	* @retval None
		1803	*/
		1804	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1805	{
		1806	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1807	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1808	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1809
		1810	}
		1811
		1812	/**
		1813	* @brief Indicates whether fast mode is enabled for the output channel.
		1814	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
		1815	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
		1816	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
		1817	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
		1818	* @param TIMx Timer instance
		1819	* @param Channel This parameter can be one of the following values:
		1820	* @arg @ref LL_TIM_CHANNEL_CH1
		1821	* @arg @ref LL_TIM_CHANNEL_CH2
		1822	* @arg @ref LL_TIM_CHANNEL_CH3
		1823	* @arg @ref LL_TIM_CHANNEL_CH4
		1824	* @retval State of bit (1 or 0).
		1825	*/
		1826	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1827	{
		1828	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1829	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1830	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
		1831	return (READ_BIT(*pReg, bitfield) == bitfield);
		1832	}
		1833
		1834	/**
		1835	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
		1836	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
		1837	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
		1838	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
		1839	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
		1840	* @param TIMx Timer instance
		1841	* @param Channel This parameter can be one of the following values:
		1842	* @arg @ref LL_TIM_CHANNEL_CH1
		1843	* @arg @ref LL_TIM_CHANNEL_CH2
		1844	* @arg @ref LL_TIM_CHANNEL_CH3
		1845	* @arg @ref LL_TIM_CHANNEL_CH4
		1846	* @retval None
		1847	*/
		1848	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1849	{
		1850	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1851	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1852	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1853	}
		1854
		1855	/**
		1856	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
		1857	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
		1858	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
		1859	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
		1860	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
		1861	* @param TIMx Timer instance
		1862	* @param Channel This parameter can be one of the following values:
		1863	* @arg @ref LL_TIM_CHANNEL_CH1
		1864	* @arg @ref LL_TIM_CHANNEL_CH2
		1865	* @arg @ref LL_TIM_CHANNEL_CH3
		1866	* @arg @ref LL_TIM_CHANNEL_CH4
		1867	* @retval None
		1868	*/
		1869	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1870	{
		1871	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1872	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1873	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1874	}
		1875
		1876	/**
		1877	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
		1878	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
		1879	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
		1880	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
		1881	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
		1882	* @param TIMx Timer instance
		1883	* @param Channel This parameter can be one of the following values:
		1884	* @arg @ref LL_TIM_CHANNEL_CH1
		1885	* @arg @ref LL_TIM_CHANNEL_CH2
		1886	* @arg @ref LL_TIM_CHANNEL_CH3
		1887	* @arg @ref LL_TIM_CHANNEL_CH4
		1888	* @retval State of bit (1 or 0).
		1889	*/
		1890	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1891	{
		1892	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1893	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1894	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
		1895	return (READ_BIT(*pReg, bitfield) == bitfield);
		1896	}
		1897
		1898	/**
		1899	* @brief Enable clearing the output channel on an external event.
		1900	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1901	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1902	* or not a timer instance can clear the OCxREF signal on an external event.
		1903	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
		1904	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
		1905	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
		1906	* CCMR2 OC4CE LL_TIM_OC_EnableClear
		1907	* @param TIMx Timer instance
		1908	* @param Channel This parameter can be one of the following values:
		1909	* @arg @ref LL_TIM_CHANNEL_CH1
		1910	* @arg @ref LL_TIM_CHANNEL_CH2
		1911	* @arg @ref LL_TIM_CHANNEL_CH3
		1912	* @arg @ref LL_TIM_CHANNEL_CH4
		1913	* @retval None
		1914	*/
		1915	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1916	{
		1917	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1918	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1919	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1920	}
		1921
		1922	/**
		1923	* @brief Disable clearing the output channel on an external event.
		1924	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1925	* or not a timer instance can clear the OCxREF signal on an external event.
		1926	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
		1927	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
		1928	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
		1929	* CCMR2 OC4CE LL_TIM_OC_DisableClear
		1930	* @param TIMx Timer instance
		1931	* @param Channel This parameter can be one of the following values:
		1932	* @arg @ref LL_TIM_CHANNEL_CH1
		1933	* @arg @ref LL_TIM_CHANNEL_CH2
		1934	* @arg @ref LL_TIM_CHANNEL_CH3
		1935	* @arg @ref LL_TIM_CHANNEL_CH4
		1936	* @retval None
		1937	*/
		1938	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1939	{
		1940	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1941	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1942	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1943	}
		1944
		1945	/**
		1946	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
		1947	* @note This function enables clearing the output channel on an external event.
		1948	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1949	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1950	* or not a timer instance can clear the OCxREF signal on an external event.
		1951	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
		1952	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
		1953	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
		1954	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
		1955	* @param TIMx Timer instance
		1956	* @param Channel This parameter can be one of the following values:
		1957	* @arg @ref LL_TIM_CHANNEL_CH1
		1958	* @arg @ref LL_TIM_CHANNEL_CH2
		1959	* @arg @ref LL_TIM_CHANNEL_CH3
		1960	* @arg @ref LL_TIM_CHANNEL_CH4
		1961	* @retval State of bit (1 or 0).
		1962	*/
		1963	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1964	{
		1965	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1966	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1967	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
		1968	return (READ_BIT(*pReg, bitfield) == bitfield);
		1969	}
		1970
		1971	/**
		1972	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
		1973	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		1974	* dead-time insertion feature is supported by a timer instance.
		1975	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
		1976	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
		1977	* @param TIMx Timer instance
		1978	* @param DeadTime between Min_Data=0 and Max_Data=255
		1979	* @retval None
		1980	*/
		1981	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
		1982	{
		1983	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
		1984	}
		1985
		1986	/**
		1987	* @brief Set compare value for output channel 1 (TIMx_CCR1).
		1988	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		1989	* output channel 1 is supported by a timer instance.
		1990	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
		1991	* @param TIMx Timer instance
		1992	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1993	* @retval None
		1994	*/
		1995	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1996	{
		1997	WRITE_REG(TIMx->CCR1, CompareValue);
		1998	}
		1999
		2000	/**
		2001	* @brief Set compare value for output channel 2 (TIMx_CCR2).
		2002	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2003	* output channel 2 is supported by a timer instance.
		2004	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
		2005	* @param TIMx Timer instance
		2006	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2007	* @retval None
		2008	*/
		2009	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2010	{
		2011	WRITE_REG(TIMx->CCR2, CompareValue);
		2012	}
		2013
		2014	/**
		2015	* @brief Set compare value for output channel 3 (TIMx_CCR3).
		2016	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2017	* output channel is supported by a timer instance.
		2018	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
		2019	* @param TIMx Timer instance
		2020	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2021	* @retval None
		2022	*/
		2023	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2024	{
		2025	WRITE_REG(TIMx->CCR3, CompareValue);
		2026	}
		2027
		2028	/**
		2029	* @brief Set compare value for output channel 4 (TIMx_CCR4).
		2030	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2031	* output channel 4 is supported by a timer instance.
		2032	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
		2033	* @param TIMx Timer instance
		2034	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2035	* @retval None
		2036	*/
		2037	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2038	{
		2039	WRITE_REG(TIMx->CCR4, CompareValue);
		2040	}
		2041
		2042	/**
		2043	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
		2044	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2045	* output channel 1 is supported by a timer instance.
		2046	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
		2047	* @param TIMx Timer instance
		2048	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2049	*/
		2050	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
		2051	{
		2052	return (uint32_t)(READ_REG(TIMx->CCR1));
		2053	}
		2054
		2055	/**
		2056	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
		2057	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2058	* output channel 2 is supported by a timer instance.
		2059	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
		2060	* @param TIMx Timer instance
		2061	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2062	*/
		2063	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
		2064	{
		2065	return (uint32_t)(READ_REG(TIMx->CCR2));
		2066	}
		2067
		2068	/**
		2069	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
		2070	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2071	* output channel 3 is supported by a timer instance.
		2072	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
		2073	* @param TIMx Timer instance
		2074	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2075	*/
		2076	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
		2077	{
		2078	return (uint32_t)(READ_REG(TIMx->CCR3));
		2079	}
		2080
		2081	/**
		2082	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
		2083	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2084	* output channel 4 is supported by a timer instance.
		2085	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
		2086	* @param TIMx Timer instance
		2087	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2088	*/
		2089	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
		2090	{
		2091	return (uint32_t)(READ_REG(TIMx->CCR4));
		2092	}
		2093
		2094	/**
		2095	* @}
		2096	*/
		2097
		2098	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
		2099	* @{
		2100	*/
		2101	/**
		2102	* @brief Configure input channel.
		2103	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
		2104	* CCMR1 IC1PSC LL_TIM_IC_Config\n
		2105	* CCMR1 IC1F LL_TIM_IC_Config\n
		2106	* CCMR1 CC2S LL_TIM_IC_Config\n
		2107	* CCMR1 IC2PSC LL_TIM_IC_Config\n
		2108	* CCMR1 IC2F LL_TIM_IC_Config\n
		2109	* CCMR2 CC3S LL_TIM_IC_Config\n
		2110	* CCMR2 IC3PSC LL_TIM_IC_Config\n
		2111	* CCMR2 IC3F LL_TIM_IC_Config\n
		2112	* CCMR2 CC4S LL_TIM_IC_Config\n
		2113	* CCMR2 IC4PSC LL_TIM_IC_Config\n
		2114	* CCMR2 IC4F LL_TIM_IC_Config\n
		2115	* CCER CC1P LL_TIM_IC_Config\n
		2116	* CCER CC1NP LL_TIM_IC_Config\n
		2117	* CCER CC2P LL_TIM_IC_Config\n
		2118	* CCER CC2NP LL_TIM_IC_Config\n
		2119	* CCER CC3P LL_TIM_IC_Config\n
		2120	* CCER CC3NP LL_TIM_IC_Config\n
		2121	* CCER CC4P LL_TIM_IC_Config\n
		2122	* @param TIMx Timer instance
		2123	* @param Channel This parameter can be one of the following values:
		2124	* @arg @ref LL_TIM_CHANNEL_CH1
		2125	* @arg @ref LL_TIM_CHANNEL_CH2
		2126	* @arg @ref LL_TIM_CHANNEL_CH3
		2127	* @arg @ref LL_TIM_CHANNEL_CH4
		2128	* @param Configuration This parameter must be a combination of all the following values:
		2129	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
		2130	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
		2131	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
		2132	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
		2133	* @retval None
		2134	*/
		2135	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		2136	{
		2137	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2138	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2139	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
		2140	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
		2141	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2142	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
		2143	}
		2144
		2145	/**
		2146	* @brief Set the active input.
		2147	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
		2148	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
		2149	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
		2150	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
		2151	* @param TIMx Timer instance
		2152	* @param Channel This parameter can be one of the following values:
		2153	* @arg @ref LL_TIM_CHANNEL_CH1
		2154	* @arg @ref LL_TIM_CHANNEL_CH2
		2155	* @arg @ref LL_TIM_CHANNEL_CH3
		2156	* @arg @ref LL_TIM_CHANNEL_CH4
		2157	* @param ICActiveInput This parameter can be one of the following values:
		2158	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2159	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2160	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2161	* @retval None
		2162	*/
		2163	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
		2164	{
		2165	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2166	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2167	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2168	}
		2169
		2170	/**
		2171	* @brief Get the current active input.
		2172	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
		2173	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
		2174	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
		2175	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
		2176	* @param TIMx Timer instance
		2177	* @param Channel This parameter can be one of the following values:
		2178	* @arg @ref LL_TIM_CHANNEL_CH1
		2179	* @arg @ref LL_TIM_CHANNEL_CH2
		2180	* @arg @ref LL_TIM_CHANNEL_CH3
		2181	* @arg @ref LL_TIM_CHANNEL_CH4
		2182	* @retval Returned value can be one of the following values:
		2183	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2184	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2185	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2186	*/
		2187	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
		2188	{
		2189	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2190	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2191	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2192	}
		2193
		2194	/**
		2195	* @brief Set the prescaler of input channel.
		2196	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
		2197	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
		2198	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
		2199	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
		2200	* @param TIMx Timer instance
		2201	* @param Channel This parameter can be one of the following values:
		2202	* @arg @ref LL_TIM_CHANNEL_CH1
		2203	* @arg @ref LL_TIM_CHANNEL_CH2
		2204	* @arg @ref LL_TIM_CHANNEL_CH3
		2205	* @arg @ref LL_TIM_CHANNEL_CH4
		2206	* @param ICPrescaler This parameter can be one of the following values:
		2207	* @arg @ref LL_TIM_ICPSC_DIV1
		2208	* @arg @ref LL_TIM_ICPSC_DIV2
		2209	* @arg @ref LL_TIM_ICPSC_DIV4
		2210	* @arg @ref LL_TIM_ICPSC_DIV8
		2211	* @retval None
		2212	*/
		2213	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
		2214	{
		2215	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2216	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2217	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2218	}
		2219
		2220	/**
		2221	* @brief Get the current prescaler value acting on an input channel.
		2222	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
		2223	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
		2224	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
		2225	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
		2226	* @param TIMx Timer instance
		2227	* @param Channel This parameter can be one of the following values:
		2228	* @arg @ref LL_TIM_CHANNEL_CH1
		2229	* @arg @ref LL_TIM_CHANNEL_CH2
		2230	* @arg @ref LL_TIM_CHANNEL_CH3
		2231	* @arg @ref LL_TIM_CHANNEL_CH4
		2232	* @retval Returned value can be one of the following values:
		2233	* @arg @ref LL_TIM_ICPSC_DIV1
		2234	* @arg @ref LL_TIM_ICPSC_DIV2
		2235	* @arg @ref LL_TIM_ICPSC_DIV4
		2236	* @arg @ref LL_TIM_ICPSC_DIV8
		2237	*/
		2238	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
		2239	{
		2240	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2241	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2242	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2243	}
		2244
		2245	/**
		2246	* @brief Set the input filter duration.
		2247	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
		2248	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
		2249	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
		2250	* CCMR2 IC4F LL_TIM_IC_SetFilter
		2251	* @param TIMx Timer instance
		2252	* @param Channel This parameter can be one of the following values:
		2253	* @arg @ref LL_TIM_CHANNEL_CH1
		2254	* @arg @ref LL_TIM_CHANNEL_CH2
		2255	* @arg @ref LL_TIM_CHANNEL_CH3
		2256	* @arg @ref LL_TIM_CHANNEL_CH4
		2257	* @param ICFilter This parameter can be one of the following values:
		2258	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2259	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2260	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2261	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2262	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2263	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2264	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2265	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2266	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2267	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2268	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2269	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2270	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2271	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2272	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2273	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2274	* @retval None
		2275	*/
		2276	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
		2277	{
		2278	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2279	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2280	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2281	}
		2282
		2283	/**
		2284	* @brief Get the input filter duration.
		2285	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
		2286	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
		2287	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
		2288	* CCMR2 IC4F LL_TIM_IC_GetFilter
		2289	* @param TIMx Timer instance
		2290	* @param Channel This parameter can be one of the following values:
		2291	* @arg @ref LL_TIM_CHANNEL_CH1
		2292	* @arg @ref LL_TIM_CHANNEL_CH2
		2293	* @arg @ref LL_TIM_CHANNEL_CH3
		2294	* @arg @ref LL_TIM_CHANNEL_CH4
		2295	* @retval Returned value can be one of the following values:
		2296	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2297	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2298	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2299	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2300	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2301	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2302	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2303	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2304	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2305	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2306	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2307	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2308	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2309	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2310	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2311	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2312	*/
		2313	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
		2314	{
		2315	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2316	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2317	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2318	}
		2319
		2320	/**
		2321	* @brief Set the input channel polarity.
		2322	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
		2323	* CCER CC1NP LL_TIM_IC_SetPolarity\n
		2324	* CCER CC2P LL_TIM_IC_SetPolarity\n
		2325	* CCER CC2NP LL_TIM_IC_SetPolarity\n
		2326	* CCER CC3P LL_TIM_IC_SetPolarity\n
		2327	* CCER CC3NP LL_TIM_IC_SetPolarity\n
		2328	* CCER CC4P LL_TIM_IC_SetPolarity\n
		2329	* @param TIMx Timer instance
		2330	* @param Channel This parameter can be one of the following values:
		2331	* @arg @ref LL_TIM_CHANNEL_CH1
		2332	* @arg @ref LL_TIM_CHANNEL_CH2
		2333	* @arg @ref LL_TIM_CHANNEL_CH3
		2334	* @arg @ref LL_TIM_CHANNEL_CH4
		2335	* @param ICPolarity This parameter can be one of the following values:
		2336	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2337	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2338	* @retval None
		2339	*/
		2340	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
		2341	{
		2342	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2343	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2344	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
		2345	}
		2346
		2347	/**
		2348	* @brief Get the current input channel polarity.
		2349	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
		2350	* CCER CC1NP LL_TIM_IC_GetPolarity\n
		2351	* CCER CC2P LL_TIM_IC_GetPolarity\n
		2352	* CCER CC2NP LL_TIM_IC_GetPolarity\n
		2353	* CCER CC3P LL_TIM_IC_GetPolarity\n
		2354	* CCER CC3NP LL_TIM_IC_GetPolarity\n
		2355	* CCER CC4P LL_TIM_IC_GetPolarity\n
		2356	* @param TIMx Timer instance
		2357	* @param Channel This parameter can be one of the following values:
		2358	* @arg @ref LL_TIM_CHANNEL_CH1
		2359	* @arg @ref LL_TIM_CHANNEL_CH2
		2360	* @arg @ref LL_TIM_CHANNEL_CH3
		2361	* @arg @ref LL_TIM_CHANNEL_CH4
		2362	* @retval Returned value can be one of the following values:
		2363	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2364	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2365	*/
		2366	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		2367	{
		2368	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2369	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
		2370	SHIFT_TAB_CCxP[iChannel]);
		2371	}
		2372
		2373	/**
		2374	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
		2375	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2376	* a timer instance provides an XOR input.
		2377	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
		2378	* @param TIMx Timer instance
		2379	* @retval None
		2380	*/
		2381	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
		2382	{
		2383	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2384	}
		2385
		2386	/**
		2387	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
		2388	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2389	* a timer instance provides an XOR input.
		2390	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
		2391	* @param TIMx Timer instance
		2392	* @retval None
		2393	*/
		2394	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
		2395	{
		2396	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2397	}
		2398
		2399	/**
		2400	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
		2401	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2402	* a timer instance provides an XOR input.
		2403	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
		2404	* @param TIMx Timer instance
		2405	* @retval State of bit (1 or 0).
		2406	*/
		2407	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
		2408	{
		2409	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
		2410	}
		2411
		2412	/**
		2413	* @brief Get captured value for input channel 1.
		2414	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2415	* input channel 1 is supported by a timer instance.
		2416	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
		2417	* @param TIMx Timer instance
		2418	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2419	*/
		2420	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
		2421	{
		2422	return (uint32_t)(READ_REG(TIMx->CCR1));
		2423	}
		2424
		2425	/**
		2426	* @brief Get captured value for input channel 2.
		2427	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2428	* input channel 2 is supported by a timer instance.
		2429	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
		2430	* @param TIMx Timer instance
		2431	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2432	*/
		2433	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
		2434	{
		2435	return (uint32_t)(READ_REG(TIMx->CCR2));
		2436	}
		2437
		2438	/**
		2439	* @brief Get captured value for input channel 3.
		2440	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2441	* input channel 3 is supported by a timer instance.
		2442	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
		2443	* @param TIMx Timer instance
		2444	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2445	*/
		2446	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
		2447	{
		2448	return (uint32_t)(READ_REG(TIMx->CCR3));
		2449	}
		2450
		2451	/**
		2452	* @brief Get captured value for input channel 4.
		2453	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2454	* input channel 4 is supported by a timer instance.
		2455	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
		2456	* @param TIMx Timer instance
		2457	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2458	*/
		2459	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
		2460	{
		2461	return (uint32_t)(READ_REG(TIMx->CCR4));
		2462	}
		2463
		2464	/**
		2465	* @}
		2466	*/
		2467
		2468	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
		2469	* @{
		2470	*/
		2471	/**
		2472	* @brief Enable external clock mode 2.
		2473	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
		2474	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2475	* whether or not a timer instance supports external clock mode2.
		2476	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
		2477	* @param TIMx Timer instance
		2478	* @retval None
		2479	*/
		2480	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
		2481	{
		2482	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2483	}
		2484
		2485	/**
		2486	* @brief Disable external clock mode 2.
		2487	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2488	* whether or not a timer instance supports external clock mode2.
		2489	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
		2490	* @param TIMx Timer instance
		2491	* @retval None
		2492	*/
		2493	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
		2494	{
		2495	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2496	}
		2497
		2498	/**
		2499	* @brief Indicate whether external clock mode 2 is enabled.
		2500	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2501	* whether or not a timer instance supports external clock mode2.
		2502	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
		2503	* @param TIMx Timer instance
		2504	* @retval State of bit (1 or 0).
		2505	*/
		2506	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
		2507	{
		2508	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
		2509	}
		2510
		2511	/**
		2512	* @brief Set the clock source of the counter clock.
		2513	* @note when selected clock source is external clock mode 1, the timer input
		2514	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
		2515	* function. This timer input must be configured by calling
		2516	* the @ref LL_TIM_IC_Config() function.
		2517	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
		2518	* whether or not a timer instance supports external clock mode1.
		2519	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2520	* whether or not a timer instance supports external clock mode2.
		2521	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
		2522	* SMCR ECE LL_TIM_SetClockSource
		2523	* @param TIMx Timer instance
		2524	* @param ClockSource This parameter can be one of the following values:
		2525	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
		2526	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
		2527	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
		2528	* @retval None
		2529	*/
		2530	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
		2531	{
		2532	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
		2533	}
		2534
		2535	/**
		2536	* @brief Set the encoder interface mode.
		2537	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
		2538	* whether or not a timer instance supports the encoder mode.
		2539	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
		2540	* @param TIMx Timer instance
		2541	* @param EncoderMode This parameter can be one of the following values:
		2542	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
		2543	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
		2544	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
		2545	* @retval None
		2546	*/
		2547	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
		2548	{
		2549	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
		2550	}
		2551
		2552	/**
		2553	* @}
		2554	*/
		2555
		2556	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
		2557	* @{
		2558	*/
		2559	/**
		2560	* @brief Set the trigger output (TRGO) used for timer synchronization .
		2561	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
		2562	* whether or not a timer instance can operate as a master timer.
		2563	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
		2564	* @param TIMx Timer instance
		2565	* @param TimerSynchronization This parameter can be one of the following values:
		2566	* @arg @ref LL_TIM_TRGO_RESET
		2567	* @arg @ref LL_TIM_TRGO_ENABLE
		2568	* @arg @ref LL_TIM_TRGO_UPDATE
		2569	* @arg @ref LL_TIM_TRGO_CC1IF
		2570	* @arg @ref LL_TIM_TRGO_OC1REF
		2571	* @arg @ref LL_TIM_TRGO_OC2REF
		2572	* @arg @ref LL_TIM_TRGO_OC3REF
		2573	* @arg @ref LL_TIM_TRGO_OC4REF
		2574	* @retval None
		2575	*/
		2576	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
		2577	{
		2578	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
		2579	}
		2580
		2581	/**
		2582	* @brief Set the synchronization mode of a slave timer.
		2583	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2584	* a timer instance can operate as a slave timer.
		2585	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
		2586	* @param TIMx Timer instance
		2587	* @param SlaveMode This parameter can be one of the following values:
		2588	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
		2589	* @arg @ref LL_TIM_SLAVEMODE_RESET
		2590	* @arg @ref LL_TIM_SLAVEMODE_GATED
		2591	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
		2592	* @retval None
		2593	*/
		2594	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
		2595	{
		2596	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
		2597	}
		2598
		2599	/**
		2600	* @brief Set the selects the trigger input to be used to synchronize the counter.
		2601	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2602	* a timer instance can operate as a slave timer.
		2603	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
		2604	* @param TIMx Timer instance
		2605	* @param TriggerInput This parameter can be one of the following values:
		2606	* @arg @ref LL_TIM_TS_ITR0
		2607	* @arg @ref LL_TIM_TS_ITR1
		2608	* @arg @ref LL_TIM_TS_ITR2
		2609	* @arg @ref LL_TIM_TS_ITR3
		2610	* @arg @ref LL_TIM_TS_TI1F_ED
		2611	* @arg @ref LL_TIM_TS_TI1FP1
		2612	* @arg @ref LL_TIM_TS_TI2FP2
		2613	* @arg @ref LL_TIM_TS_ETRF
		2614	* @retval None
		2615	*/
		2616	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
		2617	{
		2618	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
		2619	}
		2620
		2621	/**
		2622	* @brief Enable the Master/Slave mode.
		2623	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2624	* a timer instance can operate as a slave timer.
		2625	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
		2626	* @param TIMx Timer instance
		2627	* @retval None
		2628	*/
		2629	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
		2630	{
		2631	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2632	}
		2633
		2634	/**
		2635	* @brief Disable the Master/Slave mode.
		2636	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2637	* a timer instance can operate as a slave timer.
		2638	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
		2639	* @param TIMx Timer instance
		2640	* @retval None
		2641	*/
		2642	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
		2643	{
		2644	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2645	}
		2646
		2647	/**
		2648	* @brief Indicates whether the Master/Slave mode is enabled.
		2649	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2650	* a timer instance can operate as a slave timer.
		2651	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
		2652	* @param TIMx Timer instance
		2653	* @retval State of bit (1 or 0).
		2654	*/
		2655	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
		2656	{
		2657	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
		2658	}
		2659
		2660	/**
		2661	* @brief Configure the external trigger (ETR) input.
		2662	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
		2663	* a timer instance provides an external trigger input.
		2664	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
		2665	* SMCR ETPS LL_TIM_ConfigETR\n
		2666	* SMCR ETF LL_TIM_ConfigETR
		2667	* @param TIMx Timer instance
		2668	* @param ETRPolarity This parameter can be one of the following values:
		2669	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
		2670	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
		2671	* @param ETRPrescaler This parameter can be one of the following values:
		2672	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
		2673	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
		2674	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
		2675	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
		2676	* @param ETRFilter This parameter can be one of the following values:
		2677	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
		2678	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
		2679	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
		2680	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
		2681	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
		2682	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
		2683	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
		2684	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
		2685	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
		2686	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
		2687	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
		2688	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
		2689	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
		2690	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
		2691	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
		2692	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
		2693	* @retval None
		2694	*/
		2695	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
		2696	uint32_t ETRFilter)
		2697	{
		2698	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
		2699	}
		2700
		2701	/**
		2702	* @}
		2703	*/
		2704
		2705	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
		2706	* @{
		2707	*/
		2708	/**
		2709	* @brief Enable the break function.
		2710	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2711	* a timer instance provides a break input.
		2712	* @rmtoll BDTR BKE LL_TIM_EnableBRK
		2713	* @param TIMx Timer instance
		2714	* @retval None
		2715	*/
		2716	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
		2717	{
		2718	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
		2719	}
		2720
		2721	/**
		2722	* @brief Disable the break function.
		2723	* @rmtoll BDTR BKE LL_TIM_DisableBRK
		2724	* @param TIMx Timer instance
		2725	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2726	* a timer instance provides a break input.
		2727	* @retval None
		2728	*/
		2729	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
		2730	{
		2731	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
		2732	}
		2733
		2734	/**
		2735	* @brief Configure the break input.
		2736	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2737	* a timer instance provides a break input.
		2738	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
		2739	* @param TIMx Timer instance
		2740	* @param BreakPolarity This parameter can be one of the following values:
		2741	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
		2742	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
		2743	* @retval None
		2744	*/
		2745	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
		2746	{
		2747	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
		2748	}
		2749
		2750	/**
		2751	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
		2752	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2753	* a timer instance provides a break input.
		2754	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
		2755	* BDTR OSSR LL_TIM_SetOffStates
		2756	* @param TIMx Timer instance
		2757	* @param OffStateIdle This parameter can be one of the following values:
		2758	* @arg @ref LL_TIM_OSSI_DISABLE
		2759	* @arg @ref LL_TIM_OSSI_ENABLE
		2760	* @param OffStateRun This parameter can be one of the following values:
		2761	* @arg @ref LL_TIM_OSSR_DISABLE
		2762	* @arg @ref LL_TIM_OSSR_ENABLE
		2763	* @retval None
		2764	*/
		2765	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
		2766	{
		2767	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
		2768	}
		2769
		2770	/**
		2771	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
		2772	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2773	* a timer instance provides a break input.
		2774	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
		2775	* @param TIMx Timer instance
		2776	* @retval None
		2777	*/
		2778	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
		2779	{
		2780	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2781	}
		2782
		2783	/**
		2784	* @brief Disable automatic output (MOE can be set only by software).
		2785	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2786	* a timer instance provides a break input.
		2787	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
		2788	* @param TIMx Timer instance
		2789	* @retval None
		2790	*/
		2791	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
		2792	{
		2793	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2794	}
		2795
		2796	/**
		2797	* @brief Indicate whether automatic output is enabled.
		2798	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2799	* a timer instance provides a break input.
		2800	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
		2801	* @param TIMx Timer instance
		2802	* @retval State of bit (1 or 0).
		2803	*/
		2804	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
		2805	{
		2806	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
		2807	}
		2808
		2809	/**
		2810	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
		2811	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2812	* software and is reset in case of break or break2 event
		2813	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2814	* a timer instance provides a break input.
		2815	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
		2816	* @param TIMx Timer instance
		2817	* @retval None
		2818	*/
		2819	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
		2820	{
		2821	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2822	}
		2823
		2824	/**
		2825	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
		2826	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2827	* software and is reset in case of break or break2 event.
		2828	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2829	* a timer instance provides a break input.
		2830	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
		2831	* @param TIMx Timer instance
		2832	* @retval None
		2833	*/
		2834	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
		2835	{
		2836	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2837	}
		2838
		2839	/**
		2840	* @brief Indicates whether outputs are enabled.
		2841	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2842	* a timer instance provides a break input.
		2843	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
		2844	* @param TIMx Timer instance
		2845	* @retval State of bit (1 or 0).
		2846	*/
		2847	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
		2848	{
		2849	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
		2850	}
		2851
		2852	/**
		2853	* @}
		2854	*/
		2855
		2856	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
		2857	* @{
		2858	*/
		2859	/**
		2860	* @brief Configures the timer DMA burst feature.
		2861	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
		2862	* not a timer instance supports the DMA burst mode.
		2863	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
		2864	* DCR DBA LL_TIM_ConfigDMABurst
		2865	* @param TIMx Timer instance
		2866	* @param DMABurstBaseAddress This parameter can be one of the following values:
		2867	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
		2868	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
		2869	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
		2870	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
		2871	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
		2872	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
		2873	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
		2874	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
		2875	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
		2876	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
		2877	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
		2878	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
		2879	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
		2880	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
		2881	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
		2882	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
		2883	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
		2884	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
		2885	* @param DMABurstLength This parameter can be one of the following values:
		2886	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
		2887	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
		2888	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
		2889	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
		2890	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
		2891	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
		2892	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
		2893	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
		2894	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
		2895	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
		2896	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
		2897	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
		2898	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
		2899	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
		2900	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
		2901	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
		2902	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
		2903	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
		2904	* @retval None
		2905	*/
		2906	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
		2907	{
		2908	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
		2909	}
		2910
		2911	/**
		2912	* @}
		2913	*/
		2914
		2915
		2916	/**
		2917	* @}
		2918	*/
		2919
		2920
		2921	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
		2922	* @{
		2923	*/
		2924	/**
		2925	* @brief Clear the update interrupt flag (UIF).
		2926	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
		2927	* @param TIMx Timer instance
		2928	* @retval None
		2929	*/
		2930	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
		2931	{
		2932	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
		2933	}
		2934
		2935	/**
		2936	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
		2937	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
		2938	* @param TIMx Timer instance
		2939	* @retval State of bit (1 or 0).
		2940	*/
		2941	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
		2942	{
		2943	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
		2944	}
		2945
		2946	/**
		2947	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
		2948	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
		2949	* @param TIMx Timer instance
		2950	* @retval None
		2951	*/
		2952	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
		2953	{
		2954	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
		2955	}
		2956
		2957	/**
		2958	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
		2959	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
		2960	* @param TIMx Timer instance
		2961	* @retval State of bit (1 or 0).
		2962	*/
		2963	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
		2964	{
		2965	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
		2966	}
		2967
		2968	/**
		2969	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
		2970	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
		2971	* @param TIMx Timer instance
		2972	* @retval None
		2973	*/
		2974	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
		2975	{
		2976	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
		2977	}
		2978
		2979	/**
		2980	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
		2981	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
		2982	* @param TIMx Timer instance
		2983	* @retval State of bit (1 or 0).
		2984	*/
		2985	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
		2986	{
		2987	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
		2988	}
		2989
		2990	/**
		2991	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
		2992	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
		2993	* @param TIMx Timer instance
		2994	* @retval None
		2995	*/
		2996	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
		2997	{
		2998	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
		2999	}
		3000
		3001	/**
		3002	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
		3003	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
		3004	* @param TIMx Timer instance
		3005	* @retval State of bit (1 or 0).
		3006	*/
		3007	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
		3008	{
		3009	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
		3010	}
		3011
		3012	/**
		3013	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
		3014	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
		3015	* @param TIMx Timer instance
		3016	* @retval None
		3017	*/
		3018	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
		3019	{
		3020	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
		3021	}
		3022
		3023	/**
		3024	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
		3025	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
		3026	* @param TIMx Timer instance
		3027	* @retval State of bit (1 or 0).
		3028	*/
		3029	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
		3030	{
		3031	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
		3032	}
		3033
		3034	/**
		3035	* @brief Clear the commutation interrupt flag (COMIF).
		3036	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
		3037	* @param TIMx Timer instance
		3038	* @retval None
		3039	*/
		3040	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
		3041	{
		3042	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
		3043	}
		3044
		3045	/**
		3046	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
		3047	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
		3048	* @param TIMx Timer instance
		3049	* @retval State of bit (1 or 0).
		3050	*/
		3051	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
		3052	{
		3053	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
		3054	}
		3055
		3056	/**
		3057	* @brief Clear the trigger interrupt flag (TIF).
		3058	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
		3059	* @param TIMx Timer instance
		3060	* @retval None
		3061	*/
		3062	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
		3063	{
		3064	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
		3065	}
		3066
		3067	/**
		3068	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
		3069	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
		3070	* @param TIMx Timer instance
		3071	* @retval State of bit (1 or 0).
		3072	*/
		3073	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
		3074	{
		3075	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
		3076	}
		3077
		3078	/**
		3079	* @brief Clear the break interrupt flag (BIF).
		3080	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
		3081	* @param TIMx Timer instance
		3082	* @retval None
		3083	*/
		3084	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
		3085	{
		3086	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
		3087	}
		3088
		3089	/**
		3090	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
		3091	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
		3092	* @param TIMx Timer instance
		3093	* @retval State of bit (1 or 0).
		3094	*/
		3095	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
		3096	{
		3097	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
		3098	}
		3099
		3100	/**
		3101	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
		3102	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
		3103	* @param TIMx Timer instance
		3104	* @retval None
		3105	*/
		3106	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
		3107	{
		3108	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
		3109	}
		3110
		3111	/**
		3112	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
		3113	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
		3114	* @param TIMx Timer instance
		3115	* @retval State of bit (1 or 0).
		3116	*/
		3117	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
		3118	{
		3119	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
		3120	}
		3121
		3122	/**
		3123	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
		3124	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
		3125	* @param TIMx Timer instance
		3126	* @retval None
		3127	*/
		3128	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
		3129	{
		3130	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
		3131	}
		3132
		3133	/**
		3134	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
		3135	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
		3136	* @param TIMx Timer instance
		3137	* @retval State of bit (1 or 0).
		3138	*/
		3139	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
		3140	{
		3141	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
		3142	}
		3143
		3144	/**
		3145	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
		3146	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
		3147	* @param TIMx Timer instance
		3148	* @retval None
		3149	*/
		3150	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
		3151	{
		3152	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
		3153	}
		3154
		3155	/**
		3156	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
		3157	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
		3158	* @param TIMx Timer instance
		3159	* @retval State of bit (1 or 0).
		3160	*/
		3161	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
		3162	{
		3163	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
		3164	}
		3165
		3166	/**
		3167	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
		3168	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
		3169	* @param TIMx Timer instance
		3170	* @retval None
		3171	*/
		3172	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
		3173	{
		3174	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
		3175	}
		3176
		3177	/**
		3178	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
		3179	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
		3180	* @param TIMx Timer instance
		3181	* @retval State of bit (1 or 0).
		3182	*/
		3183	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
		3184	{
		3185	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
		3186	}
		3187
		3188	/**
		3189	* @}
		3190	*/
		3191
		3192	/** @defgroup TIM_LL_EF_IT_Management IT-Management
		3193	* @{
		3194	*/
		3195	/**
		3196	* @brief Enable update interrupt (UIE).
		3197	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
		3198	* @param TIMx Timer instance
		3199	* @retval None
		3200	*/
		3201	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
		3202	{
		3203	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
		3204	}
		3205
		3206	/**
		3207	* @brief Disable update interrupt (UIE).
		3208	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
		3209	* @param TIMx Timer instance
		3210	* @retval None
		3211	*/
		3212	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
		3213	{
		3214	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
		3215	}
		3216
		3217	/**
		3218	* @brief Indicates whether the update interrupt (UIE) is enabled.
		3219	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
		3220	* @param TIMx Timer instance
		3221	* @retval State of bit (1 or 0).
		3222	*/
		3223	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
		3224	{
		3225	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
		3226	}
		3227
		3228	/**
		3229	* @brief Enable capture/compare 1 interrupt (CC1IE).
		3230	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
		3231	* @param TIMx Timer instance
		3232	* @retval None
		3233	*/
		3234	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
		3235	{
		3236	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3237	}
		3238
		3239	/**
		3240	* @brief Disable capture/compare 1 interrupt (CC1IE).
		3241	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
		3242	* @param TIMx Timer instance
		3243	* @retval None
		3244	*/
		3245	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
		3246	{
		3247	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3248	}
		3249
		3250	/**
		3251	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
		3252	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
		3253	* @param TIMx Timer instance
		3254	* @retval State of bit (1 or 0).
		3255	*/
		3256	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
		3257	{
		3258	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
		3259	}
		3260
		3261	/**
		3262	* @brief Enable capture/compare 2 interrupt (CC2IE).
		3263	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
		3264	* @param TIMx Timer instance
		3265	* @retval None
		3266	*/
		3267	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
		3268	{
		3269	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3270	}
		3271
		3272	/**
		3273	* @brief Disable capture/compare 2 interrupt (CC2IE).
		3274	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
		3275	* @param TIMx Timer instance
		3276	* @retval None
		3277	*/
		3278	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
		3279	{
		3280	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3281	}
		3282
		3283	/**
		3284	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
		3285	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
		3286	* @param TIMx Timer instance
		3287	* @retval State of bit (1 or 0).
		3288	*/
		3289	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
		3290	{
		3291	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
		3292	}
		3293
		3294	/**
		3295	* @brief Enable capture/compare 3 interrupt (CC3IE).
		3296	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
		3297	* @param TIMx Timer instance
		3298	* @retval None
		3299	*/
		3300	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
		3301	{
		3302	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3303	}
		3304
		3305	/**
		3306	* @brief Disable capture/compare 3 interrupt (CC3IE).
		3307	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
		3308	* @param TIMx Timer instance
		3309	* @retval None
		3310	*/
		3311	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
		3312	{
		3313	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3314	}
		3315
		3316	/**
		3317	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
		3318	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
		3319	* @param TIMx Timer instance
		3320	* @retval State of bit (1 or 0).
		3321	*/
		3322	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
		3323	{
		3324	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
		3325	}
		3326
		3327	/**
		3328	* @brief Enable capture/compare 4 interrupt (CC4IE).
		3329	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
		3330	* @param TIMx Timer instance
		3331	* @retval None
		3332	*/
		3333	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
		3334	{
		3335	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3336	}
		3337
		3338	/**
		3339	* @brief Disable capture/compare 4 interrupt (CC4IE).
		3340	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
		3341	* @param TIMx Timer instance
		3342	* @retval None
		3343	*/
		3344	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
		3345	{
		3346	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3347	}
		3348
		3349	/**
		3350	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
		3351	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
		3352	* @param TIMx Timer instance
		3353	* @retval State of bit (1 or 0).
		3354	*/
		3355	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
		3356	{
		3357	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
		3358	}
		3359
		3360	/**
		3361	* @brief Enable commutation interrupt (COMIE).
		3362	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
		3363	* @param TIMx Timer instance
		3364	* @retval None
		3365	*/
		3366	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
		3367	{
		3368	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3369	}
		3370
		3371	/**
		3372	* @brief Disable commutation interrupt (COMIE).
		3373	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
		3374	* @param TIMx Timer instance
		3375	* @retval None
		3376	*/
		3377	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
		3378	{
		3379	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3380	}
		3381
		3382	/**
		3383	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
		3384	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
		3385	* @param TIMx Timer instance
		3386	* @retval State of bit (1 or 0).
		3387	*/
		3388	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
		3389	{
		3390	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
		3391	}
		3392
		3393	/**
		3394	* @brief Enable trigger interrupt (TIE).
		3395	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
		3396	* @param TIMx Timer instance
		3397	* @retval None
		3398	*/
		3399	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
		3400	{
		3401	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
		3402	}
		3403
		3404	/**
		3405	* @brief Disable trigger interrupt (TIE).
		3406	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
		3407	* @param TIMx Timer instance
		3408	* @retval None
		3409	*/
		3410	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
		3411	{
		3412	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
		3413	}
		3414
		3415	/**
		3416	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
		3417	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
		3418	* @param TIMx Timer instance
		3419	* @retval State of bit (1 or 0).
		3420	*/
		3421	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
		3422	{
		3423	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
		3424	}
		3425
		3426	/**
		3427	* @brief Enable break interrupt (BIE).
		3428	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
		3429	* @param TIMx Timer instance
		3430	* @retval None
		3431	*/
		3432	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
		3433	{
		3434	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
		3435	}
		3436
		3437	/**
		3438	* @brief Disable break interrupt (BIE).
		3439	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
		3440	* @param TIMx Timer instance
		3441	* @retval None
		3442	*/
		3443	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
		3444	{
		3445	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
		3446	}
		3447
		3448	/**
		3449	* @brief Indicates whether the break interrupt (BIE) is enabled.
		3450	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
		3451	* @param TIMx Timer instance
		3452	* @retval State of bit (1 or 0).
		3453	*/
		3454	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
		3455	{
		3456	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
		3457	}
		3458
		3459	/**
		3460	* @}
		3461	*/
		3462
		3463	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
		3464	* @{
		3465	*/
		3466	/**
		3467	* @brief Enable update DMA request (UDE).
		3468	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
		3469	* @param TIMx Timer instance
		3470	* @retval None
		3471	*/
		3472	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3473	{
		3474	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
		3475	}
		3476
		3477	/**
		3478	* @brief Disable update DMA request (UDE).
		3479	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
		3480	* @param TIMx Timer instance
		3481	* @retval None
		3482	*/
		3483	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3484	{
		3485	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
		3486	}
		3487
		3488	/**
		3489	* @brief Indicates whether the update DMA request (UDE) is enabled.
		3490	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
		3491	* @param TIMx Timer instance
		3492	* @retval State of bit (1 or 0).
		3493	*/
		3494	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3495	{
		3496	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
		3497	}
		3498
		3499	/**
		3500	* @brief Enable capture/compare 1 DMA request (CC1DE).
		3501	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
		3502	* @param TIMx Timer instance
		3503	* @retval None
		3504	*/
		3505	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
		3506	{
		3507	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3508	}
		3509
		3510	/**
		3511	* @brief Disable capture/compare 1 DMA request (CC1DE).
		3512	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
		3513	* @param TIMx Timer instance
		3514	* @retval None
		3515	*/
		3516	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
		3517	{
		3518	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3519	}
		3520
		3521	/**
		3522	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
		3523	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
		3524	* @param TIMx Timer instance
		3525	* @retval State of bit (1 or 0).
		3526	*/
		3527	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
		3528	{
		3529	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
		3530	}
		3531
		3532	/**
		3533	* @brief Enable capture/compare 2 DMA request (CC2DE).
		3534	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
		3535	* @param TIMx Timer instance
		3536	* @retval None
		3537	*/
		3538	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
		3539	{
		3540	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3541	}
		3542
		3543	/**
		3544	* @brief Disable capture/compare 2 DMA request (CC2DE).
		3545	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
		3546	* @param TIMx Timer instance
		3547	* @retval None
		3548	*/
		3549	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
		3550	{
		3551	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3552	}
		3553
		3554	/**
		3555	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
		3556	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
		3557	* @param TIMx Timer instance
		3558	* @retval State of bit (1 or 0).
		3559	*/
		3560	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
		3561	{
		3562	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
		3563	}
		3564
		3565	/**
		3566	* @brief Enable capture/compare 3 DMA request (CC3DE).
		3567	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
		3568	* @param TIMx Timer instance
		3569	* @retval None
		3570	*/
		3571	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
		3572	{
		3573	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3574	}
		3575
		3576	/**
		3577	* @brief Disable capture/compare 3 DMA request (CC3DE).
		3578	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
		3579	* @param TIMx Timer instance
		3580	* @retval None
		3581	*/
		3582	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
		3583	{
		3584	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3585	}
		3586
		3587	/**
		3588	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
		3589	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
		3590	* @param TIMx Timer instance
		3591	* @retval State of bit (1 or 0).
		3592	*/
		3593	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
		3594	{
		3595	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
		3596	}
		3597
		3598	/**
		3599	* @brief Enable capture/compare 4 DMA request (CC4DE).
		3600	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
		3601	* @param TIMx Timer instance
		3602	* @retval None
		3603	*/
		3604	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
		3605	{
		3606	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3607	}
		3608
		3609	/**
		3610	* @brief Disable capture/compare 4 DMA request (CC4DE).
		3611	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
		3612	* @param TIMx Timer instance
		3613	* @retval None
		3614	*/
		3615	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
		3616	{
		3617	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3618	}
		3619
		3620	/**
		3621	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
		3622	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
		3623	* @param TIMx Timer instance
		3624	* @retval State of bit (1 or 0).
		3625	*/
		3626	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
		3627	{
		3628	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
		3629	}
		3630
		3631	/**
		3632	* @brief Enable commutation DMA request (COMDE).
		3633	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
		3634	* @param TIMx Timer instance
		3635	* @retval None
		3636	*/
		3637	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
		3638	{
		3639	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3640	}
		3641
		3642	/**
		3643	* @brief Disable commutation DMA request (COMDE).
		3644	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
		3645	* @param TIMx Timer instance
		3646	* @retval None
		3647	*/
		3648	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
		3649	{
		3650	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3651	}
		3652
		3653	/**
		3654	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
		3655	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
		3656	* @param TIMx Timer instance
		3657	* @retval State of bit (1 or 0).
		3658	*/
		3659	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
		3660	{
		3661	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
		3662	}
		3663
		3664	/**
		3665	* @brief Enable trigger interrupt (TDE).
		3666	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
		3667	* @param TIMx Timer instance
		3668	* @retval None
		3669	*/
		3670	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3671	{
		3672	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
		3673	}
		3674
		3675	/**
		3676	* @brief Disable trigger interrupt (TDE).
		3677	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
		3678	* @param TIMx Timer instance
		3679	* @retval None
		3680	*/
		3681	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3682	{
		3683	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
		3684	}
		3685
		3686	/**
		3687	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
		3688	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
		3689	* @param TIMx Timer instance
		3690	* @retval State of bit (1 or 0).
		3691	*/
		3692	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
		3693	{
		3694	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
		3695	}
		3696
		3697	/**
		3698	* @}
		3699	*/
		3700
		3701	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
		3702	* @{
		3703	*/
		3704	/**
		3705	* @brief Generate an update event.
		3706	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
		3707	* @param TIMx Timer instance
		3708	* @retval None
		3709	*/
		3710	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
		3711	{
		3712	SET_BIT(TIMx->EGR, TIM_EGR_UG);
		3713	}
		3714
		3715	/**
		3716	* @brief Generate Capture/Compare 1 event.
		3717	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
		3718	* @param TIMx Timer instance
		3719	* @retval None
		3720	*/
		3721	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
		3722	{
		3723	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
		3724	}
		3725
		3726	/**
		3727	* @brief Generate Capture/Compare 2 event.
		3728	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
		3729	* @param TIMx Timer instance
		3730	* @retval None
		3731	*/
		3732	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
		3733	{
		3734	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
		3735	}
		3736
		3737	/**
		3738	* @brief Generate Capture/Compare 3 event.
		3739	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
		3740	* @param TIMx Timer instance
		3741	* @retval None
		3742	*/
		3743	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
		3744	{
		3745	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
		3746	}
		3747
		3748	/**
		3749	* @brief Generate Capture/Compare 4 event.
		3750	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
		3751	* @param TIMx Timer instance
		3752	* @retval None
		3753	*/
		3754	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
		3755	{
		3756	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
		3757	}
		3758
		3759	/**
		3760	* @brief Generate commutation event.
		3761	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
		3762	* @param TIMx Timer instance
		3763	* @retval None
		3764	*/
		3765	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
		3766	{
		3767	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
		3768	}
		3769
		3770	/**
		3771	* @brief Generate trigger event.
		3772	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
		3773	* @param TIMx Timer instance
		3774	* @retval None
		3775	*/
		3776	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
		3777	{
		3778	SET_BIT(TIMx->EGR, TIM_EGR_TG);
		3779	}
		3780
		3781	/**
		3782	* @brief Generate break event.
		3783	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
		3784	* @param TIMx Timer instance
		3785	* @retval None
		3786	*/
		3787	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
		3788	{
		3789	SET_BIT(TIMx->EGR, TIM_EGR_BG);
		3790	}
		3791
		3792	/**
		3793	* @}
		3794	*/
		3795
		3796	#if defined(USE_FULL_LL_DRIVER)
		3797	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
		3798	* @{
		3799	*/
		3800
		3801	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
		3802	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
		3803	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
		3804	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
		3805	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
		3806	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
		3807	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
		3808	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
		3809	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
		3810	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
		3811	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
		3812	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
		3813	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
		3814	/**
		3815	* @}
		3816	*/
		3817	#endif /* USE_FULL_LL_DRIVER */
		3818
		3819	/**
		3820	* @}
		3821	*/
		3822
		3823	/**
		3824	* @}
		3825	*/
		3826
		3827	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 */
		3828
		3829	/**
		3830	* @}
		3831	*/
		3832
		3833	#ifdef __cplusplus
		3834	}
		3835	#endif
		3836
		3837	#endif /* __STM32F1xx_LL_TIM_H */
		3838	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h – Rev 2