WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM LL module.
		6	******************************************************************************
		7	* @attention
		8	*
9	mjames	9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
2	mjames	11	*
9	mjames	12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
2	mjames	16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef __STM32F1xx_LL_TIM_H
		22	#define __STM32F1xx_LL_TIM_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f1xx.h"
		30
		31	/** @addtogroup STM32F1xx_LL_Driver
		32	* @{
		33	*/
		34
9	mjames	35	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17)
2	mjames	36
		37	/** @defgroup TIM_LL TIM
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
		44	* @{
		45	*/
		46	static const uint8_t OFFSET_TAB_CCMRx[] =
		47	{
		48	0x00U, /* 0: TIMx_CH1 */
		49	0x00U, /* 1: TIMx_CH1N */
		50	0x00U, /* 2: TIMx_CH2 */
		51	0x00U, /* 3: TIMx_CH2N */
		52	0x04U, /* 4: TIMx_CH3 */
		53	0x04U, /* 5: TIMx_CH3N */
		54	0x04U /* 6: TIMx_CH4 */
		55	};
		56
		57	static const uint8_t SHIFT_TAB_OCxx[] =
		58	{
		59	0U, /* 0: OC1M, OC1FE, OC1PE */
		60	0U, /* 1: - NA */
		61	8U, /* 2: OC2M, OC2FE, OC2PE */
		62	0U, /* 3: - NA */
		63	0U, /* 4: OC3M, OC3FE, OC3PE */
		64	0U, /* 5: - NA */
		65	8U /* 6: OC4M, OC4FE, OC4PE */
		66	};
		67
		68	static const uint8_t SHIFT_TAB_ICxx[] =
		69	{
		70	0U, /* 0: CC1S, IC1PSC, IC1F */
		71	0U, /* 1: - NA */
		72	8U, /* 2: CC2S, IC2PSC, IC2F */
		73	0U, /* 3: - NA */
		74	0U, /* 4: CC3S, IC3PSC, IC3F */
		75	0U, /* 5: - NA */
		76	8U /* 6: CC4S, IC4PSC, IC4F */
		77	};
		78
		79	static const uint8_t SHIFT_TAB_CCxP[] =
		80	{
		81	0U, /* 0: CC1P */
		82	2U, /* 1: CC1NP */
		83	4U, /* 2: CC2P */
		84	6U, /* 3: CC2NP */
		85	8U, /* 4: CC3P */
		86	10U, /* 5: CC3NP */
		87	12U /* 6: CC4P */
		88	};
		89
		90	static const uint8_t SHIFT_TAB_OISx[] =
		91	{
		92	0U, /* 0: OIS1 */
		93	1U, /* 1: OIS1N */
		94	2U, /* 2: OIS2 */
		95	3U, /* 3: OIS2N */
		96	4U, /* 4: OIS3 */
		97	5U, /* 5: OIS3N */
		98	6U /* 6: OIS4 */
		99	};
		100	/**
		101	* @}
		102	*/
		103
		104	/* Private constants ---------------------------------------------------------*/
		105	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
		106	* @{
		107	*/
		108
		109
		110
		111	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
		112	#define DT_DELAY_1 ((uint8_t)0x7F)
		113	#define DT_DELAY_2 ((uint8_t)0x3F)
		114	#define DT_DELAY_3 ((uint8_t)0x1F)
		115	#define DT_DELAY_4 ((uint8_t)0x1F)
		116
		117	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
		118	#define DT_RANGE_1 ((uint8_t)0x00)
		119	#define DT_RANGE_2 ((uint8_t)0x80)
		120	#define DT_RANGE_3 ((uint8_t)0xC0)
		121	#define DT_RANGE_4 ((uint8_t)0xE0)
		122
		123
		124	/**
		125	* @}
		126	*/
		127
		128	/* Private macros ------------------------------------------------------------*/
		129	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
		130	* @{
		131	*/
		132	/** @brief Convert channel id into channel index.
		133	* @param __CHANNEL__ This parameter can be one of the following values:
		134	* @arg @ref LL_TIM_CHANNEL_CH1
		135	* @arg @ref LL_TIM_CHANNEL_CH1N
		136	* @arg @ref LL_TIM_CHANNEL_CH2
		137	* @arg @ref LL_TIM_CHANNEL_CH2N
		138	* @arg @ref LL_TIM_CHANNEL_CH3
		139	* @arg @ref LL_TIM_CHANNEL_CH3N
		140	* @arg @ref LL_TIM_CHANNEL_CH4
		141	* @retval none
		142	*/
		143	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
9	mjames	144	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
		145	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
		146	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
		147	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
		148	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
		149	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
2	mjames	150
		151	/** @brief Calculate the deadtime sampling period(in ps).
		152	* @param __TIMCLK__ timer input clock frequency (in Hz).
		153	* @param __CKD__ This parameter can be one of the following values:
		154	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		155	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		156	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		157	* @retval none
		158	*/
		159	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
9	mjames	160	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
		161	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
		162	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
2	mjames	163	/**
		164	* @}
		165	*/
		166
		167
		168	/* Exported types ------------------------------------------------------------*/
		169	#if defined(USE_FULL_LL_DRIVER)
		170	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
		171	* @{
		172	*/
		173
		174	/**
		175	* @brief TIM Time Base configuration structure definition.
		176	*/
		177	typedef struct
		178	{
		179	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		180	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		181
		182	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
		183
		184	uint32_t CounterMode; /*!< Specifies the counter mode.
		185	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
		186
		187	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
		188
		189	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
		190	Auto-Reload Register at the next update event.
		191	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		192	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
		193
		194	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
		195
		196	uint32_t ClockDivision; /*!< Specifies the clock division.
		197	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
		198
		199	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
		200
9	mjames	201	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
2	mjames	202	reaches zero, an update event is generated and counting restarts
		203	from the RCR value (N).
		204	This means in PWM mode that (N+1) corresponds to:
		205	- the number of PWM periods in edge-aligned mode
		206	- the number of half PWM period in center-aligned mode
9	mjames	207	GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
		208	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
2	mjames	209
		210	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
		211	} LL_TIM_InitTypeDef;
		212
		213	/**
		214	* @brief TIM Output Compare configuration structure definition.
		215	*/
		216	typedef struct
		217	{
		218	uint32_t OCMode; /*!< Specifies the output mode.
		219	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
		220
		221	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
		222
		223	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
		224	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		225
		226	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
		227
		228	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
		229	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		230
		231	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
		232
		233	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
		234	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		235
		236	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
		237
		238	uint32_t OCPolarity; /*!< Specifies the output polarity.
		239	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		240
		241	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
		242
		243	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		244	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		245
		246	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
		247
		248
		249	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		250	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		251
		252	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
		253
		254	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		255	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		256
		257	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
		258	} LL_TIM_OC_InitTypeDef;
		259
		260	/**
		261	* @brief TIM Input Capture configuration structure definition.
		262	*/
		263
		264	typedef struct
		265	{
		266
		267	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		268	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		269
		270	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		271
		272	uint32_t ICActiveInput; /*!< Specifies the input.
		273	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		274
		275	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		276
		277	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		278	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		279
		280	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		281
		282	uint32_t ICFilter; /*!< Specifies the input capture filter.
		283	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		284
		285	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		286	} LL_TIM_IC_InitTypeDef;
		287
		288
		289	/**
		290	* @brief TIM Encoder interface configuration structure definition.
		291	*/
		292	typedef struct
		293	{
		294	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
		295	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
		296
		297	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
		298
		299	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		300	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		301
		302	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		303
		304	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
		305	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		306
		307	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		308
		309	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		310	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		311
		312	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		313
		314	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		315	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		316
		317	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		318
		319	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
		320	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		321
		322	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		323
		324	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
		325	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		326
		327	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		328
		329	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
		330	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		331
		332	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		333
		334	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
		335	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		336
		337	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		338
		339	} LL_TIM_ENCODER_InitTypeDef;
		340
		341	/**
		342	* @brief TIM Hall sensor interface configuration structure definition.
		343	*/
		344	typedef struct
		345	{
		346
		347	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		348	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		349
		350	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		351
		352	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		353	Prescaler must be set to get a maximum counter period longer than the
		354	time interval between 2 consecutive changes on the Hall inputs.
		355	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		356
		357	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		358
		359	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		360	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		361
		362	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		363
		364	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
		365	A positive pulse (TRGO event) is generated with a programmable delay every time
		366	a change occurs on the Hall inputs.
		367	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
		368
		369	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
		370	} LL_TIM_HALLSENSOR_InitTypeDef;
		371
		372	/**
		373	* @brief BDTR (Break and Dead Time) structure definition
		374	*/
		375	typedef struct
		376	{
		377	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
		378	This parameter can be a value of @ref TIM_LL_EC_OSSR
		379
		380	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
		381
		382	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
		383
		384	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
		385	This parameter can be a value of @ref TIM_LL_EC_OSSI
		386
		387	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
		388
		389	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
		390
		391	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
		392	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
		393
		394	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
		395	has been written, their content is frozen until the next reset.*/
		396
		397	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
		398	switching-on of the outputs.
		399	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
		400
		401	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
		402
		403	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
		404
		405	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
		406	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
		407
		408	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
		409
		410	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
		411
		412	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
		413	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
		414
		415	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
		416
		417	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
		418
		419	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
		420	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
		421
		422	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
		423
		424	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
		425	} LL_TIM_BDTR_InitTypeDef;
		426
		427	/**
		428	* @}
		429	*/
		430	#endif /* USE_FULL_LL_DRIVER */
		431
		432	/* Exported constants --------------------------------------------------------*/
		433	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
		434	* @{
		435	*/
		436
		437	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
		438	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
		439	* @{
		440	*/
		441	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
		442	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
		443	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
		444	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
		445	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
		446	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
		447	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
		448	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
		449	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
		450	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
		451	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
		452	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
		453	/**
		454	* @}
		455	*/
		456
		457	#if defined(USE_FULL_LL_DRIVER)
		458	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
		459	* @{
		460	*/
		461	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
		462	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
		463	/**
		464	* @}
		465	*/
		466
		467	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
		468	* @{
		469	*/
		470	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
		471	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
		472	/**
		473	* @}
		474	*/
		475	#endif /* USE_FULL_LL_DRIVER */
		476
		477	/** @defgroup TIM_LL_EC_IT IT Defines
		478	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
		479	* @{
		480	*/
		481	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
		482	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
		483	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
		484	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
		485	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
		486	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
		487	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
		488	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
		489	/**
		490	* @}
		491	*/
		492
		493	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
		494	* @{
		495	*/
		496	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
		497	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
		498	/**
		499	* @}
		500	*/
		501
		502	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
		503	* @{
		504	*/
		505	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
		506	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
		507	/**
		508	* @}
		509	*/
		510
		511	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
		512	* @{
		513	*/
		514	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
		515	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
9	mjames	516	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
		517	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
2	mjames	518	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
		519	/**
		520	* @}
		521	*/
		522
		523	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
		524	* @{
		525	*/
		526	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
		527	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
		528	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
		529	/**
		530	* @}
		531	*/
		532
		533	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
		534	* @{
		535	*/
		536	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
		537	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
		538	/**
		539	* @}
		540	*/
		541
		542	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
		543	* @{
		544	*/
		545	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
		546	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
		547	/**
		548	* @}
		549	*/
		550
		551	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
		552	* @{
		553	*/
		554	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
		555	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
		556	/**
		557	* @}
		558	*/
		559
		560	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
		561	* @{
		562	*/
		563	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
		564	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
		565	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
		566	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
		567	/**
		568	* @}
		569	*/
		570
		571	/** @defgroup TIM_LL_EC_CHANNEL Channel
		572	* @{
		573	*/
		574	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
		575	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
		576	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
		577	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
		578	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
		579	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
		580	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
		581	/**
		582	* @}
		583	*/
		584
		585	#if defined(USE_FULL_LL_DRIVER)
		586	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
		587	* @{
		588	*/
		589	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
		590	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
		591	/**
		592	* @}
		593	*/
		594	#endif /* USE_FULL_LL_DRIVER */
		595
		596	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
		597	* @{
		598	*/
		599	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
		600	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
		601	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
		602	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
9	mjames	603	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
2	mjames	604	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
		605	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
		606	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
		607	/**
		608	* @}
		609	*/
		610
		611	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
		612	* @{
		613	*/
		614	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
		615	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
		616	/**
		617	* @}
		618	*/
		619
		620	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
		621	* @{
		622	*/
		623	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
		624	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
		625	/**
		626	* @}
		627	*/
		628
		629
		630	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
		631	* @{
		632	*/
		633	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
		634	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
		635	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
		636	/**
		637	* @}
		638	*/
		639
		640	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
		641	* @{
		642	*/
9	mjames	643	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
2	mjames	644	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
		645	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
		646	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
		647	/**
		648	* @}
		649	*/
		650
		651	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
		652	* @{
		653	*/
		654	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		655	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
		656	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
		657	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
		658	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
		659	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
		660	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
		661	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
		662	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
		663	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
		664	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
		665	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
		666	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
		667	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
		668	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
		669	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
		670	/**
		671	* @}
		672	*/
		673
		674	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
		675	* @{
		676	*/
		677	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
		678	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
		679	/**
		680	* @}
		681	*/
		682
		683	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
		684	* @{
		685	*/
		686	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
9	mjames	687	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
2	mjames	688	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
		689	/**
		690	* @}
		691	*/
		692
		693	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
		694	* @{
		695	*/
9	mjames	696	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
		697	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
		698	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
2	mjames	699	/**
		700	* @}
		701	*/
		702
		703	/** @defgroup TIM_LL_EC_TRGO Trigger Output
		704	* @{
		705	*/
		706	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
		707	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
		708	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
		709	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
		710	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
		711	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
		712	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
		713	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
		714	/**
		715	* @}
		716	*/
		717
		718
		719	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
		720	* @{
		721	*/
		722	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
		723	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
		724	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
		725	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
		726	/**
		727	* @}
		728	*/
		729
		730	/** @defgroup TIM_LL_EC_TS Trigger Selection
		731	* @{
		732	*/
9	mjames	733	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
		734	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
		735	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
		736	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
		737	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
		738	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
		739	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
		740	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
2	mjames	741	/**
		742	* @}
		743	*/
		744
		745	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
		746	* @{
		747	*/
		748	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
		749	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
		750	/**
		751	* @}
		752	*/
		753
		754	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
		755	* @{
		756	*/
		757	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
		758	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
		759	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
		760	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
		761	/**
		762	* @}
		763	*/
		764
		765	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
		766	* @{
		767	*/
		768	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		769	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
		770	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
		771	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
		772	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
		773	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
		774	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
		775	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
		776	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
		777	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
		778	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
		779	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
		780	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
		781	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
		782	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
		783	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
		784	/**
		785	* @}
		786	*/
		787
		788
		789	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
		790	* @{
		791	*/
		792	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
		793	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
		794	/**
		795	* @}
		796	*/
		797
		798
		799
		800
		801	/** @defgroup TIM_LL_EC_OSSI OSSI
		802	* @{
		803	*/
		804	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		805	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
		806	/**
		807	* @}
		808	*/
		809
		810	/** @defgroup TIM_LL_EC_OSSR OSSR
		811	* @{
		812	*/
		813	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		814	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
		815	/**
		816	* @}
		817	*/
		818
		819
		820	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
		821	* @{
		822	*/
		823	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
		824	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
		825	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
		826	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
		827	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
		828	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
		829	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
		830	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
		831	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
		832	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
		833	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
		834	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
		835	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
		836	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
		837	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
		838	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
		839	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
		840	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
		841	/**
		842	* @}
		843	*/
		844
		845	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
		846	* @{
		847	*/
		848	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
		849	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
		850	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
		851	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
		852	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
		853	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
		854	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
		855	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
		856	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
		857	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
		858	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
		859	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
		860	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
		861	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
		862	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
		863	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
		864	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
		865	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
		866	/**
		867	* @}
		868	*/
		869
		870
		871	/**
		872	* @}
		873	*/
		874
		875	/* Exported macro ------------------------------------------------------------*/
		876	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
		877	* @{
		878	*/
		879
		880	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
		881	* @{
		882	*/
		883	/**
		884	* @brief Write a value in TIM register.
		885	* @param __INSTANCE__ TIM Instance
		886	* @param __REG__ Register to be written
		887	* @param __VALUE__ Value to be written in the register
		888	* @retval None
		889	*/
9	mjames	890	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
2	mjames	891
		892	/**
		893	* @brief Read a value in TIM register.
		894	* @param __INSTANCE__ TIM Instance
		895	* @param __REG__ Register to be read
		896	* @retval Register value
		897	*/
9	mjames	898	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
2	mjames	899	/**
		900	* @}
		901	*/
		902
		903	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
		904	* @{
		905	*/
		906
		907	/**
		908	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
		909	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
		910	* @param __TIMCLK__ timer input clock frequency (in Hz)
		911	* @param __CKD__ This parameter can be one of the following values:
		912	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		913	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		914	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		915	* @param __DT__ deadtime duration (in ns)
		916	* @retval DTG[0:7]
		917	*/
		918	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
9	mjames	919	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
		920	(((uint64_t)((__DT__)1000U)) < ((64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
		921	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
		922	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
		923	0U)
2	mjames	924
		925	/**
		926	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
		927	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
		928	* @param __TIMCLK__ timer input clock frequency (in Hz)
		929	* @param __CNTCLK__ counter clock frequency (in Hz)
		930	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
		931	*/
		932	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
9	mjames	933	(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
2	mjames	934
		935	/**
		936	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
		937	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
		938	* @param __TIMCLK__ timer input clock frequency (in Hz)
		939	* @param __PSC__ prescaler
		940	* @param __FREQ__ output signal frequency (in Hz)
		941	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		942	*/
		943	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
9	mjames	944	((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
2	mjames	945
		946	/**
		947	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
		948	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
		949	* @param __TIMCLK__ timer input clock frequency (in Hz)
		950	* @param __PSC__ prescaler
		951	* @param __DELAY__ timer output compare active/inactive delay (in us)
		952	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
		953	*/
		954	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
9	mjames	955	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
		956	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
2	mjames	957
		958	/**
		959	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
		960	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
		961	* @param __TIMCLK__ timer input clock frequency (in Hz)
		962	* @param __PSC__ prescaler
		963	* @param __DELAY__ timer output compare active/inactive delay (in us)
		964	* @param __PULSE__ pulse duration (in us)
		965	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		966	*/
		967	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
9	mjames	968	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
		969	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
2	mjames	970
		971	/**
		972	* @brief HELPER macro retrieving the ratio of the input capture prescaler
		973	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
		974	* @param __ICPSC__ This parameter can be one of the following values:
		975	* @arg @ref LL_TIM_ICPSC_DIV1
		976	* @arg @ref LL_TIM_ICPSC_DIV2
		977	* @arg @ref LL_TIM_ICPSC_DIV4
		978	* @arg @ref LL_TIM_ICPSC_DIV8
		979	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
		980	*/
		981	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
9	mjames	982	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
2	mjames	983
		984
		985	/**
		986	* @}
		987	*/
		988
		989
		990	/**
		991	* @}
		992	*/
		993
		994	/* Exported functions --------------------------------------------------------*/
		995	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
		996	* @{
		997	*/
		998
		999	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
		1000	* @{
		1001	*/
		1002	/**
		1003	* @brief Enable timer counter.
		1004	* @rmtoll CR1 CEN LL_TIM_EnableCounter
		1005	* @param TIMx Timer instance
		1006	* @retval None
		1007	*/
		1008	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
		1009	{
		1010	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
		1011	}
		1012
		1013	/**
		1014	* @brief Disable timer counter.
		1015	* @rmtoll CR1 CEN LL_TIM_DisableCounter
		1016	* @param TIMx Timer instance
		1017	* @retval None
		1018	*/
		1019	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
		1020	{
		1021	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
		1022	}
		1023
		1024	/**
		1025	* @brief Indicates whether the timer counter is enabled.
		1026	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
		1027	* @param TIMx Timer instance
		1028	* @retval State of bit (1 or 0).
		1029	*/
		1030	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
		1031	{
9	mjames	1032	return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
2	mjames	1033	}
		1034
		1035	/**
		1036	* @brief Enable update event generation.
		1037	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
		1038	* @param TIMx Timer instance
		1039	* @retval None
		1040	*/
		1041	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
		1042	{
		1043	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1044	}
		1045
		1046	/**
		1047	* @brief Disable update event generation.
		1048	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
		1049	* @param TIMx Timer instance
		1050	* @retval None
		1051	*/
		1052	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
		1053	{
		1054	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1055	}
		1056
		1057	/**
		1058	* @brief Indicates whether update event generation is enabled.
		1059	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
		1060	* @param TIMx Timer instance
9	mjames	1061	* @retval Inverted state of bit (0 or 1).
2	mjames	1062	*/
		1063	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
		1064	{
9	mjames	1065	return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
2	mjames	1066	}
		1067
		1068	/**
		1069	* @brief Set update event source
		1070	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
		1071	* generate an update interrupt or DMA request if enabled:
		1072	* - Counter overflow/underflow
		1073	* - Setting the UG bit
		1074	* - Update generation through the slave mode controller
		1075	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
		1076	* overflow/underflow generates an update interrupt or DMA request if enabled.
		1077	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
		1078	* @param TIMx Timer instance
		1079	* @param UpdateSource This parameter can be one of the following values:
		1080	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1081	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1082	* @retval None
		1083	*/
		1084	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
		1085	{
		1086	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
		1087	}
		1088
		1089	/**
		1090	* @brief Get actual event update source
		1091	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
		1092	* @param TIMx Timer instance
		1093	* @retval Returned value can be one of the following values:
		1094	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1095	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1096	*/
		1097	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
		1098	{
		1099	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
		1100	}
		1101
		1102	/**
		1103	* @brief Set one pulse mode (one shot v.s. repetitive).
		1104	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
		1105	* @param TIMx Timer instance
		1106	* @param OnePulseMode This parameter can be one of the following values:
		1107	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1108	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1109	* @retval None
		1110	*/
		1111	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
		1112	{
		1113	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
		1114	}
		1115
		1116	/**
		1117	* @brief Get actual one pulse mode.
		1118	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
		1119	* @param TIMx Timer instance
		1120	* @retval Returned value can be one of the following values:
		1121	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1122	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1123	*/
		1124	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
		1125	{
		1126	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
		1127	}
		1128
		1129	/**
		1130	* @brief Set the timer counter counting mode.
9	mjames	1131	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2	mjames	1132	* check whether or not the counter mode selection feature is supported
		1133	* by a timer instance.
		1134	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1135	* requires a timer reset to avoid unexpected direction
		1136	* due to DIR bit readonly in center aligned mode.
		1137	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
		1138	* CR1 CMS LL_TIM_SetCounterMode
		1139	* @param TIMx Timer instance
		1140	* @param CounterMode This parameter can be one of the following values:
		1141	* @arg @ref LL_TIM_COUNTERMODE_UP
		1142	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1143	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1144	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1145	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1146	* @retval None
		1147	*/
		1148	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
		1149	{
9	mjames	1150	MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR \| TIM_CR1_CMS), CounterMode);
2	mjames	1151	}
		1152
		1153	/**
		1154	* @brief Get actual counter mode.
9	mjames	1155	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2	mjames	1156	* check whether or not the counter mode selection feature is supported
		1157	* by a timer instance.
		1158	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
		1159	* CR1 CMS LL_TIM_GetCounterMode
		1160	* @param TIMx Timer instance
		1161	* @retval Returned value can be one of the following values:
		1162	* @arg @ref LL_TIM_COUNTERMODE_UP
		1163	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1164	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1165	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1166	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1167	*/
		1168	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
		1169	{
		1170	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
		1171	}
		1172
		1173	/**
		1174	* @brief Enable auto-reload (ARR) preload.
		1175	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
		1176	* @param TIMx Timer instance
		1177	* @retval None
		1178	*/
		1179	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
		1180	{
		1181	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1182	}
		1183
		1184	/**
		1185	* @brief Disable auto-reload (ARR) preload.
		1186	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
		1187	* @param TIMx Timer instance
		1188	* @retval None
		1189	*/
		1190	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
		1191	{
		1192	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1193	}
		1194
		1195	/**
		1196	* @brief Indicates whether auto-reload (ARR) preload is enabled.
		1197	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
		1198	* @param TIMx Timer instance
		1199	* @retval State of bit (1 or 0).
		1200	*/
		1201	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
		1202	{
9	mjames	1203	return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
2	mjames	1204	}
		1205
		1206	/**
		1207	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
9	mjames	1208	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2	mjames	1209	* whether or not the clock division feature is supported by the timer
		1210	* instance.
		1211	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
		1212	* @param TIMx Timer instance
		1213	* @param ClockDivision This parameter can be one of the following values:
		1214	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1215	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1216	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1217	* @retval None
		1218	*/
		1219	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
		1220	{
		1221	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
		1222	}
		1223
		1224	/**
		1225	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
9	mjames	1226	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2	mjames	1227	* whether or not the clock division feature is supported by the timer
		1228	* instance.
		1229	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
		1230	* @param TIMx Timer instance
		1231	* @retval Returned value can be one of the following values:
		1232	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1233	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1234	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1235	*/
		1236	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
		1237	{
		1238	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
		1239	}
		1240
		1241	/**
		1242	* @brief Set the counter value.
		1243	* @rmtoll CNT CNT LL_TIM_SetCounter
		1244	* @param TIMx Timer instance
		1245	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
		1246	* @retval None
		1247	*/
		1248	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
		1249	{
		1250	WRITE_REG(TIMx->CNT, Counter);
		1251	}
		1252
		1253	/**
		1254	* @brief Get the counter value.
		1255	* @rmtoll CNT CNT LL_TIM_GetCounter
		1256	* @param TIMx Timer instance
		1257	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
		1258	*/
		1259	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
		1260	{
		1261	return (uint32_t)(READ_REG(TIMx->CNT));
		1262	}
		1263
		1264	/**
		1265	* @brief Get the current direction of the counter
		1266	* @rmtoll CR1 DIR LL_TIM_GetDirection
		1267	* @param TIMx Timer instance
		1268	* @retval Returned value can be one of the following values:
		1269	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
		1270	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
		1271	*/
		1272	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
		1273	{
		1274	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1275	}
		1276
		1277	/**
		1278	* @brief Set the prescaler value.
		1279	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
		1280	* @note The prescaler can be changed on the fly as this control register is buffered. The new
		1281	* prescaler ratio is taken into account at the next update event.
		1282	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
		1283	* @rmtoll PSC PSC LL_TIM_SetPrescaler
		1284	* @param TIMx Timer instance
		1285	* @param Prescaler between Min_Data=0 and Max_Data=65535
		1286	* @retval None
		1287	*/
		1288	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
		1289	{
		1290	WRITE_REG(TIMx->PSC, Prescaler);
		1291	}
		1292
		1293	/**
		1294	* @brief Get the prescaler value.
		1295	* @rmtoll PSC PSC LL_TIM_GetPrescaler
		1296	* @param TIMx Timer instance
		1297	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
		1298	*/
		1299	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
		1300	{
		1301	return (uint32_t)(READ_REG(TIMx->PSC));
		1302	}
		1303
		1304	/**
		1305	* @brief Set the auto-reload value.
		1306	* @note The counter is blocked while the auto-reload value is null.
		1307	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
		1308	* @rmtoll ARR ARR LL_TIM_SetAutoReload
		1309	* @param TIMx Timer instance
		1310	* @param AutoReload between Min_Data=0 and Max_Data=65535
		1311	* @retval None
		1312	*/
		1313	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
		1314	{
		1315	WRITE_REG(TIMx->ARR, AutoReload);
		1316	}
		1317
		1318	/**
		1319	* @brief Get the auto-reload value.
		1320	* @rmtoll ARR ARR LL_TIM_GetAutoReload
		1321	* @param TIMx Timer instance
		1322	* @retval Auto-reload value
		1323	*/
		1324	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
		1325	{
		1326	return (uint32_t)(READ_REG(TIMx->ARR));
		1327	}
		1328
		1329	/**
		1330	* @brief Set the repetition counter value.
9	mjames	1331	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2	mjames	1332	* whether or not a timer instance supports a repetition counter.
		1333	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
		1334	* @param TIMx Timer instance
9	mjames	1335	* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2	mjames	1336	* @retval None
		1337	*/
		1338	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
		1339	{
		1340	WRITE_REG(TIMx->RCR, RepetitionCounter);
		1341	}
		1342
		1343	/**
		1344	* @brief Get the repetition counter value.
9	mjames	1345	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2	mjames	1346	* whether or not a timer instance supports a repetition counter.
		1347	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
		1348	* @param TIMx Timer instance
		1349	* @retval Repetition counter value
		1350	*/
		1351	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
		1352	{
		1353	return (uint32_t)(READ_REG(TIMx->RCR));
		1354	}
		1355
		1356	/**
		1357	* @}
		1358	*/
		1359
		1360	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
		1361	* @{
		1362	*/
		1363	/**
		1364	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
		1365	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
		1366	* they are updated only when a commutation event (COM) occurs.
		1367	* @note Only on channels that have a complementary output.
9	mjames	1368	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2	mjames	1369	* whether or not a timer instance is able to generate a commutation event.
		1370	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
		1371	* @param TIMx Timer instance
		1372	* @retval None
		1373	*/
		1374	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
		1375	{
		1376	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1377	}
		1378
		1379	/**
		1380	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
9	mjames	1381	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2	mjames	1382	* whether or not a timer instance is able to generate a commutation event.
		1383	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
		1384	* @param TIMx Timer instance
		1385	* @retval None
		1386	*/
		1387	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
		1388	{
		1389	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1390	}
		1391
		1392	/**
		1393	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
9	mjames	1394	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2	mjames	1395	* whether or not a timer instance is able to generate a commutation event.
		1396	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
		1397	* @param TIMx Timer instance
		1398	* @param CCUpdateSource This parameter can be one of the following values:
		1399	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
		1400	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
		1401	* @retval None
		1402	*/
		1403	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
		1404	{
		1405	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
		1406	}
		1407
		1408	/**
		1409	* @brief Set the trigger of the capture/compare DMA request.
		1410	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
		1411	* @param TIMx Timer instance
		1412	* @param DMAReqTrigger This parameter can be one of the following values:
		1413	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1414	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1415	* @retval None
		1416	*/
		1417	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
		1418	{
		1419	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
		1420	}
		1421
		1422	/**
		1423	* @brief Get actual trigger of the capture/compare DMA request.
		1424	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
		1425	* @param TIMx Timer instance
		1426	* @retval Returned value can be one of the following values:
		1427	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1428	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1429	*/
		1430	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
		1431	{
		1432	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
		1433	}
		1434
		1435	/**
		1436	* @brief Set the lock level to freeze the
		1437	* configuration of several capture/compare parameters.
9	mjames	1438	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	1439	* the lock mechanism is supported by a timer instance.
		1440	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
		1441	* @param TIMx Timer instance
		1442	* @param LockLevel This parameter can be one of the following values:
		1443	* @arg @ref LL_TIM_LOCKLEVEL_OFF
		1444	* @arg @ref LL_TIM_LOCKLEVEL_1
		1445	* @arg @ref LL_TIM_LOCKLEVEL_2
		1446	* @arg @ref LL_TIM_LOCKLEVEL_3
		1447	* @retval None
		1448	*/
		1449	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
		1450	{
		1451	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
		1452	}
		1453
		1454	/**
		1455	* @brief Enable capture/compare channels.
		1456	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
		1457	* CCER CC1NE LL_TIM_CC_EnableChannel\n
		1458	* CCER CC2E LL_TIM_CC_EnableChannel\n
		1459	* CCER CC2NE LL_TIM_CC_EnableChannel\n
		1460	* CCER CC3E LL_TIM_CC_EnableChannel\n
		1461	* CCER CC3NE LL_TIM_CC_EnableChannel\n
		1462	* CCER CC4E LL_TIM_CC_EnableChannel
		1463	* @param TIMx Timer instance
		1464	* @param Channels This parameter can be a combination of the following values:
		1465	* @arg @ref LL_TIM_CHANNEL_CH1
		1466	* @arg @ref LL_TIM_CHANNEL_CH1N
		1467	* @arg @ref LL_TIM_CHANNEL_CH2
		1468	* @arg @ref LL_TIM_CHANNEL_CH2N
		1469	* @arg @ref LL_TIM_CHANNEL_CH3
		1470	* @arg @ref LL_TIM_CHANNEL_CH3N
		1471	* @arg @ref LL_TIM_CHANNEL_CH4
		1472	* @retval None
		1473	*/
		1474	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1475	{
		1476	SET_BIT(TIMx->CCER, Channels);
		1477	}
		1478
		1479	/**
		1480	* @brief Disable capture/compare channels.
		1481	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
		1482	* CCER CC1NE LL_TIM_CC_DisableChannel\n
		1483	* CCER CC2E LL_TIM_CC_DisableChannel\n
		1484	* CCER CC2NE LL_TIM_CC_DisableChannel\n
		1485	* CCER CC3E LL_TIM_CC_DisableChannel\n
		1486	* CCER CC3NE LL_TIM_CC_DisableChannel\n
		1487	* CCER CC4E LL_TIM_CC_DisableChannel
		1488	* @param TIMx Timer instance
		1489	* @param Channels This parameter can be a combination of the following values:
		1490	* @arg @ref LL_TIM_CHANNEL_CH1
		1491	* @arg @ref LL_TIM_CHANNEL_CH1N
		1492	* @arg @ref LL_TIM_CHANNEL_CH2
		1493	* @arg @ref LL_TIM_CHANNEL_CH2N
		1494	* @arg @ref LL_TIM_CHANNEL_CH3
		1495	* @arg @ref LL_TIM_CHANNEL_CH3N
		1496	* @arg @ref LL_TIM_CHANNEL_CH4
		1497	* @retval None
		1498	*/
		1499	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1500	{
		1501	CLEAR_BIT(TIMx->CCER, Channels);
		1502	}
		1503
		1504	/**
		1505	* @brief Indicate whether channel(s) is(are) enabled.
		1506	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
		1507	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
		1508	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
		1509	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
		1510	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
		1511	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
		1512	* CCER CC4E LL_TIM_CC_IsEnabledChannel
		1513	* @param TIMx Timer instance
		1514	* @param Channels This parameter can be a combination of the following values:
		1515	* @arg @ref LL_TIM_CHANNEL_CH1
		1516	* @arg @ref LL_TIM_CHANNEL_CH1N
		1517	* @arg @ref LL_TIM_CHANNEL_CH2
		1518	* @arg @ref LL_TIM_CHANNEL_CH2N
		1519	* @arg @ref LL_TIM_CHANNEL_CH3
		1520	* @arg @ref LL_TIM_CHANNEL_CH3N
		1521	* @arg @ref LL_TIM_CHANNEL_CH4
		1522	* @retval State of bit (1 or 0).
		1523	*/
		1524	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1525	{
9	mjames	1526	return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2	mjames	1527	}
		1528
		1529	/**
		1530	* @}
		1531	*/
		1532
		1533	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
		1534	* @{
		1535	*/
		1536	/**
		1537	* @brief Configure an output channel.
		1538	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
		1539	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
		1540	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
		1541	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
		1542	* CCER CC1P LL_TIM_OC_ConfigOutput\n
		1543	* CCER CC2P LL_TIM_OC_ConfigOutput\n
		1544	* CCER CC3P LL_TIM_OC_ConfigOutput\n
		1545	* CCER CC4P LL_TIM_OC_ConfigOutput\n
		1546	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
		1547	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
		1548	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
		1549	* CR2 OIS4 LL_TIM_OC_ConfigOutput
		1550	* @param TIMx Timer instance
		1551	* @param Channel This parameter can be one of the following values:
		1552	* @arg @ref LL_TIM_CHANNEL_CH1
		1553	* @arg @ref LL_TIM_CHANNEL_CH2
		1554	* @arg @ref LL_TIM_CHANNEL_CH3
		1555	* @arg @ref LL_TIM_CHANNEL_CH4
		1556	* @param Configuration This parameter must be a combination of all the following values:
		1557	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
		1558	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
		1559	* @retval None
		1560	*/
		1561	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		1562	{
9	mjames	1563	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1564	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1565	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
		1566	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
		1567	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
		1568	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
		1569	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
		1570	}
		1571
		1572	/**
		1573	* @brief Define the behavior of the output reference signal OCxREF from which
		1574	* OCx and OCxN (when relevant) are derived.
		1575	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
		1576	* CCMR1 OC2M LL_TIM_OC_SetMode\n
		1577	* CCMR2 OC3M LL_TIM_OC_SetMode\n
		1578	* CCMR2 OC4M LL_TIM_OC_SetMode
		1579	* @param TIMx Timer instance
		1580	* @param Channel This parameter can be one of the following values:
		1581	* @arg @ref LL_TIM_CHANNEL_CH1
		1582	* @arg @ref LL_TIM_CHANNEL_CH2
		1583	* @arg @ref LL_TIM_CHANNEL_CH3
		1584	* @arg @ref LL_TIM_CHANNEL_CH4
		1585	* @param Mode This parameter can be one of the following values:
		1586	* @arg @ref LL_TIM_OCMODE_FROZEN
		1587	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1588	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1589	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1590	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1591	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1592	* @arg @ref LL_TIM_OCMODE_PWM1
		1593	* @arg @ref LL_TIM_OCMODE_PWM2
		1594	* @retval None
		1595	*/
		1596	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
		1597	{
9	mjames	1598	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1599	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1600	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
		1601	}
		1602
		1603	/**
		1604	* @brief Get the output compare mode of an output channel.
		1605	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
		1606	* CCMR1 OC2M LL_TIM_OC_GetMode\n
		1607	* CCMR2 OC3M LL_TIM_OC_GetMode\n
		1608	* CCMR2 OC4M LL_TIM_OC_GetMode
		1609	* @param TIMx Timer instance
		1610	* @param Channel This parameter can be one of the following values:
		1611	* @arg @ref LL_TIM_CHANNEL_CH1
		1612	* @arg @ref LL_TIM_CHANNEL_CH2
		1613	* @arg @ref LL_TIM_CHANNEL_CH3
		1614	* @arg @ref LL_TIM_CHANNEL_CH4
		1615	* @retval Returned value can be one of the following values:
		1616	* @arg @ref LL_TIM_OCMODE_FROZEN
		1617	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1618	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1619	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1620	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1621	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1622	* @arg @ref LL_TIM_OCMODE_PWM1
		1623	* @arg @ref LL_TIM_OCMODE_PWM2
		1624	*/
		1625	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
		1626	{
9	mjames	1627	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1628	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1629	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
		1630	}
		1631
		1632	/**
		1633	* @brief Set the polarity of an output channel.
		1634	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
		1635	* CCER CC1NP LL_TIM_OC_SetPolarity\n
		1636	* CCER CC2P LL_TIM_OC_SetPolarity\n
		1637	* CCER CC2NP LL_TIM_OC_SetPolarity\n
		1638	* CCER CC3P LL_TIM_OC_SetPolarity\n
		1639	* CCER CC3NP LL_TIM_OC_SetPolarity\n
		1640	* CCER CC4P LL_TIM_OC_SetPolarity
		1641	* @param TIMx Timer instance
		1642	* @param Channel This parameter can be one of the following values:
		1643	* @arg @ref LL_TIM_CHANNEL_CH1
		1644	* @arg @ref LL_TIM_CHANNEL_CH1N
		1645	* @arg @ref LL_TIM_CHANNEL_CH2
		1646	* @arg @ref LL_TIM_CHANNEL_CH2N
		1647	* @arg @ref LL_TIM_CHANNEL_CH3
		1648	* @arg @ref LL_TIM_CHANNEL_CH3N
		1649	* @arg @ref LL_TIM_CHANNEL_CH4
		1650	* @param Polarity This parameter can be one of the following values:
		1651	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1652	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1653	* @retval None
		1654	*/
		1655	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
		1656	{
9	mjames	1657	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	1658	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
		1659	}
		1660
		1661	/**
		1662	* @brief Get the polarity of an output channel.
		1663	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
		1664	* CCER CC1NP LL_TIM_OC_GetPolarity\n
		1665	* CCER CC2P LL_TIM_OC_GetPolarity\n
		1666	* CCER CC2NP LL_TIM_OC_GetPolarity\n
		1667	* CCER CC3P LL_TIM_OC_GetPolarity\n
		1668	* CCER CC3NP LL_TIM_OC_GetPolarity\n
		1669	* CCER CC4P LL_TIM_OC_GetPolarity
		1670	* @param TIMx Timer instance
		1671	* @param Channel This parameter can be one of the following values:
		1672	* @arg @ref LL_TIM_CHANNEL_CH1
		1673	* @arg @ref LL_TIM_CHANNEL_CH1N
		1674	* @arg @ref LL_TIM_CHANNEL_CH2
		1675	* @arg @ref LL_TIM_CHANNEL_CH2N
		1676	* @arg @ref LL_TIM_CHANNEL_CH3
		1677	* @arg @ref LL_TIM_CHANNEL_CH3N
		1678	* @arg @ref LL_TIM_CHANNEL_CH4
		1679	* @retval Returned value can be one of the following values:
		1680	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1681	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1682	*/
		1683	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		1684	{
9	mjames	1685	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	1686	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
		1687	}
		1688
		1689	/**
		1690	* @brief Set the IDLE state of an output channel
		1691	* @note This function is significant only for the timer instances
9	mjames	1692	* supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2	mjames	1693	* can be used to check whether or not a timer instance provides
		1694	* a break input.
		1695	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
		1696	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
		1697	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
		1698	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
		1699	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
		1700	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
		1701	* CR2 OIS4 LL_TIM_OC_SetIdleState
		1702	* @param TIMx Timer instance
		1703	* @param Channel This parameter can be one of the following values:
		1704	* @arg @ref LL_TIM_CHANNEL_CH1
		1705	* @arg @ref LL_TIM_CHANNEL_CH1N
		1706	* @arg @ref LL_TIM_CHANNEL_CH2
		1707	* @arg @ref LL_TIM_CHANNEL_CH2N
		1708	* @arg @ref LL_TIM_CHANNEL_CH3
		1709	* @arg @ref LL_TIM_CHANNEL_CH3N
		1710	* @arg @ref LL_TIM_CHANNEL_CH4
		1711	* @param IdleState This parameter can be one of the following values:
		1712	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1713	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1714	* @retval None
		1715	*/
		1716	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
		1717	{
9	mjames	1718	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	1719	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
		1720	}
		1721
		1722	/**
		1723	* @brief Get the IDLE state of an output channel
		1724	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
		1725	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
		1726	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
		1727	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
		1728	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
		1729	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
		1730	* CR2 OIS4 LL_TIM_OC_GetIdleState
		1731	* @param TIMx Timer instance
		1732	* @param Channel This parameter can be one of the following values:
		1733	* @arg @ref LL_TIM_CHANNEL_CH1
		1734	* @arg @ref LL_TIM_CHANNEL_CH1N
		1735	* @arg @ref LL_TIM_CHANNEL_CH2
		1736	* @arg @ref LL_TIM_CHANNEL_CH2N
		1737	* @arg @ref LL_TIM_CHANNEL_CH3
		1738	* @arg @ref LL_TIM_CHANNEL_CH3N
		1739	* @arg @ref LL_TIM_CHANNEL_CH4
		1740	* @retval Returned value can be one of the following values:
		1741	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1742	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1743	*/
		1744	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
		1745	{
9	mjames	1746	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	1747	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
		1748	}
		1749
		1750	/**
		1751	* @brief Enable fast mode for the output channel.
		1752	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
		1753	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
		1754	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
		1755	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
		1756	* CCMR2 OC4FE LL_TIM_OC_EnableFast
		1757	* @param TIMx Timer instance
		1758	* @param Channel This parameter can be one of the following values:
		1759	* @arg @ref LL_TIM_CHANNEL_CH1
		1760	* @arg @ref LL_TIM_CHANNEL_CH2
		1761	* @arg @ref LL_TIM_CHANNEL_CH3
		1762	* @arg @ref LL_TIM_CHANNEL_CH4
		1763	* @retval None
		1764	*/
		1765	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1766	{
9	mjames	1767	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1768	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1769	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1770
		1771	}
		1772
		1773	/**
		1774	* @brief Disable fast mode for the output channel.
		1775	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
		1776	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
		1777	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
		1778	* CCMR2 OC4FE LL_TIM_OC_DisableFast
		1779	* @param TIMx Timer instance
		1780	* @param Channel This parameter can be one of the following values:
		1781	* @arg @ref LL_TIM_CHANNEL_CH1
		1782	* @arg @ref LL_TIM_CHANNEL_CH2
		1783	* @arg @ref LL_TIM_CHANNEL_CH3
		1784	* @arg @ref LL_TIM_CHANNEL_CH4
		1785	* @retval None
		1786	*/
		1787	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1788	{
9	mjames	1789	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1790	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1791	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1792
		1793	}
		1794
		1795	/**
		1796	* @brief Indicates whether fast mode is enabled for the output channel.
		1797	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
		1798	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
		1799	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
		1800	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
		1801	* @param TIMx Timer instance
		1802	* @param Channel This parameter can be one of the following values:
		1803	* @arg @ref LL_TIM_CHANNEL_CH1
		1804	* @arg @ref LL_TIM_CHANNEL_CH2
		1805	* @arg @ref LL_TIM_CHANNEL_CH3
		1806	* @arg @ref LL_TIM_CHANNEL_CH4
		1807	* @retval State of bit (1 or 0).
		1808	*/
		1809	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1810	{
9	mjames	1811	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1812	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1813	uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
		1814	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2	mjames	1815	}
		1816
		1817	/**
		1818	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
		1819	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
		1820	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
		1821	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
		1822	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
		1823	* @param TIMx Timer instance
		1824	* @param Channel This parameter can be one of the following values:
		1825	* @arg @ref LL_TIM_CHANNEL_CH1
		1826	* @arg @ref LL_TIM_CHANNEL_CH2
		1827	* @arg @ref LL_TIM_CHANNEL_CH3
		1828	* @arg @ref LL_TIM_CHANNEL_CH4
		1829	* @retval None
		1830	*/
		1831	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1832	{
9	mjames	1833	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1834	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1835	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1836	}
		1837
		1838	/**
		1839	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
		1840	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
		1841	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
		1842	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
		1843	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
		1844	* @param TIMx Timer instance
		1845	* @param Channel This parameter can be one of the following values:
		1846	* @arg @ref LL_TIM_CHANNEL_CH1
		1847	* @arg @ref LL_TIM_CHANNEL_CH2
		1848	* @arg @ref LL_TIM_CHANNEL_CH3
		1849	* @arg @ref LL_TIM_CHANNEL_CH4
		1850	* @retval None
		1851	*/
		1852	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1853	{
9	mjames	1854	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1855	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1856	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1857	}
		1858
		1859	/**
		1860	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
		1861	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
		1862	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
		1863	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
		1864	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
		1865	* @param TIMx Timer instance
		1866	* @param Channel This parameter can be one of the following values:
		1867	* @arg @ref LL_TIM_CHANNEL_CH1
		1868	* @arg @ref LL_TIM_CHANNEL_CH2
		1869	* @arg @ref LL_TIM_CHANNEL_CH3
		1870	* @arg @ref LL_TIM_CHANNEL_CH4
		1871	* @retval State of bit (1 or 0).
		1872	*/
		1873	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1874	{
9	mjames	1875	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1876	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1877	uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
		1878	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2	mjames	1879	}
		1880
		1881	/**
		1882	* @brief Enable clearing the output channel on an external event.
		1883	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
9	mjames	1884	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2	mjames	1885	* or not a timer instance can clear the OCxREF signal on an external event.
		1886	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
		1887	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
		1888	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
		1889	* CCMR2 OC4CE LL_TIM_OC_EnableClear
		1890	* @param TIMx Timer instance
		1891	* @param Channel This parameter can be one of the following values:
		1892	* @arg @ref LL_TIM_CHANNEL_CH1
		1893	* @arg @ref LL_TIM_CHANNEL_CH2
		1894	* @arg @ref LL_TIM_CHANNEL_CH3
		1895	* @arg @ref LL_TIM_CHANNEL_CH4
		1896	* @retval None
		1897	*/
		1898	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1899	{
9	mjames	1900	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1901	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1902	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1903	}
		1904
		1905	/**
		1906	* @brief Disable clearing the output channel on an external event.
9	mjames	1907	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2	mjames	1908	* or not a timer instance can clear the OCxREF signal on an external event.
		1909	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
		1910	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
		1911	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
		1912	* CCMR2 OC4CE LL_TIM_OC_DisableClear
		1913	* @param TIMx Timer instance
		1914	* @param Channel This parameter can be one of the following values:
		1915	* @arg @ref LL_TIM_CHANNEL_CH1
		1916	* @arg @ref LL_TIM_CHANNEL_CH2
		1917	* @arg @ref LL_TIM_CHANNEL_CH3
		1918	* @arg @ref LL_TIM_CHANNEL_CH4
		1919	* @retval None
		1920	*/
		1921	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1922	{
9	mjames	1923	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1924	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1925	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1926	}
		1927
		1928	/**
		1929	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
		1930	* @note This function enables clearing the output channel on an external event.
		1931	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
9	mjames	1932	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2	mjames	1933	* or not a timer instance can clear the OCxREF signal on an external event.
		1934	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
		1935	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
		1936	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
		1937	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
		1938	* @param TIMx Timer instance
		1939	* @param Channel This parameter can be one of the following values:
		1940	* @arg @ref LL_TIM_CHANNEL_CH1
		1941	* @arg @ref LL_TIM_CHANNEL_CH2
		1942	* @arg @ref LL_TIM_CHANNEL_CH3
		1943	* @arg @ref LL_TIM_CHANNEL_CH4
		1944	* @retval State of bit (1 or 0).
		1945	*/
		1946	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1947	{
9	mjames	1948	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1949	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1950	uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
		1951	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2	mjames	1952	}
		1953
		1954	/**
9	mjames	1955	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
		1956	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	1957	* dead-time insertion feature is supported by a timer instance.
		1958	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
		1959	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
		1960	* @param TIMx Timer instance
		1961	* @param DeadTime between Min_Data=0 and Max_Data=255
		1962	* @retval None
		1963	*/
		1964	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
		1965	{
		1966	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
		1967	}
		1968
		1969	/**
		1970	* @brief Set compare value for output channel 1 (TIMx_CCR1).
9	mjames	1971	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2	mjames	1972	* output channel 1 is supported by a timer instance.
		1973	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
		1974	* @param TIMx Timer instance
		1975	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1976	* @retval None
		1977	*/
		1978	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1979	{
		1980	WRITE_REG(TIMx->CCR1, CompareValue);
		1981	}
		1982
		1983	/**
		1984	* @brief Set compare value for output channel 2 (TIMx_CCR2).
9	mjames	1985	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2	mjames	1986	* output channel 2 is supported by a timer instance.
		1987	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
		1988	* @param TIMx Timer instance
		1989	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1990	* @retval None
		1991	*/
		1992	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1993	{
		1994	WRITE_REG(TIMx->CCR2, CompareValue);
		1995	}
		1996
		1997	/**
		1998	* @brief Set compare value for output channel 3 (TIMx_CCR3).
9	mjames	1999	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2000	* output channel is supported by a timer instance.
		2001	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
		2002	* @param TIMx Timer instance
		2003	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2004	* @retval None
		2005	*/
		2006	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2007	{
		2008	WRITE_REG(TIMx->CCR3, CompareValue);
		2009	}
		2010
		2011	/**
		2012	* @brief Set compare value for output channel 4 (TIMx_CCR4).
9	mjames	2013	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2014	* output channel 4 is supported by a timer instance.
		2015	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
		2016	* @param TIMx Timer instance
		2017	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2018	* @retval None
		2019	*/
		2020	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2021	{
		2022	WRITE_REG(TIMx->CCR4, CompareValue);
		2023	}
		2024
		2025	/**
		2026	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
9	mjames	2027	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2028	* output channel 1 is supported by a timer instance.
		2029	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
		2030	* @param TIMx Timer instance
		2031	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2032	*/
		2033	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
		2034	{
		2035	return (uint32_t)(READ_REG(TIMx->CCR1));
		2036	}
		2037
		2038	/**
		2039	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
9	mjames	2040	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2041	* output channel 2 is supported by a timer instance.
		2042	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
		2043	* @param TIMx Timer instance
		2044	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2045	*/
		2046	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
		2047	{
		2048	return (uint32_t)(READ_REG(TIMx->CCR2));
		2049	}
		2050
		2051	/**
		2052	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
9	mjames	2053	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2054	* output channel 3 is supported by a timer instance.
		2055	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
		2056	* @param TIMx Timer instance
		2057	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2058	*/
		2059	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
		2060	{
		2061	return (uint32_t)(READ_REG(TIMx->CCR3));
		2062	}
		2063
		2064	/**
		2065	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
9	mjames	2066	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2067	* output channel 4 is supported by a timer instance.
		2068	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
		2069	* @param TIMx Timer instance
		2070	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2071	*/
		2072	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
		2073	{
		2074	return (uint32_t)(READ_REG(TIMx->CCR4));
		2075	}
		2076
		2077	/**
		2078	* @}
		2079	*/
		2080
		2081	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
		2082	* @{
		2083	*/
		2084	/**
		2085	* @brief Configure input channel.
		2086	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
		2087	* CCMR1 IC1PSC LL_TIM_IC_Config\n
		2088	* CCMR1 IC1F LL_TIM_IC_Config\n
		2089	* CCMR1 CC2S LL_TIM_IC_Config\n
		2090	* CCMR1 IC2PSC LL_TIM_IC_Config\n
		2091	* CCMR1 IC2F LL_TIM_IC_Config\n
		2092	* CCMR2 CC3S LL_TIM_IC_Config\n
		2093	* CCMR2 IC3PSC LL_TIM_IC_Config\n
		2094	* CCMR2 IC3F LL_TIM_IC_Config\n
		2095	* CCMR2 CC4S LL_TIM_IC_Config\n
		2096	* CCMR2 IC4PSC LL_TIM_IC_Config\n
		2097	* CCMR2 IC4F LL_TIM_IC_Config\n
		2098	* CCER CC1P LL_TIM_IC_Config\n
		2099	* CCER CC1NP LL_TIM_IC_Config\n
		2100	* CCER CC2P LL_TIM_IC_Config\n
		2101	* CCER CC2NP LL_TIM_IC_Config\n
		2102	* CCER CC3P LL_TIM_IC_Config\n
		2103	* CCER CC3NP LL_TIM_IC_Config\n
		2104	* CCER CC4P LL_TIM_IC_Config\n
		2105	* @param TIMx Timer instance
		2106	* @param Channel This parameter can be one of the following values:
		2107	* @arg @ref LL_TIM_CHANNEL_CH1
		2108	* @arg @ref LL_TIM_CHANNEL_CH2
		2109	* @arg @ref LL_TIM_CHANNEL_CH3
		2110	* @arg @ref LL_TIM_CHANNEL_CH4
		2111	* @param Configuration This parameter must be a combination of all the following values:
		2112	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
		2113	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
		2114	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
		2115	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
		2116	* @retval None
		2117	*/
		2118	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		2119	{
9	mjames	2120	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2121	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2122	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
		2123	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
		2124	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2125	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
		2126	}
		2127
		2128	/**
		2129	* @brief Set the active input.
		2130	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
		2131	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
		2132	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
		2133	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
		2134	* @param TIMx Timer instance
		2135	* @param Channel This parameter can be one of the following values:
		2136	* @arg @ref LL_TIM_CHANNEL_CH1
		2137	* @arg @ref LL_TIM_CHANNEL_CH2
		2138	* @arg @ref LL_TIM_CHANNEL_CH3
		2139	* @arg @ref LL_TIM_CHANNEL_CH4
		2140	* @param ICActiveInput This parameter can be one of the following values:
		2141	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2142	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2143	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2144	* @retval None
		2145	*/
		2146	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
		2147	{
9	mjames	2148	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2149	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2150	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2151	}
		2152
		2153	/**
		2154	* @brief Get the current active input.
		2155	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
		2156	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
		2157	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
		2158	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
		2159	* @param TIMx Timer instance
		2160	* @param Channel This parameter can be one of the following values:
		2161	* @arg @ref LL_TIM_CHANNEL_CH1
		2162	* @arg @ref LL_TIM_CHANNEL_CH2
		2163	* @arg @ref LL_TIM_CHANNEL_CH3
		2164	* @arg @ref LL_TIM_CHANNEL_CH4
		2165	* @retval Returned value can be one of the following values:
		2166	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2167	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2168	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2169	*/
		2170	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
		2171	{
9	mjames	2172	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2173	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2174	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2175	}
		2176
		2177	/**
		2178	* @brief Set the prescaler of input channel.
		2179	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
		2180	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
		2181	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
		2182	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
		2183	* @param TIMx Timer instance
		2184	* @param Channel This parameter can be one of the following values:
		2185	* @arg @ref LL_TIM_CHANNEL_CH1
		2186	* @arg @ref LL_TIM_CHANNEL_CH2
		2187	* @arg @ref LL_TIM_CHANNEL_CH3
		2188	* @arg @ref LL_TIM_CHANNEL_CH4
		2189	* @param ICPrescaler This parameter can be one of the following values:
		2190	* @arg @ref LL_TIM_ICPSC_DIV1
		2191	* @arg @ref LL_TIM_ICPSC_DIV2
		2192	* @arg @ref LL_TIM_ICPSC_DIV4
		2193	* @arg @ref LL_TIM_ICPSC_DIV8
		2194	* @retval None
		2195	*/
		2196	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
		2197	{
9	mjames	2198	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2199	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2200	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2201	}
		2202
		2203	/**
		2204	* @brief Get the current prescaler value acting on an input channel.
		2205	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
		2206	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
		2207	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
		2208	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
		2209	* @param TIMx Timer instance
		2210	* @param Channel This parameter can be one of the following values:
		2211	* @arg @ref LL_TIM_CHANNEL_CH1
		2212	* @arg @ref LL_TIM_CHANNEL_CH2
		2213	* @arg @ref LL_TIM_CHANNEL_CH3
		2214	* @arg @ref LL_TIM_CHANNEL_CH4
		2215	* @retval Returned value can be one of the following values:
		2216	* @arg @ref LL_TIM_ICPSC_DIV1
		2217	* @arg @ref LL_TIM_ICPSC_DIV2
		2218	* @arg @ref LL_TIM_ICPSC_DIV4
		2219	* @arg @ref LL_TIM_ICPSC_DIV8
		2220	*/
		2221	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
		2222	{
9	mjames	2223	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2224	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2225	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2226	}
		2227
		2228	/**
		2229	* @brief Set the input filter duration.
		2230	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
		2231	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
		2232	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
		2233	* CCMR2 IC4F LL_TIM_IC_SetFilter
		2234	* @param TIMx Timer instance
		2235	* @param Channel This parameter can be one of the following values:
		2236	* @arg @ref LL_TIM_CHANNEL_CH1
		2237	* @arg @ref LL_TIM_CHANNEL_CH2
		2238	* @arg @ref LL_TIM_CHANNEL_CH3
		2239	* @arg @ref LL_TIM_CHANNEL_CH4
		2240	* @param ICFilter This parameter can be one of the following values:
		2241	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2242	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2243	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2244	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2245	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2246	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2247	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2248	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2249	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2250	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2251	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2252	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2253	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2254	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2255	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2256	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2257	* @retval None
		2258	*/
		2259	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
		2260	{
9	mjames	2261	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2262	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2263	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2264	}
		2265
		2266	/**
		2267	* @brief Get the input filter duration.
		2268	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
		2269	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
		2270	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
		2271	* CCMR2 IC4F LL_TIM_IC_GetFilter
		2272	* @param TIMx Timer instance
		2273	* @param Channel This parameter can be one of the following values:
		2274	* @arg @ref LL_TIM_CHANNEL_CH1
		2275	* @arg @ref LL_TIM_CHANNEL_CH2
		2276	* @arg @ref LL_TIM_CHANNEL_CH3
		2277	* @arg @ref LL_TIM_CHANNEL_CH4
		2278	* @retval Returned value can be one of the following values:
		2279	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2280	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2281	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2282	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2283	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2284	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2285	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2286	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2287	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2288	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2289	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2290	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2291	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2292	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2293	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2294	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2295	*/
		2296	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
		2297	{
9	mjames	2298	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2299	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2300	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2301	}
		2302
		2303	/**
		2304	* @brief Set the input channel polarity.
		2305	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
		2306	* CCER CC1NP LL_TIM_IC_SetPolarity\n
		2307	* CCER CC2P LL_TIM_IC_SetPolarity\n
		2308	* CCER CC2NP LL_TIM_IC_SetPolarity\n
		2309	* CCER CC3P LL_TIM_IC_SetPolarity\n
		2310	* CCER CC3NP LL_TIM_IC_SetPolarity\n
		2311	* CCER CC4P LL_TIM_IC_SetPolarity\n
		2312	* @param TIMx Timer instance
		2313	* @param Channel This parameter can be one of the following values:
		2314	* @arg @ref LL_TIM_CHANNEL_CH1
		2315	* @arg @ref LL_TIM_CHANNEL_CH2
		2316	* @arg @ref LL_TIM_CHANNEL_CH3
		2317	* @arg @ref LL_TIM_CHANNEL_CH4
		2318	* @param ICPolarity This parameter can be one of the following values:
		2319	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2320	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2321	* @retval None
		2322	*/
		2323	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
		2324	{
9	mjames	2325	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	2326	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2327	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
		2328	}
		2329
		2330	/**
		2331	* @brief Get the current input channel polarity.
		2332	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
		2333	* CCER CC1NP LL_TIM_IC_GetPolarity\n
		2334	* CCER CC2P LL_TIM_IC_GetPolarity\n
		2335	* CCER CC2NP LL_TIM_IC_GetPolarity\n
		2336	* CCER CC3P LL_TIM_IC_GetPolarity\n
		2337	* CCER CC3NP LL_TIM_IC_GetPolarity\n
		2338	* CCER CC4P LL_TIM_IC_GetPolarity\n
		2339	* @param TIMx Timer instance
		2340	* @param Channel This parameter can be one of the following values:
		2341	* @arg @ref LL_TIM_CHANNEL_CH1
		2342	* @arg @ref LL_TIM_CHANNEL_CH2
		2343	* @arg @ref LL_TIM_CHANNEL_CH3
		2344	* @arg @ref LL_TIM_CHANNEL_CH4
		2345	* @retval Returned value can be one of the following values:
		2346	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2347	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2348	*/
		2349	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		2350	{
9	mjames	2351	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	2352	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
		2353	SHIFT_TAB_CCxP[iChannel]);
		2354	}
		2355
		2356	/**
		2357	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
9	mjames	2358	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2359	* a timer instance provides an XOR input.
		2360	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
		2361	* @param TIMx Timer instance
		2362	* @retval None
		2363	*/
		2364	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
		2365	{
		2366	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2367	}
		2368
		2369	/**
		2370	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
9	mjames	2371	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2372	* a timer instance provides an XOR input.
		2373	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
		2374	* @param TIMx Timer instance
		2375	* @retval None
		2376	*/
		2377	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
		2378	{
		2379	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2380	}
		2381
		2382	/**
		2383	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
9	mjames	2384	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2385	* a timer instance provides an XOR input.
		2386	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
		2387	* @param TIMx Timer instance
		2388	* @retval State of bit (1 or 0).
		2389	*/
		2390	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
		2391	{
9	mjames	2392	return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2	mjames	2393	}
		2394
		2395	/**
		2396	* @brief Get captured value for input channel 1.
9	mjames	2397	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2398	* input channel 1 is supported by a timer instance.
		2399	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
		2400	* @param TIMx Timer instance
		2401	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2402	*/
		2403	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
		2404	{
		2405	return (uint32_t)(READ_REG(TIMx->CCR1));
		2406	}
		2407
		2408	/**
		2409	* @brief Get captured value for input channel 2.
9	mjames	2410	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2411	* input channel 2 is supported by a timer instance.
		2412	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
		2413	* @param TIMx Timer instance
		2414	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2415	*/
		2416	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
		2417	{
		2418	return (uint32_t)(READ_REG(TIMx->CCR2));
		2419	}
		2420
		2421	/**
		2422	* @brief Get captured value for input channel 3.
9	mjames	2423	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2424	* input channel 3 is supported by a timer instance.
		2425	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
		2426	* @param TIMx Timer instance
		2427	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2428	*/
		2429	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
		2430	{
		2431	return (uint32_t)(READ_REG(TIMx->CCR3));
		2432	}
		2433
		2434	/**
		2435	* @brief Get captured value for input channel 4.
9	mjames	2436	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2437	* input channel 4 is supported by a timer instance.
		2438	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
		2439	* @param TIMx Timer instance
		2440	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2441	*/
		2442	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
		2443	{
		2444	return (uint32_t)(READ_REG(TIMx->CCR4));
		2445	}
		2446
		2447	/**
		2448	* @}
		2449	*/
		2450
		2451	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
		2452	* @{
		2453	*/
		2454	/**
		2455	* @brief Enable external clock mode 2.
		2456	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
9	mjames	2457	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2	mjames	2458	* whether or not a timer instance supports external clock mode2.
		2459	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
		2460	* @param TIMx Timer instance
		2461	* @retval None
		2462	*/
		2463	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
		2464	{
		2465	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2466	}
		2467
		2468	/**
		2469	* @brief Disable external clock mode 2.
9	mjames	2470	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2	mjames	2471	* whether or not a timer instance supports external clock mode2.
		2472	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
		2473	* @param TIMx Timer instance
		2474	* @retval None
		2475	*/
		2476	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
		2477	{
		2478	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2479	}
		2480
		2481	/**
		2482	* @brief Indicate whether external clock mode 2 is enabled.
9	mjames	2483	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2	mjames	2484	* whether or not a timer instance supports external clock mode2.
		2485	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
		2486	* @param TIMx Timer instance
		2487	* @retval State of bit (1 or 0).
		2488	*/
		2489	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
		2490	{
9	mjames	2491	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2	mjames	2492	}
		2493
		2494	/**
		2495	* @brief Set the clock source of the counter clock.
		2496	* @note when selected clock source is external clock mode 1, the timer input
		2497	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
		2498	* function. This timer input must be configured by calling
		2499	* the @ref LL_TIM_IC_Config() function.
9	mjames	2500	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2	mjames	2501	* whether or not a timer instance supports external clock mode1.
9	mjames	2502	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2	mjames	2503	* whether or not a timer instance supports external clock mode2.
		2504	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
		2505	* SMCR ECE LL_TIM_SetClockSource
		2506	* @param TIMx Timer instance
		2507	* @param ClockSource This parameter can be one of the following values:
		2508	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
		2509	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
		2510	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
		2511	* @retval None
		2512	*/
		2513	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
		2514	{
		2515	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
		2516	}
		2517
		2518	/**
		2519	* @brief Set the encoder interface mode.
9	mjames	2520	* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2	mjames	2521	* whether or not a timer instance supports the encoder mode.
		2522	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
		2523	* @param TIMx Timer instance
		2524	* @param EncoderMode This parameter can be one of the following values:
		2525	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
		2526	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
		2527	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
		2528	* @retval None
		2529	*/
		2530	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
		2531	{
		2532	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
		2533	}
		2534
		2535	/**
		2536	* @}
		2537	*/
		2538
		2539	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
		2540	* @{
		2541	*/
		2542	/**
		2543	* @brief Set the trigger output (TRGO) used for timer synchronization .
9	mjames	2544	* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2	mjames	2545	* whether or not a timer instance can operate as a master timer.
		2546	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
		2547	* @param TIMx Timer instance
		2548	* @param TimerSynchronization This parameter can be one of the following values:
		2549	* @arg @ref LL_TIM_TRGO_RESET
		2550	* @arg @ref LL_TIM_TRGO_ENABLE
		2551	* @arg @ref LL_TIM_TRGO_UPDATE
		2552	* @arg @ref LL_TIM_TRGO_CC1IF
		2553	* @arg @ref LL_TIM_TRGO_OC1REF
		2554	* @arg @ref LL_TIM_TRGO_OC2REF
		2555	* @arg @ref LL_TIM_TRGO_OC3REF
		2556	* @arg @ref LL_TIM_TRGO_OC4REF
		2557	* @retval None
		2558	*/
		2559	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
		2560	{
		2561	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
		2562	}
		2563
		2564	/**
		2565	* @brief Set the synchronization mode of a slave timer.
9	mjames	2566	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2567	* a timer instance can operate as a slave timer.
		2568	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
		2569	* @param TIMx Timer instance
		2570	* @param SlaveMode This parameter can be one of the following values:
		2571	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
		2572	* @arg @ref LL_TIM_SLAVEMODE_RESET
		2573	* @arg @ref LL_TIM_SLAVEMODE_GATED
		2574	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
		2575	* @retval None
		2576	*/
		2577	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
		2578	{
		2579	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
		2580	}
		2581
		2582	/**
		2583	* @brief Set the selects the trigger input to be used to synchronize the counter.
9	mjames	2584	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2585	* a timer instance can operate as a slave timer.
		2586	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
		2587	* @param TIMx Timer instance
		2588	* @param TriggerInput This parameter can be one of the following values:
		2589	* @arg @ref LL_TIM_TS_ITR0
		2590	* @arg @ref LL_TIM_TS_ITR1
		2591	* @arg @ref LL_TIM_TS_ITR2
		2592	* @arg @ref LL_TIM_TS_ITR3
		2593	* @arg @ref LL_TIM_TS_TI1F_ED
		2594	* @arg @ref LL_TIM_TS_TI1FP1
		2595	* @arg @ref LL_TIM_TS_TI2FP2
		2596	* @arg @ref LL_TIM_TS_ETRF
		2597	* @retval None
		2598	*/
		2599	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
		2600	{
		2601	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
		2602	}
		2603
		2604	/**
		2605	* @brief Enable the Master/Slave mode.
9	mjames	2606	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2607	* a timer instance can operate as a slave timer.
		2608	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
		2609	* @param TIMx Timer instance
		2610	* @retval None
		2611	*/
		2612	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
		2613	{
		2614	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2615	}
		2616
		2617	/**
		2618	* @brief Disable the Master/Slave mode.
9	mjames	2619	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2620	* a timer instance can operate as a slave timer.
		2621	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
		2622	* @param TIMx Timer instance
		2623	* @retval None
		2624	*/
		2625	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
		2626	{
		2627	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2628	}
		2629
		2630	/**
		2631	* @brief Indicates whether the Master/Slave mode is enabled.
9	mjames	2632	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2633	* a timer instance can operate as a slave timer.
		2634	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
		2635	* @param TIMx Timer instance
		2636	* @retval State of bit (1 or 0).
		2637	*/
		2638	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
		2639	{
9	mjames	2640	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2	mjames	2641	}
		2642
		2643	/**
		2644	* @brief Configure the external trigger (ETR) input.
9	mjames	2645	* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2646	* a timer instance provides an external trigger input.
		2647	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
		2648	* SMCR ETPS LL_TIM_ConfigETR\n
		2649	* SMCR ETF LL_TIM_ConfigETR
		2650	* @param TIMx Timer instance
		2651	* @param ETRPolarity This parameter can be one of the following values:
		2652	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
		2653	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
		2654	* @param ETRPrescaler This parameter can be one of the following values:
		2655	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
		2656	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
		2657	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
		2658	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
		2659	* @param ETRFilter This parameter can be one of the following values:
		2660	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
		2661	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
		2662	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
		2663	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
		2664	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
		2665	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
		2666	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
		2667	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
		2668	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
		2669	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
		2670	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
		2671	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
		2672	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
		2673	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
		2674	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
		2675	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
		2676	* @retval None
		2677	*/
		2678	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
		2679	uint32_t ETRFilter)
		2680	{
		2681	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
		2682	}
		2683
		2684	/**
		2685	* @}
		2686	*/
		2687
		2688	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
		2689	* @{
		2690	*/
		2691	/**
		2692	* @brief Enable the break function.
9	mjames	2693	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2694	* a timer instance provides a break input.
		2695	* @rmtoll BDTR BKE LL_TIM_EnableBRK
		2696	* @param TIMx Timer instance
		2697	* @retval None
		2698	*/
		2699	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
		2700	{
9	mjames	2701	__IO uint32_t tmpreg;
2	mjames	2702	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
9	mjames	2703	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
		2704	tmpreg = READ_REG(TIMx->BDTR);
		2705	(void)(tmpreg);
2	mjames	2706	}
		2707
		2708	/**
		2709	* @brief Disable the break function.
		2710	* @rmtoll BDTR BKE LL_TIM_DisableBRK
		2711	* @param TIMx Timer instance
9	mjames	2712	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2713	* a timer instance provides a break input.
		2714	* @retval None
		2715	*/
		2716	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
		2717	{
9	mjames	2718	__IO uint32_t tmpreg;
2	mjames	2719	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
9	mjames	2720	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
		2721	tmpreg = READ_REG(TIMx->BDTR);
		2722	(void)(tmpreg);
2	mjames	2723	}
		2724
		2725	/**
		2726	* @brief Configure the break input.
9	mjames	2727	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2728	* a timer instance provides a break input.
		2729	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
		2730	* @param TIMx Timer instance
		2731	* @param BreakPolarity This parameter can be one of the following values:
		2732	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
		2733	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
		2734	* @retval None
		2735	*/
		2736	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
		2737	{
9	mjames	2738	__IO uint32_t tmpreg;
2	mjames	2739	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
9	mjames	2740	/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
		2741	tmpreg = READ_REG(TIMx->BDTR);
		2742	(void)(tmpreg);
2	mjames	2743	}
		2744
		2745	/**
		2746	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
9	mjames	2747	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2748	* a timer instance provides a break input.
		2749	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
		2750	* BDTR OSSR LL_TIM_SetOffStates
		2751	* @param TIMx Timer instance
		2752	* @param OffStateIdle This parameter can be one of the following values:
		2753	* @arg @ref LL_TIM_OSSI_DISABLE
		2754	* @arg @ref LL_TIM_OSSI_ENABLE
		2755	* @param OffStateRun This parameter can be one of the following values:
		2756	* @arg @ref LL_TIM_OSSR_DISABLE
		2757	* @arg @ref LL_TIM_OSSR_ENABLE
		2758	* @retval None
		2759	*/
		2760	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
		2761	{
		2762	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
		2763	}
		2764
		2765	/**
		2766	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
9	mjames	2767	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2768	* a timer instance provides a break input.
		2769	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
		2770	* @param TIMx Timer instance
		2771	* @retval None
		2772	*/
		2773	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
		2774	{
		2775	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2776	}
		2777
		2778	/**
		2779	* @brief Disable automatic output (MOE can be set only by software).
9	mjames	2780	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2781	* a timer instance provides a break input.
		2782	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
		2783	* @param TIMx Timer instance
		2784	* @retval None
		2785	*/
		2786	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
		2787	{
		2788	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2789	}
		2790
		2791	/**
		2792	* @brief Indicate whether automatic output is enabled.
9	mjames	2793	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2794	* a timer instance provides a break input.
		2795	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
		2796	* @param TIMx Timer instance
		2797	* @retval State of bit (1 or 0).
		2798	*/
		2799	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
		2800	{
9	mjames	2801	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
2	mjames	2802	}
		2803
		2804	/**
		2805	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
		2806	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2807	* software and is reset in case of break or break2 event
9	mjames	2808	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2809	* a timer instance provides a break input.
		2810	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
		2811	* @param TIMx Timer instance
		2812	* @retval None
		2813	*/
		2814	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
		2815	{
		2816	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2817	}
		2818
		2819	/**
		2820	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
		2821	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2822	* software and is reset in case of break or break2 event.
9	mjames	2823	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2824	* a timer instance provides a break input.
		2825	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
		2826	* @param TIMx Timer instance
		2827	* @retval None
		2828	*/
		2829	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
		2830	{
		2831	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2832	}
		2833
		2834	/**
		2835	* @brief Indicates whether outputs are enabled.
9	mjames	2836	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2	mjames	2837	* a timer instance provides a break input.
		2838	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
		2839	* @param TIMx Timer instance
		2840	* @retval State of bit (1 or 0).
		2841	*/
		2842	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
		2843	{
9	mjames	2844	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
2	mjames	2845	}
		2846
		2847	/**
		2848	* @}
		2849	*/
		2850
		2851	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
		2852	* @{
		2853	*/
		2854	/**
		2855	* @brief Configures the timer DMA burst feature.
9	mjames	2856	* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
2	mjames	2857	* not a timer instance supports the DMA burst mode.
		2858	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
		2859	* DCR DBA LL_TIM_ConfigDMABurst
		2860	* @param TIMx Timer instance
		2861	* @param DMABurstBaseAddress This parameter can be one of the following values:
		2862	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
		2863	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
		2864	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
		2865	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
		2866	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
		2867	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
		2868	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
		2869	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
		2870	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
		2871	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
		2872	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
		2873	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
		2874	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
		2875	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
		2876	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
		2877	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
		2878	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
		2879	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
		2880	* @param DMABurstLength This parameter can be one of the following values:
		2881	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
		2882	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
		2883	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
		2884	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
		2885	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
		2886	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
		2887	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
		2888	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
		2889	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
		2890	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
		2891	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
		2892	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
		2893	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
		2894	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
		2895	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
		2896	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
		2897	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
		2898	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
		2899	* @retval None
		2900	*/
		2901	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
		2902	{
9	mjames	2903	MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL \| TIM_DCR_DBA), (DMABurstBaseAddress \| DMABurstLength));
2	mjames	2904	}
		2905
		2906	/**
		2907	* @}
		2908	*/
		2909
		2910
		2911	/**
		2912	* @}
		2913	*/
		2914
		2915	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
		2916	* @{
		2917	*/
		2918	/**
		2919	* @brief Clear the update interrupt flag (UIF).
		2920	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
		2921	* @param TIMx Timer instance
		2922	* @retval None
		2923	*/
		2924	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
		2925	{
		2926	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
		2927	}
		2928
		2929	/**
		2930	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
		2931	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
		2932	* @param TIMx Timer instance
		2933	* @retval State of bit (1 or 0).
		2934	*/
		2935	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
		2936	{
9	mjames	2937	return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
2	mjames	2938	}
		2939
		2940	/**
		2941	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
		2942	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
		2943	* @param TIMx Timer instance
		2944	* @retval None
		2945	*/
		2946	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
		2947	{
		2948	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
		2949	}
		2950
		2951	/**
		2952	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
		2953	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
		2954	* @param TIMx Timer instance
		2955	* @retval State of bit (1 or 0).
		2956	*/
		2957	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
		2958	{
9	mjames	2959	return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
2	mjames	2960	}
		2961
		2962	/**
		2963	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
		2964	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
		2965	* @param TIMx Timer instance
		2966	* @retval None
		2967	*/
		2968	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
		2969	{
		2970	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
		2971	}
		2972
		2973	/**
		2974	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
		2975	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
		2976	* @param TIMx Timer instance
		2977	* @retval State of bit (1 or 0).
		2978	*/
		2979	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
		2980	{
9	mjames	2981	return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
2	mjames	2982	}
		2983
		2984	/**
		2985	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
		2986	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
		2987	* @param TIMx Timer instance
		2988	* @retval None
		2989	*/
		2990	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
		2991	{
		2992	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
		2993	}
		2994
		2995	/**
		2996	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
		2997	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
		2998	* @param TIMx Timer instance
		2999	* @retval State of bit (1 or 0).
		3000	*/
		3001	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
		3002	{
9	mjames	3003	return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
2	mjames	3004	}
		3005
		3006	/**
		3007	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
		3008	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
		3009	* @param TIMx Timer instance
		3010	* @retval None
		3011	*/
		3012	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
		3013	{
		3014	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
		3015	}
		3016
		3017	/**
		3018	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
		3019	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
		3020	* @param TIMx Timer instance
		3021	* @retval State of bit (1 or 0).
		3022	*/
		3023	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
		3024	{
9	mjames	3025	return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
2	mjames	3026	}
		3027
		3028	/**
		3029	* @brief Clear the commutation interrupt flag (COMIF).
		3030	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
		3031	* @param TIMx Timer instance
		3032	* @retval None
		3033	*/
		3034	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
		3035	{
		3036	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
		3037	}
		3038
		3039	/**
		3040	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
		3041	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
		3042	* @param TIMx Timer instance
		3043	* @retval State of bit (1 or 0).
		3044	*/
		3045	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
		3046	{
9	mjames	3047	return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
2	mjames	3048	}
		3049
		3050	/**
		3051	* @brief Clear the trigger interrupt flag (TIF).
		3052	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
		3053	* @param TIMx Timer instance
		3054	* @retval None
		3055	*/
		3056	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
		3057	{
		3058	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
		3059	}
		3060
		3061	/**
		3062	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
		3063	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
		3064	* @param TIMx Timer instance
		3065	* @retval State of bit (1 or 0).
		3066	*/
		3067	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
		3068	{
9	mjames	3069	return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
2	mjames	3070	}
		3071
		3072	/**
		3073	* @brief Clear the break interrupt flag (BIF).
		3074	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
		3075	* @param TIMx Timer instance
		3076	* @retval None
		3077	*/
		3078	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
		3079	{
		3080	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
		3081	}
		3082
		3083	/**
		3084	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
		3085	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
		3086	* @param TIMx Timer instance
		3087	* @retval State of bit (1 or 0).
		3088	*/
		3089	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
		3090	{
9	mjames	3091	return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
2	mjames	3092	}
		3093
		3094	/**
		3095	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
		3096	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
		3097	* @param TIMx Timer instance
		3098	* @retval None
		3099	*/
		3100	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
		3101	{
		3102	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
		3103	}
		3104
		3105	/**
		3106	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
		3107	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
		3108	* @param TIMx Timer instance
		3109	* @retval State of bit (1 or 0).
		3110	*/
		3111	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
		3112	{
9	mjames	3113	return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
2	mjames	3114	}
		3115
		3116	/**
		3117	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
		3118	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
		3119	* @param TIMx Timer instance
		3120	* @retval None
		3121	*/
		3122	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
		3123	{
		3124	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
		3125	}
		3126
		3127	/**
		3128	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
		3129	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
		3130	* @param TIMx Timer instance
		3131	* @retval State of bit (1 or 0).
		3132	*/
		3133	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
		3134	{
9	mjames	3135	return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
2	mjames	3136	}
		3137
		3138	/**
		3139	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
		3140	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
		3141	* @param TIMx Timer instance
		3142	* @retval None
		3143	*/
		3144	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
		3145	{
		3146	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
		3147	}
		3148
		3149	/**
		3150	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
		3151	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
		3152	* @param TIMx Timer instance
		3153	* @retval State of bit (1 or 0).
		3154	*/
		3155	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
		3156	{
9	mjames	3157	return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
2	mjames	3158	}
		3159
		3160	/**
		3161	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
		3162	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
		3163	* @param TIMx Timer instance
		3164	* @retval None
		3165	*/
		3166	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
		3167	{
		3168	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
		3169	}
		3170
		3171	/**
		3172	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
		3173	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
		3174	* @param TIMx Timer instance
		3175	* @retval State of bit (1 or 0).
		3176	*/
		3177	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
		3178	{
9	mjames	3179	return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
2	mjames	3180	}
		3181
		3182	/**
		3183	* @}
		3184	*/
		3185
		3186	/** @defgroup TIM_LL_EF_IT_Management IT-Management
		3187	* @{
		3188	*/
		3189	/**
		3190	* @brief Enable update interrupt (UIE).
		3191	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
		3192	* @param TIMx Timer instance
		3193	* @retval None
		3194	*/
		3195	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
		3196	{
		3197	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
		3198	}
		3199
		3200	/**
		3201	* @brief Disable update interrupt (UIE).
		3202	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
		3203	* @param TIMx Timer instance
		3204	* @retval None
		3205	*/
		3206	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
		3207	{
		3208	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
		3209	}
		3210
		3211	/**
		3212	* @brief Indicates whether the update interrupt (UIE) is enabled.
		3213	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
		3214	* @param TIMx Timer instance
		3215	* @retval State of bit (1 or 0).
		3216	*/
		3217	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
		3218	{
9	mjames	3219	return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
2	mjames	3220	}
		3221
		3222	/**
		3223	* @brief Enable capture/compare 1 interrupt (CC1IE).
		3224	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
		3225	* @param TIMx Timer instance
		3226	* @retval None
		3227	*/
		3228	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
		3229	{
		3230	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3231	}
		3232
		3233	/**
		3234	* @brief Disable capture/compare 1 interrupt (CC1IE).
		3235	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
		3236	* @param TIMx Timer instance
		3237	* @retval None
		3238	*/
		3239	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
		3240	{
		3241	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3242	}
		3243
		3244	/**
		3245	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
		3246	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
		3247	* @param TIMx Timer instance
		3248	* @retval State of bit (1 or 0).
		3249	*/
		3250	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
		3251	{
9	mjames	3252	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
2	mjames	3253	}
		3254
		3255	/**
		3256	* @brief Enable capture/compare 2 interrupt (CC2IE).
		3257	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
		3258	* @param TIMx Timer instance
		3259	* @retval None
		3260	*/
		3261	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
		3262	{
		3263	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3264	}
		3265
		3266	/**
		3267	* @brief Disable capture/compare 2 interrupt (CC2IE).
		3268	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
		3269	* @param TIMx Timer instance
		3270	* @retval None
		3271	*/
		3272	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
		3273	{
		3274	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3275	}
		3276
		3277	/**
		3278	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
		3279	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
		3280	* @param TIMx Timer instance
		3281	* @retval State of bit (1 or 0).
		3282	*/
		3283	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
		3284	{
9	mjames	3285	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
2	mjames	3286	}
		3287
		3288	/**
		3289	* @brief Enable capture/compare 3 interrupt (CC3IE).
		3290	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
		3291	* @param TIMx Timer instance
		3292	* @retval None
		3293	*/
		3294	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
		3295	{
		3296	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3297	}
		3298
		3299	/**
		3300	* @brief Disable capture/compare 3 interrupt (CC3IE).
		3301	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
		3302	* @param TIMx Timer instance
		3303	* @retval None
		3304	*/
		3305	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
		3306	{
		3307	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3308	}
		3309
		3310	/**
		3311	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
		3312	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
		3313	* @param TIMx Timer instance
		3314	* @retval State of bit (1 or 0).
		3315	*/
		3316	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
		3317	{
9	mjames	3318	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
2	mjames	3319	}
		3320
		3321	/**
		3322	* @brief Enable capture/compare 4 interrupt (CC4IE).
		3323	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
		3324	* @param TIMx Timer instance
		3325	* @retval None
		3326	*/
		3327	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
		3328	{
		3329	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3330	}
		3331
		3332	/**
		3333	* @brief Disable capture/compare 4 interrupt (CC4IE).
		3334	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
		3335	* @param TIMx Timer instance
		3336	* @retval None
		3337	*/
		3338	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
		3339	{
		3340	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3341	}
		3342
		3343	/**
		3344	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
		3345	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
		3346	* @param TIMx Timer instance
		3347	* @retval State of bit (1 or 0).
		3348	*/
		3349	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
		3350	{
9	mjames	3351	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
2	mjames	3352	}
		3353
		3354	/**
		3355	* @brief Enable commutation interrupt (COMIE).
		3356	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
		3357	* @param TIMx Timer instance
		3358	* @retval None
		3359	*/
		3360	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
		3361	{
		3362	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3363	}
		3364
		3365	/**
		3366	* @brief Disable commutation interrupt (COMIE).
		3367	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
		3368	* @param TIMx Timer instance
		3369	* @retval None
		3370	*/
		3371	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
		3372	{
		3373	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3374	}
		3375
		3376	/**
		3377	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
		3378	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
		3379	* @param TIMx Timer instance
		3380	* @retval State of bit (1 or 0).
		3381	*/
		3382	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
		3383	{
9	mjames	3384	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
2	mjames	3385	}
		3386
		3387	/**
		3388	* @brief Enable trigger interrupt (TIE).
		3389	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
		3390	* @param TIMx Timer instance
		3391	* @retval None
		3392	*/
		3393	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
		3394	{
		3395	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
		3396	}
		3397
		3398	/**
		3399	* @brief Disable trigger interrupt (TIE).
		3400	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
		3401	* @param TIMx Timer instance
		3402	* @retval None
		3403	*/
		3404	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
		3405	{
		3406	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
		3407	}
		3408
		3409	/**
		3410	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
		3411	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
		3412	* @param TIMx Timer instance
		3413	* @retval State of bit (1 or 0).
		3414	*/
		3415	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
		3416	{
9	mjames	3417	return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
2	mjames	3418	}
		3419
		3420	/**
		3421	* @brief Enable break interrupt (BIE).
		3422	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
		3423	* @param TIMx Timer instance
		3424	* @retval None
		3425	*/
		3426	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
		3427	{
		3428	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
		3429	}
		3430
		3431	/**
		3432	* @brief Disable break interrupt (BIE).
		3433	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
		3434	* @param TIMx Timer instance
		3435	* @retval None
		3436	*/
		3437	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
		3438	{
		3439	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
		3440	}
		3441
		3442	/**
		3443	* @brief Indicates whether the break interrupt (BIE) is enabled.
		3444	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
		3445	* @param TIMx Timer instance
		3446	* @retval State of bit (1 or 0).
		3447	*/
		3448	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
		3449	{
9	mjames	3450	return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
2	mjames	3451	}
		3452
		3453	/**
		3454	* @}
		3455	*/
		3456
		3457	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
		3458	* @{
		3459	*/
		3460	/**
		3461	* @brief Enable update DMA request (UDE).
		3462	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
		3463	* @param TIMx Timer instance
		3464	* @retval None
		3465	*/
		3466	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3467	{
		3468	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
		3469	}
		3470
		3471	/**
		3472	* @brief Disable update DMA request (UDE).
		3473	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
		3474	* @param TIMx Timer instance
		3475	* @retval None
		3476	*/
		3477	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3478	{
		3479	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
		3480	}
		3481
		3482	/**
		3483	* @brief Indicates whether the update DMA request (UDE) is enabled.
		3484	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
		3485	* @param TIMx Timer instance
		3486	* @retval State of bit (1 or 0).
		3487	*/
		3488	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3489	{
9	mjames	3490	return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
2	mjames	3491	}
		3492
		3493	/**
		3494	* @brief Enable capture/compare 1 DMA request (CC1DE).
		3495	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
		3496	* @param TIMx Timer instance
		3497	* @retval None
		3498	*/
		3499	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
		3500	{
		3501	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3502	}
		3503
		3504	/**
		3505	* @brief Disable capture/compare 1 DMA request (CC1DE).
		3506	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
		3507	* @param TIMx Timer instance
		3508	* @retval None
		3509	*/
		3510	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
		3511	{
		3512	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3513	}
		3514
		3515	/**
		3516	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
		3517	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
		3518	* @param TIMx Timer instance
		3519	* @retval State of bit (1 or 0).
		3520	*/
		3521	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
		3522	{
9	mjames	3523	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
2	mjames	3524	}
		3525
		3526	/**
		3527	* @brief Enable capture/compare 2 DMA request (CC2DE).
		3528	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
		3529	* @param TIMx Timer instance
		3530	* @retval None
		3531	*/
		3532	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
		3533	{
		3534	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3535	}
		3536
		3537	/**
		3538	* @brief Disable capture/compare 2 DMA request (CC2DE).
		3539	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
		3540	* @param TIMx Timer instance
		3541	* @retval None
		3542	*/
		3543	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
		3544	{
		3545	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3546	}
		3547
		3548	/**
		3549	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
		3550	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
		3551	* @param TIMx Timer instance
		3552	* @retval State of bit (1 or 0).
		3553	*/
		3554	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
		3555	{
9	mjames	3556	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
2	mjames	3557	}
		3558
		3559	/**
		3560	* @brief Enable capture/compare 3 DMA request (CC3DE).
		3561	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
		3562	* @param TIMx Timer instance
		3563	* @retval None
		3564	*/
		3565	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
		3566	{
		3567	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3568	}
		3569
		3570	/**
		3571	* @brief Disable capture/compare 3 DMA request (CC3DE).
		3572	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
		3573	* @param TIMx Timer instance
		3574	* @retval None
		3575	*/
		3576	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
		3577	{
		3578	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3579	}
		3580
		3581	/**
		3582	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
		3583	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
		3584	* @param TIMx Timer instance
		3585	* @retval State of bit (1 or 0).
		3586	*/
		3587	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
		3588	{
9	mjames	3589	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
2	mjames	3590	}
		3591
		3592	/**
		3593	* @brief Enable capture/compare 4 DMA request (CC4DE).
		3594	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
		3595	* @param TIMx Timer instance
		3596	* @retval None
		3597	*/
		3598	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
		3599	{
		3600	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3601	}
		3602
		3603	/**
		3604	* @brief Disable capture/compare 4 DMA request (CC4DE).
		3605	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
		3606	* @param TIMx Timer instance
		3607	* @retval None
		3608	*/
		3609	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
		3610	{
		3611	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3612	}
		3613
		3614	/**
		3615	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
		3616	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
		3617	* @param TIMx Timer instance
		3618	* @retval State of bit (1 or 0).
		3619	*/
		3620	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
		3621	{
9	mjames	3622	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
2	mjames	3623	}
		3624
		3625	/**
		3626	* @brief Enable commutation DMA request (COMDE).
		3627	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
		3628	* @param TIMx Timer instance
		3629	* @retval None
		3630	*/
		3631	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
		3632	{
		3633	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3634	}
		3635
		3636	/**
		3637	* @brief Disable commutation DMA request (COMDE).
		3638	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
		3639	* @param TIMx Timer instance
		3640	* @retval None
		3641	*/
		3642	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
		3643	{
		3644	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3645	}
		3646
		3647	/**
		3648	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
		3649	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
		3650	* @param TIMx Timer instance
		3651	* @retval State of bit (1 or 0).
		3652	*/
		3653	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
		3654	{
9	mjames	3655	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
2	mjames	3656	}
		3657
		3658	/**
		3659	* @brief Enable trigger interrupt (TDE).
		3660	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
		3661	* @param TIMx Timer instance
		3662	* @retval None
		3663	*/
		3664	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3665	{
		3666	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
		3667	}
		3668
		3669	/**
		3670	* @brief Disable trigger interrupt (TDE).
		3671	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
		3672	* @param TIMx Timer instance
		3673	* @retval None
		3674	*/
		3675	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3676	{
		3677	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
		3678	}
		3679
		3680	/**
		3681	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
		3682	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
		3683	* @param TIMx Timer instance
		3684	* @retval State of bit (1 or 0).
		3685	*/
		3686	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
		3687	{
9	mjames	3688	return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
2	mjames	3689	}
		3690
		3691	/**
		3692	* @}
		3693	*/
		3694
		3695	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
		3696	* @{
		3697	*/
		3698	/**
		3699	* @brief Generate an update event.
		3700	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
		3701	* @param TIMx Timer instance
		3702	* @retval None
		3703	*/
		3704	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
		3705	{
		3706	SET_BIT(TIMx->EGR, TIM_EGR_UG);
		3707	}
		3708
		3709	/**
		3710	* @brief Generate Capture/Compare 1 event.
		3711	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
		3712	* @param TIMx Timer instance
		3713	* @retval None
		3714	*/
		3715	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
		3716	{
		3717	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
		3718	}
		3719
		3720	/**
		3721	* @brief Generate Capture/Compare 2 event.
		3722	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
		3723	* @param TIMx Timer instance
		3724	* @retval None
		3725	*/
		3726	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
		3727	{
		3728	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
		3729	}
		3730
		3731	/**
		3732	* @brief Generate Capture/Compare 3 event.
		3733	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
		3734	* @param TIMx Timer instance
		3735	* @retval None
		3736	*/
		3737	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
		3738	{
		3739	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
		3740	}
		3741
		3742	/**
		3743	* @brief Generate Capture/Compare 4 event.
		3744	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
		3745	* @param TIMx Timer instance
		3746	* @retval None
		3747	*/
		3748	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
		3749	{
		3750	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
		3751	}
		3752
		3753	/**
		3754	* @brief Generate commutation event.
		3755	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
		3756	* @param TIMx Timer instance
		3757	* @retval None
		3758	*/
		3759	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
		3760	{
		3761	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
		3762	}
		3763
		3764	/**
		3765	* @brief Generate trigger event.
		3766	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
		3767	* @param TIMx Timer instance
		3768	* @retval None
		3769	*/
		3770	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
		3771	{
		3772	SET_BIT(TIMx->EGR, TIM_EGR_TG);
		3773	}
		3774
		3775	/**
		3776	* @brief Generate break event.
		3777	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
		3778	* @param TIMx Timer instance
		3779	* @retval None
		3780	*/
		3781	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
		3782	{
		3783	SET_BIT(TIMx->EGR, TIM_EGR_BG);
		3784	}
		3785
		3786	/**
		3787	* @}
		3788	*/
		3789
		3790	#if defined(USE_FULL_LL_DRIVER)
		3791	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
		3792	* @{
		3793	*/
		3794
		3795	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
		3796	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
		3797	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
		3798	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
		3799	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
		3800	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
		3801	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
		3802	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
		3803	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
		3804	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
		3805	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
		3806	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
		3807	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
		3808	/**
		3809	* @}
		3810	*/
		3811	#endif /* USE_FULL_LL_DRIVER */
		3812
		3813	/**
		3814	* @}
		3815	*/
		3816
		3817	/**
		3818	* @}
		3819	*/
		3820
		3821	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 */
		3822
		3823	/**
		3824	* @}
		3825	*/
		3826
		3827	#ifdef __cplusplus
		3828	}
		3829	#endif
		3830
		3831	#endif /* __STM32F1xx_LL_TIM_H */
		3832	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h – Rev 9