Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
||
| 3 | * @file stm32f1xx_ll_system.h |
||
| 4 | * @author MCD Application Team |
||
| 5 | * @brief Header file of SYSTEM LL module. |
||
| 6 | * |
||
| 7 | ****************************************************************************** |
||
| 8 | * @attention |
||
| 9 | * |
||
| 10 | * Copyright (c) 2016 STMicroelectronics. |
||
| 11 | * All rights reserved. |
||
| 12 | * |
||
| 13 | * This software is licensed under terms that can be found in the LICENSE file |
||
| 14 | * in the root directory of this software component. |
||
| 15 | * If no LICENSE file comes with this software, it is provided AS-IS. |
||
| 16 | * |
||
| 17 | ****************************************************************************** |
||
| 18 | @verbatim |
||
| 19 | ============================================================================== |
||
| 20 | ##### How to use this driver ##### |
||
| 21 | ============================================================================== |
||
| 22 | [..] |
||
| 23 | The LL SYSTEM driver contains a set of generic APIs that can be |
||
| 24 | used by user: |
||
| 25 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
||
| 26 | (+) Access to DBGCMU registers |
||
| 27 | (+) Access to SYSCFG registers |
||
| 28 | |||
| 29 | @endverbatim |
||
| 30 | ****************************************************************************** |
||
| 31 | */ |
||
| 32 | |||
| 33 | /* Define to prevent recursive inclusion -------------------------------------*/ |
||
| 34 | #ifndef __STM32F1xx_LL_SYSTEM_H |
||
| 35 | #define __STM32F1xx_LL_SYSTEM_H |
||
| 36 | |||
| 37 | #ifdef __cplusplus |
||
| 38 | extern "C" { |
||
| 39 | #endif |
||
| 40 | |||
| 41 | /* Includes ------------------------------------------------------------------*/ |
||
| 42 | #include "stm32f1xx.h" |
||
| 43 | |||
| 44 | /** @addtogroup STM32F1xx_LL_Driver |
||
| 45 | * @{ |
||
| 46 | */ |
||
| 47 | |||
| 48 | #if defined (FLASH) || defined (DBGMCU) |
||
| 49 | |||
| 50 | /** @defgroup SYSTEM_LL SYSTEM |
||
| 51 | * @{ |
||
| 52 | */ |
||
| 53 | |||
| 54 | /* Private types -------------------------------------------------------------*/ |
||
| 55 | /* Private variables ---------------------------------------------------------*/ |
||
| 56 | |||
| 57 | /* Private constants ---------------------------------------------------------*/ |
||
| 58 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
||
| 59 | * @{ |
||
| 60 | */ |
||
| 61 | |||
| 62 | /** |
||
| 63 | * @} |
||
| 64 | */ |
||
| 65 | |||
| 66 | /* Private macros ------------------------------------------------------------*/ |
||
| 67 | |||
| 68 | /* Exported types ------------------------------------------------------------*/ |
||
| 69 | /* Exported constants --------------------------------------------------------*/ |
||
| 70 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
||
| 71 | * @{ |
||
| 72 | */ |
||
| 73 | |||
| 74 | |||
| 75 | |||
| 76 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
||
| 77 | * @{ |
||
| 78 | */ |
||
| 79 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
||
| 80 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
||
| 81 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
||
| 82 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
||
| 83 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
||
| 84 | /** |
||
| 85 | * @} |
||
| 86 | */ |
||
| 87 | |||
| 88 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
||
| 89 | * @{ |
||
| 90 | */ |
||
| 91 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ |
||
| 92 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ |
||
| 93 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ |
||
| 94 | #if defined(DBGMCU_CR_DBG_TIM5_STOP) |
||
| 95 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ |
||
| 96 | #endif /* DBGMCU_CR_DBG_TIM5_STOP */ |
||
| 97 | #if defined(DBGMCU_CR_DBG_TIM6_STOP) |
||
| 98 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ |
||
| 99 | #endif /* DBGMCU_CR_DBG_TIM6_STOP */ |
||
| 100 | #if defined(DBGMCU_CR_DBG_TIM7_STOP) |
||
| 101 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ |
||
| 102 | #endif /* DBGMCU_CR_DBG_TIM7_STOP */ |
||
| 103 | #if defined(DBGMCU_CR_DBG_TIM12_STOP) |
||
| 104 | #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ |
||
| 105 | #endif /* DBGMCU_CR_DBG_TIM12_STOP */ |
||
| 106 | #if defined(DBGMCU_CR_DBG_TIM13_STOP) |
||
| 107 | #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ |
||
| 108 | #endif /* DBGMCU_CR_DBG_TIM13_STOP */ |
||
| 109 | #if defined(DBGMCU_CR_DBG_TIM14_STOP) |
||
| 110 | #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ |
||
| 111 | #endif /* DBGMCU_CR_DBG_TIM14_STOP */ |
||
| 112 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ |
||
| 113 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ |
||
| 114 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
||
| 115 | #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
||
| 116 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ |
||
| 117 | #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */ |
||
| 118 | #if defined(DBGMCU_CR_DBG_CAN1_STOP) |
||
| 119 | #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ |
||
| 120 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
||
| 121 | #if defined(DBGMCU_CR_DBG_CAN2_STOP) |
||
| 122 | #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ |
||
| 123 | #endif /* DBGMCU_CR_DBG_CAN2_STOP */ |
||
| 124 | /** |
||
| 125 | * @} |
||
| 126 | */ |
||
| 127 | |||
| 128 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
||
| 129 | * @{ |
||
| 130 | */ |
||
| 131 | #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ |
||
| 132 | #if defined(DBGMCU_CR_DBG_TIM8_STOP) |
||
| 133 | #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ |
||
| 134 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
||
| 135 | #if defined(DBGMCU_CR_DBG_TIM9_STOP) |
||
| 136 | #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ |
||
| 137 | #endif /* DBGMCU_CR_DBG_TIM9_STOP */ |
||
| 138 | #if defined(DBGMCU_CR_DBG_TIM10_STOP) |
||
| 139 | #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ |
||
| 140 | #endif /* DBGMCU_CR_DBG_TIM10_STOP */ |
||
| 141 | #if defined(DBGMCU_CR_DBG_TIM11_STOP) |
||
| 142 | #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ |
||
| 143 | #endif /* DBGMCU_CR_DBG_TIM11_STOP */ |
||
| 144 | #if defined(DBGMCU_CR_DBG_TIM15_STOP) |
||
| 145 | #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ |
||
| 146 | #endif /* DBGMCU_CR_DBG_TIM15_STOP */ |
||
| 147 | #if defined(DBGMCU_CR_DBG_TIM16_STOP) |
||
| 148 | #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ |
||
| 149 | #endif /* DBGMCU_CR_DBG_TIM16_STOP */ |
||
| 150 | #if defined(DBGMCU_CR_DBG_TIM17_STOP) |
||
| 151 | #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ |
||
| 152 | #endif /* DBGMCU_CR_DBG_TIM17_STOP */ |
||
| 153 | /** |
||
| 154 | * @} |
||
| 155 | */ |
||
| 156 | |||
| 157 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
||
| 158 | * @{ |
||
| 159 | */ |
||
| 160 | #if defined(FLASH_ACR_LATENCY) |
||
| 161 | #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
||
| 162 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ |
||
| 163 | #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ |
||
| 164 | #else |
||
| 165 | #endif /* FLASH_ACR_LATENCY */ |
||
| 166 | /** |
||
| 167 | * @} |
||
| 168 | */ |
||
| 169 | |||
| 170 | /** |
||
| 171 | * @} |
||
| 172 | */ |
||
| 173 | |||
| 174 | /* Exported macro ------------------------------------------------------------*/ |
||
| 175 | |||
| 176 | /* Exported functions --------------------------------------------------------*/ |
||
| 177 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
||
| 178 | * @{ |
||
| 179 | */ |
||
| 180 | |||
| 181 | |||
| 182 | |||
| 183 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
||
| 184 | * @{ |
||
| 185 | */ |
||
| 186 | |||
| 187 | /** |
||
| 188 | * @brief Return the device identifier |
||
| 189 | * @note For Low Density devices, the device ID is 0x412 |
||
| 190 | * @note For Medium Density devices, the device ID is 0x410 |
||
| 191 | * @note For High Density devices, the device ID is 0x414 |
||
| 192 | * @note For XL Density devices, the device ID is 0x430 |
||
| 193 | * @note For Connectivity Line devices, the device ID is 0x418 |
||
| 194 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
||
| 195 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFF |
||
| 196 | */ |
||
| 197 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
||
| 198 | { |
||
| 199 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
||
| 200 | } |
||
| 201 | |||
| 202 | /** |
||
| 203 | * @brief Return the device revision identifier |
||
| 204 | * @note This field indicates the revision of the device. |
||
| 205 | For example, it is read as revA -> 0x1000,for Low Density devices |
||
| 206 | For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices |
||
| 207 | For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices |
||
| 208 | For example, it is read as revA or 1 -> 0x1003,for XL Density devices |
||
| 209 | For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices |
||
| 210 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
||
| 211 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
||
| 212 | */ |
||
| 213 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
||
| 214 | { |
||
| 215 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
||
| 216 | } |
||
| 217 | |||
| 218 | /** |
||
| 219 | * @brief Enable the Debug Module during SLEEP mode |
||
| 220 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
||
| 221 | * @retval None |
||
| 222 | */ |
||
| 223 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
||
| 224 | { |
||
| 225 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
||
| 226 | } |
||
| 227 | |||
| 228 | /** |
||
| 229 | * @brief Disable the Debug Module during SLEEP mode |
||
| 230 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
||
| 231 | * @retval None |
||
| 232 | */ |
||
| 233 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
||
| 234 | { |
||
| 235 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
||
| 236 | } |
||
| 237 | |||
| 238 | /** |
||
| 239 | * @brief Enable the Debug Module during STOP mode |
||
| 240 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
||
| 241 | * @retval None |
||
| 242 | */ |
||
| 243 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
||
| 244 | { |
||
| 245 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
||
| 246 | } |
||
| 247 | |||
| 248 | /** |
||
| 249 | * @brief Disable the Debug Module during STOP mode |
||
| 250 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
||
| 251 | * @retval None |
||
| 252 | */ |
||
| 253 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
||
| 254 | { |
||
| 255 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
||
| 256 | } |
||
| 257 | |||
| 258 | /** |
||
| 259 | * @brief Enable the Debug Module during STANDBY mode |
||
| 260 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
||
| 261 | * @retval None |
||
| 262 | */ |
||
| 263 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
||
| 264 | { |
||
| 265 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
||
| 266 | } |
||
| 267 | |||
| 268 | /** |
||
| 269 | * @brief Disable the Debug Module during STANDBY mode |
||
| 270 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
||
| 271 | * @retval None |
||
| 272 | */ |
||
| 273 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
||
| 274 | { |
||
| 275 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
||
| 276 | } |
||
| 277 | |||
| 278 | /** |
||
| 279 | * @brief Set Trace pin assignment control |
||
| 280 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
||
| 281 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
||
| 282 | * @param PinAssignment This parameter can be one of the following values: |
||
| 283 | * @arg @ref LL_DBGMCU_TRACE_NONE |
||
| 284 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
||
| 285 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
||
| 286 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
||
| 287 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
||
| 288 | * @retval None |
||
| 289 | */ |
||
| 290 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
||
| 291 | { |
||
| 292 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
||
| 293 | } |
||
| 294 | |||
| 295 | /** |
||
| 296 | * @brief Get Trace pin assignment control |
||
| 297 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
||
| 298 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
||
| 299 | * @retval Returned value can be one of the following values: |
||
| 300 | * @arg @ref LL_DBGMCU_TRACE_NONE |
||
| 301 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
||
| 302 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
||
| 303 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
||
| 304 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
||
| 305 | */ |
||
| 306 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
||
| 307 | { |
||
| 308 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
||
| 309 | } |
||
| 310 | |||
| 311 | /** |
||
| 312 | * @brief Freeze APB1 peripherals (group1 peripherals) |
||
| 313 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 314 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 315 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 316 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 317 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 318 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 319 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 320 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 321 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 322 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 323 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 324 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 325 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 326 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 327 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
||
| 328 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph |
||
| 329 | * @param Periphs This parameter can be a combination of the following values: |
||
| 330 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
||
| 331 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
||
| 332 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
||
| 333 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
||
| 334 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
||
| 335 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
||
| 336 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
||
| 337 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
||
| 338 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
||
| 339 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
||
| 340 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
||
| 341 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
||
| 342 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
||
| 343 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
||
| 344 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
||
| 345 | * |
||
| 346 | * (*) value not defined in all devices. |
||
| 347 | * @retval None |
||
| 348 | */ |
||
| 349 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
||
| 350 | { |
||
| 351 | SET_BIT(DBGMCU->CR, Periphs); |
||
| 352 | } |
||
| 353 | |||
| 354 | /** |
||
| 355 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
||
| 356 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 357 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 358 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 359 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 360 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 361 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 362 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 363 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 364 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 365 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 366 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 367 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 368 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 369 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 370 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
||
| 371 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
||
| 372 | * @param Periphs This parameter can be a combination of the following values: |
||
| 373 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
||
| 374 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
||
| 375 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
||
| 376 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
||
| 377 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
||
| 378 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
||
| 379 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
||
| 380 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
||
| 381 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
||
| 382 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP |
||
| 383 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
||
| 384 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
||
| 385 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
||
| 386 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
||
| 387 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
||
| 388 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
||
| 389 | * |
||
| 390 | * (*) value not defined in all devices. |
||
| 391 | * @retval None |
||
| 392 | */ |
||
| 393 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
||
| 394 | { |
||
| 395 | CLEAR_BIT(DBGMCU->CR, Periphs); |
||
| 396 | } |
||
| 397 | |||
| 398 | /** |
||
| 399 | * @brief Freeze APB2 peripherals |
||
| 400 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 401 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 402 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 403 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 404 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 405 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 406 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 407 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
||
| 408 | * @param Periphs This parameter can be a combination of the following values: |
||
| 409 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
||
| 410 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
||
| 411 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
||
| 412 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
||
| 413 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
||
| 414 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
||
| 415 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
||
| 416 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
||
| 417 | * |
||
| 418 | * (*) value not defined in all devices. |
||
| 419 | * @retval None |
||
| 420 | */ |
||
| 421 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
||
| 422 | { |
||
| 423 | SET_BIT(DBGMCU->CR, Periphs); |
||
| 424 | } |
||
| 425 | |||
| 426 | /** |
||
| 427 | * @brief Unfreeze APB2 peripherals |
||
| 428 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 429 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 430 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 431 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 432 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 433 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 434 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
||
| 435 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
||
| 436 | * @param Periphs This parameter can be a combination of the following values: |
||
| 437 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
||
| 438 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
||
| 439 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
||
| 440 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
||
| 441 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
||
| 442 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
||
| 443 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
||
| 444 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
||
| 445 | * |
||
| 446 | * (*) value not defined in all devices. |
||
| 447 | * @retval None |
||
| 448 | */ |
||
| 449 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
||
| 450 | { |
||
| 451 | CLEAR_BIT(DBGMCU->CR, Periphs); |
||
| 452 | } |
||
| 453 | /** |
||
| 454 | * @} |
||
| 455 | */ |
||
| 456 | |||
| 457 | #if defined(FLASH_ACR_LATENCY) |
||
| 458 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
||
| 459 | * @{ |
||
| 460 | */ |
||
| 461 | |||
| 462 | /** |
||
| 463 | * @brief Set FLASH Latency |
||
| 464 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
||
| 465 | * @param Latency This parameter can be one of the following values: |
||
| 466 | * @arg @ref LL_FLASH_LATENCY_0 |
||
| 467 | * @arg @ref LL_FLASH_LATENCY_1 |
||
| 468 | * @arg @ref LL_FLASH_LATENCY_2 |
||
| 469 | * @retval None |
||
| 470 | */ |
||
| 471 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
||
| 472 | { |
||
| 473 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
||
| 474 | } |
||
| 475 | |||
| 476 | /** |
||
| 477 | * @brief Get FLASH Latency |
||
| 478 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
||
| 479 | * @retval Returned value can be one of the following values: |
||
| 480 | * @arg @ref LL_FLASH_LATENCY_0 |
||
| 481 | * @arg @ref LL_FLASH_LATENCY_1 |
||
| 482 | * @arg @ref LL_FLASH_LATENCY_2 |
||
| 483 | */ |
||
| 484 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
||
| 485 | { |
||
| 486 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
||
| 487 | } |
||
| 488 | |||
| 489 | /** |
||
| 490 | * @brief Enable Prefetch |
||
| 491 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch |
||
| 492 | * @retval None |
||
| 493 | */ |
||
| 494 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
||
| 495 | { |
||
| 496 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
||
| 497 | } |
||
| 498 | |||
| 499 | /** |
||
| 500 | * @brief Disable Prefetch |
||
| 501 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch |
||
| 502 | * @retval None |
||
| 503 | */ |
||
| 504 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
||
| 505 | { |
||
| 506 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
||
| 507 | } |
||
| 508 | |||
| 509 | /** |
||
| 510 | * @brief Check if Prefetch buffer is enabled |
||
| 511 | * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled |
||
| 512 | * @retval State of bit (1 or 0). |
||
| 513 | */ |
||
| 514 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
||
| 515 | { |
||
| 516 | return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); |
||
| 517 | } |
||
| 518 | |||
| 519 | #endif /* FLASH_ACR_LATENCY */ |
||
| 520 | /** |
||
| 521 | * @brief Enable Flash Half Cycle Access |
||
| 522 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess |
||
| 523 | * @retval None |
||
| 524 | */ |
||
| 525 | __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) |
||
| 526 | { |
||
| 527 | SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
||
| 528 | } |
||
| 529 | |||
| 530 | /** |
||
| 531 | * @brief Disable Flash Half Cycle Access |
||
| 532 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess |
||
| 533 | * @retval None |
||
| 534 | */ |
||
| 535 | __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) |
||
| 536 | { |
||
| 537 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
||
| 538 | } |
||
| 539 | |||
| 540 | /** |
||
| 541 | * @brief Check if Flash Half Cycle Access is enabled or not |
||
| 542 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled |
||
| 543 | * @retval State of bit (1 or 0). |
||
| 544 | */ |
||
| 545 | __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) |
||
| 546 | { |
||
| 547 | return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); |
||
| 548 | } |
||
| 549 | |||
| 550 | |||
| 551 | /** |
||
| 552 | * @} |
||
| 553 | */ |
||
| 554 | |||
| 555 | /** |
||
| 556 | * @} |
||
| 557 | */ |
||
| 558 | |||
| 559 | /** |
||
| 560 | * @} |
||
| 561 | */ |
||
| 562 | |||
| 563 | #endif /* defined (FLASH) || defined (DBGMCU) */ |
||
| 564 | |||
| 565 | /** |
||
| 566 | * @} |
||
| 567 | */ |
||
| 568 | |||
| 569 | #ifdef __cplusplus |
||
| 570 | } |
||
| 571 | #endif |
||
| 572 | |||
| 573 | #endif /* __STM32F1xx_LL_SYSTEM_H */ |
||
| 574 | |||
| 575 |