WebSVN – testOled – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_spi.h
		4	* @author MCD Application Team
		5	* @brief Header file of SPI LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef STM32F1xx_LL_SPI_H
		22	#define STM32F1xx_LL_SPI_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f1xx.h"
		30
		31	/** @addtogroup STM32F1xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3)
		36
		37	/** @defgroup SPI_LL SPI
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/* Private macros ------------------------------------------------------------*/
		44
		45	/* Exported types ------------------------------------------------------------*/
		46	#if defined(USE_FULL_LL_DRIVER)
		47	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
		48	* @{
		49	*/
		50
		51	/**
		52	* @brief SPI Init structures definition
		53	*/
		54	typedef struct
		55	{
		56	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
		57	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
		58
		59	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
		60
		61	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
		62	This parameter can be a value of @ref SPI_LL_EC_MODE.
		63
		64	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
		65
		66	uint32_t DataWidth; /*!< Specifies the SPI data width.
		67	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
		68
		69	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
		70
		71	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
		72	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
		73
		74	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
		75
		76	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
		77	This parameter can be a value of @ref SPI_LL_EC_PHASE.
		78
		79	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
		80
		81	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
		82	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
		83
		84	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
		85
		86	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
		87	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
		88	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
		89
		90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
		91
		92	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
		93	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
		94
		95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
		96
		97	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
		98	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
		99
		100	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
		101
		102	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
		103	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
		104
		105	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
		106
		107	} LL_SPI_InitTypeDef;
		108
		109	/**
		110	* @}
		111	*/
		112	#endif /* USE_FULL_LL_DRIVER */
		113
		114	/* Exported constants --------------------------------------------------------*/
		115	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
		116	* @{
		117	*/
		118
		119	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
		120	* @brief Flags defines which can be used with LL_SPI_ReadReg function
		121	* @{
		122	*/
		123	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
		124	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
		125	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
		126	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
		127	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
		128	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
		129	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
		130	/**
		131	* @}
		132	*/
		133
		134	/** @defgroup SPI_LL_EC_IT IT Defines
		135	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
		136	* @{
		137	*/
		138	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
		139	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
		140	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
		141	/**
		142	* @}
		143	*/
		144
		145	/** @defgroup SPI_LL_EC_MODE Operation Mode
		146	* @{
		147	*/
		148	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
		149	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
		150	/**
		151	* @}
		152	*/
		153
		154
		155	/** @defgroup SPI_LL_EC_PHASE Clock Phase
		156	* @{
		157	*/
		158	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
		159	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
		160	/**
		161	* @}
		162	*/
		163
		164	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
		165	* @{
		166	*/
		167	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
		168	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
		169	/**
		170	* @}
		171	*/
		172
		173	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
		174	* @{
		175	*/
		176	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
		177	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
		178	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
		179	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
		180	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
		181	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
		182	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
		183	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
		184	/**
		185	* @}
		186	*/
		187
		188	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
		189	* @{
		190	*/
		191	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
		192	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
		193	/**
		194	* @}
		195	*/
		196
		197	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
		198	* @{
		199	*/
		200	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
		201	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
		202	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
		203	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
		204	/**
		205	* @}
		206	*/
		207
		208	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
		209	* @{
		210	*/
		211	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
		212	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
		213	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
		214	/**
		215	* @}
		216	*/
		217
		218	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
		219	* @{
		220	*/
		221	#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /!< Data length for SPI transfer: 8 bits /
		222	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /!< Data length for SPI transfer: 16 bits /
		223	/**
		224	* @}
		225	*/
		226	#if defined(USE_FULL_LL_DRIVER)
		227
		228	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
		229	* @{
		230	*/
		231	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
		232	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
		233	/**
		234	* @}
		235	*/
		236	#endif /* USE_FULL_LL_DRIVER */
		237
		238	/**
		239	* @}
		240	*/
		241
		242	/* Exported macro ------------------------------------------------------------*/
		243	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
		244	* @{
		245	*/
		246
		247	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
		248	* @{
		249	*/
		250
		251	/**
		252	* @brief Write a value in SPI register
		253	* @param __INSTANCE__ SPI Instance
		254	* @param __REG__ Register to be written
		255	* @param __VALUE__ Value to be written in the register
		256	* @retval None
		257	*/
		258	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		259
		260	/**
		261	* @brief Read a value in SPI register
		262	* @param __INSTANCE__ SPI Instance
		263	* @param __REG__ Register to be read
		264	* @retval Register value
		265	*/
		266	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		267	/**
		268	* @}
		269	*/
		270
		271	/**
		272	* @}
		273	*/
		274
		275	/* Exported functions --------------------------------------------------------*/
		276	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
		277	* @{
		278	*/
		279
		280	/** @defgroup SPI_LL_EF_Configuration Configuration
		281	* @{
		282	*/
		283
		284	/**
		285	* @brief Enable SPI peripheral
		286	* @rmtoll CR1 SPE LL_SPI_Enable
		287	* @param SPIx SPI Instance
		288	* @retval None
		289	*/
		290	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
		291	{
		292	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
		293	}
		294
		295	/**
		296	* @brief Disable SPI peripheral
		297	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
		298	* @rmtoll CR1 SPE LL_SPI_Disable
		299	* @param SPIx SPI Instance
		300	* @retval None
		301	*/
		302	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
		303	{
		304	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
		305	}
		306
		307	/**
		308	* @brief Check if SPI peripheral is enabled
		309	* @rmtoll CR1 SPE LL_SPI_IsEnabled
		310	* @param SPIx SPI Instance
		311	* @retval State of bit (1 or 0).
		312	*/
		313	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
		314	{
		315	return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
		316	}
		317
		318	/**
		319	* @brief Set SPI operation mode to Master or Slave
		320	* @note This bit should not be changed when communication is ongoing.
		321	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
		322	* CR1 SSI LL_SPI_SetMode
		323	* @param SPIx SPI Instance
		324	* @param Mode This parameter can be one of the following values:
		325	* @arg @ref LL_SPI_MODE_MASTER
		326	* @arg @ref LL_SPI_MODE_SLAVE
		327	* @retval None
		328	*/
		329	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
		330	{
		331	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
		332	}
		333
		334	/**
		335	* @brief Get SPI operation mode (Master or Slave)
		336	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
		337	* CR1 SSI LL_SPI_GetMode
		338	* @param SPIx SPI Instance
		339	* @retval Returned value can be one of the following values:
		340	* @arg @ref LL_SPI_MODE_MASTER
		341	* @arg @ref LL_SPI_MODE_SLAVE
		342	*/
		343	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
		344	{
		345	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
		346	}
		347
		348
		349	/**
		350	* @brief Set clock phase
		351	* @note This bit should not be changed when communication is ongoing.
		352	* This bit is not used in SPI TI mode.
		353	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
		354	* @param SPIx SPI Instance
		355	* @param ClockPhase This parameter can be one of the following values:
		356	* @arg @ref LL_SPI_PHASE_1EDGE
		357	* @arg @ref LL_SPI_PHASE_2EDGE
		358	* @retval None
		359	*/
		360	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
		361	{
		362	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
		363	}
		364
		365	/**
		366	* @brief Get clock phase
		367	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
		368	* @param SPIx SPI Instance
		369	* @retval Returned value can be one of the following values:
		370	* @arg @ref LL_SPI_PHASE_1EDGE
		371	* @arg @ref LL_SPI_PHASE_2EDGE
		372	*/
		373	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
		374	{
		375	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
		376	}
		377
		378	/**
		379	* @brief Set clock polarity
		380	* @note This bit should not be changed when communication is ongoing.
		381	* This bit is not used in SPI TI mode.
		382	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
		383	* @param SPIx SPI Instance
		384	* @param ClockPolarity This parameter can be one of the following values:
		385	* @arg @ref LL_SPI_POLARITY_LOW
		386	* @arg @ref LL_SPI_POLARITY_HIGH
		387	* @retval None
		388	*/
		389	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
		390	{
		391	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
		392	}
		393
		394	/**
		395	* @brief Get clock polarity
		396	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
		397	* @param SPIx SPI Instance
		398	* @retval Returned value can be one of the following values:
		399	* @arg @ref LL_SPI_POLARITY_LOW
		400	* @arg @ref LL_SPI_POLARITY_HIGH
		401	*/
		402	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
		403	{
		404	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
		405	}
		406
		407	/**
		408	* @brief Set baud rate prescaler
		409	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
		410	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
		411	* @param SPIx SPI Instance
		412	* @param BaudRate This parameter can be one of the following values:
		413	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
		414	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
		415	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
		416	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
		417	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
		418	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
		419	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
		420	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
		421	* @retval None
		422	*/
		423	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
		424	{
		425	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
		426	}
		427
		428	/**
		429	* @brief Get baud rate prescaler
		430	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
		431	* @param SPIx SPI Instance
		432	* @retval Returned value can be one of the following values:
		433	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
		434	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
		435	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
		436	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
		437	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
		438	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
		439	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
		440	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
		441	*/
		442	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
		443	{
		444	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
		445	}
		446
		447	/**
		448	* @brief Set transfer bit order
		449	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
		450	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
		451	* @param SPIx SPI Instance
		452	* @param BitOrder This parameter can be one of the following values:
		453	* @arg @ref LL_SPI_LSB_FIRST
		454	* @arg @ref LL_SPI_MSB_FIRST
		455	* @retval None
		456	*/
		457	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
		458	{
		459	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
		460	}
		461
		462	/**
		463	* @brief Get transfer bit order
		464	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
		465	* @param SPIx SPI Instance
		466	* @retval Returned value can be one of the following values:
		467	* @arg @ref LL_SPI_LSB_FIRST
		468	* @arg @ref LL_SPI_MSB_FIRST
		469	*/
		470	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
		471	{
		472	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
		473	}
		474
		475	/**
		476	* @brief Set transfer direction mode
		477	* @note For Half-Duplex mode, Rx Direction is set by default.
		478	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
		479	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
		480	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
		481	* CR1 BIDIOE LL_SPI_SetTransferDirection
		482	* @param SPIx SPI Instance
		483	* @param TransferDirection This parameter can be one of the following values:
		484	* @arg @ref LL_SPI_FULL_DUPLEX
		485	* @arg @ref LL_SPI_SIMPLEX_RX
		486	* @arg @ref LL_SPI_HALF_DUPLEX_RX
		487	* @arg @ref LL_SPI_HALF_DUPLEX_TX
		488	* @retval None
		489	*/
		490	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
		491	{
		492	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
		493	}
		494
		495	/**
		496	* @brief Get transfer direction mode
		497	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
		498	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
		499	* CR1 BIDIOE LL_SPI_GetTransferDirection
		500	* @param SPIx SPI Instance
		501	* @retval Returned value can be one of the following values:
		502	* @arg @ref LL_SPI_FULL_DUPLEX
		503	* @arg @ref LL_SPI_SIMPLEX_RX
		504	* @arg @ref LL_SPI_HALF_DUPLEX_RX
		505	* @arg @ref LL_SPI_HALF_DUPLEX_TX
		506	*/
		507	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
		508	{
		509	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
		510	}
		511
		512	/**
		513	* @brief Set frame data width
		514	* @rmtoll CR1 DFF LL_SPI_SetDataWidth
		515	* @param SPIx SPI Instance
		516	* @param DataWidth This parameter can be one of the following values:
		517	* @arg @ref LL_SPI_DATAWIDTH_8BIT
		518	* @arg @ref LL_SPI_DATAWIDTH_16BIT
		519	* @retval None
		520	*/
		521	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
		522	{
		523	MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
		524	}
		525
		526	/**
		527	* @brief Get frame data width
		528	* @rmtoll CR1 DFF LL_SPI_GetDataWidth
		529	* @param SPIx SPI Instance
		530	* @retval Returned value can be one of the following values:
		531	* @arg @ref LL_SPI_DATAWIDTH_8BIT
		532	* @arg @ref LL_SPI_DATAWIDTH_16BIT
		533	*/
		534	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
		535	{
		536	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
		537	}
		538
		539	/**
		540	* @}
		541	*/
		542
		543	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
		544	* @{
		545	*/
		546
		547	/**
		548	* @brief Enable CRC
		549	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
		550	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
		551	* @param SPIx SPI Instance
		552	* @retval None
		553	*/
		554	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
		555	{
		556	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
		557	}
		558
		559	/**
		560	* @brief Disable CRC
		561	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
		562	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
		563	* @param SPIx SPI Instance
		564	* @retval None
		565	*/
		566	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
		567	{
		568	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
		569	}
		570
		571	/**
		572	* @brief Check if CRC is enabled
		573	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
		574	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
		575	* @param SPIx SPI Instance
		576	* @retval State of bit (1 or 0).
		577	*/
		578	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
		579	{
		580	return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
		581	}
		582
		583	/**
		584	* @brief Set CRCNext to transfer CRC on the line
		585	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
		586	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
		587	* @param SPIx SPI Instance
		588	* @retval None
		589	*/
		590	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
		591	{
		592	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
		593	}
		594
		595	/**
		596	* @brief Set polynomial for CRC calculation
		597	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
		598	* @param SPIx SPI Instance
		599	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
		600	* @retval None
		601	*/
		602	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
		603	{
		604	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
		605	}
		606
		607	/**
		608	* @brief Get polynomial for CRC calculation
		609	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
		610	* @param SPIx SPI Instance
		611	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
		612	*/
		613	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
		614	{
		615	return (uint32_t)(READ_REG(SPIx->CRCPR));
		616	}
		617
		618	/**
		619	* @brief Get Rx CRC
		620	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
		621	* @param SPIx SPI Instance
		622	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
		623	*/
		624	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
		625	{
		626	return (uint32_t)(READ_REG(SPIx->RXCRCR));
		627	}
		628
		629	/**
		630	* @brief Get Tx CRC
		631	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
		632	* @param SPIx SPI Instance
		633	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
		634	*/
		635	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
		636	{
		637	return (uint32_t)(READ_REG(SPIx->TXCRCR));
		638	}
		639
		640	/**
		641	* @}
		642	*/
		643
		644	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
		645	* @{
		646	*/
		647
		648	/**
		649	* @brief Set NSS mode
		650	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
		651	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
		652	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
		653	* @param SPIx SPI Instance
		654	* @param NSS This parameter can be one of the following values:
		655	* @arg @ref LL_SPI_NSS_SOFT
		656	* @arg @ref LL_SPI_NSS_HARD_INPUT
		657	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
		658	* @retval None
		659	*/
		660	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
		661	{
		662	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
		663	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
		664	}
		665
		666	/**
		667	* @brief Get NSS mode
		668	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
		669	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
		670	* @param SPIx SPI Instance
		671	* @retval Returned value can be one of the following values:
		672	* @arg @ref LL_SPI_NSS_SOFT
		673	* @arg @ref LL_SPI_NSS_HARD_INPUT
		674	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
		675	*/
		676	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
		677	{
		678	uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
		679	uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
		680	return (Ssm \| Ssoe);
		681	}
		682
		683	/**
		684	* @}
		685	*/
		686
		687	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
		688	* @{
		689	*/
		690
		691	/**
		692	* @brief Check if Rx buffer is not empty
		693	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
		694	* @param SPIx SPI Instance
		695	* @retval State of bit (1 or 0).
		696	*/
		697	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
		698	{
		699	return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
		700	}
		701
		702	/**
		703	* @brief Check if Tx buffer is empty
		704	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
		705	* @param SPIx SPI Instance
		706	* @retval State of bit (1 or 0).
		707	*/
		708	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
		709	{
		710	return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
		711	}
		712
		713	/**
		714	* @brief Get CRC error flag
		715	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
		716	* @param SPIx SPI Instance
		717	* @retval State of bit (1 or 0).
		718	*/
		719	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
		720	{
		721	return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
		722	}
		723
		724	/**
		725	* @brief Get mode fault error flag
		726	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
		727	* @param SPIx SPI Instance
		728	* @retval State of bit (1 or 0).
		729	*/
		730	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
		731	{
		732	return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
		733	}
		734
		735	/**
		736	* @brief Get overrun error flag
		737	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
		738	* @param SPIx SPI Instance
		739	* @retval State of bit (1 or 0).
		740	*/
		741	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
		742	{
		743	return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
		744	}
		745
		746	/**
		747	* @brief Get busy flag
		748	* @note The BSY flag is cleared under any one of the following conditions:
		749	* -When the SPI is correctly disabled
		750	* -When a fault is detected in Master mode (MODF bit set to 1)
		751	* -In Master mode, when it finishes a data transmission and no new data is ready to be
		752	* sent
		753	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
		754	* each data transfer.
		755	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
		756	* @param SPIx SPI Instance
		757	* @retval State of bit (1 or 0).
		758	*/
		759	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
		760	{
		761	return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
		762	}
		763
		764
		765	/**
		766	* @brief Clear CRC error flag
		767	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
		768	* @param SPIx SPI Instance
		769	* @retval None
		770	*/
		771	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
		772	{
		773	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
		774	}
		775
		776	/**
		777	* @brief Clear mode fault error flag
		778	* @note Clearing this flag is done by a read access to the SPIx_SR
		779	* register followed by a write access to the SPIx_CR1 register
		780	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
		781	* @param SPIx SPI Instance
		782	* @retval None
		783	*/
		784	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
		785	{
		786	__IO uint32_t tmpreg_sr;
		787	tmpreg_sr = SPIx->SR;
		788	(void) tmpreg_sr;
		789	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
		790	}
		791
		792	/**
		793	* @brief Clear overrun error flag
		794	* @note Clearing this flag is done by a read access to the SPIx_DR
		795	* register followed by a read access to the SPIx_SR register
		796	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
		797	* @param SPIx SPI Instance
		798	* @retval None
		799	*/
		800	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
		801	{
		802	__IO uint32_t tmpreg;
		803	tmpreg = SPIx->DR;
		804	(void) tmpreg;
		805	tmpreg = SPIx->SR;
		806	(void) tmpreg;
		807	}
		808
		809	/**
		810	* @brief Clear frame format error flag
		811	* @note Clearing this flag is done by reading SPIx_SR register
		812	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
		813	* @param SPIx SPI Instance
		814	* @retval None
		815	*/
		816	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
		817	{
		818	__IO uint32_t tmpreg;
		819	tmpreg = SPIx->SR;
		820	(void) tmpreg;
		821	}
		822
		823	/**
		824	* @}
		825	*/
		826
		827	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
		828	* @{
		829	*/
		830
		831	/**
		832	* @brief Enable error interrupt
		833	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
		834	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
		835	* @param SPIx SPI Instance
		836	* @retval None
		837	*/
		838	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
		839	{
		840	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
		841	}
		842
		843	/**
		844	* @brief Enable Rx buffer not empty interrupt
		845	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
		846	* @param SPIx SPI Instance
		847	* @retval None
		848	*/
		849	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
		850	{
		851	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
		852	}
		853
		854	/**
		855	* @brief Enable Tx buffer empty interrupt
		856	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
		857	* @param SPIx SPI Instance
		858	* @retval None
		859	*/
		860	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
		861	{
		862	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
		863	}
		864
		865	/**
		866	* @brief Disable error interrupt
		867	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
		868	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
		869	* @param SPIx SPI Instance
		870	* @retval None
		871	*/
		872	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
		873	{
		874	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
		875	}
		876
		877	/**
		878	* @brief Disable Rx buffer not empty interrupt
		879	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
		880	* @param SPIx SPI Instance
		881	* @retval None
		882	*/
		883	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
		884	{
		885	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
		886	}
		887
		888	/**
		889	* @brief Disable Tx buffer empty interrupt
		890	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
		891	* @param SPIx SPI Instance
		892	* @retval None
		893	*/
		894	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
		895	{
		896	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
		897	}
		898
		899	/**
		900	* @brief Check if error interrupt is enabled
		901	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
		902	* @param SPIx SPI Instance
		903	* @retval State of bit (1 or 0).
		904	*/
		905	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
		906	{
		907	return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
		908	}
		909
		910	/**
		911	* @brief Check if Rx buffer not empty interrupt is enabled
		912	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
		913	* @param SPIx SPI Instance
		914	* @retval State of bit (1 or 0).
		915	*/
		916	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
		917	{
		918	return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
		919	}
		920
		921	/**
		922	* @brief Check if Tx buffer empty interrupt
		923	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
		924	* @param SPIx SPI Instance
		925	* @retval State of bit (1 or 0).
		926	*/
		927	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
		928	{
		929	return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
		930	}
		931
		932	/**
		933	* @}
		934	*/
		935
		936	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
		937	* @{
		938	*/
		939
		940	/**
		941	* @brief Enable DMA Rx
		942	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
		943	* @param SPIx SPI Instance
		944	* @retval None
		945	*/
		946	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
		947	{
		948	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
		949	}
		950
		951	/**
		952	* @brief Disable DMA Rx
		953	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
		954	* @param SPIx SPI Instance
		955	* @retval None
		956	*/
		957	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
		958	{
		959	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
		960	}
		961
		962	/**
		963	* @brief Check if DMA Rx is enabled
		964	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
		965	* @param SPIx SPI Instance
		966	* @retval State of bit (1 or 0).
		967	*/
		968	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
		969	{
		970	return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
		971	}
		972
		973	/**
		974	* @brief Enable DMA Tx
		975	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
		976	* @param SPIx SPI Instance
		977	* @retval None
		978	*/
		979	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
		980	{
		981	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
		982	}
		983
		984	/**
		985	* @brief Disable DMA Tx
		986	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
		987	* @param SPIx SPI Instance
		988	* @retval None
		989	*/
		990	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
		991	{
		992	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
		993	}
		994
		995	/**
		996	* @brief Check if DMA Tx is enabled
		997	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
		998	* @param SPIx SPI Instance
		999	* @retval State of bit (1 or 0).
		1000	*/
		1001	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
		1002	{
		1003	return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
		1004	}
		1005
		1006	/**
		1007	* @brief Get the data register address used for DMA transfer
		1008	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
		1009	* @param SPIx SPI Instance
		1010	* @retval Address of data register
		1011	*/
		1012	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
		1013	{
		1014	return (uint32_t) &(SPIx->DR);
		1015	}
		1016
		1017	/**
		1018	* @}
		1019	*/
		1020
		1021	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
		1022	* @{
		1023	*/
		1024
		1025	/**
		1026	* @brief Read 8-Bits in the data register
		1027	* @rmtoll DR DR LL_SPI_ReceiveData8
		1028	* @param SPIx SPI Instance
		1029	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
		1030	*/
		1031	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
		1032	{
		1033	return (((__IO uint8_t )&SPIx->DR));
		1034	}
		1035
		1036	/**
		1037	* @brief Read 16-Bits in the data register
		1038	* @rmtoll DR DR LL_SPI_ReceiveData16
		1039	* @param SPIx SPI Instance
		1040	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
		1041	*/
		1042	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
		1043	{
		1044	return (uint16_t)(READ_REG(SPIx->DR));
		1045	}
		1046
		1047	/**
		1048	* @brief Write 8-Bits in the data register
		1049	* @rmtoll DR DR LL_SPI_TransmitData8
		1050	* @param SPIx SPI Instance
		1051	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
		1052	* @retval None
		1053	*/
		1054	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
		1055	{
		1056	#if defined (__GNUC__)
		1057	__IO uint8_t spidr = ((__IO uint8_t )&SPIx->DR);
		1058	*spidr = TxData;
		1059	#else
		1060	((__IO uint8_t )&SPIx->DR) = TxData;
		1061	#endif /* __GNUC__ */
		1062	}
		1063
		1064	/**
		1065	* @brief Write 16-Bits in the data register
		1066	* @rmtoll DR DR LL_SPI_TransmitData16
		1067	* @param SPIx SPI Instance
		1068	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
		1069	* @retval None
		1070	*/
		1071	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
		1072	{
		1073	#if defined (__GNUC__)
		1074	__IO uint16_t spidr = ((__IO uint16_t )&SPIx->DR);
		1075	*spidr = TxData;
		1076	#else
		1077	SPIx->DR = TxData;
		1078	#endif /* __GNUC__ */
		1079	}
		1080
		1081	/**
		1082	* @}
		1083	*/
		1084	#if defined(USE_FULL_LL_DRIVER)
		1085	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
		1086	* @{
		1087	*/
		1088
		1089	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
		1090	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
		1091	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
		1092
		1093	/**
		1094	* @}
		1095	*/
		1096	#endif /* USE_FULL_LL_DRIVER */
		1097	/**
		1098	* @}
		1099	*/
		1100
		1101	/**
		1102	* @}
		1103	*/
		1104
		1105	#if defined(SPI_I2S_SUPPORT)
		1106	/** @defgroup I2S_LL I2S
		1107	* @{
		1108	*/
		1109
		1110	/* Private variables ---------------------------------------------------------*/
		1111	/* Private constants ---------------------------------------------------------*/
		1112	/* Private macros ------------------------------------------------------------*/
		1113
		1114	/* Exported types ------------------------------------------------------------*/
		1115	#if defined(USE_FULL_LL_DRIVER)
		1116	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
		1117	* @{
		1118	*/
		1119
		1120	/**
		1121	* @brief I2S Init structure definition
		1122	*/
		1123
		1124	typedef struct
		1125	{
		1126	uint32_t Mode; /*!< Specifies the I2S operating mode.
		1127	This parameter can be a value of @ref I2S_LL_EC_MODE
		1128
		1129	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
		1130
		1131	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
		1132	This parameter can be a value of @ref I2S_LL_EC_STANDARD
		1133
		1134	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
		1135
		1136
		1137	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
		1138	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
		1139
		1140	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
		1141
		1142
		1143	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
		1144	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
		1145
		1146	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
		1147
		1148
		1149	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
		1150	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
		1151
		1152	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
		1153	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
		1154
		1155
		1156	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
		1157	This parameter can be a value of @ref I2S_LL_EC_POLARITY
		1158
		1159	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
		1160
		1161	} LL_I2S_InitTypeDef;
		1162
		1163	/**
		1164	* @}
		1165	*/
		1166	#endif /USE_FULL_LL_DRIVER/
		1167
		1168	/* Exported constants --------------------------------------------------------*/
		1169	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
		1170	* @{
		1171	*/
		1172
		1173	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
		1174	* @brief Flags defines which can be used with LL_I2S_ReadReg function
		1175	* @{
		1176	*/
		1177	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
		1178	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
		1179	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
		1180	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
		1181	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
		1182	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
		1183	/**
		1184	* @}
		1185	*/
		1186
		1187	/** @defgroup SPI_LL_EC_IT IT Defines
		1188	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
		1189	* @{
		1190	*/
		1191	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
		1192	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
		1193	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
		1194	/**
		1195	* @}
		1196	*/
		1197
		1198	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
		1199	* @{
		1200	*/
		1201	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel length 16bit /
		1202	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel length 32bit /
		1203	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel length 32bit /
		1204	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel length 32bit /
		1205	/**
		1206	* @}
		1207	*/
		1208
		1209	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
		1210	* @{
		1211	*/
		1212	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
		1213	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
		1214	/**
		1215	* @}
		1216	*/
		1217
		1218	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
		1219	* @{
		1220	*/
		1221	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
		1222	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
		1223	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
		1224	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
		1225	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
		1226	/**
		1227	* @}
		1228	*/
		1229
		1230	/** @defgroup I2S_LL_EC_MODE Operation Mode
		1231	* @{
		1232	*/
		1233	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
		1234	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
		1235	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
		1236	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
		1237	/**
		1238	* @}
		1239	*/
		1240
		1241	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
		1242	* @{
		1243	*/
		1244	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
		1245	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
		1246	/**
		1247	* @}
		1248	*/
		1249
		1250	#if defined(USE_FULL_LL_DRIVER)
		1251
		1252	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
		1253	* @{
		1254	*/
		1255	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
		1256	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
		1257	/**
		1258	* @}
		1259	*/
		1260
		1261	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
		1262	* @{
		1263	*/
		1264
		1265	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
		1266	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
		1267	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
		1268	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
		1269	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
		1270	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
		1271	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
		1272	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
		1273	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
		1274	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
		1275	/**
		1276	* @}
		1277	*/
		1278	#endif /* USE_FULL_LL_DRIVER */
		1279
		1280	/**
		1281	* @}
		1282	*/
		1283
		1284	/* Exported macro ------------------------------------------------------------*/
		1285	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
		1286	* @{
		1287	*/
		1288
		1289	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
		1290	* @{
		1291	*/
		1292
		1293	/**
		1294	* @brief Write a value in I2S register
		1295	* @param __INSTANCE__ I2S Instance
		1296	* @param __REG__ Register to be written
		1297	* @param __VALUE__ Value to be written in the register
		1298	* @retval None
		1299	*/
		1300	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		1301
		1302	/**
		1303	* @brief Read a value in I2S register
		1304	* @param __INSTANCE__ I2S Instance
		1305	* @param __REG__ Register to be read
		1306	* @retval Register value
		1307	*/
		1308	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		1309	/**
		1310	* @}
		1311	*/
		1312
		1313	/**
		1314	* @}
		1315	*/
		1316
		1317
		1318	/* Exported functions --------------------------------------------------------*/
		1319
		1320	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
		1321	* @{
		1322	*/
		1323
		1324	/** @defgroup I2S_LL_EF_Configuration Configuration
		1325	* @{
		1326	*/
		1327
		1328	/**
		1329	* @brief Select I2S mode and Enable I2S peripheral
		1330	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
		1331	* I2SCFGR I2SE LL_I2S_Enable
		1332	* @param SPIx SPI Instance
		1333	* @retval None
		1334	*/
		1335	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
		1336	{
		1337	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
		1338	}
		1339
		1340	/**
		1341	* @brief Disable I2S peripheral
		1342	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
		1343	* @param SPIx SPI Instance
		1344	* @retval None
		1345	*/
		1346	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
		1347	{
		1348	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
		1349	}
		1350
		1351	/**
		1352	* @brief Check if I2S peripheral is enabled
		1353	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
		1354	* @param SPIx SPI Instance
		1355	* @retval State of bit (1 or 0).
		1356	*/
		1357	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
		1358	{
		1359	return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
		1360	}
		1361
		1362	/**
		1363	* @brief Set I2S data frame length
		1364	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
		1365	* I2SCFGR CHLEN LL_I2S_SetDataFormat
		1366	* @param SPIx SPI Instance
		1367	* @param DataFormat This parameter can be one of the following values:
		1368	* @arg @ref LL_I2S_DATAFORMAT_16B
		1369	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
		1370	* @arg @ref LL_I2S_DATAFORMAT_24B
		1371	* @arg @ref LL_I2S_DATAFORMAT_32B
		1372	* @retval None
		1373	*/
		1374	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
		1375	{
		1376	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
		1377	}
		1378
		1379	/**
		1380	* @brief Get I2S data frame length
		1381	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
		1382	* I2SCFGR CHLEN LL_I2S_GetDataFormat
		1383	* @param SPIx SPI Instance
		1384	* @retval Returned value can be one of the following values:
		1385	* @arg @ref LL_I2S_DATAFORMAT_16B
		1386	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
		1387	* @arg @ref LL_I2S_DATAFORMAT_24B
		1388	* @arg @ref LL_I2S_DATAFORMAT_32B
		1389	*/
		1390	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
		1391	{
		1392	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
		1393	}
		1394
		1395	/**
		1396	* @brief Set I2S clock polarity
		1397	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
		1398	* @param SPIx SPI Instance
		1399	* @param ClockPolarity This parameter can be one of the following values:
		1400	* @arg @ref LL_I2S_POLARITY_LOW
		1401	* @arg @ref LL_I2S_POLARITY_HIGH
		1402	* @retval None
		1403	*/
		1404	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
		1405	{
		1406	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
		1407	}
		1408
		1409	/**
		1410	* @brief Get I2S clock polarity
		1411	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
		1412	* @param SPIx SPI Instance
		1413	* @retval Returned value can be one of the following values:
		1414	* @arg @ref LL_I2S_POLARITY_LOW
		1415	* @arg @ref LL_I2S_POLARITY_HIGH
		1416	*/
		1417	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
		1418	{
		1419	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
		1420	}
		1421
		1422	/**
		1423	* @brief Set I2S standard protocol
		1424	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
		1425	* I2SCFGR PCMSYNC LL_I2S_SetStandard
		1426	* @param SPIx SPI Instance
		1427	* @param Standard This parameter can be one of the following values:
		1428	* @arg @ref LL_I2S_STANDARD_PHILIPS
		1429	* @arg @ref LL_I2S_STANDARD_MSB
		1430	* @arg @ref LL_I2S_STANDARD_LSB
		1431	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
		1432	* @arg @ref LL_I2S_STANDARD_PCM_LONG
		1433	* @retval None
		1434	*/
		1435	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
		1436	{
		1437	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
		1438	}
		1439
		1440	/**
		1441	* @brief Get I2S standard protocol
		1442	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
		1443	* I2SCFGR PCMSYNC LL_I2S_GetStandard
		1444	* @param SPIx SPI Instance
		1445	* @retval Returned value can be one of the following values:
		1446	* @arg @ref LL_I2S_STANDARD_PHILIPS
		1447	* @arg @ref LL_I2S_STANDARD_MSB
		1448	* @arg @ref LL_I2S_STANDARD_LSB
		1449	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
		1450	* @arg @ref LL_I2S_STANDARD_PCM_LONG
		1451	*/
		1452	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
		1453	{
		1454	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
		1455	}
		1456
		1457	/**
		1458	* @brief Set I2S transfer mode
		1459	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
		1460	* @param SPIx SPI Instance
		1461	* @param Mode This parameter can be one of the following values:
		1462	* @arg @ref LL_I2S_MODE_SLAVE_TX
		1463	* @arg @ref LL_I2S_MODE_SLAVE_RX
		1464	* @arg @ref LL_I2S_MODE_MASTER_TX
		1465	* @arg @ref LL_I2S_MODE_MASTER_RX
		1466	* @retval None
		1467	*/
		1468	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
		1469	{
		1470	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
		1471	}
		1472
		1473	/**
		1474	* @brief Get I2S transfer mode
		1475	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
		1476	* @param SPIx SPI Instance
		1477	* @retval Returned value can be one of the following values:
		1478	* @arg @ref LL_I2S_MODE_SLAVE_TX
		1479	* @arg @ref LL_I2S_MODE_SLAVE_RX
		1480	* @arg @ref LL_I2S_MODE_MASTER_TX
		1481	* @arg @ref LL_I2S_MODE_MASTER_RX
		1482	*/
		1483	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
		1484	{
		1485	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
		1486	}
		1487
		1488	/**
		1489	* @brief Set I2S linear prescaler
		1490	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
		1491	* @param SPIx SPI Instance
		1492	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
		1493	* @retval None
		1494	*/
		1495	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
		1496	{
		1497	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
		1498	}
		1499
		1500	/**
		1501	* @brief Get I2S linear prescaler
		1502	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
		1503	* @param SPIx SPI Instance
		1504	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
		1505	*/
		1506	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
		1507	{
		1508	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
		1509	}
		1510
		1511	/**
		1512	* @brief Set I2S parity prescaler
		1513	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
		1514	* @param SPIx SPI Instance
		1515	* @param PrescalerParity This parameter can be one of the following values:
		1516	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
		1517	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
		1518	* @retval None
		1519	*/
		1520	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
		1521	{
		1522	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
		1523	}
		1524
		1525	/**
		1526	* @brief Get I2S parity prescaler
		1527	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
		1528	* @param SPIx SPI Instance
		1529	* @retval Returned value can be one of the following values:
		1530	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
		1531	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
		1532	*/
		1533	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
		1534	{
		1535	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
		1536	}
		1537
		1538	/**
		1539	* @brief Enable the master clock output (Pin MCK)
		1540	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
		1541	* @param SPIx SPI Instance
		1542	* @retval None
		1543	*/
		1544	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
		1545	{
		1546	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
		1547	}
		1548
		1549	/**
		1550	* @brief Disable the master clock output (Pin MCK)
		1551	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
		1552	* @param SPIx SPI Instance
		1553	* @retval None
		1554	*/
		1555	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
		1556	{
		1557	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
		1558	}
		1559
		1560	/**
		1561	* @brief Check if the master clock output (Pin MCK) is enabled
		1562	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
		1563	* @param SPIx SPI Instance
		1564	* @retval State of bit (1 or 0).
		1565	*/
		1566	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
		1567	{
		1568	return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
		1569	}
		1570
		1571	/**
		1572	* @}
		1573	*/
		1574
		1575	/** @defgroup I2S_LL_EF_FLAG FLAG Management
		1576	* @{
		1577	*/
		1578
		1579	/**
		1580	* @brief Check if Rx buffer is not empty
		1581	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
		1582	* @param SPIx SPI Instance
		1583	* @retval State of bit (1 or 0).
		1584	*/
		1585	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
		1586	{
		1587	return LL_SPI_IsActiveFlag_RXNE(SPIx);
		1588	}
		1589
		1590	/**
		1591	* @brief Check if Tx buffer is empty
		1592	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
		1593	* @param SPIx SPI Instance
		1594	* @retval State of bit (1 or 0).
		1595	*/
		1596	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
		1597	{
		1598	return LL_SPI_IsActiveFlag_TXE(SPIx);
		1599	}
		1600
		1601	/**
		1602	* @brief Get busy flag
		1603	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
		1604	* @param SPIx SPI Instance
		1605	* @retval State of bit (1 or 0).
		1606	*/
		1607	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
		1608	{
		1609	return LL_SPI_IsActiveFlag_BSY(SPIx);
		1610	}
		1611
		1612	/**
		1613	* @brief Get overrun error flag
		1614	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
		1615	* @param SPIx SPI Instance
		1616	* @retval State of bit (1 or 0).
		1617	*/
		1618	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
		1619	{
		1620	return LL_SPI_IsActiveFlag_OVR(SPIx);
		1621	}
		1622
		1623	/**
		1624	* @brief Get underrun error flag
		1625	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
		1626	* @param SPIx SPI Instance
		1627	* @retval State of bit (1 or 0).
		1628	*/
		1629	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
		1630	{
		1631	return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
		1632	}
		1633
		1634
		1635	/**
		1636	* @brief Get channel side flag.
		1637	* @note 0: Channel Left has to be transmitted or has been received\n
		1638	* 1: Channel Right has to be transmitted or has been received\n
		1639	* It has no significance in PCM mode.
		1640	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
		1641	* @param SPIx SPI Instance
		1642	* @retval State of bit (1 or 0).
		1643	*/
		1644	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
		1645	{
		1646	return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
		1647	}
		1648
		1649	/**
		1650	* @brief Clear overrun error flag
		1651	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
		1652	* @param SPIx SPI Instance
		1653	* @retval None
		1654	*/
		1655	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
		1656	{
		1657	LL_SPI_ClearFlag_OVR(SPIx);
		1658	}
		1659
		1660	/**
		1661	* @brief Clear underrun error flag
		1662	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
		1663	* @param SPIx SPI Instance
		1664	* @retval None
		1665	*/
		1666	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
		1667	{
		1668	__IO uint32_t tmpreg;
		1669	tmpreg = SPIx->SR;
		1670	(void)tmpreg;
		1671	}
		1672
		1673	/**
		1674	* @brief Clear frame format error flag
		1675	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
		1676	* @param SPIx SPI Instance
		1677	* @retval None
		1678	*/
		1679	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
		1680	{
		1681	LL_SPI_ClearFlag_FRE(SPIx);
		1682	}
		1683
		1684	/**
		1685	* @}
		1686	*/
		1687
		1688	/** @defgroup I2S_LL_EF_IT Interrupt Management
		1689	* @{
		1690	*/
		1691
		1692	/**
		1693	* @brief Enable error IT
		1694	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
		1695	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
		1696	* @param SPIx SPI Instance
		1697	* @retval None
		1698	*/
		1699	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
		1700	{
		1701	LL_SPI_EnableIT_ERR(SPIx);
		1702	}
		1703
		1704	/**
		1705	* @brief Enable Rx buffer not empty IT
		1706	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
		1707	* @param SPIx SPI Instance
		1708	* @retval None
		1709	*/
		1710	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
		1711	{
		1712	LL_SPI_EnableIT_RXNE(SPIx);
		1713	}
		1714
		1715	/**
		1716	* @brief Enable Tx buffer empty IT
		1717	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
		1718	* @param SPIx SPI Instance
		1719	* @retval None
		1720	*/
		1721	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
		1722	{
		1723	LL_SPI_EnableIT_TXE(SPIx);
		1724	}
		1725
		1726	/**
		1727	* @brief Disable error IT
		1728	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
		1729	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
		1730	* @param SPIx SPI Instance
		1731	* @retval None
		1732	*/
		1733	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
		1734	{
		1735	LL_SPI_DisableIT_ERR(SPIx);
		1736	}
		1737
		1738	/**
		1739	* @brief Disable Rx buffer not empty IT
		1740	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
		1741	* @param SPIx SPI Instance
		1742	* @retval None
		1743	*/
		1744	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
		1745	{
		1746	LL_SPI_DisableIT_RXNE(SPIx);
		1747	}
		1748
		1749	/**
		1750	* @brief Disable Tx buffer empty IT
		1751	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
		1752	* @param SPIx SPI Instance
		1753	* @retval None
		1754	*/
		1755	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
		1756	{
		1757	LL_SPI_DisableIT_TXE(SPIx);
		1758	}
		1759
		1760	/**
		1761	* @brief Check if ERR IT is enabled
		1762	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
		1763	* @param SPIx SPI Instance
		1764	* @retval State of bit (1 or 0).
		1765	*/
		1766	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
		1767	{
		1768	return LL_SPI_IsEnabledIT_ERR(SPIx);
		1769	}
		1770
		1771	/**
		1772	* @brief Check if RXNE IT is enabled
		1773	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
		1774	* @param SPIx SPI Instance
		1775	* @retval State of bit (1 or 0).
		1776	*/
		1777	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
		1778	{
		1779	return LL_SPI_IsEnabledIT_RXNE(SPIx);
		1780	}
		1781
		1782	/**
		1783	* @brief Check if TXE IT is enabled
		1784	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
		1785	* @param SPIx SPI Instance
		1786	* @retval State of bit (1 or 0).
		1787	*/
		1788	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
		1789	{
		1790	return LL_SPI_IsEnabledIT_TXE(SPIx);
		1791	}
		1792
		1793	/**
		1794	* @}
		1795	*/
		1796
		1797	/** @defgroup I2S_LL_EF_DMA DMA Management
		1798	* @{
		1799	*/
		1800
		1801	/**
		1802	* @brief Enable DMA Rx
		1803	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
		1804	* @param SPIx SPI Instance
		1805	* @retval None
		1806	*/
		1807	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
		1808	{
		1809	LL_SPI_EnableDMAReq_RX(SPIx);
		1810	}
		1811
		1812	/**
		1813	* @brief Disable DMA Rx
		1814	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
		1815	* @param SPIx SPI Instance
		1816	* @retval None
		1817	*/
		1818	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
		1819	{
		1820	LL_SPI_DisableDMAReq_RX(SPIx);
		1821	}
		1822
		1823	/**
		1824	* @brief Check if DMA Rx is enabled
		1825	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
		1826	* @param SPIx SPI Instance
		1827	* @retval State of bit (1 or 0).
		1828	*/
		1829	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
		1830	{
		1831	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
		1832	}
		1833
		1834	/**
		1835	* @brief Enable DMA Tx
		1836	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
		1837	* @param SPIx SPI Instance
		1838	* @retval None
		1839	*/
		1840	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
		1841	{
		1842	LL_SPI_EnableDMAReq_TX(SPIx);
		1843	}
		1844
		1845	/**
		1846	* @brief Disable DMA Tx
		1847	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
		1848	* @param SPIx SPI Instance
		1849	* @retval None
		1850	*/
		1851	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
		1852	{
		1853	LL_SPI_DisableDMAReq_TX(SPIx);
		1854	}
		1855
		1856	/**
		1857	* @brief Check if DMA Tx is enabled
		1858	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
		1859	* @param SPIx SPI Instance
		1860	* @retval State of bit (1 or 0).
		1861	*/
		1862	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
		1863	{
		1864	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
		1865	}
		1866
		1867	/**
		1868	* @}
		1869	*/
		1870
		1871	/** @defgroup I2S_LL_EF_DATA DATA Management
		1872	* @{
		1873	*/
		1874
		1875	/**
		1876	* @brief Read 16-Bits in data register
		1877	* @rmtoll DR DR LL_I2S_ReceiveData16
		1878	* @param SPIx SPI Instance
		1879	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
		1880	*/
		1881	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
		1882	{
		1883	return LL_SPI_ReceiveData16(SPIx);
		1884	}
		1885
		1886	/**
		1887	* @brief Write 16-Bits in data register
		1888	* @rmtoll DR DR LL_I2S_TransmitData16
		1889	* @param SPIx SPI Instance
		1890	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
		1891	* @retval None
		1892	*/
		1893	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
		1894	{
		1895	LL_SPI_TransmitData16(SPIx, TxData);
		1896	}
		1897
		1898	/**
		1899	* @}
		1900	*/
		1901
		1902	#if defined(USE_FULL_LL_DRIVER)
		1903	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
		1904	* @{
		1905	*/
		1906
		1907	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
		1908	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
		1909	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
		1910	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
		1911
		1912	/**
		1913	* @}
		1914	*/
		1915	#endif /* USE_FULL_LL_DRIVER */
		1916
		1917	/**
		1918	* @}
		1919	*/
		1920
		1921	/**
		1922	* @}
		1923	*/
		1924	#endif /* SPI_I2S_SUPPORT */
		1925
		1926	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) */
		1927
		1928	/**
		1929	* @}
		1930	*/
		1931
		1932	#ifdef __cplusplus
		1933	}
		1934	#endif
		1935
		1936	#endif /* STM32F1xx_LL_SPI_H */
		1937
		1938	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h – Rev 2