WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_sdmmc.h
		4	* @author MCD Application Team
9	mjames	5	* @brief Header file of SDMMC HAL module.
2	mjames	6	******************************************************************************
		7	* @attention
		8	*
9	mjames	9	* <h2><center>© Copyright (c) 2018 STMicroelectronics.
		10	* All rights reserved.</center></h2>
2	mjames	11	*
9	mjames	12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
2	mjames	16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
9	mjames	21	#ifndef STM32F1xx_LL_SDMMC_H
		22	#define STM32F1xx_LL_SDMMC_H
2	mjames	23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
9	mjames	28	#if defined(SDIO)
		29
2	mjames	30	/* Includes ------------------------------------------------------------------*/
		31	#include "stm32f1xx_hal_def.h"
		32
9	mjames	33	/** @addtogroup STM32F1xx_Driver
2	mjames	34	* @{
		35	*/
		36
		37	/** @addtogroup SDMMC_LL
		38	* @{
		39	*/
		40
		41	/* Exported types ------------------------------------------------------------*/
		42	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
		43	* @{
		44	*/
		45
		46	/**
		47	* @brief SDMMC Configuration Structure definition
		48	*/
		49	typedef struct
		50	{
		51	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
		52	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
		53
9	mjames	54	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
2	mjames	55	enabled or disabled.
		56	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
		57
9	mjames	58	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
2	mjames	59	disabled when the bus is idle.
		60	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
		61
9	mjames	62	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
2	mjames	63	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
		64
9	mjames	65	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
2	mjames	66	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
		67
9	mjames	68	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
2	mjames	69	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
		70
		71	}SDIO_InitTypeDef;
		72
		73
		74	/**
9	mjames	75	* @brief SDMMC Command Control structure
2	mjames	76	*/
		77	typedef struct
		78	{
9	mjames	79	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
2	mjames	80	to a card as part of a command message. If a command
		81	contains an argument, it must be loaded into this register
		82	before writing the command to the command register. */
		83
9	mjames	84	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
2	mjames	85	Max_Data = 64 */
		86
9	mjames	87	uint32_t Response; /*!< Specifies the SDMMC response type.
2	mjames	88	This parameter can be a value of @ref SDMMC_LL_Response_Type */
		89
9	mjames	90	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
2	mjames	91	enabled or disabled.
		92	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
		93
9	mjames	94	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
2	mjames	95	is enabled or disabled.
		96	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
		97	}SDIO_CmdInitTypeDef;
		98
		99
		100	/**
9	mjames	101	* @brief SDMMC Data Control structure
2	mjames	102	*/
		103	typedef struct
		104	{
		105	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
		106
		107	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
		108
		109	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
		110	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
		111
		112	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
		113	is a read or write.
		114	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
		115
		116	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
		117	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
		118
9	mjames	119	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
2	mjames	120	is enabled or disabled.
		121	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
		122	}SDIO_DataInitTypeDef;
		123
		124	/**
		125	* @}
		126	*/
		127
		128	/* Exported constants --------------------------------------------------------*/
		129	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
		130	* @{
		131	*/
9	mjames	132	#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
		133	#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /!< Command response received (but CRC check failed) /
		134	#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /!< Data block sent/received (CRC check failed) /
		135	#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /!< Command response timeout /
		136	#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /!< Data timeout /
		137	#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /!< Transmit FIFO underrun /
		138	#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /!< Receive FIFO overrun /
		139	#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /!< Misaligned address /
		140	#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
		141	number of transferred bytes does not match the block length */
		142	#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /!< An error in the sequence of erase command occurs /
		143	#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /!< An invalid selection for erase groups /
		144	#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /!< Attempt to program a write protect block /
		145	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
		146	command or if there was an attempt to access a locked card */
		147	#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /!< CRC check of the previous command failed /
		148	#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /!< Command is not legal for the card state /
		149	#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /!< Card internal ECC was applied but failed to correct the data /
		150	#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /!< Internal card controller error /
		151	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /!< General or unknown error /
		152	#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /!< The card could not sustain data reading in stream rmode /
		153	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /!< The card could not sustain data programming in stream mode /
		154	#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /!< CID/CSD overwrite error /
		155	#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /!< Only partial address space was erased /
		156	#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /!< Command has been executed without using internal ECC /
		157	#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
		158	of erase sequence command was received */
		159	#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /!< Error in sequence of authentication /
		160	#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /!< Error in case of invalid voltage range /
		161	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /!< Error when addressed block is out of range /
		162	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /!< Error when command request is not applicable /
		163	#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /!< the used parameter is not valid /
		164	#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /!< Error when feature is not insupported /
		165	#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /!< Error when transfer process is busy /
		166	#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /!< Error while DMA transfer /
		167	#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /!< Timeout error /
2	mjames	168
		169	/**
		170	* @brief SDMMC Commands Index
		171	*/
9	mjames	172	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /!< Resets the SD memory card. /
		173	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /!< Sends host capacity support information and activates the card's initialization process. /
		174	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
		175	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /!< Asks the card to publish a new relative address (RCA). /
		176	#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /!< Programs the DSR of all cards. /
		177	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
		178	operating condition register (OCR) content in the response on the CMD line. */
		179	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
		180	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /!< Selects the card by its own relative address and gets deselected by any other address /
		181	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
		182	and asks the card whether card supports voltage. */
		183	#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
		184	#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /!< Addressed card sends its card identification (CID) on the CMD line. /
		185	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /!< SD card doesn't support it. /
		186	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /!< Forces the card to stop transmission. /
		187	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /!< Addressed card sends its status register. /
		188	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /!< Reserved /
		189	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /!< Sends an addressed card into the inactive state. /
		190	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
2	mjames	191	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
		192	for SDHS and SDXC. */
9	mjames	193	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
2	mjames	194	fixed 512 bytes in case of SDHC and SDXC. */
9	mjames	195	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
2	mjames	196	STOP_TRANSMISSION command. */
9	mjames	197	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
		198	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /!< Speed class control command. /
		199	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /!< Specify block count for CMD18 and CMD25. /
		200	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
2	mjames	201	fixed 512 bytes in case of SDHC and SDXC. */
9	mjames	202	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
		203	#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /!< Reserved for manufacturers. /
		204	#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /!< Programming of the programmable bits of the CSD. /
		205	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /!< Sets the write protection bit of the addressed group. /
		206	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /!< Clears the write protection bit of the addressed group. /
		207	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /!< Asks the card to send the status of the write protection bits. /
		208	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /!< Sets the address of the first write block to be erased. (For SD card only). /
		209	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /!< Sets the address of the last write block of the continuous range to be erased. /
		210	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
2	mjames	211	system set by switch function command (CMD6). */
9	mjames	212	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
2	mjames	213	Reserved for each command system set by switch function command (CMD6). */
9	mjames	214	#define SDMMC_CMD_ERASE ((uint8_t)38U) /!< Reserved for SD security applications. /
		215	#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /!< SD card doesn't support it (Reserved). /
		216	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /!< SD card doesn't support it (Reserved). /
		217	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
2	mjames	218	the SET_BLOCK_LEN command. */
9	mjames	219	#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
2	mjames	220	than a standard command. */
9	mjames	221	#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
2	mjames	222	for general purpose/application specific commands. */
9	mjames	223	#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /!< No command /
2	mjames	224
		225	/**
		226	* @brief Following commands are SD Card Specific commands.
		227	* SDMMC_APP_CMD should be sent before sending these commands.
		228	*/
9	mjames	229	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
2	mjames	230	widths are given in SCR register. */
9	mjames	231	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /!< (ACMD13) Sends the SD status. /
		232	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
2	mjames	233	32bit+CRC data block. */
9	mjames	234	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
2	mjames	235	send its operating condition register (OCR) content in the response on the CMD line. */
9	mjames	236	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
		237	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /!< Reads the SD Configuration Register (SCR). /
		238	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /!< For SD I/O card only, reserved for security specification. /
		239	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /!< For SD I/O card only, reserved for security specification. /
2	mjames	240
		241	/**
		242	* @brief Following commands are SD Card Specific security commands.
		243	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
		244	*/
9	mjames	245	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
		246	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
		247	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
		248	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
		249	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
		250	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
		251	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
		252	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
		253	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
		254	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
		255	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
2	mjames	256
		257	/**
		258	* @brief Masks for errors Card Status R1 (OCR Register)
		259	*/
9	mjames	260	#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
		261	#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
		262	#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
		263	#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
		264	#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
		265	#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
		266	#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
		267	#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
		268	#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
		269	#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
		270	#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
		271	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
		272	#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
		273	#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
		274	#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
		275	#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
		276	#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
		277	#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
		278	#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
		279	#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
2	mjames	280
		281	/**
		282	* @brief Masks for R6 Response
		283	*/
9	mjames	284	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
		285	#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
		286	#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
2	mjames	287
9	mjames	288	#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
		289	#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
		290	#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
		291	#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
		292	#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
2	mjames	293
9	mjames	294	#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
2	mjames	295
9	mjames	296	#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
2	mjames	297
9	mjames	298	#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
2	mjames	299
9	mjames	300	#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
		301	#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
		302	#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
2	mjames	303
9	mjames	304	#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
2	mjames	305
9	mjames	306	#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
		307	#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
		308	#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
		309	#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
		310	#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
		311
		312	#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
		313	#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
		314
2	mjames	315	/**
		316	* @brief Command Class supported
		317	*/
9	mjames	318	#define SDIO_CCCC_ERASE ((uint32_t)0x00000020U)
2	mjames	319
9	mjames	320	#define SDIO_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
		321	#define SDIO_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
		322	#define SDIO_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
2	mjames	323
		324	/** @defgroup SDIO_LL_Clock_Edge Clock Edge
		325	* @{
		326	*/
9	mjames	327	#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
2	mjames	328	#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
		329
		330	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
9	mjames	331	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
2	mjames	332	/**
		333	* @}
		334	*/
		335
		336	/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
		337	* @{
		338	*/
9	mjames	339	#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
2	mjames	340	#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
		341
		342	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
9	mjames	343	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
2	mjames	344	/**
		345	* @}
		346	*/
		347
		348	/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
		349	* @{
		350	*/
9	mjames	351	#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
2	mjames	352	#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
		353
		354	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
9	mjames	355	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
2	mjames	356	/**
		357	* @}
		358	*/
		359
		360	/** @defgroup SDIO_LL_Bus_Wide Bus Width
		361	* @{
		362	*/
9	mjames	363	#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000U)
2	mjames	364	#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
		365	#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
		366
		367	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
9	mjames	368	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
		369	((WIDE) == SDIO_BUS_WIDE_8B))
2	mjames	370	/**
		371	* @}
		372	*/
		373
		374	/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
		375	* @{
		376	*/
9	mjames	377	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
2	mjames	378	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
		379
		380	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
9	mjames	381	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
2	mjames	382	/**
		383	* @}
		384	*/
		385
		386	/** @defgroup SDIO_LL_Clock_Division Clock Division
		387	* @{
		388	*/
		389	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
		390	/**
		391	* @}
		392	*/
		393
		394	/** @defgroup SDIO_LL_Command_Index Command Index
		395	* @{
		396	*/
		397	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
		398	/**
		399	* @}
		400	*/
		401
		402	/** @defgroup SDIO_LL_Response_Type Response Type
		403	* @{
		404	*/
9	mjames	405	#define SDIO_RESPONSE_NO ((uint32_t)0x00000000U)
2	mjames	406	#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
		407	#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
		408
		409	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
9	mjames	410	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
		411	((RESPONSE) == SDIO_RESPONSE_LONG))
2	mjames	412	/**
		413	* @}
		414	*/
		415
		416	/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
		417	* @{
		418	*/
9	mjames	419	#define SDIO_WAIT_NO ((uint32_t)0x00000000U)
2	mjames	420	#define SDIO_WAIT_IT SDIO_CMD_WAITINT
		421	#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
		422
		423	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
9	mjames	424	((WAIT) == SDIO_WAIT_IT) \|\| \
		425	((WAIT) == SDIO_WAIT_PEND))
2	mjames	426	/**
		427	* @}
		428	*/
		429
		430	/** @defgroup SDIO_LL_CPSM_State CPSM State
		431	* @{
		432	*/
9	mjames	433	#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000U)
2	mjames	434	#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
		435
		436	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
9	mjames	437	((CPSM) == SDIO_CPSM_ENABLE))
2	mjames	438	/**
		439	* @}
		440	*/
		441
		442	/** @defgroup SDIO_LL_Response_Registers Response Register
		443	* @{
		444	*/
9	mjames	445	#define SDIO_RESP1 ((uint32_t)0x00000000U)
		446	#define SDIO_RESP2 ((uint32_t)0x00000004U)
		447	#define SDIO_RESP3 ((uint32_t)0x00000008U)
		448	#define SDIO_RESP4 ((uint32_t)0x0000000CU)
2	mjames	449
		450	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
9	mjames	451	((RESP) == SDIO_RESP2) \|\| \
		452	((RESP) == SDIO_RESP3) \|\| \
		453	((RESP) == SDIO_RESP4))
2	mjames	454	/**
		455	* @}
		456	*/
		457
		458	/** @defgroup SDIO_LL_Data_Length Data Lenght
		459	* @{
		460	*/
		461	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
		462	/**
		463	* @}
		464	*/
		465
		466	/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
		467	* @{
		468	*/
9	mjames	469	#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
2	mjames	470	#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
		471	#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
		472	#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1)
		473	#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
		474	#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2)
		475	#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
		476	#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
		477	#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
		478	#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_3)
		479	#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
		480	#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
		481	#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
		482	#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
		483	#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
		484
		485	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
9	mjames	486	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
		487	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
		488	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
		489	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
		490	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
		491	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
		492	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
		493	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
		494	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
		495	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
		496	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
		497	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
		498	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
		499	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
2	mjames	500	/**
		501	* @}
		502	*/
		503
		504	/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
		505	* @{
		506	*/
9	mjames	507	#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
		508	#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
2	mjames	509
		510	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
9	mjames	511	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
2	mjames	512	/**
		513	* @}
		514	*/
		515
		516	/** @defgroup SDIO_LL_Transfer_Type Transfer Type
		517	* @{
		518	*/
9	mjames	519	#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
2	mjames	520	#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
		521
		522	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
9	mjames	523	((MODE) == SDIO_TRANSFER_MODE_STREAM))
2	mjames	524	/**
		525	* @}
		526	*/
		527
		528	/** @defgroup SDIO_LL_DPSM_State DPSM State
		529	* @{
		530	*/
9	mjames	531	#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000U)
2	mjames	532	#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
		533
		534	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
9	mjames	535	((DPSM) == SDIO_DPSM_ENABLE))
2	mjames	536	/**
		537	* @}
		538	*/
		539
		540	/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
		541	* @{
		542	*/
9	mjames	543	#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
2	mjames	544	#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
		545
		546	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
9	mjames	547	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
2	mjames	548	/**
		549	* @}
		550	*/
		551
		552	/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
		553	* @{
		554	*/
9	mjames	555	#define SDIO_IT_CCRCFAIL SDIO_MASK_CCRCFAILIE
		556	#define SDIO_IT_DCRCFAIL SDIO_MASK_DCRCFAILIE
		557	#define SDIO_IT_CTIMEOUT SDIO_MASK_CTIMEOUTIE
		558	#define SDIO_IT_DTIMEOUT SDIO_MASK_DTIMEOUTIE
		559	#define SDIO_IT_TXUNDERR SDIO_MASK_TXUNDERRIE
		560	#define SDIO_IT_RXOVERR SDIO_MASK_RXOVERRIE
		561	#define SDIO_IT_CMDREND SDIO_MASK_CMDRENDIE
		562	#define SDIO_IT_CMDSENT SDIO_MASK_CMDSENTIE
		563	#define SDIO_IT_DATAEND SDIO_MASK_DATAENDIE
		564	#define SDIO_IT_STBITERR SDIO_MASK_STBITERRIE
		565	#define SDIO_IT_DBCKEND SDIO_MASK_DBCKENDIE
		566	#define SDIO_IT_CMDACT SDIO_MASK_CMDACTIE
		567	#define SDIO_IT_TXACT SDIO_MASK_TXACTIE
		568	#define SDIO_IT_RXACT SDIO_MASK_RXACTIE
		569	#define SDIO_IT_TXFIFOHE SDIO_MASK_TXFIFOHEIE
		570	#define SDIO_IT_RXFIFOHF SDIO_MASK_RXFIFOHFIE
		571	#define SDIO_IT_TXFIFOF SDIO_MASK_TXFIFOFIE
		572	#define SDIO_IT_RXFIFOF SDIO_MASK_RXFIFOFIE
		573	#define SDIO_IT_TXFIFOE SDIO_MASK_TXFIFOEIE
		574	#define SDIO_IT_RXFIFOE SDIO_MASK_RXFIFOEIE
		575	#define SDIO_IT_TXDAVL SDIO_MASK_TXDAVLIE
		576	#define SDIO_IT_RXDAVL SDIO_MASK_RXDAVLIE
		577	#define SDIO_IT_SDIOIT SDIO_MASK_SDIOITIE
		578	#define SDIO_IT_CEATAEND SDIO_MASK_CEATAENDIE
2	mjames	579	/**
		580	* @}
		581	*/
		582
9	mjames	583	/** @defgroup SDIO_LL_Flags Flags
2	mjames	584	* @{
		585	*/
		586	#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
		587	#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
		588	#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
		589	#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
		590	#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
		591	#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
		592	#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
		593	#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
		594	#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
		595	#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
		596	#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
		597	#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
		598	#define SDIO_FLAG_TXACT SDIO_STA_TXACT
		599	#define SDIO_FLAG_RXACT SDIO_STA_RXACT
		600	#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
		601	#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
		602	#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
		603	#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
		604	#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
		605	#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
		606	#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
		607	#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
		608	#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
		609	#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
		610	#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL \| SDIO_FLAG_DCRCFAIL \| SDIO_FLAG_CTIMEOUT \|\
		611	SDIO_FLAG_DTIMEOUT \| SDIO_FLAG_TXUNDERR \| SDIO_FLAG_RXOVERR \|\
		612	SDIO_FLAG_CMDREND \| SDIO_FLAG_CMDSENT \| SDIO_FLAG_DATAEND \|\
9	mjames	613	SDIO_FLAG_DBCKEND \| SDIO_FLAG_SDIOIT))
		614
		615	#define SDIO_STATIC_CMD_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL \| SDIO_FLAG_CTIMEOUT \| SDIO_FLAG_CMDREND \|\
		616	SDIO_FLAG_CMDSENT))
		617
		618	#define SDIO_STATIC_DATA_FLAGS ((uint32_t)(SDIO_FLAG_DCRCFAIL \| SDIO_FLAG_DTIMEOUT \| SDIO_FLAG_TXUNDERR \|\
		619	SDIO_FLAG_RXOVERR \| SDIO_FLAG_DATAEND \| SDIO_FLAG_DBCKEND))
2	mjames	620	/**
		621	* @}
		622	*/
		623
		624	/**
		625	* @}
		626	*/
		627
		628	/* Exported macro ------------------------------------------------------------*/
		629	/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
		630	* @{
		631	*/
		632
		633	/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
		634	* @{
		635	*/
		636	/* ------------ SDIO registers bit address in the alias region -------------- */
		637	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
		638
		639	/* --- CLKCR Register ---*/
		640	/* Alias word address of CLKEN bit */
		641	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
		642	#define CLKEN_BITNUMBER 0x08U
		643	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
		644
		645	/* --- CMD Register ---*/
		646	/* Alias word address of SDIOSUSPEND bit */
		647	#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
		648	#define SDIOSUSPEND_BITNUMBER 0x0BU
		649	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
		650
		651	/* Alias word address of ENCMDCOMPL bit */
		652	#define ENCMDCOMPL_BITNUMBER 0x0CU
		653	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
		654
		655	/* Alias word address of NIEN bit */
		656	#define NIEN_BITNUMBER 0x0DU
		657	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
		658
		659	/* Alias word address of ATACMD bit */
		660	#define ATACMD_BITNUMBER 0x0EU
		661	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
		662
		663	/* --- DCTRL Register ---*/
		664	/* Alias word address of DMAEN bit */
		665	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
		666	#define DMAEN_BITNUMBER 0x03U
		667	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
		668
		669	/* Alias word address of RWSTART bit */
		670	#define RWSTART_BITNUMBER 0x08U
		671	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
		672
		673	/* Alias word address of RWSTOP bit */
		674	#define RWSTOP_BITNUMBER 0x09U
		675	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
		676
		677	/* Alias word address of RWMOD bit */
		678	#define RWMOD_BITNUMBER 0x0AU
		679	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
		680
		681	/* Alias word address of SDIOEN bit */
		682	#define SDIOEN_BITNUMBER 0x0BU
		683	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
		684	/**
		685	* @}
		686	*/
		687
		688	/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
		689	* @brief SDIO_LL registers bit address in the alias region
		690	* @{
		691	*/
		692	/* ---------------------- SDIO registers bit mask --------------------------- */
		693	/* --- CLKCR Register ---*/
		694	/* CLKCR register clear mask */
		695	#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV \| SDIO_CLKCR_PWRSAV \|\
		696	SDIO_CLKCR_BYPASS \| SDIO_CLKCR_WIDBUS \|\
		697	SDIO_CLKCR_NEGEDGE \| SDIO_CLKCR_HWFC_EN))
		698
		699	/* --- DCTRL Register ---*/
		700	/* SDIO DCTRL Clear Mask */
		701	#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN \| SDIO_DCTRL_DTDIR \|\
		702	SDIO_DCTRL_DTMODE \| SDIO_DCTRL_DBLOCKSIZE))
		703
		704	/* --- CMD Register ---*/
		705	/* CMD Register clear mask */
		706	#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX \| SDIO_CMD_WAITRESP \|\
		707	SDIO_CMD_WAITINT \| SDIO_CMD_WAITPEND \|\
		708	SDIO_CMD_CPSMEN \| SDIO_CMD_SDIOSUSPEND))
		709
9	mjames	710	/* SDIO Initialization Frequency (400KHz max) */
		711	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
2	mjames	712
9	mjames	713	/* SDIO Data Transfer Frequency (25MHz max) */
		714	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4)
2	mjames	715	/**
		716	* @}
		717	*/
		718
		719	/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
		720	* @brief macros to handle interrupts and specific clock configurations
		721	* @{
		722	*/
		723
		724	/**
		725	* @brief Enable the SDIO device.
		726	* @param __INSTANCE__: SDIO Instance
		727	* @retval None
9	mjames	728	*/
2	mjames	729	#define __SDIO_ENABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
		730
		731	/**
		732	* @brief Disable the SDIO device.
		733	* @param __INSTANCE__: SDIO Instance
		734	* @retval None
		735	*/
		736	#define __SDIO_DISABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
		737
		738	/**
		739	* @brief Enable the SDIO DMA transfer.
		740	* @param __INSTANCE__: SDIO Instance
		741	* @retval None
9	mjames	742	*/
2	mjames	743	#define __SDIO_DMA_ENABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
9	mjames	744
2	mjames	745	/**
		746	* @brief Disable the SDIO DMA transfer.
		747	* @param __INSTANCE__: SDIO Instance
		748	* @retval None
		749	*/
		750	#define __SDIO_DMA_DISABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
		751
		752	/**
		753	* @brief Enable the SDIO device interrupt.
		754	* @param __INSTANCE__ : Pointer to SDIO register base
		755	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
		756	* This parameter can be one or a combination of the following values:
		757	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
		758	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
		759	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
		760	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
		761	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
		762	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
		763	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
		764	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
9	mjames	765	* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
2	mjames	766	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
		767	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
		768	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
		769	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
		770	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
		771	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
		772	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
		773	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
		774	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
		775	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
		776	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
		777	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
9	mjames	778	* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
2	mjames	779	* @retval None
		780	*/
		781	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
		782
		783	/**
		784	* @brief Disable the SDIO device interrupt.
		785	* @param __INSTANCE__ : Pointer to SDIO register base
		786	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
		787	* This parameter can be one or a combination of the following values:
		788	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
		789	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
		790	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
		791	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
		792	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
		793	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
		794	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
		795	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
9	mjames	796	* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
2	mjames	797	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
		798	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
		799	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
		800	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
		801	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
		802	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
		803	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
		804	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
		805	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
		806	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
		807	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
		808	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
9	mjames	809	* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
2	mjames	810	* @retval None
		811	*/
		812	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
		813
		814	/**
		815	* @brief Checks whether the specified SDIO flag is set or not.
		816	* @param __INSTANCE__ : Pointer to SDIO register base
		817	* @param __FLAG__: specifies the flag to check.
		818	* This parameter can be one of the following values:
		819	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
		820	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
		821	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
		822	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
		823	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
		824	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
		825	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
		826	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
9	mjames	827	* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
2	mjames	828	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
		829	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
		830	* @arg SDIO_FLAG_TXACT: Data transmit in progress
		831	* @arg SDIO_FLAG_RXACT: Data receive in progress
		832	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
		833	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
		834	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
		835	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
		836	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
		837	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
		838	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
		839	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
9	mjames	840	* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
2	mjames	841	* @retval The new state of SDIO_FLAG (SET or RESET).
		842	*/
9	mjames	843	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
2	mjames	844
		845
		846	/**
		847	* @brief Clears the SDIO pending flags.
		848	* @param __INSTANCE__ : Pointer to SDIO register base
		849	* @param __FLAG__: specifies the flag to clear.
		850	* This parameter can be one or a combination of the following values:
		851	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
		852	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
		853	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
		854	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
		855	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
		856	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
		857	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
		858	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
9	mjames	859	* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
2	mjames	860	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
9	mjames	861	* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
2	mjames	862	* @retval None
		863	*/
		864	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
		865
		866	/**
		867	* @brief Checks whether the specified SDIO interrupt has occurred or not.
		868	* @param __INSTANCE__ : Pointer to SDIO register base
		869	* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
		870	* This parameter can be one of the following values:
		871	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
		872	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
		873	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
		874	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
		875	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
		876	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
		877	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
		878	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
9	mjames	879	* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
2	mjames	880	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
		881	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
		882	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
		883	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
		884	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
		885	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
		886	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
		887	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
		888	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
		889	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
		890	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
		891	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
9	mjames	892	* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
2	mjames	893	* @retval The new state of SDIO_IT (SET or RESET).
		894	*/
		895	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
		896
		897	/**
		898	* @brief Clears the SDIO's interrupt pending bits.
		899	* @param __INSTANCE__ : Pointer to SDIO register base
		900	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
		901	* This parameter can be one or a combination of the following values:
		902	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
		903	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
		904	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
		905	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
		906	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
		907	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
		908	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
		909	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
9	mjames	910	* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
		911	* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
2	mjames	912	* @retval None
		913	*/
		914	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
		915
		916	/**
		917	* @brief Enable Start the SD I/O Read Wait operation.
		918	* @param __INSTANCE__ : Pointer to SDIO register base
		919	* @retval None
9	mjames	920	*/
2	mjames	921	#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
		922
		923	/**
		924	* @brief Disable Start the SD I/O Read Wait operations.
		925	* @param __INSTANCE__ : Pointer to SDIO register base
		926	* @retval None
9	mjames	927	*/
2	mjames	928	#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
		929
		930	/**
		931	* @brief Enable Start the SD I/O Read Wait operation.
		932	* @param __INSTANCE__ : Pointer to SDIO register base
		933	* @retval None
9	mjames	934	*/
2	mjames	935	#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
		936
		937	/**
		938	* @brief Disable Stop the SD I/O Read Wait operations.
		939	* @param __INSTANCE__ : Pointer to SDIO register base
		940	* @retval None
9	mjames	941	*/
2	mjames	942	#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
		943
		944	/**
		945	* @brief Enable the SD I/O Mode Operation.
		946	* @param __INSTANCE__ : Pointer to SDIO register base
		947	* @retval None
9	mjames	948	*/
2	mjames	949	#define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
		950
		951	/**
		952	* @brief Disable the SD I/O Mode Operation.
		953	* @param __INSTANCE__ : Pointer to SDIO register base
		954	* @retval None
9	mjames	955	*/
2	mjames	956	#define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
		957
		958	/**
		959	* @brief Enable the SD I/O Suspend command sending.
		960	* @param __INSTANCE__ : Pointer to SDIO register base
		961	* @retval None
9	mjames	962	*/
2	mjames	963	#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
		964
		965	/**
		966	* @brief Disable the SD I/O Suspend command sending.
		967	* @param __INSTANCE__ : Pointer to SDIO register base
		968	* @retval None
9	mjames	969	*/
2	mjames	970	#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
9	mjames	971
2	mjames	972	/**
		973	* @brief Enable the command completion signal.
		974	* @retval None
		975	*/
		976	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
		977
		978	/**
		979	* @brief Disable the command completion signal.
		980	* @retval None
		981	*/
		982	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
		983
		984	/**
		985	* @brief Enable the CE-ATA interrupt.
		986	* @retval None
		987	*/
		988	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0U)
		989
		990	/**
		991	* @brief Disable the CE-ATA interrupt.
		992	* @retval None
		993	*/
		994	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1U)
		995
		996	/**
		997	* @brief Enable send CE-ATA command (CMD61).
		998	* @retval None
		999	*/
		1000	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
		1001
		1002	/**
		1003	* @brief Disable send CE-ATA command (CMD61).
		1004	* @retval None
		1005	*/
		1006	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
9	mjames	1007
2	mjames	1008	/**
		1009	* @}
		1010	*/
		1011
		1012	/**
		1013	* @}
9	mjames	1014	*/
2	mjames	1015
		1016	/* Exported functions --------------------------------------------------------*/
		1017	/** @addtogroup SDMMC_LL_Exported_Functions
		1018	* @{
		1019	*/
		1020
		1021	/* Initialization/de-initialization functions **********************************/
		1022	/** @addtogroup HAL_SDMMC_LL_Group1
		1023	* @{
		1024	*/
		1025	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
		1026	/**
		1027	* @}
		1028	*/
9	mjames	1029
2	mjames	1030	/* I/O operation functions *****************************************************/
		1031	/** @addtogroup HAL_SDMMC_LL_Group2
		1032	* @{
		1033	*/
		1034	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
		1035	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
		1036	/**
		1037	* @}
		1038	*/
		1039
		1040	/* Peripheral Control functions ************************************************/
		1041	/** @addtogroup HAL_SDMMC_LL_Group3
		1042	* @{
		1043	*/
		1044	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
		1045	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
		1046	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
		1047
		1048	/* Command path state machine (CPSM) management functions */
		1049	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef Command);
		1050	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
		1051	uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
		1052
		1053	/* Data path state machine (DPSM) management functions */
		1054	HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef Data);
		1055	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
		1056	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
		1057
		1058	/* SDMMC Cards mode management functions */
		1059	HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
		1060
		1061	/* SDMMC Commands management functions */
		1062	uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
		1063	uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
		1064	uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
		1065	uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
		1066	uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
9	mjames	1067	uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
2	mjames	1068	uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
9	mjames	1069	uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
2	mjames	1070	uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
		1071	uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
		1072	uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
		1073	uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
		1074	uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
		1075	uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
		1076	uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
9	mjames	1077	uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
2	mjames	1078	uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
		1079	uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
		1080	uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
		1081	uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
		1082	uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef SDIOx, uint16_t pRCA);
		1083	uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
		1084	uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
		1085	uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
		1086	uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
		1087
		1088	/**
		1089	* @}
		1090	*/
		1091
		1092	/**
		1093	* @}
		1094	*/
		1095
		1096	/**
		1097	* @}
		1098	*/
		1099
		1100	/**
		1101	* @}
		1102	*/
9	mjames	1103
		1104	#endif /* SDIO */
		1105
2	mjames	1106	#ifdef __cplusplus
		1107	}
		1108	#endif
		1109
9	mjames	1110	#endif /* STM32F1xx_LL_SDMMC_H */
2	mjames	1111
		1112	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h – Rev 9