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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_sdmmc.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of low layer SDMMC HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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| 10 | * |
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| 11 | * Redistribution and use in source and binary forms, with or without modification, |
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| 12 | * are permitted provided that the following conditions are met: |
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| 13 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 14 | * this list of conditions and the following disclaimer. |
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| 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 16 | * this list of conditions and the following disclaimer in the documentation |
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| 17 | * and/or other materials provided with the distribution. |
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| 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 19 | * may be used to endorse or promote products derived from this software |
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| 20 | * without specific prior written permission. |
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| 21 | * |
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| 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 32 | * |
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| 33 | ****************************************************************************** |
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| 34 | */ |
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| 35 | |||
| 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 37 | #ifndef __stm32f1xx_LL_SD_H |
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| 38 | #define __stm32f1xx_LL_SD_H |
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| 39 | |||
| 40 | #if defined(STM32F103xE) || defined(STM32F103xG) |
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| 41 | |||
| 42 | #ifdef __cplusplus |
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| 43 | extern "C" { |
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| 44 | #endif |
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| 45 | |||
| 46 | /* Includes ------------------------------------------------------------------*/ |
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| 47 | #include "stm32f1xx_hal_def.h" |
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| 48 | |||
| 49 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 50 | * @{ |
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| 51 | */ |
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| 52 | |||
| 53 | /** @addtogroup SDMMC_LL |
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| 54 | * @{ |
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| 55 | */ |
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| 56 | |||
| 57 | /* Exported types ------------------------------------------------------------*/ |
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| 58 | /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types |
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| 59 | * @{ |
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| 60 | */ |
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| 61 | |||
| 62 | /** |
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| 63 | * @brief SDMMC Configuration Structure definition |
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| 64 | */ |
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| 65 | typedef struct |
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| 66 | { |
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| 67 | uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. |
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| 68 | This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ |
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| 69 | |||
| 70 | uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is |
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| 71 | enabled or disabled. |
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| 72 | This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ |
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| 73 | |||
| 74 | uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or |
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| 75 | disabled when the bus is idle. |
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| 76 | This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ |
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| 77 | |||
| 78 | uint32_t BusWide; /*!< Specifies the SDIO bus width. |
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| 79 | This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ |
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| 80 | |||
| 81 | uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. |
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| 82 | This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ |
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| 83 | |||
| 84 | uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. |
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| 85 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
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| 86 | |||
| 87 | }SDIO_InitTypeDef; |
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| 88 | |||
| 89 | |||
| 90 | /** |
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| 91 | * @brief SDIO Command Control structure |
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| 92 | */ |
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| 93 | typedef struct |
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| 94 | { |
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| 95 | uint32_t Argument; /*!< Specifies the SDIO command argument which is sent |
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| 96 | to a card as part of a command message. If a command |
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| 97 | contains an argument, it must be loaded into this register |
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| 98 | before writing the command to the command register. */ |
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| 99 | |||
| 100 | uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and |
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| 101 | Max_Data = 64 */ |
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| 102 | |||
| 103 | uint32_t Response; /*!< Specifies the SDIO response type. |
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| 104 | This parameter can be a value of @ref SDMMC_LL_Response_Type */ |
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| 105 | |||
| 106 | uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is |
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| 107 | enabled or disabled. |
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| 108 | This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ |
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| 109 | |||
| 110 | uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) |
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| 111 | is enabled or disabled. |
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| 112 | This parameter can be a value of @ref SDMMC_LL_CPSM_State */ |
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| 113 | }SDIO_CmdInitTypeDef; |
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| 114 | |||
| 115 | |||
| 116 | /** |
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| 117 | * @brief SDIO Data Control structure |
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| 118 | */ |
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| 119 | typedef struct |
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| 120 | { |
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| 121 | uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ |
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| 122 | |||
| 123 | uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ |
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| 124 | |||
| 125 | uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. |
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| 126 | This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ |
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| 127 | |||
| 128 | uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer |
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| 129 | is a read or write. |
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| 130 | This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ |
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| 131 | |||
| 132 | uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. |
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| 133 | This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ |
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| 134 | |||
| 135 | uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) |
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| 136 | is enabled or disabled. |
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| 137 | This parameter can be a value of @ref SDMMC_LL_DPSM_State */ |
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| 138 | }SDIO_DataInitTypeDef; |
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| 139 | |||
| 140 | /** |
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| 141 | * @} |
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| 142 | */ |
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| 143 | |||
| 144 | /* Exported constants --------------------------------------------------------*/ |
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| 145 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
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| 146 | * @{ |
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| 147 | */ |
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| 148 | #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ |
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| 149 | #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ |
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| 150 | #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ |
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| 151 | #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ |
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| 152 | #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ |
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| 153 | #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ |
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| 154 | #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ |
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| 155 | #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ |
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| 156 | #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the |
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| 157 | number of transferred bytes does not match the block length */ |
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| 158 | #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ |
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| 159 | #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ |
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| 160 | #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ |
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| 161 | #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock |
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| 162 | command or if there was an attempt to access a locked card */ |
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| 163 | #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ |
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| 164 | #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ |
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| 165 | #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ |
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| 166 | #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ |
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| 167 | #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ |
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| 168 | #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ |
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| 169 | #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ |
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| 170 | #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ |
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| 171 | #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ |
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| 172 | #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ |
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| 173 | #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out |
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| 174 | of erase sequence command was received */ |
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| 175 | #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ |
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| 176 | #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ |
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| 177 | #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ |
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| 178 | #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ |
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| 179 | #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ |
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| 180 | #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ |
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| 181 | #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ |
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| 182 | #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ |
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| 183 | #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ |
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| 184 | |||
| 185 | /** |
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| 186 | * @brief SDMMC Commands Index |
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| 187 | */ |
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| 188 | #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ |
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| 189 | #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ |
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| 190 | #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ |
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| 191 | #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ |
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| 192 | #define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ |
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| 193 | #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its |
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| 194 | operating condition register (OCR) content in the response on the CMD line. */ |
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| 195 | #define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ |
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| 196 | #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ |
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| 197 | #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information |
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| 198 | and asks the card whether card supports voltage. */ |
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| 199 | #define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ |
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| 200 | #define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ |
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| 201 | #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ |
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| 202 | #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ |
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| 203 | #define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ |
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| 204 | #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */ |
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| 205 | #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ |
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| 206 | #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands |
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| 207 | (read, write, lock). Default block length is fixed to 512 Bytes. Not effective |
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| 208 | for SDHS and SDXC. */ |
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| 209 | #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
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| 210 | fixed 512 bytes in case of SDHC and SDXC. */ |
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| 211 | #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by |
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| 212 | STOP_TRANSMISSION command. */ |
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| 213 | #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ |
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| 214 | #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ |
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| 215 | #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ |
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| 216 | #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
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| 217 | fixed 512 bytes in case of SDHC and SDXC. */ |
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| 218 | #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ |
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| 219 | #define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ |
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| 220 | #define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ |
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| 221 | #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ |
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| 222 | #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ |
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| 223 | #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ |
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| 224 | #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ |
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| 225 | #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ |
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| 226 | #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command |
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| 227 | system set by switch function command (CMD6). */ |
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| 228 | #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. |
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| 229 | Reserved for each command system set by switch function command (CMD6). */ |
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| 230 | #define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ |
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| 231 | #define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ |
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| 232 | #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ |
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| 233 | #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by |
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| 234 | the SET_BLOCK_LEN command. */ |
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| 235 | #define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather |
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| 236 | than a standard command. */ |
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| 237 | #define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card |
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| 238 | for general purpose/application specific commands. */ |
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| 239 | #define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */ |
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| 240 | |||
| 241 | /** |
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| 242 | * @brief Following commands are SD Card Specific commands. |
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| 243 | * SDMMC_APP_CMD should be sent before sending these commands. |
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| 244 | */ |
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| 245 | #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus |
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| 246 | widths are given in SCR register. */ |
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| 247 | #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ |
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| 248 | #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with |
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| 249 | 32bit+CRC data block. */ |
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| 250 | #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to |
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| 251 | send its operating condition register (OCR) content in the response on the CMD line. */ |
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| 252 | #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ |
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| 253 | #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ |
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| 254 | #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ |
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| 255 | #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ |
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| 256 | |||
| 257 | /** |
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| 258 | * @brief Following commands are SD Card Specific security commands. |
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| 259 | * SDMMC_CMD_APP_CMD should be sent before sending these commands. |
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| 260 | */ |
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| 261 | #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43) |
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| 262 | #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44) |
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| 263 | #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) |
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| 264 | #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) |
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| 265 | #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) |
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| 266 | #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) |
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| 267 | #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) |
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| 268 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) |
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| 269 | #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) |
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| 270 | #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) |
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| 271 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) |
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| 272 | |||
| 273 | /** |
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| 274 | * @brief Masks for errors Card Status R1 (OCR Register) |
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| 275 | */ |
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| 276 | #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U |
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| 277 | #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U |
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| 278 | #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U |
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| 279 | #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U |
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| 280 | #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U |
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| 281 | #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U |
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| 282 | #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U |
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| 283 | #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U |
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| 284 | #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U |
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| 285 | #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U |
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| 286 | #define SDMMC_OCR_CC_ERROR 0x00100000U |
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| 287 | #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U |
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| 288 | #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U |
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| 289 | #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U |
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| 290 | #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U |
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| 291 | #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U |
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| 292 | #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U |
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| 293 | #define SDMMC_OCR_ERASE_RESET 0x00002000U |
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| 294 | #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U |
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| 295 | #define SDMMC_OCR_ERRORBITS 0xFDFFE008U |
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| 296 | |||
| 297 | /** |
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| 298 | * @brief Masks for R6 Response |
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| 299 | */ |
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| 300 | #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U |
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| 301 | #define SDMMC_R6_ILLEGAL_CMD 0x00004000U |
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| 302 | #define SDMMC_R6_COM_CRC_FAILED 0x00008000U |
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| 303 | |||
| 304 | #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U |
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| 305 | #define SDMMC_HIGH_CAPACITY 0x40000000U |
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| 306 | #define SDMMC_STD_CAPACITY 0x00000000U |
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| 307 | #define SDMMC_CHECK_PATTERN 0x000001AAU |
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| 308 | |||
| 309 | #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU |
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| 310 | |||
| 311 | #define SDMMC_MAX_TRIAL 0x0000FFFFU |
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| 312 | |||
| 313 | #define SDMMC_ALLZERO 0x00000000U |
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| 314 | |||
| 315 | #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U |
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| 316 | #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U |
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| 317 | #define SDMMC_CARD_LOCKED 0x02000000U |
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| 318 | |||
| 319 | #define SDMMC_DATATIMEOUT 0xFFFFFFFFU |
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| 320 | |||
| 321 | #define SDMMC_0TO7BITS 0x000000FFU |
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| 322 | #define SDMMC_8TO15BITS 0x0000FF00U |
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| 323 | #define SDMMC_16TO23BITS 0x00FF0000U |
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| 324 | #define SDMMC_24TO31BITS 0xFF000000U |
||
| 325 | #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU |
||
| 326 | |||
| 327 | #define SDMMC_HALFFIFO 0x00000008U |
||
| 328 | #define SDMMC_HALFFIFOBYTES 0x00000020U |
||
| 329 | |||
| 330 | /** |
||
| 331 | * @brief Command Class supported |
||
| 332 | */ |
||
| 333 | #define SDIO_CCCC_ERASE 0x00000020U |
||
| 334 | |||
| 335 | #define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */ |
||
| 336 | #define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ |
||
| 337 | |||
| 338 | |||
| 339 | /** @defgroup SDIO_LL_Clock_Edge Clock Edge |
||
| 340 | * @{ |
||
| 341 | */ |
||
| 342 | #define SDIO_CLOCK_EDGE_RISING 0x00000000U |
||
| 343 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
||
| 344 | |||
| 345 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
||
| 346 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
||
| 347 | /** |
||
| 348 | * @} |
||
| 349 | */ |
||
| 350 | |||
| 351 | /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass |
||
| 352 | * @{ |
||
| 353 | */ |
||
| 354 | #define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U |
||
| 355 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
||
| 356 | |||
| 357 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
||
| 358 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
||
| 359 | /** |
||
| 360 | * @} |
||
| 361 | */ |
||
| 362 | |||
| 363 | /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving |
||
| 364 | * @{ |
||
| 365 | */ |
||
| 366 | #define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U |
||
| 367 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
||
| 368 | |||
| 369 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
||
| 370 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
||
| 371 | /** |
||
| 372 | * @} |
||
| 373 | */ |
||
| 374 | |||
| 375 | /** @defgroup SDIO_LL_Bus_Wide Bus Width |
||
| 376 | * @{ |
||
| 377 | */ |
||
| 378 | #define SDIO_BUS_WIDE_1B 0x00000000U |
||
| 379 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
||
| 380 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
||
| 381 | |||
| 382 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
||
| 383 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
||
| 384 | ((WIDE) == SDIO_BUS_WIDE_8B)) |
||
| 385 | /** |
||
| 386 | * @} |
||
| 387 | */ |
||
| 388 | |||
| 389 | /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control |
||
| 390 | * @{ |
||
| 391 | */ |
||
| 392 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U |
||
| 393 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
||
| 394 | |||
| 395 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
||
| 396 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
||
| 397 | /** |
||
| 398 | * @} |
||
| 399 | */ |
||
| 400 | |||
| 401 | /** @defgroup SDIO_LL_Clock_Division Clock Division |
||
| 402 | * @{ |
||
| 403 | */ |
||
| 404 | #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU) |
||
| 405 | /** |
||
| 406 | * @} |
||
| 407 | */ |
||
| 408 | |||
| 409 | /** @defgroup SDIO_LL_Command_Index Command Index |
||
| 410 | * @{ |
||
| 411 | */ |
||
| 412 | #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U) |
||
| 413 | /** |
||
| 414 | * @} |
||
| 415 | */ |
||
| 416 | |||
| 417 | /** @defgroup SDIO_LL_Response_Type Response Type |
||
| 418 | * @{ |
||
| 419 | */ |
||
| 420 | #define SDIO_RESPONSE_NO 0x00000000U |
||
| 421 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
||
| 422 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
||
| 423 | |||
| 424 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
||
| 425 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
||
| 426 | ((RESPONSE) == SDIO_RESPONSE_LONG)) |
||
| 427 | /** |
||
| 428 | * @} |
||
| 429 | */ |
||
| 430 | |||
| 431 | /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt |
||
| 432 | * @{ |
||
| 433 | */ |
||
| 434 | #define SDIO_WAIT_NO 0x00000000U |
||
| 435 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
||
| 436 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
||
| 437 | |||
| 438 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
||
| 439 | ((WAIT) == SDIO_WAIT_IT) || \ |
||
| 440 | ((WAIT) == SDIO_WAIT_PEND)) |
||
| 441 | /** |
||
| 442 | * @} |
||
| 443 | */ |
||
| 444 | |||
| 445 | /** @defgroup SDIO_LL_CPSM_State CPSM State |
||
| 446 | * @{ |
||
| 447 | */ |
||
| 448 | #define SDIO_CPSM_DISABLE 0x00000000U |
||
| 449 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
||
| 450 | |||
| 451 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
||
| 452 | ((CPSM) == SDIO_CPSM_ENABLE)) |
||
| 453 | /** |
||
| 454 | * @} |
||
| 455 | */ |
||
| 456 | |||
| 457 | /** @defgroup SDIO_LL_Response_Registers Response Register |
||
| 458 | * @{ |
||
| 459 | */ |
||
| 460 | #define SDIO_RESP1 0x00000000U |
||
| 461 | #define SDIO_RESP2 0x00000004U |
||
| 462 | #define SDIO_RESP3 0x00000008U |
||
| 463 | #define SDIO_RESP4 0x0000000CU |
||
| 464 | |||
| 465 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
||
| 466 | ((RESP) == SDIO_RESP2) || \ |
||
| 467 | ((RESP) == SDIO_RESP3) || \ |
||
| 468 | ((RESP) == SDIO_RESP4)) |
||
| 469 | /** |
||
| 470 | * @} |
||
| 471 | */ |
||
| 472 | |||
| 473 | /** @defgroup SDIO_LL_Data_Length Data Lenght |
||
| 474 | * @{ |
||
| 475 | */ |
||
| 476 | #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) |
||
| 477 | /** |
||
| 478 | * @} |
||
| 479 | */ |
||
| 480 | |||
| 481 | /** @defgroup SDIO_LL_Data_Block_Size Data Block Size |
||
| 482 | * @{ |
||
| 483 | */ |
||
| 484 | #define SDIO_DATABLOCK_SIZE_1B 0x00000000U |
||
| 485 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
||
| 486 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
||
| 487 | #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) |
||
| 488 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
||
| 489 | #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) |
||
| 490 | #define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) |
||
| 491 | #define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) |
||
| 492 | #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 |
||
| 493 | #define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3) |
||
| 494 | #define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) |
||
| 495 | #define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) |
||
| 496 | #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
||
| 497 | #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
||
| 498 | #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
||
| 499 | |||
| 500 | #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ |
||
| 501 | ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ |
||
| 502 | ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ |
||
| 503 | ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ |
||
| 504 | ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ |
||
| 505 | ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ |
||
| 506 | ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ |
||
| 507 | ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ |
||
| 508 | ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ |
||
| 509 | ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ |
||
| 510 | ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ |
||
| 511 | ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ |
||
| 512 | ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ |
||
| 513 | ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ |
||
| 514 | ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) |
||
| 515 | /** |
||
| 516 | * @} |
||
| 517 | */ |
||
| 518 | |||
| 519 | /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction |
||
| 520 | * @{ |
||
| 521 | */ |
||
| 522 | #define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U |
||
| 523 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
||
| 524 | |||
| 525 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
||
| 526 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
||
| 527 | /** |
||
| 528 | * @} |
||
| 529 | */ |
||
| 530 | |||
| 531 | /** @defgroup SDIO_LL_Transfer_Type Transfer Type |
||
| 532 | * @{ |
||
| 533 | */ |
||
| 534 | #define SDIO_TRANSFER_MODE_BLOCK 0x00000000U |
||
| 535 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
||
| 536 | |||
| 537 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
||
| 538 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
||
| 539 | /** |
||
| 540 | * @} |
||
| 541 | */ |
||
| 542 | |||
| 543 | /** @defgroup SDIO_LL_DPSM_State DPSM State |
||
| 544 | * @{ |
||
| 545 | */ |
||
| 546 | #define SDIO_DPSM_DISABLE 0x00000000U |
||
| 547 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
||
| 548 | |||
| 549 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
||
| 550 | ((DPSM) == SDIO_DPSM_ENABLE)) |
||
| 551 | /** |
||
| 552 | * @} |
||
| 553 | */ |
||
| 554 | |||
| 555 | /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode |
||
| 556 | * @{ |
||
| 557 | */ |
||
| 558 | #define SDIO_READ_WAIT_MODE_DATA2 0x00000000U |
||
| 559 | #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) |
||
| 560 | |||
| 561 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
||
| 562 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
||
| 563 | /** |
||
| 564 | * @} |
||
| 565 | */ |
||
| 566 | |||
| 567 | /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources |
||
| 568 | * @{ |
||
| 569 | */ |
||
| 570 | #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL |
||
| 571 | #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL |
||
| 572 | #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT |
||
| 573 | #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT |
||
| 574 | #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR |
||
| 575 | #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR |
||
| 576 | #define SDIO_IT_CMDREND SDIO_STA_CMDREND |
||
| 577 | #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT |
||
| 578 | #define SDIO_IT_DATAEND SDIO_STA_DATAEND |
||
| 579 | #define SDIO_IT_STBITERR SDIO_STA_STBITERR |
||
| 580 | #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND |
||
| 581 | #define SDIO_IT_CMDACT SDIO_STA_CMDACT |
||
| 582 | #define SDIO_IT_TXACT SDIO_STA_TXACT |
||
| 583 | #define SDIO_IT_RXACT SDIO_STA_RXACT |
||
| 584 | #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE |
||
| 585 | #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF |
||
| 586 | #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF |
||
| 587 | #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF |
||
| 588 | #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE |
||
| 589 | #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE |
||
| 590 | #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL |
||
| 591 | #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL |
||
| 592 | #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT |
||
| 593 | #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND |
||
| 594 | /** |
||
| 595 | * @} |
||
| 596 | */ |
||
| 597 | |||
| 598 | /** @defgroup SDMMC_LL_Flags Flags |
||
| 599 | * @{ |
||
| 600 | */ |
||
| 601 | #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL |
||
| 602 | #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL |
||
| 603 | #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT |
||
| 604 | #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT |
||
| 605 | #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR |
||
| 606 | #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR |
||
| 607 | #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND |
||
| 608 | #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT |
||
| 609 | #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND |
||
| 610 | #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR |
||
| 611 | #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND |
||
| 612 | #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT |
||
| 613 | #define SDIO_FLAG_TXACT SDIO_STA_TXACT |
||
| 614 | #define SDIO_FLAG_RXACT SDIO_STA_RXACT |
||
| 615 | #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE |
||
| 616 | #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF |
||
| 617 | #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF |
||
| 618 | #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF |
||
| 619 | #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE |
||
| 620 | #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE |
||
| 621 | #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL |
||
| 622 | #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL |
||
| 623 | #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT |
||
| 624 | #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND |
||
| 625 | #define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ |
||
| 626 | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ |
||
| 627 | SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ |
||
| 628 | SDIO_FLAG_DBCKEND)) |
||
| 629 | /** |
||
| 630 | * @} |
||
| 631 | */ |
||
| 632 | |||
| 633 | /** |
||
| 634 | * @} |
||
| 635 | */ |
||
| 636 | |||
| 637 | /* Exported macro ------------------------------------------------------------*/ |
||
| 638 | /** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros |
||
| 639 | * @{ |
||
| 640 | */ |
||
| 641 | |||
| 642 | /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region |
||
| 643 | * @{ |
||
| 644 | */ |
||
| 645 | /* ------------ SDIO registers bit address in the alias region -------------- */ |
||
| 646 | #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) |
||
| 647 | |||
| 648 | /* --- CLKCR Register ---*/ |
||
| 649 | /* Alias word address of CLKEN bit */ |
||
| 650 | #define CLKCR_OFFSET (SDIO_OFFSET + 0x04U) |
||
| 651 | #define CLKEN_BITNUMBER 0x08U |
||
| 652 | #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U)) |
||
| 653 | |||
| 654 | /* --- CMD Register ---*/ |
||
| 655 | /* Alias word address of SDIOSUSPEND bit */ |
||
| 656 | #define CMD_OFFSET (SDIO_OFFSET + 0x0CU) |
||
| 657 | #define SDIOSUSPEND_BITNUMBER 0x0BU |
||
| 658 | #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U)) |
||
| 659 | |||
| 660 | /* Alias word address of ENCMDCOMPL bit */ |
||
| 661 | #define ENCMDCOMPL_BITNUMBER 0x0CU |
||
| 662 | #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U)) |
||
| 663 | |||
| 664 | /* Alias word address of NIEN bit */ |
||
| 665 | #define NIEN_BITNUMBER 0x0DU |
||
| 666 | #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U)) |
||
| 667 | |||
| 668 | /* Alias word address of ATACMD bit */ |
||
| 669 | #define ATACMD_BITNUMBER 0x0EU |
||
| 670 | #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U)) |
||
| 671 | |||
| 672 | /* --- DCTRL Register ---*/ |
||
| 673 | /* Alias word address of DMAEN bit */ |
||
| 674 | #define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU) |
||
| 675 | #define DMAEN_BITNUMBER 0x03U |
||
| 676 | #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U)) |
||
| 677 | |||
| 678 | /* Alias word address of RWSTART bit */ |
||
| 679 | #define RWSTART_BITNUMBER 0x08U |
||
| 680 | #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U)) |
||
| 681 | |||
| 682 | /* Alias word address of RWSTOP bit */ |
||
| 683 | #define RWSTOP_BITNUMBER 0x09U |
||
| 684 | #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U)) |
||
| 685 | |||
| 686 | /* Alias word address of RWMOD bit */ |
||
| 687 | #define RWMOD_BITNUMBER 0x0AU |
||
| 688 | #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U)) |
||
| 689 | |||
| 690 | /* Alias word address of SDIOEN bit */ |
||
| 691 | #define SDIOEN_BITNUMBER 0x0BU |
||
| 692 | #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U)) |
||
| 693 | /** |
||
| 694 | * @} |
||
| 695 | */ |
||
| 696 | |||
| 697 | /** @defgroup SDIO_LL_Register Bits And Addresses Definitions |
||
| 698 | * @brief SDIO_LL registers bit address in the alias region |
||
| 699 | * @{ |
||
| 700 | */ |
||
| 701 | /* ---------------------- SDIO registers bit mask --------------------------- */ |
||
| 702 | /* --- CLKCR Register ---*/ |
||
| 703 | /* CLKCR register clear mask */ |
||
| 704 | #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ |
||
| 705 | SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ |
||
| 706 | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) |
||
| 707 | |||
| 708 | /* --- DCTRL Register ---*/ |
||
| 709 | /* SDIO DCTRL Clear Mask */ |
||
| 710 | #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ |
||
| 711 | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) |
||
| 712 | |||
| 713 | /* --- CMD Register ---*/ |
||
| 714 | /* CMD Register clear mask */ |
||
| 715 | #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ |
||
| 716 | SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ |
||
| 717 | SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) |
||
| 718 | |||
| 719 | /* SDIO RESP Registers Address */ |
||
| 720 | #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) |
||
| 721 | |||
| 722 | /* SDIO Intialization Frequency (400KHz max) */ |
||
| 723 | #define SDIO_INIT_CLK_DIV ((uint8_t)0xC3) |
||
| 724 | |||
| 725 | /* SDIO Data Transfer Frequency */ |
||
| 726 | #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x9) |
||
| 727 | |||
| 728 | /** |
||
| 729 | * @} |
||
| 730 | */ |
||
| 731 | |||
| 732 | /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration |
||
| 733 | * @brief macros to handle interrupts and specific clock configurations |
||
| 734 | * @{ |
||
| 735 | */ |
||
| 736 | |||
| 737 | /** |
||
| 738 | * @brief Enable the SDIO device. |
||
| 739 | * @param __INSTANCE__: SDIO Instance |
||
| 740 | * @retval None |
||
| 741 | */ |
||
| 742 | #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) |
||
| 743 | |||
| 744 | /** |
||
| 745 | * @brief Disable the SDIO device. |
||
| 746 | * @param __INSTANCE__: SDIO Instance |
||
| 747 | * @retval None |
||
| 748 | */ |
||
| 749 | #define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) |
||
| 750 | |||
| 751 | /** |
||
| 752 | * @brief Enable the SDIO DMA transfer. |
||
| 753 | * @param __INSTANCE__: SDIO Instance |
||
| 754 | * @retval None |
||
| 755 | */ |
||
| 756 | #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) |
||
| 757 | /** |
||
| 758 | * @brief Disable the SDIO DMA transfer. |
||
| 759 | * @param __INSTANCE__: SDIO Instance |
||
| 760 | * @retval None |
||
| 761 | */ |
||
| 762 | #define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) |
||
| 763 | |||
| 764 | /** |
||
| 765 | * @brief Enable the SDIO device interrupt. |
||
| 766 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 767 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. |
||
| 768 | * This parameter can be one or a combination of the following values: |
||
| 769 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
||
| 770 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
||
| 771 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
||
| 772 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
||
| 773 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
||
| 774 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
||
| 775 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
||
| 776 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
||
| 777 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
||
| 778 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
||
| 779 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
||
| 780 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
||
| 781 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
||
| 782 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
||
| 783 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
||
| 784 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
||
| 785 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
||
| 786 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
||
| 787 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
||
| 788 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
||
| 789 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
||
| 790 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
||
| 791 | * @retval None |
||
| 792 | */ |
||
| 793 | #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) |
||
| 794 | |||
| 795 | /** |
||
| 796 | * @brief Disable the SDIO device interrupt. |
||
| 797 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 798 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. |
||
| 799 | * This parameter can be one or a combination of the following values: |
||
| 800 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
||
| 801 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
||
| 802 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
||
| 803 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
||
| 804 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
||
| 805 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
||
| 806 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
||
| 807 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
||
| 808 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
||
| 809 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
||
| 810 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
||
| 811 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
||
| 812 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
||
| 813 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
||
| 814 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
||
| 815 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
||
| 816 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
||
| 817 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
||
| 818 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
||
| 819 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
||
| 820 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
||
| 821 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
||
| 822 | * @retval None |
||
| 823 | */ |
||
| 824 | #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) |
||
| 825 | |||
| 826 | /** |
||
| 827 | * @brief Checks whether the specified SDIO flag is set or not. |
||
| 828 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 829 | * @param __FLAG__: specifies the flag to check. |
||
| 830 | * This parameter can be one of the following values: |
||
| 831 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
||
| 832 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
||
| 833 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
||
| 834 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
||
| 835 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
||
| 836 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
||
| 837 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
||
| 838 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
||
| 839 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
||
| 840 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
||
| 841 | * @arg SDIO_FLAG_CMDACT: Command transfer in progress |
||
| 842 | * @arg SDIO_FLAG_TXACT: Data transmit in progress |
||
| 843 | * @arg SDIO_FLAG_RXACT: Data receive in progress |
||
| 844 | * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
||
| 845 | * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full |
||
| 846 | * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full |
||
| 847 | * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
||
| 848 | * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
||
| 849 | * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
||
| 850 | * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
||
| 851 | * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
||
| 852 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
||
| 853 | * @retval The new state of SDIO_FLAG (SET or RESET). |
||
| 854 | */ |
||
| 855 | #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) |
||
| 856 | |||
| 857 | |||
| 858 | /** |
||
| 859 | * @brief Clears the SDIO pending flags. |
||
| 860 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 861 | * @param __FLAG__: specifies the flag to clear. |
||
| 862 | * This parameter can be one or a combination of the following values: |
||
| 863 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
||
| 864 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
||
| 865 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
||
| 866 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
||
| 867 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
||
| 868 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
||
| 869 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
||
| 870 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
||
| 871 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
||
| 872 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
||
| 873 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
||
| 874 | * @retval None |
||
| 875 | */ |
||
| 876 | #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) |
||
| 877 | |||
| 878 | /** |
||
| 879 | * @brief Checks whether the specified SDIO interrupt has occurred or not. |
||
| 880 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 881 | * @param __INTERRUPT__: specifies the SDIO interrupt source to check. |
||
| 882 | * This parameter can be one of the following values: |
||
| 883 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
||
| 884 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
||
| 885 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
||
| 886 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
||
| 887 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
||
| 888 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
||
| 889 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
||
| 890 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
||
| 891 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
||
| 892 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
||
| 893 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
||
| 894 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
||
| 895 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
||
| 896 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
||
| 897 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
||
| 898 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
||
| 899 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
||
| 900 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
||
| 901 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
||
| 902 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
||
| 903 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
||
| 904 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
||
| 905 | * @retval The new state of SDIO_IT (SET or RESET). |
||
| 906 | */ |
||
| 907 | #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) |
||
| 908 | |||
| 909 | /** |
||
| 910 | * @brief Clears the SDIO's interrupt pending bits. |
||
| 911 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 912 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
||
| 913 | * This parameter can be one or a combination of the following values: |
||
| 914 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
||
| 915 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
||
| 916 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
||
| 917 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
||
| 918 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
||
| 919 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
||
| 920 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
||
| 921 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
||
| 922 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt |
||
| 923 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
||
| 924 | * @retval None |
||
| 925 | */ |
||
| 926 | #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) |
||
| 927 | |||
| 928 | /** |
||
| 929 | * @brief Enable Start the SD I/O Read Wait operation. |
||
| 930 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 931 | * @retval None |
||
| 932 | */ |
||
| 933 | #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) |
||
| 934 | |||
| 935 | /** |
||
| 936 | * @brief Disable Start the SD I/O Read Wait operations. |
||
| 937 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 938 | * @retval None |
||
| 939 | */ |
||
| 940 | #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) |
||
| 941 | |||
| 942 | /** |
||
| 943 | * @brief Enable Start the SD I/O Read Wait operation. |
||
| 944 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 945 | * @retval None |
||
| 946 | */ |
||
| 947 | #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) |
||
| 948 | |||
| 949 | /** |
||
| 950 | * @brief Disable Stop the SD I/O Read Wait operations. |
||
| 951 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 952 | * @retval None |
||
| 953 | */ |
||
| 954 | #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) |
||
| 955 | |||
| 956 | /** |
||
| 957 | * @brief Enable the SD I/O Mode Operation. |
||
| 958 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 959 | * @retval None |
||
| 960 | */ |
||
| 961 | #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) |
||
| 962 | |||
| 963 | /** |
||
| 964 | * @brief Disable the SD I/O Mode Operation. |
||
| 965 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 966 | * @retval None |
||
| 967 | */ |
||
| 968 | #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) |
||
| 969 | |||
| 970 | /** |
||
| 971 | * @brief Enable the SD I/O Suspend command sending. |
||
| 972 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 973 | * @retval None |
||
| 974 | */ |
||
| 975 | #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) |
||
| 976 | |||
| 977 | /** |
||
| 978 | * @brief Disable the SD I/O Suspend command sending. |
||
| 979 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 980 | * @retval None |
||
| 981 | */ |
||
| 982 | #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) |
||
| 983 | /** |
||
| 984 | * @brief Enable the command completion signal. |
||
| 985 | * @retval None |
||
| 986 | */ |
||
| 987 | #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) |
||
| 988 | |||
| 989 | /** |
||
| 990 | * @brief Disable the command completion signal. |
||
| 991 | * @retval None |
||
| 992 | */ |
||
| 993 | #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) |
||
| 994 | |||
| 995 | /** |
||
| 996 | * @brief Enable the CE-ATA interrupt. |
||
| 997 | * @retval None |
||
| 998 | */ |
||
| 999 | #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U) |
||
| 1000 | |||
| 1001 | /** |
||
| 1002 | * @brief Disable the CE-ATA interrupt. |
||
| 1003 | * @retval None |
||
| 1004 | */ |
||
| 1005 | #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U) |
||
| 1006 | |||
| 1007 | /** |
||
| 1008 | * @brief Enable send CE-ATA command (CMD61). |
||
| 1009 | * @retval None |
||
| 1010 | */ |
||
| 1011 | #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) |
||
| 1012 | |||
| 1013 | /** |
||
| 1014 | * @brief Disable send CE-ATA command (CMD61). |
||
| 1015 | * @retval None |
||
| 1016 | */ |
||
| 1017 | #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) |
||
| 1018 | |||
| 1019 | /** |
||
| 1020 | * @} |
||
| 1021 | */ |
||
| 1022 | |||
| 1023 | /** |
||
| 1024 | * @} |
||
| 1025 | */ |
||
| 1026 | |||
| 1027 | /* Exported functions --------------------------------------------------------*/ |
||
| 1028 | /** @addtogroup SDMMC_LL_Exported_Functions |
||
| 1029 | * @{ |
||
| 1030 | */ |
||
| 1031 | |||
| 1032 | /* Initialization/de-initialization functions **********************************/ |
||
| 1033 | /** @addtogroup HAL_SDMMC_LL_Group1 |
||
| 1034 | * @{ |
||
| 1035 | */ |
||
| 1036 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); |
||
| 1037 | /** |
||
| 1038 | * @} |
||
| 1039 | */ |
||
| 1040 | |||
| 1041 | /* I/O operation functions *****************************************************/ |
||
| 1042 | /** @addtogroup HAL_SDMMC_LL_Group2 |
||
| 1043 | * @{ |
||
| 1044 | */ |
||
| 1045 | /* Blocking mode: Polling */ |
||
| 1046 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); |
||
| 1047 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); |
||
| 1048 | /** |
||
| 1049 | * @} |
||
| 1050 | */ |
||
| 1051 | |||
| 1052 | /* Peripheral Control functions ************************************************/ |
||
| 1053 | /** @addtogroup HAL_SDMMC_LL_Group3 |
||
| 1054 | * @{ |
||
| 1055 | */ |
||
| 1056 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); |
||
| 1057 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); |
||
| 1058 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); |
||
| 1059 | |||
| 1060 | /* Command path state machine (CPSM) management functions */ |
||
| 1061 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command); |
||
| 1062 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); |
||
| 1063 | uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response); |
||
| 1064 | |||
| 1065 | /* Data path state machine (DPSM) management functions */ |
||
| 1066 | HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); |
||
| 1067 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); |
||
| 1068 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); |
||
| 1069 | |||
| 1070 | /* SDMMC Cards mode management functions */ |
||
| 1071 | HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); |
||
| 1072 | |||
| 1073 | /* SDMMC Commands management functions */ |
||
| 1074 | uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); |
||
| 1075 | uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); |
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| 1076 | uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); |
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| 1077 | uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); |
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| 1078 | uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); |
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| 1079 | uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); |
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| 1080 | uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); |
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| 1081 | uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx); |
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| 1082 | uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx); |
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| 1083 | uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr); |
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| 1084 | uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx); |
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| 1085 | uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx); |
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| 1086 | uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); |
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| 1087 | uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType); |
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| 1088 | uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); |
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| 1089 | uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); |
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| 1090 | uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); |
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| 1091 | uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); |
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| 1092 | uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); |
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| 1093 | uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); |
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| 1094 | uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); |
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| 1095 | |||
| 1096 | uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); |
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| 1097 | uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); |
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| 1098 | uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); |
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| 1099 | uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); |
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| 1100 | |||
| 1101 | /** |
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| 1102 | * @} |
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| 1103 | */ |
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| 1104 | |||
| 1105 | /** |
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| 1106 | * @} |
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| 1107 | */ |
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| 1108 | |||
| 1109 | /** |
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| 1110 | * @} |
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| 1111 | */ |
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| 1112 | |||
| 1113 | /** |
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| 1114 | * @} |
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| 1115 | */ |
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| 1116 | |||
| 1117 | #ifdef __cplusplus |
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| 1118 | } |
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| 1119 | #endif |
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| 1120 | |||
| 1121 | #endif /* STM32F103xE || STM32F103xG */ |
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| 1122 | |||
| 1123 | #endif /* __stm32f1xx_LL_SD_H */ |
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| 1124 | |||
| 1125 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |