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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_sdmmc.h |
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| 4 | * @author MCD Application Team |
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| 5 | mjames | 5 | * @version V1.0.4 |
| 6 | * @date 29-April-2016 |
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| 2 | mjames | 7 | * @brief Header file of low layer SDMMC HAL module. |
| 8 | ****************************************************************************** |
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| 9 | * @attention |
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| 10 | * |
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| 5 | mjames | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| 2 | mjames | 12 | * |
| 13 | * Redistribution and use in source and binary forms, with or without modification, |
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| 14 | * are permitted provided that the following conditions are met: |
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| 15 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 16 | * this list of conditions and the following disclaimer. |
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| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 18 | * this list of conditions and the following disclaimer in the documentation |
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| 19 | * and/or other materials provided with the distribution. |
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| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 21 | * may be used to endorse or promote products derived from this software |
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| 22 | * without specific prior written permission. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 34 | * |
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| 35 | ****************************************************************************** |
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| 36 | */ |
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| 37 | |||
| 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 39 | #ifndef __stm32f1xx_LL_SD_H |
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| 40 | #define __stm32f1xx_LL_SD_H |
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| 41 | |||
| 42 | #if defined(STM32F103xE) || defined(STM32F103xG) |
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| 43 | |||
| 44 | #ifdef __cplusplus |
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| 45 | extern "C" { |
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| 46 | #endif |
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| 47 | |||
| 48 | /* Includes ------------------------------------------------------------------*/ |
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| 49 | #include "stm32f1xx_hal_def.h" |
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| 50 | |||
| 51 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 52 | * @{ |
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| 53 | */ |
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| 54 | |||
| 55 | /** @addtogroup SDMMC_LL |
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| 56 | * @{ |
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| 57 | */ |
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| 58 | |||
| 59 | /* Exported types ------------------------------------------------------------*/ |
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| 60 | /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types |
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| 61 | * @{ |
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| 62 | */ |
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| 63 | |||
| 64 | /** |
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| 65 | * @brief SDMMC Configuration Structure definition |
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| 66 | */ |
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| 67 | typedef struct |
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| 68 | { |
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| 69 | uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. |
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| 70 | This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ |
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| 71 | |||
| 72 | uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is |
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| 73 | enabled or disabled. |
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| 74 | This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ |
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| 75 | |||
| 76 | uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or |
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| 77 | disabled when the bus is idle. |
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| 78 | This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ |
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| 79 | |||
| 80 | uint32_t BusWide; /*!< Specifies the SDIO bus width. |
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| 81 | This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ |
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| 82 | |||
| 83 | uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. |
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| 84 | This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ |
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| 85 | |||
| 86 | uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. |
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| 87 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
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| 88 | |||
| 89 | }SDIO_InitTypeDef; |
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| 90 | |||
| 91 | |||
| 92 | /** |
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| 93 | * @brief SDIO Command Control structure |
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| 94 | */ |
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| 95 | typedef struct |
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| 96 | { |
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| 97 | uint32_t Argument; /*!< Specifies the SDIO command argument which is sent |
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| 98 | to a card as part of a command message. If a command |
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| 99 | contains an argument, it must be loaded into this register |
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| 100 | before writing the command to the command register. */ |
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| 101 | |||
| 102 | uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and |
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| 103 | Max_Data = 64 */ |
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| 104 | |||
| 105 | uint32_t Response; /*!< Specifies the SDIO response type. |
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| 106 | This parameter can be a value of @ref SDMMC_LL_Response_Type */ |
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| 107 | |||
| 108 | uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is |
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| 109 | enabled or disabled. |
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| 110 | This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ |
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| 111 | |||
| 112 | uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) |
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| 113 | is enabled or disabled. |
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| 114 | This parameter can be a value of @ref SDMMC_LL_CPSM_State */ |
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| 115 | }SDIO_CmdInitTypeDef; |
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| 116 | |||
| 117 | |||
| 118 | /** |
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| 119 | * @brief SDIO Data Control structure |
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| 120 | */ |
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| 121 | typedef struct |
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| 122 | { |
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| 123 | uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ |
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| 124 | |||
| 125 | uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ |
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| 126 | |||
| 127 | uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. |
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| 128 | This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ |
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| 129 | |||
| 130 | uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer |
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| 131 | is a read or write. |
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| 132 | This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ |
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| 133 | |||
| 134 | uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. |
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| 135 | This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ |
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| 136 | |||
| 137 | uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) |
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| 138 | is enabled or disabled. |
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| 139 | This parameter can be a value of @ref SDMMC_LL_DPSM_State */ |
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| 140 | }SDIO_DataInitTypeDef; |
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| 141 | |||
| 142 | /** |
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| 143 | * @} |
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| 144 | */ |
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| 145 | |||
| 146 | /* Exported constants --------------------------------------------------------*/ |
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| 147 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
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| 148 | * @{ |
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| 149 | */ |
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| 150 | |||
| 151 | /** @defgroup SDMMC_LL_Clock_Edge Clock Edge |
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| 152 | * @{ |
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| 153 | */ |
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| 154 | #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000) |
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| 155 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
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| 156 | |||
| 157 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
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| 158 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
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| 159 | /** |
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| 160 | * @} |
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| 161 | */ |
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| 162 | |||
| 163 | /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass |
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| 164 | * @{ |
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| 165 | */ |
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| 166 | #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) |
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| 167 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
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| 168 | |||
| 169 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
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| 170 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
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| 171 | /** |
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| 172 | * @} |
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| 173 | */ |
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| 174 | |||
| 175 | /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving |
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| 176 | * @{ |
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| 177 | */ |
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| 178 | #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) |
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| 179 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
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| 180 | |||
| 181 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
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| 182 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
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| 183 | /** |
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| 184 | * @} |
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| 185 | */ |
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| 186 | |||
| 187 | /** @defgroup SDMMC_LL_Bus_Wide Bus Width |
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| 188 | * @{ |
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| 189 | */ |
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| 190 | #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000) |
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| 191 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
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| 192 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
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| 193 | |||
| 194 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
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| 195 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
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| 196 | ((WIDE) == SDIO_BUS_WIDE_8B)) |
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| 197 | /** |
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| 198 | * @} |
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| 199 | */ |
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| 200 | |||
| 201 | /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control |
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| 202 | * @{ |
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| 203 | */ |
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| 204 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) |
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| 205 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
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| 206 | |||
| 207 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
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| 208 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
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| 209 | /** |
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| 210 | * @} |
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| 211 | */ |
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| 212 | |||
| 213 | /** @defgroup SDMMC_LL_Clock_Division Clock Division |
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| 214 | * @{ |
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| 215 | */ |
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| 216 | #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) |
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| 217 | /** |
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| 218 | * @} |
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| 219 | */ |
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| 220 | |||
| 221 | /** @defgroup SDMMC_LL_Command_Index Command Index |
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| 222 | * @{ |
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| 223 | */ |
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| 224 | #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) |
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| 225 | /** |
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| 226 | * @} |
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| 227 | */ |
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| 228 | |||
| 229 | /** @defgroup SDMMC_LL_Response_Type Response Type |
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| 230 | * @{ |
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| 231 | */ |
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| 232 | #define SDIO_RESPONSE_NO ((uint32_t)0x00000000) |
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| 233 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
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| 234 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
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| 235 | |||
| 236 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
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| 237 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
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| 238 | ((RESPONSE) == SDIO_RESPONSE_LONG)) |
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| 239 | /** |
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| 240 | * @} |
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| 241 | */ |
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| 242 | |||
| 243 | /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt |
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| 244 | * @{ |
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| 245 | */ |
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| 246 | #define SDIO_WAIT_NO ((uint32_t)0x00000000) |
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| 247 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
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| 248 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
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| 249 | |||
| 250 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
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| 251 | ((WAIT) == SDIO_WAIT_IT) || \ |
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| 252 | ((WAIT) == SDIO_WAIT_PEND)) |
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| 253 | /** |
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| 254 | * @} |
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| 255 | */ |
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| 256 | |||
| 257 | /** @defgroup SDMMC_LL_CPSM_State CPSM State |
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| 258 | * @{ |
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| 259 | */ |
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| 260 | #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) |
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| 261 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
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| 262 | |||
| 263 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
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| 264 | ((CPSM) == SDIO_CPSM_ENABLE)) |
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| 265 | /** |
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| 266 | * @} |
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| 267 | */ |
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| 268 | |||
| 269 | /** @defgroup SDMMC_LL_Response_Registers Response Register |
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| 270 | * @{ |
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| 271 | */ |
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| 272 | #define SDIO_RESP1 ((uint32_t)0x00000000) |
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| 273 | #define SDIO_RESP2 ((uint32_t)0x00000004) |
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| 274 | #define SDIO_RESP3 ((uint32_t)0x00000008) |
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| 275 | #define SDIO_RESP4 ((uint32_t)0x0000000C) |
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| 276 | |||
| 277 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
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| 278 | ((RESP) == SDIO_RESP2) || \ |
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| 279 | ((RESP) == SDIO_RESP3) || \ |
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| 280 | ((RESP) == SDIO_RESP4)) |
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| 281 | /** |
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| 282 | * @} |
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| 283 | */ |
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| 284 | |||
| 285 | /** @defgroup SDMMC_LL_Data_Length Data Lenght |
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| 286 | * @{ |
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| 287 | */ |
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| 288 | #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) |
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| 289 | /** |
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| 290 | * @} |
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| 291 | */ |
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| 292 | |||
| 293 | /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size |
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| 294 | * @{ |
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| 295 | */ |
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| 296 | #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) |
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| 297 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
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| 298 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
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| 299 | #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) |
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| 300 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
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| 301 | #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) |
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| 302 | #define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) |
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| 303 | #define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) |
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| 304 | #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 |
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| 305 | #define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3) |
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| 306 | #define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) |
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| 307 | #define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) |
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| 308 | #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
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| 309 | #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
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| 310 | #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
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| 311 | |||
| 312 | #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ |
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| 313 | ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ |
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| 314 | ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ |
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| 315 | ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ |
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| 316 | ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ |
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| 317 | ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ |
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| 318 | ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ |
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| 319 | ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ |
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| 320 | ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ |
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| 321 | ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ |
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| 322 | ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ |
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| 323 | ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ |
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| 324 | ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ |
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| 325 | ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ |
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| 326 | ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) |
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| 327 | /** |
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| 328 | * @} |
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| 329 | */ |
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| 330 | |||
| 331 | /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction |
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| 332 | * @{ |
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| 333 | */ |
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| 334 | #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) |
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| 335 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
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| 336 | |||
| 337 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
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| 338 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
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| 339 | /** |
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| 340 | * @} |
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| 341 | */ |
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| 342 | |||
| 343 | /** @defgroup SDMMC_LL_Transfer_Type Transfer Type |
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| 344 | * @{ |
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| 345 | */ |
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| 346 | #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) |
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| 347 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
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| 348 | |||
| 349 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
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| 350 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
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| 351 | /** |
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| 352 | * @} |
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| 353 | */ |
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| 354 | |||
| 355 | /** @defgroup SDMMC_LL_DPSM_State DPSM State |
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| 356 | * @{ |
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| 357 | */ |
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| 358 | #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) |
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| 359 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
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| 360 | |||
| 361 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
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| 362 | ((DPSM) == SDIO_DPSM_ENABLE)) |
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| 363 | /** |
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| 364 | * @} |
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| 365 | */ |
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| 366 | |||
| 367 | /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode |
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| 368 | * @{ |
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| 369 | */ |
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| 370 | #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000) |
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| 371 | #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) |
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| 372 | |||
| 373 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
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| 374 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
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| 375 | /** |
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| 376 | * @} |
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| 377 | */ |
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| 378 | |||
| 379 | /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources |
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| 380 | * @{ |
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| 381 | */ |
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| 382 | #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL |
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| 383 | #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL |
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| 384 | #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT |
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| 385 | #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT |
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| 386 | #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR |
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| 387 | #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR |
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| 388 | #define SDIO_IT_CMDREND SDIO_STA_CMDREND |
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| 389 | #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT |
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| 390 | #define SDIO_IT_DATAEND SDIO_STA_DATAEND |
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| 391 | #define SDIO_IT_STBITERR SDIO_STA_STBITERR |
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| 392 | #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND |
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| 393 | #define SDIO_IT_CMDACT SDIO_STA_CMDACT |
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| 394 | #define SDIO_IT_TXACT SDIO_STA_TXACT |
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| 395 | #define SDIO_IT_RXACT SDIO_STA_RXACT |
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| 396 | #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE |
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| 397 | #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF |
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| 398 | #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF |
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| 399 | #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF |
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| 400 | #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE |
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| 401 | #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE |
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| 402 | #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL |
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| 403 | #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL |
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| 404 | #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT |
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| 405 | #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND |
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| 406 | |||
| 407 | /** |
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| 408 | * @} |
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| 409 | */ |
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| 410 | |||
| 411 | /** @defgroup SDMMC_LL_Flags Flags |
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| 412 | * @{ |
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| 413 | */ |
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| 414 | #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL |
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| 415 | #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL |
||
| 416 | #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT |
||
| 417 | #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT |
||
| 418 | #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR |
||
| 419 | #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR |
||
| 420 | #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND |
||
| 421 | #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT |
||
| 422 | #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND |
||
| 423 | #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR |
||
| 424 | #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND |
||
| 425 | #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT |
||
| 426 | #define SDIO_FLAG_TXACT SDIO_STA_TXACT |
||
| 427 | #define SDIO_FLAG_RXACT SDIO_STA_RXACT |
||
| 428 | #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE |
||
| 429 | #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF |
||
| 430 | #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF |
||
| 431 | #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF |
||
| 432 | #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE |
||
| 433 | #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE |
||
| 434 | #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL |
||
| 435 | #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL |
||
| 436 | #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT |
||
| 437 | #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND |
||
| 438 | |||
| 439 | /** |
||
| 440 | * @} |
||
| 441 | */ |
||
| 442 | |||
| 443 | /** |
||
| 444 | * @} |
||
| 445 | */ |
||
| 446 | |||
| 447 | /* Exported macro ------------------------------------------------------------*/ |
||
| 448 | /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros |
||
| 449 | * @{ |
||
| 450 | */ |
||
| 451 | |||
| 452 | /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions |
||
| 453 | * @brief SDMMC_LL registers bit address in the alias region |
||
| 454 | * @{ |
||
| 455 | */ |
||
| 456 | |||
| 457 | /* ---------------------- SDIO registers bit mask --------------------------- */ |
||
| 458 | /* --- CLKCR Register ---*/ |
||
| 459 | /* CLKCR register clear mask */ |
||
| 460 | #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ |
||
| 461 | SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ |
||
| 462 | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) |
||
| 463 | |||
| 464 | /* --- DCTRL Register ---*/ |
||
| 465 | /* SDIO DCTRL Clear Mask */ |
||
| 466 | #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ |
||
| 467 | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) |
||
| 468 | |||
| 469 | /* --- CMD Register ---*/ |
||
| 470 | /* CMD Register clear mask */ |
||
| 471 | #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ |
||
| 472 | SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ |
||
| 473 | SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) |
||
| 474 | |||
| 475 | /* SDIO RESP Registers Address */ |
||
| 476 | #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) |
||
| 477 | |||
| 478 | /* SDIO Intialization Frequency (400KHz max) */ |
||
| 479 | #define SDIO_INIT_CLK_DIV ((uint8_t)0xC3) |
||
| 480 | |||
| 481 | /* SDIO Data Transfer Frequency */ |
||
| 482 | #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x9) |
||
| 483 | |||
| 484 | /** |
||
| 485 | * @} |
||
| 486 | */ |
||
| 487 | |||
| 488 | /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration |
||
| 489 | * @brief macros to handle interrupts and specific clock configurations |
||
| 490 | * @{ |
||
| 491 | */ |
||
| 492 | |||
| 493 | /** |
||
| 494 | * @brief Enable the SDIO device. |
||
| 495 | * @param __INSTANCE__: SDIO Instance |
||
| 496 | * @retval None |
||
| 497 | */ |
||
| 498 | #define __SDIO_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDIO_CLKCR_CLKEN) |
||
| 499 | |||
| 500 | /** |
||
| 501 | * @brief Disable the SDIO device. |
||
| 502 | * @param __INSTANCE__: SDIO Instance |
||
| 503 | * @retval None |
||
| 504 | */ |
||
| 505 | #define __SDIO_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDIO_CLKCR_CLKEN) |
||
| 506 | |||
| 507 | /** |
||
| 508 | * @brief Enable the SDIO DMA transfer. |
||
| 509 | * @param None |
||
| 510 | * @retval None |
||
| 511 | */ |
||
| 512 | #define __SDIO_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_DMAEN) |
||
| 513 | /** |
||
| 514 | * @brief Disable the SDIO DMA transfer. |
||
| 515 | * @param None |
||
| 516 | * @retval None |
||
| 517 | */ |
||
| 518 | #define __SDIO_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_DMAEN) |
||
| 519 | |||
| 520 | /** |
||
| 521 | * @brief Enable the SDIO device interrupt. |
||
| 522 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 523 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. |
||
| 524 | * This parameter can be one or a combination of the following values: |
||
| 525 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
||
| 526 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
||
| 527 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
||
| 528 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
||
| 529 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
||
| 530 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
||
| 531 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
||
| 532 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
||
| 533 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
||
| 534 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
||
| 535 | * bus mode interrupt |
||
| 536 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
||
| 537 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
||
| 538 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
||
| 539 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
||
| 540 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
||
| 541 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
||
| 542 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
||
| 543 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
||
| 544 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
||
| 545 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
||
| 546 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
||
| 547 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
||
| 548 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
||
| 549 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
||
| 550 | * @retval None |
||
| 551 | */ |
||
| 552 | #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) |
||
| 553 | |||
| 554 | /** |
||
| 555 | * @brief Disable the SDIO device interrupt. |
||
| 556 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 557 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. |
||
| 558 | * This parameter can be one or a combination of the following values: |
||
| 559 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
||
| 560 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
||
| 561 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
||
| 562 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
||
| 563 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
||
| 564 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
||
| 565 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
||
| 566 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
||
| 567 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
||
| 568 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
||
| 569 | * bus mode interrupt |
||
| 570 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
||
| 571 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
||
| 572 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
||
| 573 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
||
| 574 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
||
| 575 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
||
| 576 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
||
| 577 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
||
| 578 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
||
| 579 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
||
| 580 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
||
| 581 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
||
| 582 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
||
| 583 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
||
| 584 | * @retval None |
||
| 585 | */ |
||
| 586 | #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) |
||
| 587 | |||
| 588 | /** |
||
| 589 | * @brief Checks whether the specified SDIO flag is set or not. |
||
| 590 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 591 | * @param __FLAG__: specifies the flag to check. |
||
| 592 | * This parameter can be one of the following values: |
||
| 593 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
||
| 594 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
||
| 595 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
||
| 596 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
||
| 597 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
||
| 598 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
||
| 599 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
||
| 600 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
||
| 601 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
||
| 602 | * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. |
||
| 603 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
||
| 604 | * @arg SDIO_FLAG_CMDACT: Command transfer in progress |
||
| 605 | * @arg SDIO_FLAG_TXACT: Data transmit in progress |
||
| 606 | * @arg SDIO_FLAG_RXACT: Data receive in progress |
||
| 607 | * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
||
| 608 | * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full |
||
| 609 | * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full |
||
| 610 | * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
||
| 611 | * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
||
| 612 | * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
||
| 613 | * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
||
| 614 | * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
||
| 615 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
||
| 616 | * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
||
| 617 | * @retval The new state of SDIO_FLAG (SET or RESET). |
||
| 618 | */ |
||
| 619 | #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) |
||
| 620 | |||
| 621 | |||
| 622 | /** |
||
| 623 | * @brief Clears the SDIO pending flags. |
||
| 624 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 625 | * @param __FLAG__: specifies the flag to clear. |
||
| 626 | * This parameter can be one or a combination of the following values: |
||
| 627 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
||
| 628 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
||
| 629 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
||
| 630 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
||
| 631 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
||
| 632 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
||
| 633 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
||
| 634 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
||
| 635 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
||
| 636 | * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode |
||
| 637 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
||
| 638 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
||
| 639 | * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
||
| 640 | * @retval None |
||
| 641 | */ |
||
| 642 | #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) |
||
| 643 | |||
| 644 | /** |
||
| 645 | * @brief Checks whether the specified SDIO interrupt has occurred or not. |
||
| 646 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 647 | * @param __INTERRUPT__: specifies the SDIO interrupt source to check. |
||
| 648 | * This parameter can be one of the following values: |
||
| 649 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
||
| 650 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
||
| 651 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
||
| 652 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
||
| 653 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
||
| 654 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
||
| 655 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
||
| 656 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
||
| 657 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
||
| 658 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
||
| 659 | * bus mode interrupt |
||
| 660 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
||
| 661 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
||
| 662 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
||
| 663 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
||
| 664 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
||
| 665 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
||
| 666 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
||
| 667 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
||
| 668 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
||
| 669 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
||
| 670 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
||
| 671 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
||
| 672 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
||
| 673 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
||
| 674 | * @retval The new state of SDIO_IT (SET or RESET). |
||
| 675 | */ |
||
| 676 | #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) |
||
| 677 | |||
| 678 | /** |
||
| 679 | * @brief Clears the SDIO's interrupt pending bits. |
||
| 680 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 681 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
||
| 682 | * This parameter can be one or a combination of the following values: |
||
| 683 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
||
| 684 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
||
| 685 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
||
| 686 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
||
| 687 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
||
| 688 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
||
| 689 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
||
| 690 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
||
| 691 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt |
||
| 692 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
||
| 693 | * bus mode interrupt |
||
| 694 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
||
| 695 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 |
||
| 696 | * @retval None |
||
| 697 | */ |
||
| 698 | #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) |
||
| 699 | |||
| 700 | /** |
||
| 701 | * @brief Enable Start the SD I/O Read Wait operation. |
||
| 702 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 703 | * @retval None |
||
| 704 | */ |
||
| 705 | #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTART) |
||
| 706 | |||
| 707 | /** |
||
| 708 | * @brief Disable Start the SD I/O Read Wait operations. |
||
| 709 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 710 | * @retval None |
||
| 711 | */ |
||
| 712 | #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTART) |
||
| 713 | |||
| 714 | /** |
||
| 715 | * @brief Enable Start the SD I/O Read Wait operation. |
||
| 716 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 717 | * @retval None |
||
| 718 | */ |
||
| 719 | #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTOP) |
||
| 720 | |||
| 721 | /** |
||
| 722 | * @brief Disable Stop the SD I/O Read Wait operations. |
||
| 723 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 724 | * @retval None |
||
| 725 | */ |
||
| 726 | #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTOP) |
||
| 727 | |||
| 728 | /** |
||
| 729 | * @brief Enable the SD I/O Mode Operation. |
||
| 730 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 731 | * @retval None |
||
| 732 | */ |
||
| 733 | #define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_SDIOEN) |
||
| 734 | |||
| 735 | /** |
||
| 736 | * @brief Disable the SD I/O Mode Operation. |
||
| 737 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 738 | * @retval None |
||
| 739 | */ |
||
| 740 | #define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_SDIOEN) |
||
| 741 | |||
| 742 | /** |
||
| 743 | * @brief Enable the SD I/O Suspend command sending. |
||
| 744 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 745 | * @retval None |
||
| 746 | */ |
||
| 747 | #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_SDIOSUSPEND) |
||
| 748 | |||
| 749 | /** |
||
| 750 | * @brief Disable the SD I/O Suspend command sending. |
||
| 751 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 752 | * @retval None |
||
| 753 | */ |
||
| 754 | #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_SDIOSUSPEND) |
||
| 755 | |||
| 756 | /** |
||
| 757 | * @brief Enable the command completion signal. |
||
| 758 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 759 | * @retval None |
||
| 760 | */ |
||
| 761 | #define __SDIO_CEATA_CMD_COMPLETION_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_ENCMDCOMPL) |
||
| 762 | |||
| 763 | /** |
||
| 764 | * @brief Disable the command completion signal. |
||
| 765 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 766 | * @retval None |
||
| 767 | */ |
||
| 768 | #define __SDIO_CEATA_CMD_COMPLETION_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_ENCMDCOMPL) |
||
| 769 | |||
| 770 | /** |
||
| 771 | * @brief Enable the CE-ATA interrupt. |
||
| 772 | * @param __INSTANCE__ : Pointer to SDIO register base |
||
| 773 | * @retval None |
||
| 774 | */ |
||
| 775 | #define __SDIO_CEATA_ENABLE_IT(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_NIEN) |
||
| 776 | |||
| 777 | /** |
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| 778 | * @brief Disable the CE-ATA interrupt. |
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| 779 | * @param __INSTANCE__ : Pointer to SDIO register base |
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| 780 | * @retval None |
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| 781 | */ |
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| 782 | #define __SDIO_CEATA_DISABLE_IT(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_NIEN) |
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| 783 | |||
| 784 | /** |
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| 785 | * @brief Enable send CE-ATA command (CMD61). |
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| 786 | * @param __INSTANCE__ : Pointer to SDIO register base |
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| 787 | * @retval None |
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| 788 | */ |
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| 789 | #define __SDIO_CEATA_SENDCMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_CEATACMD) |
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| 790 | |||
| 791 | /** |
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| 792 | * @brief Disable send CE-ATA command (CMD61). |
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| 793 | * @param __INSTANCE__ : Pointer to SDIO register base |
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| 794 | * @retval None |
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| 795 | */ |
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| 796 | #define __SDIO_CEATA_SENDCMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_CEATACMD) |
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| 797 | |||
| 798 | /** |
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| 799 | * @} |
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| 800 | */ |
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| 801 | |||
| 802 | /** |
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| 803 | * @} |
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| 804 | */ |
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| 805 | |||
| 806 | /* Exported functions --------------------------------------------------------*/ |
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| 807 | /** @addtogroup SDMMC_LL_Exported_Functions |
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| 808 | * @{ |
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| 809 | */ |
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| 810 | |||
| 811 | /* Initialization/de-initialization functions **********************************/ |
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| 812 | /** @addtogroup HAL_SDMMC_LL_Group1 |
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| 813 | * @{ |
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| 814 | */ |
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| 815 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); |
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| 816 | /** |
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| 817 | * @} |
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| 818 | */ |
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| 819 | |||
| 820 | /* I/O operation functions *****************************************************/ |
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| 821 | /** @addtogroup HAL_SDMMC_LL_Group2 |
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| 822 | * @{ |
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| 823 | */ |
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| 824 | /* Blocking mode: Polling */ |
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| 825 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); |
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| 826 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); |
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| 827 | /** |
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| 828 | * @} |
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| 829 | */ |
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| 830 | |||
| 831 | /* Peripheral Control functions ************************************************/ |
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| 832 | /** @addtogroup HAL_SDMMC_LL_Group3 |
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| 833 | * @{ |
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| 834 | */ |
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| 835 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); |
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| 836 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); |
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| 837 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); |
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| 838 | |||
| 839 | /* Command path state machine (CPSM) management functions */ |
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| 840 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command); |
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| 841 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); |
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| 842 | uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response); |
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| 843 | |||
| 844 | /* Data path state machine (DPSM) management functions */ |
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| 845 | HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); |
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| 846 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); |
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| 847 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); |
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| 848 | |||
| 849 | /* SDIO Cards mode management functions */ |
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| 850 | HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); |
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| 851 | |||
| 852 | /** |
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| 853 | * @} |
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| 854 | */ |
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| 855 | |||
| 856 | /** |
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| 857 | * @} |
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| 858 | */ |
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| 859 | |||
| 860 | /** |
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| 861 | * @} |
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| 862 | */ |
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| 863 | |||
| 864 | /** |
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| 865 | * @} |
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| 866 | */ |
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| 867 | |||
| 868 | #ifdef __cplusplus |
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| 869 | } |
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| 870 | #endif |
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| 871 | |||
| 872 | #endif /* STM32F103xE || STM32F103xG */ |
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| 873 | |||
| 874 | #endif /* __stm32f1xx_LL_SD_H */ |
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| 875 | |||
| 876 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |