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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_rcc.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of RCC LL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32F1xx_LL_RCC_H |
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| 22 | #define __STM32F1xx_LL_RCC_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f1xx.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F1xx_LL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | #if defined(RCC) |
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| 36 | |||
| 37 | /** @defgroup RCC_LL RCC |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Private types -------------------------------------------------------------*/ |
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| 42 | /* Private variables ---------------------------------------------------------*/ |
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| 43 | /* Private constants ---------------------------------------------------------*/ |
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| 44 | /* Private macros ------------------------------------------------------------*/ |
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| 45 | #if defined(USE_FULL_LL_DRIVER) |
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| 46 | /** @defgroup RCC_LL_Private_Macros RCC Private Macros |
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| 47 | * @{ |
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| 48 | */ |
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| 49 | /** |
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| 50 | * @} |
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| 51 | */ |
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| 52 | #endif /*USE_FULL_LL_DRIVER*/ |
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| 53 | /* Exported types ------------------------------------------------------------*/ |
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| 54 | #if defined(USE_FULL_LL_DRIVER) |
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| 55 | /** @defgroup RCC_LL_Exported_Types RCC Exported Types |
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| 56 | * @{ |
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| 57 | */ |
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| 58 | |||
| 59 | /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure |
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| 60 | * @{ |
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| 61 | */ |
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| 62 | |||
| 63 | /** |
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| 64 | * @brief RCC Clocks Frequency Structure |
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| 65 | */ |
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| 66 | typedef struct |
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| 67 | { |
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| 68 | uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ |
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| 69 | uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ |
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| 70 | uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ |
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| 71 | uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ |
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| 72 | } LL_RCC_ClocksTypeDef; |
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| 73 | |||
| 74 | /** |
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| 75 | * @} |
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| 76 | */ |
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| 77 | |||
| 78 | /** |
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| 79 | * @} |
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| 80 | */ |
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| 81 | #endif /* USE_FULL_LL_DRIVER */ |
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| 82 | |||
| 83 | /* Exported constants --------------------------------------------------------*/ |
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| 84 | /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants |
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| 85 | * @{ |
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| 86 | */ |
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| 87 | |||
| 88 | /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation |
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| 89 | * @brief Defines used to adapt values of different oscillators |
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| 90 | * @note These values could be modified in the user environment according to |
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| 91 | * HW set-up. |
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| 92 | * @{ |
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| 93 | */ |
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| 94 | #if !defined (HSE_VALUE) |
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| 95 | #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ |
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| 96 | #endif /* HSE_VALUE */ |
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| 97 | |||
| 98 | #if !defined (HSI_VALUE) |
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| 99 | #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ |
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| 100 | #endif /* HSI_VALUE */ |
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| 101 | |||
| 102 | #if !defined (LSE_VALUE) |
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| 103 | #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ |
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| 104 | #endif /* LSE_VALUE */ |
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| 105 | |||
| 106 | #if !defined (LSI_VALUE) |
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| 107 | #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ |
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| 108 | #endif /* LSI_VALUE */ |
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| 109 | /** |
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| 110 | * @} |
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| 111 | */ |
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| 112 | |||
| 113 | /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines |
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| 114 | * @brief Flags defines which can be used with LL_RCC_WriteReg function |
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| 115 | * @{ |
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| 116 | */ |
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| 117 | #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ |
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| 118 | #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ |
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| 119 | #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ |
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| 120 | #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ |
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| 121 | #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ |
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| 122 | #define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */ |
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| 123 | #define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */ |
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| 124 | #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ |
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| 125 | /** |
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| 126 | * @} |
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| 127 | */ |
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| 128 | |||
| 129 | /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines |
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| 130 | * @brief Flags defines which can be used with LL_RCC_ReadReg function |
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| 131 | * @{ |
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| 132 | */ |
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| 133 | #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ |
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| 134 | #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ |
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| 135 | #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ |
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| 136 | #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ |
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| 137 | #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ |
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| 138 | #define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */ |
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| 139 | #define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ |
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| 140 | #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ |
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| 141 | #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ |
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| 142 | #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ |
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| 143 | #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ |
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| 144 | #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ |
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| 145 | #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ |
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| 146 | #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ |
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| 147 | /** |
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| 148 | * @} |
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| 149 | */ |
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| 150 | |||
| 151 | /** @defgroup RCC_LL_EC_IT IT Defines |
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| 152 | * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions |
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| 153 | * @{ |
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| 154 | */ |
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| 155 | #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ |
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| 156 | #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ |
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| 157 | #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ |
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| 158 | #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ |
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| 159 | #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ |
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| 160 | #define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */ |
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| 161 | #define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */ |
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| 162 | /** |
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| 163 | * @} |
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| 164 | */ |
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| 165 | |||
| 166 | #if defined(RCC_CFGR2_PREDIV2) |
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| 167 | /** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor |
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| 168 | * @{ |
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| 169 | */ |
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| 170 | #define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ |
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| 171 | #define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ |
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| 172 | #define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ |
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| 173 | #define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ |
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| 174 | #define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ |
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| 175 | #define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ |
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| 176 | #define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ |
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| 177 | #define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ |
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| 178 | #define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ |
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| 179 | #define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ |
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| 180 | #define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ |
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| 181 | #define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ |
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| 182 | #define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ |
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| 183 | #define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ |
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| 184 | #define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ |
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| 185 | #define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ |
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| 186 | /** |
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| 187 | * @} |
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| 188 | */ |
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| 189 | |||
| 190 | #endif /* RCC_CFGR2_PREDIV2 */ |
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| 191 | |||
| 192 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch |
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| 193 | * @{ |
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| 194 | */ |
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| 195 | #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ |
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| 196 | #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ |
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| 197 | #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ |
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| 198 | /** |
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| 199 | * @} |
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| 200 | */ |
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| 201 | |||
| 202 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status |
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| 203 | * @{ |
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| 204 | */ |
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| 205 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
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| 206 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
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| 207 | #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
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| 208 | /** |
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| 209 | * @} |
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| 210 | */ |
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| 211 | |||
| 212 | /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler |
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| 213 | * @{ |
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| 214 | */ |
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| 215 | #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
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| 216 | #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
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| 217 | #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
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| 218 | #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
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| 219 | #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
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| 220 | #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
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| 221 | #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
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| 222 | #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
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| 223 | #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
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| 224 | /** |
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| 225 | * @} |
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| 226 | */ |
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| 227 | |||
| 228 | /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) |
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| 229 | * @{ |
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| 230 | */ |
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| 231 | #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
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| 232 | #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
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| 233 | #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
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| 234 | #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
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| 235 | #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
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| 236 | /** |
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| 237 | * @} |
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| 238 | */ |
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| 239 | |||
| 240 | /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) |
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| 241 | * @{ |
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| 242 | */ |
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| 243 | #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ |
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| 244 | #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ |
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| 245 | #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ |
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| 246 | #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ |
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| 247 | #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ |
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| 248 | /** |
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| 249 | * @} |
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| 250 | */ |
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| 251 | |||
| 252 | /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection |
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| 253 | * @{ |
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| 254 | */ |
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| 255 | #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK /*!< MCO output disabled, no clock on MCO */ |
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| 256 | #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK /*!< SYSCLK selection as MCO source */ |
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| 257 | #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI /*!< HSI selection as MCO source */ |
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| 258 | #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE /*!< HSE selection as MCO source */ |
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| 259 | #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!< PLL clock divided by 2*/ |
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| 260 | #if defined(RCC_CFGR_MCO_PLL2CLK) |
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| 261 | #define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCO_PLL2CLK /*!< PLL2 clock selected as MCO source*/ |
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| 262 | #endif /* RCC_CFGR_MCO_PLL2CLK */ |
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| 263 | #if defined(RCC_CFGR_MCO_PLL3CLK_DIV2) |
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| 264 | #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/ |
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| 265 | #endif /* RCC_CFGR_MCO_PLL3CLK_DIV2 */ |
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| 266 | #if defined(RCC_CFGR_MCO_EXT_HSE) |
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| 267 | #define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCO_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ |
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| 268 | #endif /* RCC_CFGR_MCO_EXT_HSE */ |
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| 269 | #if defined(RCC_CFGR_MCO_PLL3CLK) |
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| 270 | #define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCO_PLL3CLK /*!< PLLI2S clock selected as MCO source */ |
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| 271 | #endif /* RCC_CFGR_MCO_PLL3CLK */ |
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| 272 | /** |
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| 273 | * @} |
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| 274 | */ |
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| 275 | |||
| 276 | #if defined(USE_FULL_LL_DRIVER) |
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| 277 | /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency |
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| 278 | * @{ |
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| 279 | */ |
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| 280 | #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ |
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| 281 | #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ |
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| 282 | /** |
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| 283 | * @} |
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| 284 | */ |
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| 285 | #endif /* USE_FULL_LL_DRIVER */ |
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| 286 | |||
| 287 | #if defined(RCC_CFGR2_I2S2SRC) |
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| 288 | /** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection |
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| 289 | * @{ |
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| 290 | */ |
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| 291 | #define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */ |
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| 292 | #define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */ |
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| 293 | #define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */ |
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| 294 | #define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */ |
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| 295 | /** |
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| 296 | * @} |
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| 297 | */ |
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| 298 | #endif /* RCC_CFGR2_I2S2SRC */ |
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| 299 | |||
| 300 | #if defined(USB_OTG_FS) || defined(USB) |
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| 301 | /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection |
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| 302 | * @{ |
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| 303 | */ |
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| 304 | #if defined(RCC_CFGR_USBPRE) |
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| 305 | #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ |
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| 306 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */ |
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| 307 | #endif /*RCC_CFGR_USBPRE*/ |
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| 308 | #if defined(RCC_CFGR_OTGFSPRE) |
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| 309 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ |
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| 310 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */ |
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| 311 | #endif /*RCC_CFGR_OTGFSPRE*/ |
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| 312 | /** |
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| 313 | * @} |
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| 314 | */ |
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| 315 | #endif /* USB_OTG_FS || USB */ |
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| 316 | |||
| 317 | /** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection |
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| 318 | * @{ |
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| 319 | */ |
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| 320 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/ |
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| 321 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/ |
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| 322 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/ |
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| 323 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/ |
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| 324 | /** |
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| 325 | * @} |
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| 326 | */ |
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| 327 | |||
| 328 | #if defined(RCC_CFGR2_I2S2SRC) |
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| 329 | /** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source |
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| 330 | * @{ |
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| 331 | */ |
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| 332 | #define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */ |
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| 333 | #define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */ |
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| 334 | /** |
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| 335 | * @} |
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| 336 | */ |
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| 337 | |||
| 338 | #endif /* RCC_CFGR2_I2S2SRC */ |
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| 339 | |||
| 340 | #if defined(USB_OTG_FS) || defined(USB) |
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| 341 | /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source |
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| 342 | * @{ |
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| 343 | */ |
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| 344 | #define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */ |
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| 345 | /** |
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| 346 | * @} |
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| 347 | */ |
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| 348 | |||
| 349 | #endif /* USB_OTG_FS || USB */ |
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| 350 | |||
| 351 | /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source |
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| 352 | * @{ |
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| 353 | */ |
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| 354 | #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ |
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| 355 | /** |
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| 356 | * @} |
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| 357 | */ |
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| 358 | |||
| 359 | /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection |
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| 360 | * @{ |
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| 361 | */ |
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| 362 | #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ |
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| 363 | #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ |
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| 364 | #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ |
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| 365 | #define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
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| 366 | /** |
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| 367 | * @} |
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| 368 | */ |
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| 369 | |||
| 370 | /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor |
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| 371 | * @{ |
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| 372 | */ |
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| 373 | #if defined(RCC_CFGR_PLLMULL2) |
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| 374 | #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */ |
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| 375 | #endif /*RCC_CFGR_PLLMULL2*/ |
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| 376 | #if defined(RCC_CFGR_PLLMULL3) |
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| 377 | #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */ |
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| 378 | #endif /*RCC_CFGR_PLLMULL3*/ |
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| 379 | #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */ |
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| 380 | #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */ |
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| 381 | #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */ |
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| 382 | #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */ |
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| 383 | #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */ |
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| 384 | #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */ |
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| 385 | #if defined(RCC_CFGR_PLLMULL6_5) |
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| 386 | #define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */ |
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| 387 | #else |
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| 388 | #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */ |
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| 389 | #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */ |
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| 390 | #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */ |
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| 391 | #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */ |
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| 392 | #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */ |
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| 393 | #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */ |
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| 394 | #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */ |
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| 395 | #endif /*RCC_CFGR_PLLMULL6_5*/ |
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| 396 | /** |
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| 397 | * @} |
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| 398 | */ |
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| 399 | |||
| 400 | /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE |
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| 401 | * @{ |
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| 402 | */ |
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| 403 | #define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
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| 404 | #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */ |
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| 405 | #if defined(RCC_CFGR2_PREDIV1SRC) |
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| 406 | #define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */ |
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| 407 | #endif /*RCC_CFGR2_PREDIV1SRC*/ |
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| 408 | |||
| 409 | #if defined(RCC_CFGR2_PREDIV1) |
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| 410 | #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1 clock selected as PLL entry clock source */ |
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| 411 | #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ |
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| 412 | #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ |
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| 413 | #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ |
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| 414 | #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ |
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| 415 | #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ |
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| 416 | #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ |
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| 417 | #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ |
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| 418 | #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ |
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| 419 | #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ |
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| 420 | #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ |
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| 421 | #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ |
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| 422 | #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ |
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| 423 | #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ |
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| 424 | #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ |
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| 425 | #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ |
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| 426 | #if defined(RCC_CFGR2_PREDIV1SRC) |
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| 427 | #define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/1 clock selected as PLL entry clock source */ |
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| 428 | #define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */ |
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| 429 | #define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */ |
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| 430 | #define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */ |
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| 431 | #define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */ |
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| 432 | #define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */ |
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| 433 | #define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */ |
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| 434 | #define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */ |
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| 435 | #define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */ |
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| 436 | #define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */ |
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| 437 | #define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */ |
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| 438 | #define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */ |
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| 439 | #define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */ |
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| 440 | #define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */ |
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| 441 | #define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */ |
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| 442 | #define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */ |
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| 443 | #endif /*RCC_CFGR2_PREDIV1SRC*/ |
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| 444 | #else |
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| 445 | #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1 clock selected as PLL entry clock source */ |
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| 446 | #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */ |
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| 447 | #endif /*RCC_CFGR2_PREDIV1*/ |
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| 448 | /** |
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| 449 | * @} |
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| 450 | */ |
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| 451 | |||
| 452 | /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor |
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| 453 | * @{ |
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| 454 | */ |
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| 455 | #if defined(RCC_CFGR2_PREDIV1) |
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| 456 | #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */ |
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| 457 | #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */ |
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| 458 | #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */ |
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| 459 | #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */ |
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| 460 | #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */ |
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| 461 | #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */ |
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| 462 | #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */ |
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| 463 | #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */ |
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| 464 | #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */ |
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| 465 | #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */ |
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| 466 | #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */ |
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| 467 | #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */ |
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| 468 | #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */ |
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| 469 | #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */ |
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| 470 | #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */ |
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| 471 | #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */ |
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| 472 | #else |
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| 473 | #define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */ |
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| 474 | #define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */ |
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| 475 | #endif /*RCC_CFGR2_PREDIV1*/ |
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| 476 | /** |
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| 477 | * @} |
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| 478 | */ |
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| 479 | |||
| 480 | #if defined(RCC_PLLI2S_SUPPORT) |
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| 481 | /** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL |
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| 482 | * @{ |
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| 483 | */ |
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| 484 | #define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ |
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| 485 | #define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ |
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| 486 | #define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ |
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| 487 | #define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ |
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| 488 | #define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ |
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| 489 | #define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ |
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| 490 | #define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ |
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| 491 | #define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ |
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| 492 | #define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ |
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| 493 | /** |
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| 494 | * @} |
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| 495 | */ |
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| 496 | |||
| 497 | #endif /* RCC_PLLI2S_SUPPORT */ |
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| 498 | |||
| 499 | #if defined(RCC_PLL2_SUPPORT) |
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| 500 | /** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL |
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| 501 | * @{ |
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| 502 | */ |
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| 503 | #define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ |
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| 504 | #define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ |
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| 505 | #define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ |
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| 506 | #define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ |
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| 507 | #define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ |
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| 508 | #define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ |
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| 509 | #define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ |
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| 510 | #define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ |
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| 511 | #define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ |
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| 512 | /** |
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| 513 | * @} |
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| 514 | */ |
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| 515 | |||
| 516 | #endif /* RCC_PLL2_SUPPORT */ |
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| 517 | |||
| 518 | /** |
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| 519 | * @} |
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| 520 | */ |
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| 521 | |||
| 522 | /* Exported macro ------------------------------------------------------------*/ |
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| 523 | /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros |
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| 524 | * @{ |
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| 525 | */ |
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| 526 | |||
| 527 | /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros |
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| 528 | * @{ |
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| 529 | */ |
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| 530 | |||
| 531 | /** |
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| 532 | * @brief Write a value in RCC register |
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| 533 | * @param __REG__ Register to be written |
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| 534 | * @param __VALUE__ Value to be written in the register |
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| 535 | * @retval None |
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| 536 | */ |
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| 537 | #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) |
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| 538 | |||
| 539 | /** |
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| 540 | * @brief Read a value in RCC register |
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| 541 | * @param __REG__ Register to be read |
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| 542 | * @retval Register value |
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| 543 | */ |
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| 544 | #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) |
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| 545 | /** |
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| 546 | * @} |
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| 547 | */ |
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| 548 | |||
| 549 | /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies |
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| 550 | * @{ |
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| 551 | */ |
||
| 552 | |||
| 553 | #if defined(RCC_CFGR_PLLMULL6_5) |
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| 554 | /** |
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| 555 | * @brief Helper macro to calculate the PLLCLK frequency |
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| 556 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); |
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| 557 | * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1) |
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| 558 | * @param __PLLMUL__: This parameter can be one of the following values: |
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| 559 | * @arg @ref LL_RCC_PLL_MUL_4 |
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| 560 | * @arg @ref LL_RCC_PLL_MUL_5 |
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| 561 | * @arg @ref LL_RCC_PLL_MUL_6 |
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| 562 | * @arg @ref LL_RCC_PLL_MUL_7 |
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| 563 | * @arg @ref LL_RCC_PLL_MUL_8 |
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| 564 | * @arg @ref LL_RCC_PLL_MUL_9 |
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| 565 | * @arg @ref LL_RCC_PLL_MUL_6_5 |
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| 566 | * @retval PLL clock frequency (in Hz) |
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| 567 | */ |
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| 568 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ |
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| 569 | (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \ |
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| 570 | ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\ |
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| 571 | (((__INPUTFREQ__) * 13U) / 2U)) |
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| 572 | |||
| 573 | #else |
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| 574 | /** |
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| 575 | * @brief Helper macro to calculate the PLLCLK frequency |
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| 576 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ()); |
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| 577 | * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2) |
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| 578 | * @param __PLLMUL__: This parameter can be one of the following values: |
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| 579 | * @arg @ref LL_RCC_PLL_MUL_2 |
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| 580 | * @arg @ref LL_RCC_PLL_MUL_3 |
||
| 581 | * @arg @ref LL_RCC_PLL_MUL_4 |
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| 582 | * @arg @ref LL_RCC_PLL_MUL_5 |
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| 583 | * @arg @ref LL_RCC_PLL_MUL_6 |
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| 584 | * @arg @ref LL_RCC_PLL_MUL_7 |
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| 585 | * @arg @ref LL_RCC_PLL_MUL_8 |
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| 586 | * @arg @ref LL_RCC_PLL_MUL_9 |
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| 587 | * @arg @ref LL_RCC_PLL_MUL_10 |
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| 588 | * @arg @ref LL_RCC_PLL_MUL_11 |
||
| 589 | * @arg @ref LL_RCC_PLL_MUL_12 |
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| 590 | * @arg @ref LL_RCC_PLL_MUL_13 |
||
| 591 | * @arg @ref LL_RCC_PLL_MUL_14 |
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| 592 | * @arg @ref LL_RCC_PLL_MUL_15 |
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| 593 | * @arg @ref LL_RCC_PLL_MUL_16 |
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| 594 | * @retval PLL clock frequency (in Hz) |
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| 595 | */ |
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| 596 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U)) |
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| 597 | #endif /* RCC_CFGR_PLLMULL6_5 */ |
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| 598 | |||
| 599 | #if defined(RCC_PLLI2S_SUPPORT) |
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| 600 | /** |
||
| 601 | * @brief Helper macro to calculate the PLLI2S frequency |
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| 602 | * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); |
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| 603 | * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value) |
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| 604 | * @param __PLLI2SMUL__: This parameter can be one of the following values: |
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| 605 | * @arg @ref LL_RCC_PLLI2S_MUL_8 |
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| 606 | * @arg @ref LL_RCC_PLLI2S_MUL_9 |
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| 607 | * @arg @ref LL_RCC_PLLI2S_MUL_10 |
||
| 608 | * @arg @ref LL_RCC_PLLI2S_MUL_11 |
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| 609 | * @arg @ref LL_RCC_PLLI2S_MUL_12 |
||
| 610 | * @arg @ref LL_RCC_PLLI2S_MUL_13 |
||
| 611 | * @arg @ref LL_RCC_PLLI2S_MUL_14 |
||
| 612 | * @arg @ref LL_RCC_PLLI2S_MUL_16 |
||
| 613 | * @arg @ref LL_RCC_PLLI2S_MUL_20 |
||
| 614 | * @param __PLLI2SDIV__: This parameter can be one of the following values: |
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| 615 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 |
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| 616 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 |
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| 617 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 |
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| 618 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 |
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| 619 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 |
||
| 620 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 |
||
| 621 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 |
||
| 622 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 |
||
| 623 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 |
||
| 624 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 |
||
| 625 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 |
||
| 626 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 |
||
| 627 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 |
||
| 628 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 |
||
| 629 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 |
||
| 630 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 |
||
| 631 | * @retval PLLI2S clock frequency (in Hz) |
||
| 632 | */ |
||
| 633 | #define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) |
||
| 634 | #endif /* RCC_PLLI2S_SUPPORT */ |
||
| 635 | |||
| 636 | #if defined(RCC_PLL2_SUPPORT) |
||
| 637 | /** |
||
| 638 | * @brief Helper macro to calculate the PLL2 frequency |
||
| 639 | * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); |
||
| 640 | * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value) |
||
| 641 | * @param __PLL2MUL__: This parameter can be one of the following values: |
||
| 642 | * @arg @ref LL_RCC_PLL2_MUL_8 |
||
| 643 | * @arg @ref LL_RCC_PLL2_MUL_9 |
||
| 644 | * @arg @ref LL_RCC_PLL2_MUL_10 |
||
| 645 | * @arg @ref LL_RCC_PLL2_MUL_11 |
||
| 646 | * @arg @ref LL_RCC_PLL2_MUL_12 |
||
| 647 | * @arg @ref LL_RCC_PLL2_MUL_13 |
||
| 648 | * @arg @ref LL_RCC_PLL2_MUL_14 |
||
| 649 | * @arg @ref LL_RCC_PLL2_MUL_16 |
||
| 650 | * @arg @ref LL_RCC_PLL2_MUL_20 |
||
| 651 | * @param __PLL2DIV__: This parameter can be one of the following values: |
||
| 652 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 |
||
| 653 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 |
||
| 654 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 |
||
| 655 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 |
||
| 656 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 |
||
| 657 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 |
||
| 658 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 |
||
| 659 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 |
||
| 660 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 |
||
| 661 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 |
||
| 662 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 |
||
| 663 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 |
||
| 664 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 |
||
| 665 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 |
||
| 666 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 |
||
| 667 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 |
||
| 668 | * @retval PLL2 clock frequency (in Hz) |
||
| 669 | */ |
||
| 670 | #define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) |
||
| 671 | #endif /* RCC_PLL2_SUPPORT */ |
||
| 672 | |||
| 673 | /** |
||
| 674 | * @brief Helper macro to calculate the HCLK frequency |
||
| 675 | * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler |
||
| 676 | * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) |
||
| 677 | * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) |
||
| 678 | * @param __AHBPRESCALER__: This parameter can be one of the following values: |
||
| 679 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
||
| 680 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
||
| 681 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
||
| 682 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
||
| 683 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
||
| 684 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
||
| 685 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
||
| 686 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
||
| 687 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
||
| 688 | * @retval HCLK clock frequency (in Hz) |
||
| 689 | */ |
||
| 690 | #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) |
||
| 691 | |||
| 692 | /** |
||
| 693 | * @brief Helper macro to calculate the PCLK1 frequency (ABP1) |
||
| 694 | * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler |
||
| 695 | * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) |
||
| 696 | * @param __HCLKFREQ__ HCLK frequency |
||
| 697 | * @param __APB1PRESCALER__: This parameter can be one of the following values: |
||
| 698 | * @arg @ref LL_RCC_APB1_DIV_1 |
||
| 699 | * @arg @ref LL_RCC_APB1_DIV_2 |
||
| 700 | * @arg @ref LL_RCC_APB1_DIV_4 |
||
| 701 | * @arg @ref LL_RCC_APB1_DIV_8 |
||
| 702 | * @arg @ref LL_RCC_APB1_DIV_16 |
||
| 703 | * @retval PCLK1 clock frequency (in Hz) |
||
| 704 | */ |
||
| 705 | #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) |
||
| 706 | |||
| 707 | /** |
||
| 708 | * @brief Helper macro to calculate the PCLK2 frequency (ABP2) |
||
| 709 | * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler |
||
| 710 | * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) |
||
| 711 | * @param __HCLKFREQ__ HCLK frequency |
||
| 712 | * @param __APB2PRESCALER__: This parameter can be one of the following values: |
||
| 713 | * @arg @ref LL_RCC_APB2_DIV_1 |
||
| 714 | * @arg @ref LL_RCC_APB2_DIV_2 |
||
| 715 | * @arg @ref LL_RCC_APB2_DIV_4 |
||
| 716 | * @arg @ref LL_RCC_APB2_DIV_8 |
||
| 717 | * @arg @ref LL_RCC_APB2_DIV_16 |
||
| 718 | * @retval PCLK2 clock frequency (in Hz) |
||
| 719 | */ |
||
| 720 | #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) |
||
| 721 | |||
| 722 | /** |
||
| 723 | * @} |
||
| 724 | */ |
||
| 725 | |||
| 726 | /** |
||
| 727 | * @} |
||
| 728 | */ |
||
| 729 | |||
| 730 | /* Exported functions --------------------------------------------------------*/ |
||
| 731 | /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions |
||
| 732 | * @{ |
||
| 733 | */ |
||
| 734 | |||
| 735 | /** @defgroup RCC_LL_EF_HSE HSE |
||
| 736 | * @{ |
||
| 737 | */ |
||
| 738 | |||
| 739 | /** |
||
| 740 | * @brief Enable the Clock Security System. |
||
| 741 | * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS |
||
| 742 | * @retval None |
||
| 743 | */ |
||
| 744 | __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) |
||
| 745 | { |
||
| 746 | SET_BIT(RCC->CR, RCC_CR_CSSON); |
||
| 747 | } |
||
| 748 | |||
| 749 | /** |
||
| 750 | * @brief Enable HSE external oscillator (HSE Bypass) |
||
| 751 | * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass |
||
| 752 | * @retval None |
||
| 753 | */ |
||
| 754 | __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) |
||
| 755 | { |
||
| 756 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); |
||
| 757 | } |
||
| 758 | |||
| 759 | /** |
||
| 760 | * @brief Disable HSE external oscillator (HSE Bypass) |
||
| 761 | * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass |
||
| 762 | * @retval None |
||
| 763 | */ |
||
| 764 | __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) |
||
| 765 | { |
||
| 766 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
||
| 767 | } |
||
| 768 | |||
| 769 | /** |
||
| 770 | * @brief Enable HSE crystal oscillator (HSE ON) |
||
| 771 | * @rmtoll CR HSEON LL_RCC_HSE_Enable |
||
| 772 | * @retval None |
||
| 773 | */ |
||
| 774 | __STATIC_INLINE void LL_RCC_HSE_Enable(void) |
||
| 775 | { |
||
| 776 | SET_BIT(RCC->CR, RCC_CR_HSEON); |
||
| 777 | } |
||
| 778 | |||
| 779 | /** |
||
| 780 | * @brief Disable HSE crystal oscillator (HSE ON) |
||
| 781 | * @rmtoll CR HSEON LL_RCC_HSE_Disable |
||
| 782 | * @retval None |
||
| 783 | */ |
||
| 784 | __STATIC_INLINE void LL_RCC_HSE_Disable(void) |
||
| 785 | { |
||
| 786 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); |
||
| 787 | } |
||
| 788 | |||
| 789 | /** |
||
| 790 | * @brief Check if HSE oscillator Ready |
||
| 791 | * @rmtoll CR HSERDY LL_RCC_HSE_IsReady |
||
| 792 | * @retval State of bit (1 or 0). |
||
| 793 | */ |
||
| 794 | __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) |
||
| 795 | { |
||
| 796 | return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); |
||
| 797 | } |
||
| 798 | |||
| 799 | #if defined(RCC_CFGR2_PREDIV2) |
||
| 800 | /** |
||
| 801 | * @brief Get PREDIV2 division factor |
||
| 802 | * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2 |
||
| 803 | * @retval Returned value can be one of the following values: |
||
| 804 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 |
||
| 805 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 |
||
| 806 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 |
||
| 807 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 |
||
| 808 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 |
||
| 809 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 |
||
| 810 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 |
||
| 811 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 |
||
| 812 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 |
||
| 813 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 |
||
| 814 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 |
||
| 815 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 |
||
| 816 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 |
||
| 817 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 |
||
| 818 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 |
||
| 819 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 |
||
| 820 | */ |
||
| 821 | __STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void) |
||
| 822 | { |
||
| 823 | return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); |
||
| 824 | } |
||
| 825 | #endif /* RCC_CFGR2_PREDIV2 */ |
||
| 826 | |||
| 827 | /** |
||
| 828 | * @} |
||
| 829 | */ |
||
| 830 | |||
| 831 | /** @defgroup RCC_LL_EF_HSI HSI |
||
| 832 | * @{ |
||
| 833 | */ |
||
| 834 | |||
| 835 | /** |
||
| 836 | * @brief Enable HSI oscillator |
||
| 837 | * @rmtoll CR HSION LL_RCC_HSI_Enable |
||
| 838 | * @retval None |
||
| 839 | */ |
||
| 840 | __STATIC_INLINE void LL_RCC_HSI_Enable(void) |
||
| 841 | { |
||
| 842 | SET_BIT(RCC->CR, RCC_CR_HSION); |
||
| 843 | } |
||
| 844 | |||
| 845 | /** |
||
| 846 | * @brief Disable HSI oscillator |
||
| 847 | * @rmtoll CR HSION LL_RCC_HSI_Disable |
||
| 848 | * @retval None |
||
| 849 | */ |
||
| 850 | __STATIC_INLINE void LL_RCC_HSI_Disable(void) |
||
| 851 | { |
||
| 852 | CLEAR_BIT(RCC->CR, RCC_CR_HSION); |
||
| 853 | } |
||
| 854 | |||
| 855 | /** |
||
| 856 | * @brief Check if HSI clock is ready |
||
| 857 | * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady |
||
| 858 | * @retval State of bit (1 or 0). |
||
| 859 | */ |
||
| 860 | __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) |
||
| 861 | { |
||
| 862 | return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); |
||
| 863 | } |
||
| 864 | |||
| 865 | /** |
||
| 866 | * @brief Get HSI Calibration value |
||
| 867 | * @note When HSITRIM is written, HSICAL is updated with the sum of |
||
| 868 | * HSITRIM and the factory trim value |
||
| 869 | * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration |
||
| 870 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
||
| 871 | */ |
||
| 872 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) |
||
| 873 | { |
||
| 874 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); |
||
| 875 | } |
||
| 876 | |||
| 877 | /** |
||
| 878 | * @brief Set HSI Calibration trimming |
||
| 879 | * @note user-programmable trimming value that is added to the HSICAL |
||
| 880 | * @note Default value is 16, which, when added to the HSICAL value, |
||
| 881 | * should trim the HSI to 16 MHz +/- 1 % |
||
| 882 | * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming |
||
| 883 | * @param Value between Min_Data = 0x00 and Max_Data = 0x1F |
||
| 884 | * @retval None |
||
| 885 | */ |
||
| 886 | __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) |
||
| 887 | { |
||
| 888 | MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); |
||
| 889 | } |
||
| 890 | |||
| 891 | /** |
||
| 892 | * @brief Get HSI Calibration trimming |
||
| 893 | * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming |
||
| 894 | * @retval Between Min_Data = 0x00 and Max_Data = 0x1F |
||
| 895 | */ |
||
| 896 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) |
||
| 897 | { |
||
| 898 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); |
||
| 899 | } |
||
| 900 | |||
| 901 | /** |
||
| 902 | * @} |
||
| 903 | */ |
||
| 904 | |||
| 905 | /** @defgroup RCC_LL_EF_LSE LSE |
||
| 906 | * @{ |
||
| 907 | */ |
||
| 908 | |||
| 909 | /** |
||
| 910 | * @brief Enable Low Speed External (LSE) crystal. |
||
| 911 | * @rmtoll BDCR LSEON LL_RCC_LSE_Enable |
||
| 912 | * @retval None |
||
| 913 | */ |
||
| 914 | __STATIC_INLINE void LL_RCC_LSE_Enable(void) |
||
| 915 | { |
||
| 916 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
||
| 917 | } |
||
| 918 | |||
| 919 | /** |
||
| 920 | * @brief Disable Low Speed External (LSE) crystal. |
||
| 921 | * @rmtoll BDCR LSEON LL_RCC_LSE_Disable |
||
| 922 | * @retval None |
||
| 923 | */ |
||
| 924 | __STATIC_INLINE void LL_RCC_LSE_Disable(void) |
||
| 925 | { |
||
| 926 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
||
| 927 | } |
||
| 928 | |||
| 929 | /** |
||
| 930 | * @brief Enable external clock source (LSE bypass). |
||
| 931 | * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass |
||
| 932 | * @retval None |
||
| 933 | */ |
||
| 934 | __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) |
||
| 935 | { |
||
| 936 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
||
| 937 | } |
||
| 938 | |||
| 939 | /** |
||
| 940 | * @brief Disable external clock source (LSE bypass). |
||
| 941 | * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass |
||
| 942 | * @retval None |
||
| 943 | */ |
||
| 944 | __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) |
||
| 945 | { |
||
| 946 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
||
| 947 | } |
||
| 948 | |||
| 949 | /** |
||
| 950 | * @brief Check if LSE oscillator Ready |
||
| 951 | * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady |
||
| 952 | * @retval State of bit (1 or 0). |
||
| 953 | */ |
||
| 954 | __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) |
||
| 955 | { |
||
| 956 | return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); |
||
| 957 | } |
||
| 958 | |||
| 959 | /** |
||
| 960 | * @} |
||
| 961 | */ |
||
| 962 | |||
| 963 | /** @defgroup RCC_LL_EF_LSI LSI |
||
| 964 | * @{ |
||
| 965 | */ |
||
| 966 | |||
| 967 | /** |
||
| 968 | * @brief Enable LSI Oscillator |
||
| 969 | * @rmtoll CSR LSION LL_RCC_LSI_Enable |
||
| 970 | * @retval None |
||
| 971 | */ |
||
| 972 | __STATIC_INLINE void LL_RCC_LSI_Enable(void) |
||
| 973 | { |
||
| 974 | SET_BIT(RCC->CSR, RCC_CSR_LSION); |
||
| 975 | } |
||
| 976 | |||
| 977 | /** |
||
| 978 | * @brief Disable LSI Oscillator |
||
| 979 | * @rmtoll CSR LSION LL_RCC_LSI_Disable |
||
| 980 | * @retval None |
||
| 981 | */ |
||
| 982 | __STATIC_INLINE void LL_RCC_LSI_Disable(void) |
||
| 983 | { |
||
| 984 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); |
||
| 985 | } |
||
| 986 | |||
| 987 | /** |
||
| 988 | * @brief Check if LSI is Ready |
||
| 989 | * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady |
||
| 990 | * @retval State of bit (1 or 0). |
||
| 991 | */ |
||
| 992 | __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) |
||
| 993 | { |
||
| 994 | return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); |
||
| 995 | } |
||
| 996 | |||
| 997 | /** |
||
| 998 | * @} |
||
| 999 | */ |
||
| 1000 | |||
| 1001 | /** @defgroup RCC_LL_EF_System System |
||
| 1002 | * @{ |
||
| 1003 | */ |
||
| 1004 | |||
| 1005 | /** |
||
| 1006 | * @brief Configure the system clock source |
||
| 1007 | * @rmtoll CFGR SW LL_RCC_SetSysClkSource |
||
| 1008 | * @param Source This parameter can be one of the following values: |
||
| 1009 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI |
||
| 1010 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE |
||
| 1011 | * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL |
||
| 1012 | * @retval None |
||
| 1013 | */ |
||
| 1014 | __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) |
||
| 1015 | { |
||
| 1016 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); |
||
| 1017 | } |
||
| 1018 | |||
| 1019 | /** |
||
| 1020 | * @brief Get the system clock source |
||
| 1021 | * @rmtoll CFGR SWS LL_RCC_GetSysClkSource |
||
| 1022 | * @retval Returned value can be one of the following values: |
||
| 1023 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI |
||
| 1024 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE |
||
| 1025 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL |
||
| 1026 | */ |
||
| 1027 | __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) |
||
| 1028 | { |
||
| 1029 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); |
||
| 1030 | } |
||
| 1031 | |||
| 1032 | /** |
||
| 1033 | * @brief Set AHB prescaler |
||
| 1034 | * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler |
||
| 1035 | * @param Prescaler This parameter can be one of the following values: |
||
| 1036 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
||
| 1037 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
||
| 1038 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
||
| 1039 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
||
| 1040 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
||
| 1041 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
||
| 1042 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
||
| 1043 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
||
| 1044 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
||
| 1045 | * @retval None |
||
| 1046 | */ |
||
| 1047 | __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) |
||
| 1048 | { |
||
| 1049 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); |
||
| 1050 | } |
||
| 1051 | |||
| 1052 | /** |
||
| 1053 | * @brief Set APB1 prescaler |
||
| 1054 | * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler |
||
| 1055 | * @param Prescaler This parameter can be one of the following values: |
||
| 1056 | * @arg @ref LL_RCC_APB1_DIV_1 |
||
| 1057 | * @arg @ref LL_RCC_APB1_DIV_2 |
||
| 1058 | * @arg @ref LL_RCC_APB1_DIV_4 |
||
| 1059 | * @arg @ref LL_RCC_APB1_DIV_8 |
||
| 1060 | * @arg @ref LL_RCC_APB1_DIV_16 |
||
| 1061 | * @retval None |
||
| 1062 | */ |
||
| 1063 | __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) |
||
| 1064 | { |
||
| 1065 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); |
||
| 1066 | } |
||
| 1067 | |||
| 1068 | /** |
||
| 1069 | * @brief Set APB2 prescaler |
||
| 1070 | * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler |
||
| 1071 | * @param Prescaler This parameter can be one of the following values: |
||
| 1072 | * @arg @ref LL_RCC_APB2_DIV_1 |
||
| 1073 | * @arg @ref LL_RCC_APB2_DIV_2 |
||
| 1074 | * @arg @ref LL_RCC_APB2_DIV_4 |
||
| 1075 | * @arg @ref LL_RCC_APB2_DIV_8 |
||
| 1076 | * @arg @ref LL_RCC_APB2_DIV_16 |
||
| 1077 | * @retval None |
||
| 1078 | */ |
||
| 1079 | __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) |
||
| 1080 | { |
||
| 1081 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); |
||
| 1082 | } |
||
| 1083 | |||
| 1084 | /** |
||
| 1085 | * @brief Get AHB prescaler |
||
| 1086 | * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler |
||
| 1087 | * @retval Returned value can be one of the following values: |
||
| 1088 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
||
| 1089 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
||
| 1090 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
||
| 1091 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
||
| 1092 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
||
| 1093 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
||
| 1094 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
||
| 1095 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
||
| 1096 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
||
| 1097 | */ |
||
| 1098 | __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) |
||
| 1099 | { |
||
| 1100 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); |
||
| 1101 | } |
||
| 1102 | |||
| 1103 | /** |
||
| 1104 | * @brief Get APB1 prescaler |
||
| 1105 | * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler |
||
| 1106 | * @retval Returned value can be one of the following values: |
||
| 1107 | * @arg @ref LL_RCC_APB1_DIV_1 |
||
| 1108 | * @arg @ref LL_RCC_APB1_DIV_2 |
||
| 1109 | * @arg @ref LL_RCC_APB1_DIV_4 |
||
| 1110 | * @arg @ref LL_RCC_APB1_DIV_8 |
||
| 1111 | * @arg @ref LL_RCC_APB1_DIV_16 |
||
| 1112 | */ |
||
| 1113 | __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) |
||
| 1114 | { |
||
| 1115 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); |
||
| 1116 | } |
||
| 1117 | |||
| 1118 | /** |
||
| 1119 | * @brief Get APB2 prescaler |
||
| 1120 | * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler |
||
| 1121 | * @retval Returned value can be one of the following values: |
||
| 1122 | * @arg @ref LL_RCC_APB2_DIV_1 |
||
| 1123 | * @arg @ref LL_RCC_APB2_DIV_2 |
||
| 1124 | * @arg @ref LL_RCC_APB2_DIV_4 |
||
| 1125 | * @arg @ref LL_RCC_APB2_DIV_8 |
||
| 1126 | * @arg @ref LL_RCC_APB2_DIV_16 |
||
| 1127 | */ |
||
| 1128 | __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) |
||
| 1129 | { |
||
| 1130 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); |
||
| 1131 | } |
||
| 1132 | |||
| 1133 | /** |
||
| 1134 | * @} |
||
| 1135 | */ |
||
| 1136 | |||
| 1137 | /** @defgroup RCC_LL_EF_MCO MCO |
||
| 1138 | * @{ |
||
| 1139 | */ |
||
| 1140 | |||
| 1141 | /** |
||
| 1142 | * @brief Configure MCOx |
||
| 1143 | * @rmtoll CFGR MCO LL_RCC_ConfigMCO |
||
| 1144 | * @param MCOxSource This parameter can be one of the following values: |
||
| 1145 | * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK |
||
| 1146 | * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK |
||
| 1147 | * @arg @ref LL_RCC_MCO1SOURCE_HSI |
||
| 1148 | * @arg @ref LL_RCC_MCO1SOURCE_HSE |
||
| 1149 | * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 |
||
| 1150 | * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*) |
||
| 1151 | * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*) |
||
| 1152 | * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*) |
||
| 1153 | * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*) |
||
| 1154 | * |
||
| 1155 | * (*) value not defined in all devices |
||
| 1156 | * @retval None |
||
| 1157 | */ |
||
| 1158 | __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource) |
||
| 1159 | { |
||
| 1160 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); |
||
| 1161 | } |
||
| 1162 | |||
| 1163 | /** |
||
| 1164 | * @} |
||
| 1165 | */ |
||
| 1166 | |||
| 1167 | /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source |
||
| 1168 | * @{ |
||
| 1169 | */ |
||
| 1170 | |||
| 1171 | #if defined(RCC_CFGR2_I2S2SRC) |
||
| 1172 | /** |
||
| 1173 | * @brief Configure I2Sx clock source |
||
| 1174 | * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n |
||
| 1175 | * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource |
||
| 1176 | * @param I2SxSource This parameter can be one of the following values: |
||
| 1177 | * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK |
||
| 1178 | * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO |
||
| 1179 | * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK |
||
| 1180 | * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO |
||
| 1181 | * @retval None |
||
| 1182 | */ |
||
| 1183 | __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) |
||
| 1184 | { |
||
| 1185 | MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U)); |
||
| 1186 | } |
||
| 1187 | #endif /* RCC_CFGR2_I2S2SRC */ |
||
| 1188 | |||
| 1189 | #if defined(USB_OTG_FS) || defined(USB) |
||
| 1190 | /** |
||
| 1191 | * @brief Configure USB clock source |
||
| 1192 | * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n |
||
| 1193 | * CFGR USBPRE LL_RCC_SetUSBClockSource |
||
| 1194 | * @param USBxSource This parameter can be one of the following values: |
||
| 1195 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) |
||
| 1196 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) |
||
| 1197 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) |
||
| 1198 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) |
||
| 1199 | * |
||
| 1200 | * (*) value not defined in all devices |
||
| 1201 | * @retval None |
||
| 1202 | */ |
||
| 1203 | __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) |
||
| 1204 | { |
||
| 1205 | #if defined(RCC_CFGR_USBPRE) |
||
| 1206 | MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); |
||
| 1207 | #else /*RCC_CFGR_OTGFSPRE*/ |
||
| 1208 | MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource); |
||
| 1209 | #endif /*RCC_CFGR_USBPRE*/ |
||
| 1210 | } |
||
| 1211 | #endif /* USB_OTG_FS || USB */ |
||
| 1212 | |||
| 1213 | /** |
||
| 1214 | * @brief Configure ADC clock source |
||
| 1215 | * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource |
||
| 1216 | * @param ADCxSource This parameter can be one of the following values: |
||
| 1217 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 |
||
| 1218 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 |
||
| 1219 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 |
||
| 1220 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 |
||
| 1221 | * @retval None |
||
| 1222 | */ |
||
| 1223 | __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) |
||
| 1224 | { |
||
| 1225 | MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); |
||
| 1226 | } |
||
| 1227 | |||
| 1228 | #if defined(RCC_CFGR2_I2S2SRC) |
||
| 1229 | /** |
||
| 1230 | * @brief Get I2Sx clock source |
||
| 1231 | * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n |
||
| 1232 | * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource |
||
| 1233 | * @param I2Sx This parameter can be one of the following values: |
||
| 1234 | * @arg @ref LL_RCC_I2S2_CLKSOURCE |
||
| 1235 | * @arg @ref LL_RCC_I2S3_CLKSOURCE |
||
| 1236 | * @retval Returned value can be one of the following values: |
||
| 1237 | * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK |
||
| 1238 | * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO |
||
| 1239 | * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK |
||
| 1240 | * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO |
||
| 1241 | */ |
||
| 1242 | __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) |
||
| 1243 | { |
||
| 1244 | return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx); |
||
| 1245 | } |
||
| 1246 | #endif /* RCC_CFGR2_I2S2SRC */ |
||
| 1247 | |||
| 1248 | #if defined(USB_OTG_FS) || defined(USB) |
||
| 1249 | /** |
||
| 1250 | * @brief Get USBx clock source |
||
| 1251 | * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n |
||
| 1252 | * CFGR USBPRE LL_RCC_GetUSBClockSource |
||
| 1253 | * @param USBx This parameter can be one of the following values: |
||
| 1254 | * @arg @ref LL_RCC_USB_CLKSOURCE |
||
| 1255 | * @retval Returned value can be one of the following values: |
||
| 1256 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) |
||
| 1257 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) |
||
| 1258 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) |
||
| 1259 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) |
||
| 1260 | * |
||
| 1261 | * (*) value not defined in all devices |
||
| 1262 | */ |
||
| 1263 | __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) |
||
| 1264 | { |
||
| 1265 | return (uint32_t)(READ_BIT(RCC->CFGR, USBx)); |
||
| 1266 | } |
||
| 1267 | #endif /* USB_OTG_FS || USB */ |
||
| 1268 | |||
| 1269 | /** |
||
| 1270 | * @brief Get ADCx clock source |
||
| 1271 | * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource |
||
| 1272 | * @param ADCx This parameter can be one of the following values: |
||
| 1273 | * @arg @ref LL_RCC_ADC_CLKSOURCE |
||
| 1274 | * @retval Returned value can be one of the following values: |
||
| 1275 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 |
||
| 1276 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 |
||
| 1277 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 |
||
| 1278 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 |
||
| 1279 | */ |
||
| 1280 | __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) |
||
| 1281 | { |
||
| 1282 | return (uint32_t)(READ_BIT(RCC->CFGR, ADCx)); |
||
| 1283 | } |
||
| 1284 | |||
| 1285 | /** |
||
| 1286 | * @} |
||
| 1287 | */ |
||
| 1288 | |||
| 1289 | /** @defgroup RCC_LL_EF_RTC RTC |
||
| 1290 | * @{ |
||
| 1291 | */ |
||
| 1292 | |||
| 1293 | /** |
||
| 1294 | * @brief Set RTC Clock Source |
||
| 1295 | * @note Once the RTC clock source has been selected, it cannot be changed any more unless |
||
| 1296 | * the Backup domain is reset. The BDRST bit can be used to reset them. |
||
| 1297 | * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource |
||
| 1298 | * @param Source This parameter can be one of the following values: |
||
| 1299 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
||
| 1300 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
||
| 1301 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
||
| 1302 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 |
||
| 1303 | * @retval None |
||
| 1304 | */ |
||
| 1305 | __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) |
||
| 1306 | { |
||
| 1307 | MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); |
||
| 1308 | } |
||
| 1309 | |||
| 1310 | /** |
||
| 1311 | * @brief Get RTC Clock Source |
||
| 1312 | * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource |
||
| 1313 | * @retval Returned value can be one of the following values: |
||
| 1314 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
||
| 1315 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
||
| 1316 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
||
| 1317 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 |
||
| 1318 | */ |
||
| 1319 | __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) |
||
| 1320 | { |
||
| 1321 | return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); |
||
| 1322 | } |
||
| 1323 | |||
| 1324 | /** |
||
| 1325 | * @brief Enable RTC |
||
| 1326 | * @rmtoll BDCR RTCEN LL_RCC_EnableRTC |
||
| 1327 | * @retval None |
||
| 1328 | */ |
||
| 1329 | __STATIC_INLINE void LL_RCC_EnableRTC(void) |
||
| 1330 | { |
||
| 1331 | SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
||
| 1332 | } |
||
| 1333 | |||
| 1334 | /** |
||
| 1335 | * @brief Disable RTC |
||
| 1336 | * @rmtoll BDCR RTCEN LL_RCC_DisableRTC |
||
| 1337 | * @retval None |
||
| 1338 | */ |
||
| 1339 | __STATIC_INLINE void LL_RCC_DisableRTC(void) |
||
| 1340 | { |
||
| 1341 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
||
| 1342 | } |
||
| 1343 | |||
| 1344 | /** |
||
| 1345 | * @brief Check if RTC has been enabled or not |
||
| 1346 | * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC |
||
| 1347 | * @retval State of bit (1 or 0). |
||
| 1348 | */ |
||
| 1349 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) |
||
| 1350 | { |
||
| 1351 | return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); |
||
| 1352 | } |
||
| 1353 | |||
| 1354 | /** |
||
| 1355 | * @brief Force the Backup domain reset |
||
| 1356 | * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset |
||
| 1357 | * @retval None |
||
| 1358 | */ |
||
| 1359 | __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) |
||
| 1360 | { |
||
| 1361 | SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
||
| 1362 | } |
||
| 1363 | |||
| 1364 | /** |
||
| 1365 | * @brief Release the Backup domain reset |
||
| 1366 | * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset |
||
| 1367 | * @retval None |
||
| 1368 | */ |
||
| 1369 | __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) |
||
| 1370 | { |
||
| 1371 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
||
| 1372 | } |
||
| 1373 | |||
| 1374 | /** |
||
| 1375 | * @} |
||
| 1376 | */ |
||
| 1377 | |||
| 1378 | /** @defgroup RCC_LL_EF_PLL PLL |
||
| 1379 | * @{ |
||
| 1380 | */ |
||
| 1381 | |||
| 1382 | /** |
||
| 1383 | * @brief Enable PLL |
||
| 1384 | * @rmtoll CR PLLON LL_RCC_PLL_Enable |
||
| 1385 | * @retval None |
||
| 1386 | */ |
||
| 1387 | __STATIC_INLINE void LL_RCC_PLL_Enable(void) |
||
| 1388 | { |
||
| 1389 | SET_BIT(RCC->CR, RCC_CR_PLLON); |
||
| 1390 | } |
||
| 1391 | |||
| 1392 | /** |
||
| 1393 | * @brief Disable PLL |
||
| 1394 | * @note Cannot be disabled if the PLL clock is used as the system clock |
||
| 1395 | * @rmtoll CR PLLON LL_RCC_PLL_Disable |
||
| 1396 | * @retval None |
||
| 1397 | */ |
||
| 1398 | __STATIC_INLINE void LL_RCC_PLL_Disable(void) |
||
| 1399 | { |
||
| 1400 | CLEAR_BIT(RCC->CR, RCC_CR_PLLON); |
||
| 1401 | } |
||
| 1402 | |||
| 1403 | /** |
||
| 1404 | * @brief Check if PLL Ready |
||
| 1405 | * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady |
||
| 1406 | * @retval State of bit (1 or 0). |
||
| 1407 | */ |
||
| 1408 | __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) |
||
| 1409 | { |
||
| 1410 | return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); |
||
| 1411 | } |
||
| 1412 | |||
| 1413 | /** |
||
| 1414 | * @brief Configure PLL used for SYSCLK Domain |
||
| 1415 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
||
| 1416 | * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n |
||
| 1417 | * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n |
||
| 1418 | * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n |
||
| 1419 | * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS |
||
| 1420 | * @param Source This parameter can be one of the following values: |
||
| 1421 | * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 |
||
| 1422 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 |
||
| 1423 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*) |
||
| 1424 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*) |
||
| 1425 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*) |
||
| 1426 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*) |
||
| 1427 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*) |
||
| 1428 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*) |
||
| 1429 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*) |
||
| 1430 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*) |
||
| 1431 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*) |
||
| 1432 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*) |
||
| 1433 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*) |
||
| 1434 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*) |
||
| 1435 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*) |
||
| 1436 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*) |
||
| 1437 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*) |
||
| 1438 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*) |
||
| 1439 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*) |
||
| 1440 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*) |
||
| 1441 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*) |
||
| 1442 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*) |
||
| 1443 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*) |
||
| 1444 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*) |
||
| 1445 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*) |
||
| 1446 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*) |
||
| 1447 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*) |
||
| 1448 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*) |
||
| 1449 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*) |
||
| 1450 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*) |
||
| 1451 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*) |
||
| 1452 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*) |
||
| 1453 | * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*) |
||
| 1454 | * |
||
| 1455 | * (*) value not defined in all devices |
||
| 1456 | * @param PLLMul This parameter can be one of the following values: |
||
| 1457 | * @arg @ref LL_RCC_PLL_MUL_2 (*) |
||
| 1458 | * @arg @ref LL_RCC_PLL_MUL_3 (*) |
||
| 1459 | * @arg @ref LL_RCC_PLL_MUL_4 |
||
| 1460 | * @arg @ref LL_RCC_PLL_MUL_5 |
||
| 1461 | * @arg @ref LL_RCC_PLL_MUL_6 |
||
| 1462 | * @arg @ref LL_RCC_PLL_MUL_7 |
||
| 1463 | * @arg @ref LL_RCC_PLL_MUL_8 |
||
| 1464 | * @arg @ref LL_RCC_PLL_MUL_9 |
||
| 1465 | * @arg @ref LL_RCC_PLL_MUL_6_5 (*) |
||
| 1466 | * @arg @ref LL_RCC_PLL_MUL_10 (*) |
||
| 1467 | * @arg @ref LL_RCC_PLL_MUL_11 (*) |
||
| 1468 | * @arg @ref LL_RCC_PLL_MUL_12 (*) |
||
| 1469 | * @arg @ref LL_RCC_PLL_MUL_13 (*) |
||
| 1470 | * @arg @ref LL_RCC_PLL_MUL_14 (*) |
||
| 1471 | * @arg @ref LL_RCC_PLL_MUL_15 (*) |
||
| 1472 | * @arg @ref LL_RCC_PLL_MUL_16 (*) |
||
| 1473 | * |
||
| 1474 | * (*) value not defined in all devices |
||
| 1475 | * @retval None |
||
| 1476 | */ |
||
| 1477 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) |
||
| 1478 | { |
||
| 1479 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL, |
||
| 1480 | (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul); |
||
| 1481 | #if defined(RCC_CFGR2_PREDIV1) |
||
| 1482 | #if defined(RCC_CFGR2_PREDIV1SRC) |
||
| 1483 | MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), |
||
| 1484 | (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); |
||
| 1485 | #else |
||
| 1486 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); |
||
| 1487 | #endif /*RCC_CFGR2_PREDIV1SRC*/ |
||
| 1488 | #endif /*RCC_CFGR2_PREDIV1*/ |
||
| 1489 | } |
||
| 1490 | |||
| 1491 | /** |
||
| 1492 | * @brief Configure PLL clock source |
||
| 1493 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n |
||
| 1494 | * CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource |
||
| 1495 | * @param PLLSource This parameter can be one of the following values: |
||
| 1496 | * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 |
||
| 1497 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
||
| 1498 | * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) |
||
| 1499 | * @retval None |
||
| 1500 | */ |
||
| 1501 | __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) |
||
| 1502 | { |
||
| 1503 | #if defined(RCC_CFGR2_PREDIV1SRC) |
||
| 1504 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); |
||
| 1505 | #endif /* RCC_CFGR2_PREDIV1SRC */ |
||
| 1506 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); |
||
| 1507 | } |
||
| 1508 | |||
| 1509 | /** |
||
| 1510 | * @brief Get the oscillator used as PLL clock source. |
||
| 1511 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n |
||
| 1512 | * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource |
||
| 1513 | * @retval Returned value can be one of the following values: |
||
| 1514 | * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 |
||
| 1515 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
||
| 1516 | * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) |
||
| 1517 | * |
||
| 1518 | * (*) value not defined in all devices |
||
| 1519 | */ |
||
| 1520 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) |
||
| 1521 | { |
||
| 1522 | #if defined(RCC_CFGR2_PREDIV1SRC) |
||
| 1523 | uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); |
||
| 1524 | uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); |
||
| 1525 | return (uint32_t)(pllsrc | predivsrc); |
||
| 1526 | #else |
||
| 1527 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); |
||
| 1528 | #endif /*RCC_CFGR2_PREDIV1SRC*/ |
||
| 1529 | } |
||
| 1530 | |||
| 1531 | /** |
||
| 1532 | * @brief Get PLL multiplication Factor |
||
| 1533 | * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator |
||
| 1534 | * @retval Returned value can be one of the following values: |
||
| 1535 | * @arg @ref LL_RCC_PLL_MUL_2 (*) |
||
| 1536 | * @arg @ref LL_RCC_PLL_MUL_3 (*) |
||
| 1537 | * @arg @ref LL_RCC_PLL_MUL_4 |
||
| 1538 | * @arg @ref LL_RCC_PLL_MUL_5 |
||
| 1539 | * @arg @ref LL_RCC_PLL_MUL_6 |
||
| 1540 | * @arg @ref LL_RCC_PLL_MUL_7 |
||
| 1541 | * @arg @ref LL_RCC_PLL_MUL_8 |
||
| 1542 | * @arg @ref LL_RCC_PLL_MUL_9 |
||
| 1543 | * @arg @ref LL_RCC_PLL_MUL_6_5 (*) |
||
| 1544 | * @arg @ref LL_RCC_PLL_MUL_10 (*) |
||
| 1545 | * @arg @ref LL_RCC_PLL_MUL_11 (*) |
||
| 1546 | * @arg @ref LL_RCC_PLL_MUL_12 (*) |
||
| 1547 | * @arg @ref LL_RCC_PLL_MUL_13 (*) |
||
| 1548 | * @arg @ref LL_RCC_PLL_MUL_14 (*) |
||
| 1549 | * @arg @ref LL_RCC_PLL_MUL_15 (*) |
||
| 1550 | * @arg @ref LL_RCC_PLL_MUL_16 (*) |
||
| 1551 | * |
||
| 1552 | * (*) value not defined in all devices |
||
| 1553 | */ |
||
| 1554 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) |
||
| 1555 | { |
||
| 1556 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL)); |
||
| 1557 | } |
||
| 1558 | |||
| 1559 | /** |
||
| 1560 | * @brief Get PREDIV1 division factor for the main PLL |
||
| 1561 | * @note They can be written only when the PLL is disabled |
||
| 1562 | * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n |
||
| 1563 | * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv |
||
| 1564 | * @retval Returned value can be one of the following values: |
||
| 1565 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
||
| 1566 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
||
| 1567 | * @arg @ref LL_RCC_PREDIV_DIV_3 (*) |
||
| 1568 | * @arg @ref LL_RCC_PREDIV_DIV_4 (*) |
||
| 1569 | * @arg @ref LL_RCC_PREDIV_DIV_5 (*) |
||
| 1570 | * @arg @ref LL_RCC_PREDIV_DIV_6 (*) |
||
| 1571 | * @arg @ref LL_RCC_PREDIV_DIV_7 (*) |
||
| 1572 | * @arg @ref LL_RCC_PREDIV_DIV_8 (*) |
||
| 1573 | * @arg @ref LL_RCC_PREDIV_DIV_9 (*) |
||
| 1574 | * @arg @ref LL_RCC_PREDIV_DIV_10 (*) |
||
| 1575 | * @arg @ref LL_RCC_PREDIV_DIV_11 (*) |
||
| 1576 | * @arg @ref LL_RCC_PREDIV_DIV_12 (*) |
||
| 1577 | * @arg @ref LL_RCC_PREDIV_DIV_13 (*) |
||
| 1578 | * @arg @ref LL_RCC_PREDIV_DIV_14 (*) |
||
| 1579 | * @arg @ref LL_RCC_PREDIV_DIV_15 (*) |
||
| 1580 | * @arg @ref LL_RCC_PREDIV_DIV_16 (*) |
||
| 1581 | * |
||
| 1582 | * (*) value not defined in all devices |
||
| 1583 | */ |
||
| 1584 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) |
||
| 1585 | { |
||
| 1586 | #if defined(RCC_CFGR2_PREDIV1) |
||
| 1587 | return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); |
||
| 1588 | #else |
||
| 1589 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos); |
||
| 1590 | #endif /*RCC_CFGR2_PREDIV1*/ |
||
| 1591 | } |
||
| 1592 | |||
| 1593 | /** |
||
| 1594 | * @} |
||
| 1595 | */ |
||
| 1596 | |||
| 1597 | #if defined(RCC_PLLI2S_SUPPORT) |
||
| 1598 | /** @defgroup RCC_LL_EF_PLLI2S PLLI2S |
||
| 1599 | * @{ |
||
| 1600 | */ |
||
| 1601 | |||
| 1602 | /** |
||
| 1603 | * @brief Enable PLLI2S |
||
| 1604 | * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable |
||
| 1605 | * @retval None |
||
| 1606 | */ |
||
| 1607 | __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) |
||
| 1608 | { |
||
| 1609 | SET_BIT(RCC->CR, RCC_CR_PLL3ON); |
||
| 1610 | } |
||
| 1611 | |||
| 1612 | /** |
||
| 1613 | * @brief Disable PLLI2S |
||
| 1614 | * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable |
||
| 1615 | * @retval None |
||
| 1616 | */ |
||
| 1617 | __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) |
||
| 1618 | { |
||
| 1619 | CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); |
||
| 1620 | } |
||
| 1621 | |||
| 1622 | /** |
||
| 1623 | * @brief Check if PLLI2S Ready |
||
| 1624 | * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady |
||
| 1625 | * @retval State of bit (1 or 0). |
||
| 1626 | */ |
||
| 1627 | __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) |
||
| 1628 | { |
||
| 1629 | return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)); |
||
| 1630 | } |
||
| 1631 | |||
| 1632 | /** |
||
| 1633 | * @brief Configure PLLI2S used for I2S Domain |
||
| 1634 | * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n |
||
| 1635 | * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S |
||
| 1636 | * @param Divider This parameter can be one of the following values: |
||
| 1637 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 |
||
| 1638 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 |
||
| 1639 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 |
||
| 1640 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 |
||
| 1641 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 |
||
| 1642 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 |
||
| 1643 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 |
||
| 1644 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 |
||
| 1645 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 |
||
| 1646 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 |
||
| 1647 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 |
||
| 1648 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 |
||
| 1649 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 |
||
| 1650 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 |
||
| 1651 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 |
||
| 1652 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 |
||
| 1653 | * @param Multiplicator This parameter can be one of the following values: |
||
| 1654 | * @arg @ref LL_RCC_PLLI2S_MUL_8 |
||
| 1655 | * @arg @ref LL_RCC_PLLI2S_MUL_9 |
||
| 1656 | * @arg @ref LL_RCC_PLLI2S_MUL_10 |
||
| 1657 | * @arg @ref LL_RCC_PLLI2S_MUL_11 |
||
| 1658 | * @arg @ref LL_RCC_PLLI2S_MUL_12 |
||
| 1659 | * @arg @ref LL_RCC_PLLI2S_MUL_13 |
||
| 1660 | * @arg @ref LL_RCC_PLLI2S_MUL_14 |
||
| 1661 | * @arg @ref LL_RCC_PLLI2S_MUL_16 |
||
| 1662 | * @arg @ref LL_RCC_PLLI2S_MUL_20 |
||
| 1663 | * @retval None |
||
| 1664 | */ |
||
| 1665 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator) |
||
| 1666 | { |
||
| 1667 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator); |
||
| 1668 | } |
||
| 1669 | |||
| 1670 | /** |
||
| 1671 | * @brief Get PLLI2S Multiplication Factor |
||
| 1672 | * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator |
||
| 1673 | * @retval Returned value can be one of the following values: |
||
| 1674 | * @arg @ref LL_RCC_PLLI2S_MUL_8 |
||
| 1675 | * @arg @ref LL_RCC_PLLI2S_MUL_9 |
||
| 1676 | * @arg @ref LL_RCC_PLLI2S_MUL_10 |
||
| 1677 | * @arg @ref LL_RCC_PLLI2S_MUL_11 |
||
| 1678 | * @arg @ref LL_RCC_PLLI2S_MUL_12 |
||
| 1679 | * @arg @ref LL_RCC_PLLI2S_MUL_13 |
||
| 1680 | * @arg @ref LL_RCC_PLLI2S_MUL_14 |
||
| 1681 | * @arg @ref LL_RCC_PLLI2S_MUL_16 |
||
| 1682 | * @arg @ref LL_RCC_PLLI2S_MUL_20 |
||
| 1683 | */ |
||
| 1684 | __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void) |
||
| 1685 | { |
||
| 1686 | return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL)); |
||
| 1687 | } |
||
| 1688 | |||
| 1689 | /** |
||
| 1690 | * @} |
||
| 1691 | */ |
||
| 1692 | #endif /* RCC_PLLI2S_SUPPORT */ |
||
| 1693 | |||
| 1694 | #if defined(RCC_PLL2_SUPPORT) |
||
| 1695 | /** @defgroup RCC_LL_EF_PLL2 PLL2 |
||
| 1696 | * @{ |
||
| 1697 | */ |
||
| 1698 | |||
| 1699 | /** |
||
| 1700 | * @brief Enable PLL2 |
||
| 1701 | * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable |
||
| 1702 | * @retval None |
||
| 1703 | */ |
||
| 1704 | __STATIC_INLINE void LL_RCC_PLL2_Enable(void) |
||
| 1705 | { |
||
| 1706 | SET_BIT(RCC->CR, RCC_CR_PLL2ON); |
||
| 1707 | } |
||
| 1708 | |||
| 1709 | /** |
||
| 1710 | * @brief Disable PLL2 |
||
| 1711 | * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable |
||
| 1712 | * @retval None |
||
| 1713 | */ |
||
| 1714 | __STATIC_INLINE void LL_RCC_PLL2_Disable(void) |
||
| 1715 | { |
||
| 1716 | CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); |
||
| 1717 | } |
||
| 1718 | |||
| 1719 | /** |
||
| 1720 | * @brief Check if PLL2 Ready |
||
| 1721 | * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady |
||
| 1722 | * @retval State of bit (1 or 0). |
||
| 1723 | */ |
||
| 1724 | __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) |
||
| 1725 | { |
||
| 1726 | return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)); |
||
| 1727 | } |
||
| 1728 | |||
| 1729 | /** |
||
| 1730 | * @brief Configure PLL2 used for PLL2 Domain |
||
| 1731 | * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n |
||
| 1732 | * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2 |
||
| 1733 | * @param Divider This parameter can be one of the following values: |
||
| 1734 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 |
||
| 1735 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 |
||
| 1736 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 |
||
| 1737 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 |
||
| 1738 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 |
||
| 1739 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 |
||
| 1740 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 |
||
| 1741 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 |
||
| 1742 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 |
||
| 1743 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 |
||
| 1744 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 |
||
| 1745 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 |
||
| 1746 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 |
||
| 1747 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 |
||
| 1748 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 |
||
| 1749 | * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 |
||
| 1750 | * @param Multiplicator This parameter can be one of the following values: |
||
| 1751 | * @arg @ref LL_RCC_PLL2_MUL_8 |
||
| 1752 | * @arg @ref LL_RCC_PLL2_MUL_9 |
||
| 1753 | * @arg @ref LL_RCC_PLL2_MUL_10 |
||
| 1754 | * @arg @ref LL_RCC_PLL2_MUL_11 |
||
| 1755 | * @arg @ref LL_RCC_PLL2_MUL_12 |
||
| 1756 | * @arg @ref LL_RCC_PLL2_MUL_13 |
||
| 1757 | * @arg @ref LL_RCC_PLL2_MUL_14 |
||
| 1758 | * @arg @ref LL_RCC_PLL2_MUL_16 |
||
| 1759 | * @arg @ref LL_RCC_PLL2_MUL_20 |
||
| 1760 | * @retval None |
||
| 1761 | */ |
||
| 1762 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator) |
||
| 1763 | { |
||
| 1764 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator); |
||
| 1765 | } |
||
| 1766 | |||
| 1767 | /** |
||
| 1768 | * @brief Get PLL2 Multiplication Factor |
||
| 1769 | * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator |
||
| 1770 | * @retval Returned value can be one of the following values: |
||
| 1771 | * @arg @ref LL_RCC_PLL2_MUL_8 |
||
| 1772 | * @arg @ref LL_RCC_PLL2_MUL_9 |
||
| 1773 | * @arg @ref LL_RCC_PLL2_MUL_10 |
||
| 1774 | * @arg @ref LL_RCC_PLL2_MUL_11 |
||
| 1775 | * @arg @ref LL_RCC_PLL2_MUL_12 |
||
| 1776 | * @arg @ref LL_RCC_PLL2_MUL_13 |
||
| 1777 | * @arg @ref LL_RCC_PLL2_MUL_14 |
||
| 1778 | * @arg @ref LL_RCC_PLL2_MUL_16 |
||
| 1779 | * @arg @ref LL_RCC_PLL2_MUL_20 |
||
| 1780 | */ |
||
| 1781 | __STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void) |
||
| 1782 | { |
||
| 1783 | return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL)); |
||
| 1784 | } |
||
| 1785 | |||
| 1786 | /** |
||
| 1787 | * @} |
||
| 1788 | */ |
||
| 1789 | #endif /* RCC_PLL2_SUPPORT */ |
||
| 1790 | |||
| 1791 | /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management |
||
| 1792 | * @{ |
||
| 1793 | */ |
||
| 1794 | |||
| 1795 | /** |
||
| 1796 | * @brief Clear LSI ready interrupt flag |
||
| 1797 | * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY |
||
| 1798 | * @retval None |
||
| 1799 | */ |
||
| 1800 | __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) |
||
| 1801 | { |
||
| 1802 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); |
||
| 1803 | } |
||
| 1804 | |||
| 1805 | /** |
||
| 1806 | * @brief Clear LSE ready interrupt flag |
||
| 1807 | * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY |
||
| 1808 | * @retval None |
||
| 1809 | */ |
||
| 1810 | __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) |
||
| 1811 | { |
||
| 1812 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); |
||
| 1813 | } |
||
| 1814 | |||
| 1815 | /** |
||
| 1816 | * @brief Clear HSI ready interrupt flag |
||
| 1817 | * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY |
||
| 1818 | * @retval None |
||
| 1819 | */ |
||
| 1820 | __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) |
||
| 1821 | { |
||
| 1822 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); |
||
| 1823 | } |
||
| 1824 | |||
| 1825 | /** |
||
| 1826 | * @brief Clear HSE ready interrupt flag |
||
| 1827 | * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY |
||
| 1828 | * @retval None |
||
| 1829 | */ |
||
| 1830 | __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) |
||
| 1831 | { |
||
| 1832 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); |
||
| 1833 | } |
||
| 1834 | |||
| 1835 | /** |
||
| 1836 | * @brief Clear PLL ready interrupt flag |
||
| 1837 | * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY |
||
| 1838 | * @retval None |
||
| 1839 | */ |
||
| 1840 | __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) |
||
| 1841 | { |
||
| 1842 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); |
||
| 1843 | } |
||
| 1844 | |||
| 1845 | #if defined(RCC_PLLI2S_SUPPORT) |
||
| 1846 | /** |
||
| 1847 | * @brief Clear PLLI2S ready interrupt flag |
||
| 1848 | * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY |
||
| 1849 | * @retval None |
||
| 1850 | */ |
||
| 1851 | __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) |
||
| 1852 | { |
||
| 1853 | SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC); |
||
| 1854 | } |
||
| 1855 | #endif /* RCC_PLLI2S_SUPPORT */ |
||
| 1856 | |||
| 1857 | #if defined(RCC_PLL2_SUPPORT) |
||
| 1858 | /** |
||
| 1859 | * @brief Clear PLL2 ready interrupt flag |
||
| 1860 | * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY |
||
| 1861 | * @retval None |
||
| 1862 | */ |
||
| 1863 | __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) |
||
| 1864 | { |
||
| 1865 | SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC); |
||
| 1866 | } |
||
| 1867 | #endif /* RCC_PLL2_SUPPORT */ |
||
| 1868 | |||
| 1869 | /** |
||
| 1870 | * @brief Clear Clock security system interrupt flag |
||
| 1871 | * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS |
||
| 1872 | * @retval None |
||
| 1873 | */ |
||
| 1874 | __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) |
||
| 1875 | { |
||
| 1876 | SET_BIT(RCC->CIR, RCC_CIR_CSSC); |
||
| 1877 | } |
||
| 1878 | |||
| 1879 | /** |
||
| 1880 | * @brief Check if LSI ready interrupt occurred or not |
||
| 1881 | * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY |
||
| 1882 | * @retval State of bit (1 or 0). |
||
| 1883 | */ |
||
| 1884 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) |
||
| 1885 | { |
||
| 1886 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); |
||
| 1887 | } |
||
| 1888 | |||
| 1889 | /** |
||
| 1890 | * @brief Check if LSE ready interrupt occurred or not |
||
| 1891 | * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY |
||
| 1892 | * @retval State of bit (1 or 0). |
||
| 1893 | */ |
||
| 1894 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) |
||
| 1895 | { |
||
| 1896 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); |
||
| 1897 | } |
||
| 1898 | |||
| 1899 | /** |
||
| 1900 | * @brief Check if HSI ready interrupt occurred or not |
||
| 1901 | * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY |
||
| 1902 | * @retval State of bit (1 or 0). |
||
| 1903 | */ |
||
| 1904 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) |
||
| 1905 | { |
||
| 1906 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); |
||
| 1907 | } |
||
| 1908 | |||
| 1909 | /** |
||
| 1910 | * @brief Check if HSE ready interrupt occurred or not |
||
| 1911 | * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY |
||
| 1912 | * @retval State of bit (1 or 0). |
||
| 1913 | */ |
||
| 1914 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) |
||
| 1915 | { |
||
| 1916 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); |
||
| 1917 | } |
||
| 1918 | |||
| 1919 | /** |
||
| 1920 | * @brief Check if PLL ready interrupt occurred or not |
||
| 1921 | * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY |
||
| 1922 | * @retval State of bit (1 or 0). |
||
| 1923 | */ |
||
| 1924 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) |
||
| 1925 | { |
||
| 1926 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); |
||
| 1927 | } |
||
| 1928 | |||
| 1929 | #if defined(RCC_PLLI2S_SUPPORT) |
||
| 1930 | /** |
||
| 1931 | * @brief Check if PLLI2S ready interrupt occurred or not |
||
| 1932 | * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY |
||
| 1933 | * @retval State of bit (1 or 0). |
||
| 1934 | */ |
||
| 1935 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) |
||
| 1936 | { |
||
| 1937 | return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF)); |
||
| 1938 | } |
||
| 1939 | #endif /* RCC_PLLI2S_SUPPORT */ |
||
| 1940 | |||
| 1941 | #if defined(RCC_PLL2_SUPPORT) |
||
| 1942 | /** |
||
| 1943 | * @brief Check if PLL2 ready interrupt occurred or not |
||
| 1944 | * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY |
||
| 1945 | * @retval State of bit (1 or 0). |
||
| 1946 | */ |
||
| 1947 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) |
||
| 1948 | { |
||
| 1949 | return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF)); |
||
| 1950 | } |
||
| 1951 | #endif /* RCC_PLL2_SUPPORT */ |
||
| 1952 | |||
| 1953 | /** |
||
| 1954 | * @brief Check if Clock security system interrupt occurred or not |
||
| 1955 | * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS |
||
| 1956 | * @retval State of bit (1 or 0). |
||
| 1957 | */ |
||
| 1958 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) |
||
| 1959 | { |
||
| 1960 | return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); |
||
| 1961 | } |
||
| 1962 | |||
| 1963 | /** |
||
| 1964 | * @brief Check if RCC flag Independent Watchdog reset is set or not. |
||
| 1965 | * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST |
||
| 1966 | * @retval State of bit (1 or 0). |
||
| 1967 | */ |
||
| 1968 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) |
||
| 1969 | { |
||
| 1970 | return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); |
||
| 1971 | } |
||
| 1972 | |||
| 1973 | /** |
||
| 1974 | * @brief Check if RCC flag Low Power reset is set or not. |
||
| 1975 | * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST |
||
| 1976 | * @retval State of bit (1 or 0). |
||
| 1977 | */ |
||
| 1978 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) |
||
| 1979 | { |
||
| 1980 | return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); |
||
| 1981 | } |
||
| 1982 | |||
| 1983 | /** |
||
| 1984 | * @brief Check if RCC flag Pin reset is set or not. |
||
| 1985 | * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST |
||
| 1986 | * @retval State of bit (1 or 0). |
||
| 1987 | */ |
||
| 1988 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) |
||
| 1989 | { |
||
| 1990 | return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); |
||
| 1991 | } |
||
| 1992 | |||
| 1993 | /** |
||
| 1994 | * @brief Check if RCC flag POR/PDR reset is set or not. |
||
| 1995 | * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST |
||
| 1996 | * @retval State of bit (1 or 0). |
||
| 1997 | */ |
||
| 1998 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) |
||
| 1999 | { |
||
| 2000 | return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); |
||
| 2001 | } |
||
| 2002 | |||
| 2003 | /** |
||
| 2004 | * @brief Check if RCC flag Software reset is set or not. |
||
| 2005 | * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST |
||
| 2006 | * @retval State of bit (1 or 0). |
||
| 2007 | */ |
||
| 2008 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) |
||
| 2009 | { |
||
| 2010 | return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); |
||
| 2011 | } |
||
| 2012 | |||
| 2013 | /** |
||
| 2014 | * @brief Check if RCC flag Window Watchdog reset is set or not. |
||
| 2015 | * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST |
||
| 2016 | * @retval State of bit (1 or 0). |
||
| 2017 | */ |
||
| 2018 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) |
||
| 2019 | { |
||
| 2020 | return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); |
||
| 2021 | } |
||
| 2022 | |||
| 2023 | /** |
||
| 2024 | * @brief Set RMVF bit to clear the reset flags. |
||
| 2025 | * @rmtoll CSR RMVF LL_RCC_ClearResetFlags |
||
| 2026 | * @retval None |
||
| 2027 | */ |
||
| 2028 | __STATIC_INLINE void LL_RCC_ClearResetFlags(void) |
||
| 2029 | { |
||
| 2030 | SET_BIT(RCC->CSR, RCC_CSR_RMVF); |
||
| 2031 | } |
||
| 2032 | |||
| 2033 | /** |
||
| 2034 | * @} |
||
| 2035 | */ |
||
| 2036 | |||
| 2037 | /** @defgroup RCC_LL_EF_IT_Management IT Management |
||
| 2038 | * @{ |
||
| 2039 | */ |
||
| 2040 | |||
| 2041 | /** |
||
| 2042 | * @brief Enable LSI ready interrupt |
||
| 2043 | * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY |
||
| 2044 | * @retval None |
||
| 2045 | */ |
||
| 2046 | __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) |
||
| 2047 | { |
||
| 2048 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
||
| 2049 | } |
||
| 2050 | |||
| 2051 | /** |
||
| 2052 | * @brief Enable LSE ready interrupt |
||
| 2053 | * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY |
||
| 2054 | * @retval None |
||
| 2055 | */ |
||
| 2056 | __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) |
||
| 2057 | { |
||
| 2058 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
||
| 2059 | } |
||
| 2060 | |||
| 2061 | /** |
||
| 2062 | * @brief Enable HSI ready interrupt |
||
| 2063 | * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY |
||
| 2064 | * @retval None |
||
| 2065 | */ |
||
| 2066 | __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) |
||
| 2067 | { |
||
| 2068 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
||
| 2069 | } |
||
| 2070 | |||
| 2071 | /** |
||
| 2072 | * @brief Enable HSE ready interrupt |
||
| 2073 | * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY |
||
| 2074 | * @retval None |
||
| 2075 | */ |
||
| 2076 | __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) |
||
| 2077 | { |
||
| 2078 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
||
| 2079 | } |
||
| 2080 | |||
| 2081 | /** |
||
| 2082 | * @brief Enable PLL ready interrupt |
||
| 2083 | * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY |
||
| 2084 | * @retval None |
||
| 2085 | */ |
||
| 2086 | __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) |
||
| 2087 | { |
||
| 2088 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
||
| 2089 | } |
||
| 2090 | |||
| 2091 | #if defined(RCC_PLLI2S_SUPPORT) |
||
| 2092 | /** |
||
| 2093 | * @brief Enable PLLI2S ready interrupt |
||
| 2094 | * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY |
||
| 2095 | * @retval None |
||
| 2096 | */ |
||
| 2097 | __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) |
||
| 2098 | { |
||
| 2099 | SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); |
||
| 2100 | } |
||
| 2101 | #endif /* RCC_PLLI2S_SUPPORT */ |
||
| 2102 | |||
| 2103 | #if defined(RCC_PLL2_SUPPORT) |
||
| 2104 | /** |
||
| 2105 | * @brief Enable PLL2 ready interrupt |
||
| 2106 | * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY |
||
| 2107 | * @retval None |
||
| 2108 | */ |
||
| 2109 | __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) |
||
| 2110 | { |
||
| 2111 | SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); |
||
| 2112 | } |
||
| 2113 | #endif /* RCC_PLL2_SUPPORT */ |
||
| 2114 | |||
| 2115 | /** |
||
| 2116 | * @brief Disable LSI ready interrupt |
||
| 2117 | * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY |
||
| 2118 | * @retval None |
||
| 2119 | */ |
||
| 2120 | __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) |
||
| 2121 | { |
||
| 2122 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
||
| 2123 | } |
||
| 2124 | |||
| 2125 | /** |
||
| 2126 | * @brief Disable LSE ready interrupt |
||
| 2127 | * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY |
||
| 2128 | * @retval None |
||
| 2129 | */ |
||
| 2130 | __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) |
||
| 2131 | { |
||
| 2132 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
||
| 2133 | } |
||
| 2134 | |||
| 2135 | /** |
||
| 2136 | * @brief Disable HSI ready interrupt |
||
| 2137 | * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY |
||
| 2138 | * @retval None |
||
| 2139 | */ |
||
| 2140 | __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) |
||
| 2141 | { |
||
| 2142 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
||
| 2143 | } |
||
| 2144 | |||
| 2145 | /** |
||
| 2146 | * @brief Disable HSE ready interrupt |
||
| 2147 | * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY |
||
| 2148 | * @retval None |
||
| 2149 | */ |
||
| 2150 | __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) |
||
| 2151 | { |
||
| 2152 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
||
| 2153 | } |
||
| 2154 | |||
| 2155 | /** |
||
| 2156 | * @brief Disable PLL ready interrupt |
||
| 2157 | * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY |
||
| 2158 | * @retval None |
||
| 2159 | */ |
||
| 2160 | __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) |
||
| 2161 | { |
||
| 2162 | CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
||
| 2163 | } |
||
| 2164 | |||
| 2165 | #if defined(RCC_PLLI2S_SUPPORT) |
||
| 2166 | /** |
||
| 2167 | * @brief Disable PLLI2S ready interrupt |
||
| 2168 | * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY |
||
| 2169 | * @retval None |
||
| 2170 | */ |
||
| 2171 | __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) |
||
| 2172 | { |
||
| 2173 | CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); |
||
| 2174 | } |
||
| 2175 | #endif /* RCC_PLLI2S_SUPPORT */ |
||
| 2176 | |||
| 2177 | #if defined(RCC_PLL2_SUPPORT) |
||
| 2178 | /** |
||
| 2179 | * @brief Disable PLL2 ready interrupt |
||
| 2180 | * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY |
||
| 2181 | * @retval None |
||
| 2182 | */ |
||
| 2183 | __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) |
||
| 2184 | { |
||
| 2185 | CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); |
||
| 2186 | } |
||
| 2187 | #endif /* RCC_PLL2_SUPPORT */ |
||
| 2188 | |||
| 2189 | /** |
||
| 2190 | * @brief Checks if LSI ready interrupt source is enabled or disabled. |
||
| 2191 | * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY |
||
| 2192 | * @retval State of bit (1 or 0). |
||
| 2193 | */ |
||
| 2194 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) |
||
| 2195 | { |
||
| 2196 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); |
||
| 2197 | } |
||
| 2198 | |||
| 2199 | /** |
||
| 2200 | * @brief Checks if LSE ready interrupt source is enabled or disabled. |
||
| 2201 | * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY |
||
| 2202 | * @retval State of bit (1 or 0). |
||
| 2203 | */ |
||
| 2204 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) |
||
| 2205 | { |
||
| 2206 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); |
||
| 2207 | } |
||
| 2208 | |||
| 2209 | /** |
||
| 2210 | * @brief Checks if HSI ready interrupt source is enabled or disabled. |
||
| 2211 | * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY |
||
| 2212 | * @retval State of bit (1 or 0). |
||
| 2213 | */ |
||
| 2214 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) |
||
| 2215 | { |
||
| 2216 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); |
||
| 2217 | } |
||
| 2218 | |||
| 2219 | /** |
||
| 2220 | * @brief Checks if HSE ready interrupt source is enabled or disabled. |
||
| 2221 | * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY |
||
| 2222 | * @retval State of bit (1 or 0). |
||
| 2223 | */ |
||
| 2224 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) |
||
| 2225 | { |
||
| 2226 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); |
||
| 2227 | } |
||
| 2228 | |||
| 2229 | /** |
||
| 2230 | * @brief Checks if PLL ready interrupt source is enabled or disabled. |
||
| 2231 | * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY |
||
| 2232 | * @retval State of bit (1 or 0). |
||
| 2233 | */ |
||
| 2234 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) |
||
| 2235 | { |
||
| 2236 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); |
||
| 2237 | } |
||
| 2238 | |||
| 2239 | #if defined(RCC_PLLI2S_SUPPORT) |
||
| 2240 | /** |
||
| 2241 | * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. |
||
| 2242 | * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY |
||
| 2243 | * @retval State of bit (1 or 0). |
||
| 2244 | */ |
||
| 2245 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) |
||
| 2246 | { |
||
| 2247 | return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE)); |
||
| 2248 | } |
||
| 2249 | #endif /* RCC_PLLI2S_SUPPORT */ |
||
| 2250 | |||
| 2251 | #if defined(RCC_PLL2_SUPPORT) |
||
| 2252 | /** |
||
| 2253 | * @brief Checks if PLL2 ready interrupt source is enabled or disabled. |
||
| 2254 | * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY |
||
| 2255 | * @retval State of bit (1 or 0). |
||
| 2256 | */ |
||
| 2257 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) |
||
| 2258 | { |
||
| 2259 | return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE)); |
||
| 2260 | } |
||
| 2261 | #endif /* RCC_PLL2_SUPPORT */ |
||
| 2262 | |||
| 2263 | /** |
||
| 2264 | * @} |
||
| 2265 | */ |
||
| 2266 | |||
| 2267 | #if defined(USE_FULL_LL_DRIVER) |
||
| 2268 | /** @defgroup RCC_LL_EF_Init De-initialization function |
||
| 2269 | * @{ |
||
| 2270 | */ |
||
| 2271 | ErrorStatus LL_RCC_DeInit(void); |
||
| 2272 | /** |
||
| 2273 | * @} |
||
| 2274 | */ |
||
| 2275 | |||
| 2276 | /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions |
||
| 2277 | * @{ |
||
| 2278 | */ |
||
| 2279 | void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); |
||
| 2280 | #if defined(RCC_CFGR2_I2S2SRC) |
||
| 2281 | uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); |
||
| 2282 | #endif /* RCC_CFGR2_I2S2SRC */ |
||
| 2283 | #if defined(USB_OTG_FS) || defined(USB) |
||
| 2284 | uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); |
||
| 2285 | #endif /* USB_OTG_FS || USB */ |
||
| 2286 | uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); |
||
| 2287 | /** |
||
| 2288 | * @} |
||
| 2289 | */ |
||
| 2290 | #endif /* USE_FULL_LL_DRIVER */ |
||
| 2291 | |||
| 2292 | /** |
||
| 2293 | * @} |
||
| 2294 | */ |
||
| 2295 | |||
| 2296 | /** |
||
| 2297 | * @} |
||
| 2298 | */ |
||
| 2299 | |||
| 2300 | #endif /* RCC */ |
||
| 2301 | |||
| 2302 | /** |
||
| 2303 | * @} |
||
| 2304 | */ |
||
| 2305 | |||
| 2306 | #ifdef __cplusplus |
||
| 2307 | } |
||
| 2308 | #endif |
||
| 2309 | |||
| 2310 | #endif /* __STM32F1xx_LL_RCC_H */ |
||
| 2311 | |||
| 2312 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |