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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_pwr.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of PWR LL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32F1xx_LL_PWR_H |
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| 22 | #define __STM32F1xx_LL_PWR_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f1xx.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F1xx_LL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | #if defined(PWR) |
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| 36 | |||
| 37 | /** @defgroup PWR_LL PWR |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Private types -------------------------------------------------------------*/ |
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| 42 | /* Private variables ---------------------------------------------------------*/ |
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| 43 | /* Private constants ---------------------------------------------------------*/ |
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| 44 | /* Private macros ------------------------------------------------------------*/ |
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| 45 | /* Exported types ------------------------------------------------------------*/ |
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| 46 | /* Exported constants --------------------------------------------------------*/ |
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| 47 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
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| 48 | * @{ |
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| 49 | */ |
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| 50 | |||
| 51 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
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| 52 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
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| 53 | * @{ |
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| 54 | */ |
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| 55 | #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ |
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| 56 | #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ |
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| 57 | /** |
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| 58 | * @} |
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| 59 | */ |
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| 60 | |||
| 61 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
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| 62 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
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| 63 | * @{ |
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| 64 | */ |
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| 65 | #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ |
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| 66 | #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ |
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| 67 | #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ |
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| 68 | #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */ |
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| 69 | /** |
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| 70 | * @} |
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| 71 | */ |
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| 72 | |||
| 73 | |||
| 74 | /** @defgroup PWR_LL_EC_MODE_PWR Mode Power |
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| 75 | * @{ |
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| 76 | */ |
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| 77 | #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ |
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| 78 | #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ |
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| 79 | #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ |
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| 80 | /** |
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| 81 | * @} |
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| 82 | */ |
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| 83 | |||
| 84 | /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode |
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| 85 | * @{ |
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| 86 | */ |
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| 87 | #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ |
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| 88 | #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ |
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| 89 | /** |
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| 90 | * @} |
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| 91 | */ |
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| 92 | |||
| 93 | /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level |
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| 94 | * @{ |
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| 95 | */ |
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| 96 | #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ |
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| 97 | #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ |
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| 98 | #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ |
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| 99 | #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ |
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| 100 | #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ |
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| 101 | #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ |
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| 102 | #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ |
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| 103 | #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ |
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| 104 | /** |
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| 105 | * @} |
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| 106 | */ |
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| 107 | /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins |
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| 108 | * @{ |
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| 109 | */ |
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| 110 | #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */ |
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| 111 | /** |
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| 112 | * @} |
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| 113 | */ |
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| 114 | |||
| 115 | /** |
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| 116 | * @} |
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| 117 | */ |
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| 118 | |||
| 119 | |||
| 120 | /* Exported macro ------------------------------------------------------------*/ |
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| 121 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
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| 122 | * @{ |
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| 123 | */ |
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| 124 | |||
| 125 | /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros |
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| 126 | * @{ |
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| 127 | */ |
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| 128 | |||
| 129 | /** |
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| 130 | * @brief Write a value in PWR register |
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| 131 | * @param __REG__ Register to be written |
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| 132 | * @param __VALUE__ Value to be written in the register |
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| 133 | * @retval None |
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| 134 | */ |
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| 135 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
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| 136 | |||
| 137 | /** |
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| 138 | * @brief Read a value in PWR register |
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| 139 | * @param __REG__ Register to be read |
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| 140 | * @retval Register value |
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| 141 | */ |
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| 142 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
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| 143 | /** |
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| 144 | * @} |
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| 145 | */ |
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| 146 | |||
| 147 | /** |
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| 148 | * @} |
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| 149 | */ |
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| 150 | |||
| 151 | /* Exported functions --------------------------------------------------------*/ |
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| 152 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
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| 153 | * @{ |
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| 154 | */ |
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| 155 | |||
| 156 | /** @defgroup PWR_LL_EF_Configuration Configuration |
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| 157 | * @{ |
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| 158 | */ |
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| 159 | |||
| 160 | /** |
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| 161 | * @brief Enable access to the backup domain |
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| 162 | * @rmtoll CR DBP LL_PWR_EnableBkUpAccess |
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| 163 | * @retval None |
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| 164 | */ |
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| 165 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
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| 166 | { |
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| 167 | SET_BIT(PWR->CR, PWR_CR_DBP); |
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| 168 | } |
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| 169 | |||
| 170 | /** |
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| 171 | * @brief Disable access to the backup domain |
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| 172 | * @rmtoll CR DBP LL_PWR_DisableBkUpAccess |
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| 173 | * @retval None |
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| 174 | */ |
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| 175 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
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| 176 | { |
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| 177 | CLEAR_BIT(PWR->CR, PWR_CR_DBP); |
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| 178 | } |
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| 179 | |||
| 180 | /** |
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| 181 | * @brief Check if the backup domain is enabled |
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| 182 | * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess |
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| 183 | * @retval State of bit (1 or 0). |
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| 184 | */ |
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| 185 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
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| 186 | { |
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| 187 | return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); |
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| 188 | } |
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| 189 | |||
| 190 | /** |
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| 191 | * @brief Set voltage Regulator mode during deep sleep mode |
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| 192 | * @rmtoll CR LPDS LL_PWR_SetRegulModeDS |
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| 193 | * @param RegulMode This parameter can be one of the following values: |
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| 194 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
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| 195 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
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| 196 | * @retval None |
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| 197 | */ |
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| 198 | __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) |
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| 199 | { |
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| 200 | MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); |
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| 201 | } |
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| 202 | |||
| 203 | /** |
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| 204 | * @brief Get voltage Regulator mode during deep sleep mode |
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| 205 | * @rmtoll CR LPDS LL_PWR_GetRegulModeDS |
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| 206 | * @retval Returned value can be one of the following values: |
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| 207 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
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| 208 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
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| 209 | */ |
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| 210 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) |
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| 211 | { |
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| 212 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); |
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| 213 | } |
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| 214 | |||
| 215 | /** |
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| 216 | * @brief Set Power Down mode when CPU enters deepsleep |
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| 217 | * @rmtoll CR PDDS LL_PWR_SetPowerMode\n |
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| 218 | * @rmtoll CR LPDS LL_PWR_SetPowerMode |
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| 219 | * @param PDMode This parameter can be one of the following values: |
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| 220 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
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| 221 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
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| 222 | * @arg @ref LL_PWR_MODE_STANDBY |
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| 223 | * @retval None |
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| 224 | */ |
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| 225 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) |
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| 226 | { |
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| 227 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); |
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| 228 | } |
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| 229 | |||
| 230 | /** |
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| 231 | * @brief Get Power Down mode when CPU enters deepsleep |
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| 232 | * @rmtoll CR PDDS LL_PWR_GetPowerMode\n |
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| 233 | * @rmtoll CR LPDS LL_PWR_GetPowerMode |
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| 234 | * @retval Returned value can be one of the following values: |
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| 235 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
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| 236 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
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| 237 | * @arg @ref LL_PWR_MODE_STANDBY |
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| 238 | */ |
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| 239 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
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| 240 | { |
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| 241 | return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); |
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| 242 | } |
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| 243 | |||
| 244 | /** |
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| 245 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
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| 246 | * @rmtoll CR PLS LL_PWR_SetPVDLevel |
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| 247 | * @param PVDLevel This parameter can be one of the following values: |
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| 248 | * @arg @ref LL_PWR_PVDLEVEL_0 |
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| 249 | * @arg @ref LL_PWR_PVDLEVEL_1 |
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| 250 | * @arg @ref LL_PWR_PVDLEVEL_2 |
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| 251 | * @arg @ref LL_PWR_PVDLEVEL_3 |
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| 252 | * @arg @ref LL_PWR_PVDLEVEL_4 |
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| 253 | * @arg @ref LL_PWR_PVDLEVEL_5 |
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| 254 | * @arg @ref LL_PWR_PVDLEVEL_6 |
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| 255 | * @arg @ref LL_PWR_PVDLEVEL_7 |
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| 256 | * @retval None |
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| 257 | */ |
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| 258 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
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| 259 | { |
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| 260 | MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); |
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| 261 | } |
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| 262 | |||
| 263 | /** |
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| 264 | * @brief Get the voltage threshold detection |
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| 265 | * @rmtoll CR PLS LL_PWR_GetPVDLevel |
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| 266 | * @retval Returned value can be one of the following values: |
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| 267 | * @arg @ref LL_PWR_PVDLEVEL_0 |
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| 268 | * @arg @ref LL_PWR_PVDLEVEL_1 |
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| 269 | * @arg @ref LL_PWR_PVDLEVEL_2 |
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| 270 | * @arg @ref LL_PWR_PVDLEVEL_3 |
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| 271 | * @arg @ref LL_PWR_PVDLEVEL_4 |
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| 272 | * @arg @ref LL_PWR_PVDLEVEL_5 |
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| 273 | * @arg @ref LL_PWR_PVDLEVEL_6 |
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| 274 | * @arg @ref LL_PWR_PVDLEVEL_7 |
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| 275 | */ |
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| 276 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
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| 277 | { |
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| 278 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); |
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| 279 | } |
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| 280 | |||
| 281 | /** |
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| 282 | * @brief Enable Power Voltage Detector |
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| 283 | * @rmtoll CR PVDE LL_PWR_EnablePVD |
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| 284 | * @retval None |
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| 285 | */ |
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| 286 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
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| 287 | { |
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| 288 | SET_BIT(PWR->CR, PWR_CR_PVDE); |
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| 289 | } |
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| 290 | |||
| 291 | /** |
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| 292 | * @brief Disable Power Voltage Detector |
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| 293 | * @rmtoll CR PVDE LL_PWR_DisablePVD |
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| 294 | * @retval None |
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| 295 | */ |
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| 296 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
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| 297 | { |
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| 298 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); |
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| 299 | } |
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| 300 | |||
| 301 | /** |
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| 302 | * @brief Check if Power Voltage Detector is enabled |
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| 303 | * @rmtoll CR PVDE LL_PWR_IsEnabledPVD |
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| 304 | * @retval State of bit (1 or 0). |
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| 305 | */ |
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| 306 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
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| 307 | { |
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| 308 | return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); |
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| 309 | } |
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| 310 | |||
| 311 | /** |
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| 312 | * @brief Enable the WakeUp PINx functionality |
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| 313 | * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin |
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| 314 | * @param WakeUpPin This parameter can be one of the following values: |
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| 315 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
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| 316 | * @retval None |
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| 317 | */ |
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| 318 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
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| 319 | { |
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| 320 | SET_BIT(PWR->CSR, WakeUpPin); |
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| 321 | } |
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| 322 | |||
| 323 | /** |
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| 324 | * @brief Disable the WakeUp PINx functionality |
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| 325 | * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin |
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| 326 | * @param WakeUpPin This parameter can be one of the following values: |
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| 327 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
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| 328 | * @retval None |
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| 329 | */ |
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| 330 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
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| 331 | { |
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| 332 | CLEAR_BIT(PWR->CSR, WakeUpPin); |
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| 333 | } |
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| 334 | |||
| 335 | /** |
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| 336 | * @brief Check if the WakeUp PINx functionality is enabled |
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| 337 | * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin |
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| 338 | * @param WakeUpPin This parameter can be one of the following values: |
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| 339 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
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| 340 | * @retval State of bit (1 or 0). |
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| 341 | */ |
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| 342 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
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| 343 | { |
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| 344 | return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); |
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| 345 | } |
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| 346 | |||
| 347 | |||
| 348 | /** |
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| 349 | * @} |
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| 350 | */ |
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| 351 | |||
| 352 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
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| 353 | * @{ |
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| 354 | */ |
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| 355 | |||
| 356 | /** |
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| 357 | * @brief Get Wake-up Flag |
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| 358 | * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU |
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| 359 | * @retval State of bit (1 or 0). |
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| 360 | */ |
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| 361 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) |
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| 362 | { |
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| 363 | return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); |
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| 364 | } |
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| 365 | |||
| 366 | /** |
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| 367 | * @brief Get Standby Flag |
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| 368 | * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB |
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| 369 | * @retval State of bit (1 or 0). |
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| 370 | */ |
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| 371 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
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| 372 | { |
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| 373 | return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); |
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| 374 | } |
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| 375 | |||
| 376 | /** |
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| 377 | * @brief Indicate whether VDD voltage is below the selected PVD threshold |
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| 378 | * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO |
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| 379 | * @retval State of bit (1 or 0). |
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| 380 | */ |
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| 381 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
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| 382 | { |
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| 383 | return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); |
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| 384 | } |
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| 385 | |||
| 386 | /** |
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| 387 | * @brief Clear Standby Flag |
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| 388 | * @rmtoll CR CSBF LL_PWR_ClearFlag_SB |
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| 389 | * @retval None |
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| 390 | */ |
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| 391 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
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| 392 | { |
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| 393 | SET_BIT(PWR->CR, PWR_CR_CSBF); |
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| 394 | } |
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| 395 | |||
| 396 | /** |
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| 397 | * @brief Clear Wake-up Flags |
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| 398 | * @rmtoll CR CWUF LL_PWR_ClearFlag_WU |
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| 399 | * @retval None |
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| 400 | */ |
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| 401 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
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| 402 | { |
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| 403 | SET_BIT(PWR->CR, PWR_CR_CWUF); |
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| 404 | } |
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| 405 | |||
| 406 | /** |
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| 407 | * @} |
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| 408 | */ |
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| 409 | |||
| 410 | #if defined(USE_FULL_LL_DRIVER) |
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| 411 | /** @defgroup PWR_LL_EF_Init De-initialization function |
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| 412 | * @{ |
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| 413 | */ |
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| 414 | ErrorStatus LL_PWR_DeInit(void); |
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| 415 | /** |
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| 416 | * @} |
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| 417 | */ |
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| 418 | #endif /* USE_FULL_LL_DRIVER */ |
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| 419 | |||
| 420 | /** |
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| 421 | * @} |
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| 422 | */ |
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| 423 | |||
| 424 | /** |
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| 425 | * @} |
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| 426 | */ |
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| 427 | |||
| 428 | #endif /* defined(PWR) */ |
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| 429 | |||
| 430 | /** |
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| 431 | * @} |
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| 432 | */ |
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| 433 | |||
| 434 | #ifdef __cplusplus |
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| 435 | } |
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| 436 | #endif |
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| 437 | |||
| 438 | #endif /* __STM32F1xx_LL_PWR_H */ |
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| 439 | |||
| 440 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |