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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f1xx_ll_pwr.h |
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4 | * @author MCD Application Team |
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5 | * @brief Header file of PWR LL module. |
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6 | ****************************************************************************** |
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7 | * @attention |
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8 | * |
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9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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10 | * |
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11 | * Redistribution and use in source and binary forms, with or without modification, |
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12 | * are permitted provided that the following conditions are met: |
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13 | * 1. Redistributions of source code must retain the above copyright notice, |
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14 | * this list of conditions and the following disclaimer. |
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15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 | * this list of conditions and the following disclaimer in the documentation |
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17 | * and/or other materials provided with the distribution. |
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18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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19 | * may be used to endorse or promote products derived from this software |
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20 | * without specific prior written permission. |
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21 | * |
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22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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32 | * |
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33 | ****************************************************************************** |
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34 | */ |
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35 | |||
36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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37 | #ifndef __STM32F1xx_LL_PWR_H |
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38 | #define __STM32F1xx_LL_PWR_H |
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39 | |||
40 | #ifdef __cplusplus |
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41 | extern "C" { |
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42 | #endif |
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43 | |||
44 | /* Includes ------------------------------------------------------------------*/ |
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45 | #include "stm32f1xx.h" |
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46 | |||
47 | /** @addtogroup STM32F1xx_LL_Driver |
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48 | * @{ |
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49 | */ |
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50 | |||
51 | #if defined(PWR) |
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52 | |||
53 | /** @defgroup PWR_LL PWR |
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54 | * @{ |
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55 | */ |
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56 | |||
57 | /* Private types -------------------------------------------------------------*/ |
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58 | /* Private variables ---------------------------------------------------------*/ |
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59 | /* Private constants ---------------------------------------------------------*/ |
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60 | /* Private macros ------------------------------------------------------------*/ |
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61 | /* Exported types ------------------------------------------------------------*/ |
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62 | /* Exported constants --------------------------------------------------------*/ |
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63 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
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64 | * @{ |
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65 | */ |
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66 | |||
67 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
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68 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
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69 | * @{ |
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70 | */ |
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71 | #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ |
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72 | #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ |
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73 | /** |
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74 | * @} |
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75 | */ |
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76 | |||
77 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
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78 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
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79 | * @{ |
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80 | */ |
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81 | #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ |
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82 | #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ |
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83 | #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ |
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84 | #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */ |
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85 | /** |
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86 | * @} |
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87 | */ |
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88 | |||
89 | |||
90 | /** @defgroup PWR_LL_EC_MODE_PWR Mode Power |
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91 | * @{ |
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92 | */ |
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93 | #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ |
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94 | #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ |
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95 | #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ |
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96 | /** |
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97 | * @} |
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98 | */ |
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99 | |||
100 | /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode |
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101 | * @{ |
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102 | */ |
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103 | #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ |
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104 | #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ |
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105 | /** |
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106 | * @} |
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107 | */ |
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108 | |||
109 | /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level |
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110 | * @{ |
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111 | */ |
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112 | #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ |
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113 | #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ |
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114 | #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ |
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115 | #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ |
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116 | #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ |
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117 | #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ |
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118 | #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ |
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119 | #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ |
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120 | /** |
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121 | * @} |
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122 | */ |
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123 | /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins |
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124 | * @{ |
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125 | */ |
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126 | #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */ |
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127 | /** |
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128 | * @} |
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129 | */ |
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130 | |||
131 | /** |
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132 | * @} |
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133 | */ |
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134 | |||
135 | |||
136 | /* Exported macro ------------------------------------------------------------*/ |
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137 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
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138 | * @{ |
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139 | */ |
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140 | |||
141 | /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros |
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142 | * @{ |
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143 | */ |
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144 | |||
145 | /** |
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146 | * @brief Write a value in PWR register |
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147 | * @param __REG__ Register to be written |
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148 | * @param __VALUE__ Value to be written in the register |
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149 | * @retval None |
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150 | */ |
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151 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
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152 | |||
153 | /** |
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154 | * @brief Read a value in PWR register |
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155 | * @param __REG__ Register to be read |
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156 | * @retval Register value |
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157 | */ |
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158 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
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159 | /** |
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160 | * @} |
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161 | */ |
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162 | |||
163 | /** |
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164 | * @} |
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165 | */ |
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166 | |||
167 | /* Exported functions --------------------------------------------------------*/ |
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168 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
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169 | * @{ |
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170 | */ |
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171 | |||
172 | /** @defgroup PWR_LL_EF_Configuration Configuration |
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173 | * @{ |
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174 | */ |
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175 | |||
176 | /** |
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177 | * @brief Enable access to the backup domain |
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178 | * @rmtoll CR DBP LL_PWR_EnableBkUpAccess |
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179 | * @retval None |
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180 | */ |
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181 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
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182 | { |
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183 | SET_BIT(PWR->CR, PWR_CR_DBP); |
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184 | } |
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185 | |||
186 | /** |
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187 | * @brief Disable access to the backup domain |
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188 | * @rmtoll CR DBP LL_PWR_DisableBkUpAccess |
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189 | * @retval None |
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190 | */ |
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191 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
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192 | { |
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193 | CLEAR_BIT(PWR->CR, PWR_CR_DBP); |
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194 | } |
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195 | |||
196 | /** |
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197 | * @brief Check if the backup domain is enabled |
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198 | * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess |
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199 | * @retval State of bit (1 or 0). |
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200 | */ |
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201 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
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202 | { |
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203 | return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); |
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204 | } |
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205 | |||
206 | /** |
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207 | * @brief Set voltage Regulator mode during deep sleep mode |
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208 | * @rmtoll CR LPDS LL_PWR_SetRegulModeDS |
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209 | * @param RegulMode This parameter can be one of the following values: |
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210 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
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211 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
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212 | * @retval None |
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213 | */ |
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214 | __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) |
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215 | { |
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216 | MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); |
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217 | } |
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218 | |||
219 | /** |
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220 | * @brief Get voltage Regulator mode during deep sleep mode |
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221 | * @rmtoll CR LPDS LL_PWR_GetRegulModeDS |
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222 | * @retval Returned value can be one of the following values: |
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223 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
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224 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
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225 | */ |
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226 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) |
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227 | { |
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228 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); |
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229 | } |
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230 | |||
231 | /** |
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232 | * @brief Set Power Down mode when CPU enters deepsleep |
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233 | * @rmtoll CR PDDS LL_PWR_SetPowerMode\n |
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234 | * @rmtoll CR LPDS LL_PWR_SetPowerMode |
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235 | * @param PDMode This parameter can be one of the following values: |
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236 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
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237 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
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238 | * @arg @ref LL_PWR_MODE_STANDBY |
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239 | * @retval None |
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240 | */ |
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241 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) |
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242 | { |
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243 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); |
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244 | } |
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245 | |||
246 | /** |
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247 | * @brief Get Power Down mode when CPU enters deepsleep |
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248 | * @rmtoll CR PDDS LL_PWR_GetPowerMode\n |
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249 | * @rmtoll CR LPDS LL_PWR_GetPowerMode |
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250 | * @retval Returned value can be one of the following values: |
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251 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
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252 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
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253 | * @arg @ref LL_PWR_MODE_STANDBY |
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254 | */ |
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255 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
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256 | { |
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257 | return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); |
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258 | } |
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259 | |||
260 | /** |
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261 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
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262 | * @rmtoll CR PLS LL_PWR_SetPVDLevel |
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263 | * @param PVDLevel This parameter can be one of the following values: |
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264 | * @arg @ref LL_PWR_PVDLEVEL_0 |
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265 | * @arg @ref LL_PWR_PVDLEVEL_1 |
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266 | * @arg @ref LL_PWR_PVDLEVEL_2 |
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267 | * @arg @ref LL_PWR_PVDLEVEL_3 |
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268 | * @arg @ref LL_PWR_PVDLEVEL_4 |
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269 | * @arg @ref LL_PWR_PVDLEVEL_5 |
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270 | * @arg @ref LL_PWR_PVDLEVEL_6 |
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271 | * @arg @ref LL_PWR_PVDLEVEL_7 |
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272 | * @retval None |
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273 | */ |
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274 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
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275 | { |
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276 | MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); |
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277 | } |
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278 | |||
279 | /** |
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280 | * @brief Get the voltage threshold detection |
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281 | * @rmtoll CR PLS LL_PWR_GetPVDLevel |
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282 | * @retval Returned value can be one of the following values: |
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283 | * @arg @ref LL_PWR_PVDLEVEL_0 |
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284 | * @arg @ref LL_PWR_PVDLEVEL_1 |
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285 | * @arg @ref LL_PWR_PVDLEVEL_2 |
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286 | * @arg @ref LL_PWR_PVDLEVEL_3 |
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287 | * @arg @ref LL_PWR_PVDLEVEL_4 |
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288 | * @arg @ref LL_PWR_PVDLEVEL_5 |
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289 | * @arg @ref LL_PWR_PVDLEVEL_6 |
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290 | * @arg @ref LL_PWR_PVDLEVEL_7 |
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291 | */ |
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292 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
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293 | { |
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294 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); |
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295 | } |
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296 | |||
297 | /** |
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298 | * @brief Enable Power Voltage Detector |
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299 | * @rmtoll CR PVDE LL_PWR_EnablePVD |
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300 | * @retval None |
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301 | */ |
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302 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
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303 | { |
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304 | SET_BIT(PWR->CR, PWR_CR_PVDE); |
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305 | } |
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306 | |||
307 | /** |
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308 | * @brief Disable Power Voltage Detector |
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309 | * @rmtoll CR PVDE LL_PWR_DisablePVD |
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310 | * @retval None |
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311 | */ |
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312 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
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313 | { |
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314 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); |
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315 | } |
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316 | |||
317 | /** |
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318 | * @brief Check if Power Voltage Detector is enabled |
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319 | * @rmtoll CR PVDE LL_PWR_IsEnabledPVD |
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320 | * @retval State of bit (1 or 0). |
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321 | */ |
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322 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
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323 | { |
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324 | return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); |
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325 | } |
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326 | |||
327 | /** |
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328 | * @brief Enable the WakeUp PINx functionality |
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329 | * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin |
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330 | * @param WakeUpPin This parameter can be one of the following values: |
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331 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
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332 | * @retval None |
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333 | */ |
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334 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
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335 | { |
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336 | SET_BIT(PWR->CSR, WakeUpPin); |
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337 | } |
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338 | |||
339 | /** |
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340 | * @brief Disable the WakeUp PINx functionality |
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341 | * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin |
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342 | * @param WakeUpPin This parameter can be one of the following values: |
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343 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
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344 | * @retval None |
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345 | */ |
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346 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
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347 | { |
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348 | CLEAR_BIT(PWR->CSR, WakeUpPin); |
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349 | } |
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350 | |||
351 | /** |
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352 | * @brief Check if the WakeUp PINx functionality is enabled |
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353 | * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin |
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354 | * @param WakeUpPin This parameter can be one of the following values: |
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355 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
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356 | * @retval State of bit (1 or 0). |
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357 | */ |
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358 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
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359 | { |
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360 | return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); |
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361 | } |
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362 | |||
363 | |||
364 | /** |
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365 | * @} |
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366 | */ |
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367 | |||
368 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
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369 | * @{ |
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370 | */ |
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371 | |||
372 | /** |
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373 | * @brief Get Wake-up Flag |
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374 | * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU |
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375 | * @retval State of bit (1 or 0). |
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376 | */ |
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377 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) |
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378 | { |
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379 | return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); |
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380 | } |
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381 | |||
382 | /** |
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383 | * @brief Get Standby Flag |
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384 | * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB |
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385 | * @retval State of bit (1 or 0). |
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386 | */ |
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387 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
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388 | { |
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389 | return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); |
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390 | } |
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391 | |||
392 | /** |
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393 | * @brief Indicate whether VDD voltage is below the selected PVD threshold |
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394 | * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO |
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395 | * @retval State of bit (1 or 0). |
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396 | */ |
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397 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
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398 | { |
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399 | return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); |
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400 | } |
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401 | |||
402 | /** |
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403 | * @brief Clear Standby Flag |
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404 | * @rmtoll CR CSBF LL_PWR_ClearFlag_SB |
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405 | * @retval None |
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406 | */ |
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407 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
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408 | { |
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409 | SET_BIT(PWR->CR, PWR_CR_CSBF); |
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410 | } |
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411 | |||
412 | /** |
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413 | * @brief Clear Wake-up Flags |
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414 | * @rmtoll CR CWUF LL_PWR_ClearFlag_WU |
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415 | * @retval None |
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416 | */ |
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417 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
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418 | { |
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419 | SET_BIT(PWR->CR, PWR_CR_CWUF); |
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420 | } |
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421 | |||
422 | /** |
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423 | * @} |
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424 | */ |
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425 | |||
426 | #if defined(USE_FULL_LL_DRIVER) |
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427 | /** @defgroup PWR_LL_EF_Init De-initialization function |
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428 | * @{ |
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429 | */ |
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430 | ErrorStatus LL_PWR_DeInit(void); |
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431 | /** |
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432 | * @} |
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433 | */ |
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434 | #endif /* USE_FULL_LL_DRIVER */ |
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435 | |||
436 | /** |
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437 | * @} |
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438 | */ |
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439 | |||
440 | /** |
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441 | * @} |
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442 | */ |
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443 | |||
444 | #endif /* defined(PWR) */ |
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445 | |||
446 | /** |
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447 | * @} |
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448 | */ |
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449 | |||
450 | #ifdef __cplusplus |
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451 | } |
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452 | #endif |
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453 | |||
454 | #endif /* __STM32F1xx_LL_PWR_H */ |
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455 | |||
456 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |