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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_iwdg.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of IWDG LL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved. |
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| 11 | * |
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| 12 | * This software is licensed under terms that can be found in the LICENSE file |
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| 13 | * in the root directory of this software component. |
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| 14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | */ |
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| 18 | |||
| 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 20 | #ifndef STM32F1xx_LL_IWDG_H |
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| 21 | #define STM32F1xx_LL_IWDG_H |
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| 22 | |||
| 23 | #ifdef __cplusplus |
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| 24 | extern "C" { |
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| 25 | #endif |
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| 26 | |||
| 27 | /* Includes ------------------------------------------------------------------*/ |
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| 28 | #include "stm32f1xx.h" |
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| 29 | |||
| 30 | /** @addtogroup STM32F1xx_LL_Driver |
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| 31 | * @{ |
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| 32 | */ |
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| 33 | |||
| 34 | #if defined(IWDG) |
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| 35 | |||
| 36 | /** @defgroup IWDG_LL IWDG |
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| 37 | * @{ |
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| 38 | */ |
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| 39 | |||
| 40 | /* Private types -------------------------------------------------------------*/ |
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| 41 | /* Private variables ---------------------------------------------------------*/ |
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| 42 | |||
| 43 | /* Private constants ---------------------------------------------------------*/ |
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| 44 | /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants |
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| 45 | * @{ |
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| 46 | */ |
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| 47 | #define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ |
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| 48 | #define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ |
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| 49 | #define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ |
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| 50 | #define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ |
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| 51 | /** |
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| 52 | * @} |
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| 53 | */ |
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| 54 | |||
| 55 | /* Private macros ------------------------------------------------------------*/ |
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| 56 | |||
| 57 | /* Exported types ------------------------------------------------------------*/ |
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| 58 | /* Exported constants --------------------------------------------------------*/ |
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| 59 | /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants |
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| 60 | * @{ |
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| 61 | */ |
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| 62 | |||
| 63 | /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines |
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| 64 | * @brief Flags defines which can be used with LL_IWDG_ReadReg function |
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| 65 | * @{ |
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| 66 | */ |
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| 67 | #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ |
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| 68 | #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ |
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| 69 | /** |
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| 70 | * @} |
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| 71 | */ |
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| 72 | |||
| 73 | /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider |
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| 74 | * @{ |
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| 75 | */ |
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| 76 | #define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ |
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| 77 | #define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ |
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| 78 | #define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ |
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| 79 | #define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ |
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| 80 | #define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ |
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| 81 | #define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ |
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| 82 | #define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ |
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| 83 | /** |
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| 84 | * @} |
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| 85 | */ |
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| 86 | |||
| 87 | /** |
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| 88 | * @} |
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| 89 | */ |
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| 90 | |||
| 91 | /* Exported macro ------------------------------------------------------------*/ |
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| 92 | /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros |
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| 93 | * @{ |
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| 94 | */ |
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| 95 | |||
| 96 | /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros |
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| 97 | * @{ |
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| 98 | */ |
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| 99 | |||
| 100 | /** |
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| 101 | * @brief Write a value in IWDG register |
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| 102 | * @param __INSTANCE__ IWDG Instance |
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| 103 | * @param __REG__ Register to be written |
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| 104 | * @param __VALUE__ Value to be written in the register |
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| 105 | * @retval None |
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| 106 | */ |
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| 107 | #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
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| 108 | |||
| 109 | /** |
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| 110 | * @brief Read a value in IWDG register |
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| 111 | * @param __INSTANCE__ IWDG Instance |
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| 112 | * @param __REG__ Register to be read |
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| 113 | * @retval Register value |
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| 114 | */ |
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| 115 | #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
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| 116 | /** |
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| 117 | * @} |
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| 118 | */ |
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| 119 | |||
| 120 | /** |
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| 121 | * @} |
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| 122 | */ |
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| 123 | |||
| 124 | |||
| 125 | /* Exported functions --------------------------------------------------------*/ |
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| 126 | /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions |
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| 127 | * @{ |
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| 128 | */ |
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| 129 | /** @defgroup IWDG_LL_EF_Configuration Configuration |
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| 130 | * @{ |
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| 131 | */ |
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| 132 | |||
| 133 | /** |
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| 134 | * @brief Start the Independent Watchdog |
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| 135 | * @note Except if the hardware watchdog option is selected |
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| 136 | * @rmtoll KR KEY LL_IWDG_Enable |
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| 137 | * @param IWDGx IWDG Instance |
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| 138 | * @retval None |
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| 139 | */ |
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| 140 | __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) |
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| 141 | { |
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| 142 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); |
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| 143 | } |
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| 144 | |||
| 145 | /** |
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| 146 | * @brief Reloads IWDG counter with value defined in the reload register |
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| 147 | * @rmtoll KR KEY LL_IWDG_ReloadCounter |
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| 148 | * @param IWDGx IWDG Instance |
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| 149 | * @retval None |
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| 150 | */ |
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| 151 | __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) |
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| 152 | { |
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| 153 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); |
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| 154 | } |
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| 155 | |||
| 156 | /** |
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| 157 | * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
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| 158 | * @rmtoll KR KEY LL_IWDG_EnableWriteAccess |
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| 159 | * @param IWDGx IWDG Instance |
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| 160 | * @retval None |
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| 161 | */ |
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| 162 | __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) |
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| 163 | { |
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| 164 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); |
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| 165 | } |
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| 166 | |||
| 167 | /** |
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| 168 | * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
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| 169 | * @rmtoll KR KEY LL_IWDG_DisableWriteAccess |
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| 170 | * @param IWDGx IWDG Instance |
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| 171 | * @retval None |
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| 172 | */ |
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| 173 | __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) |
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| 174 | { |
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| 175 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); |
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| 176 | } |
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| 177 | |||
| 178 | /** |
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| 179 | * @brief Select the prescaler of the IWDG |
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| 180 | * @rmtoll PR PR LL_IWDG_SetPrescaler |
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| 181 | * @param IWDGx IWDG Instance |
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| 182 | * @param Prescaler This parameter can be one of the following values: |
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| 183 | * @arg @ref LL_IWDG_PRESCALER_4 |
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| 184 | * @arg @ref LL_IWDG_PRESCALER_8 |
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| 185 | * @arg @ref LL_IWDG_PRESCALER_16 |
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| 186 | * @arg @ref LL_IWDG_PRESCALER_32 |
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| 187 | * @arg @ref LL_IWDG_PRESCALER_64 |
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| 188 | * @arg @ref LL_IWDG_PRESCALER_128 |
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| 189 | * @arg @ref LL_IWDG_PRESCALER_256 |
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| 190 | * @retval None |
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| 191 | */ |
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| 192 | __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) |
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| 193 | { |
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| 194 | WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); |
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| 195 | } |
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| 196 | |||
| 197 | /** |
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| 198 | * @brief Get the selected prescaler of the IWDG |
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| 199 | * @rmtoll PR PR LL_IWDG_GetPrescaler |
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| 200 | * @param IWDGx IWDG Instance |
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| 201 | * @retval Returned value can be one of the following values: |
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| 202 | * @arg @ref LL_IWDG_PRESCALER_4 |
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| 203 | * @arg @ref LL_IWDG_PRESCALER_8 |
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| 204 | * @arg @ref LL_IWDG_PRESCALER_16 |
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| 205 | * @arg @ref LL_IWDG_PRESCALER_32 |
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| 206 | * @arg @ref LL_IWDG_PRESCALER_64 |
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| 207 | * @arg @ref LL_IWDG_PRESCALER_128 |
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| 208 | * @arg @ref LL_IWDG_PRESCALER_256 |
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| 209 | */ |
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| 210 | __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) |
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| 211 | { |
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| 212 | return (READ_REG(IWDGx->PR)); |
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| 213 | } |
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| 214 | |||
| 215 | /** |
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| 216 | * @brief Specify the IWDG down-counter reload value |
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| 217 | * @rmtoll RLR RL LL_IWDG_SetReloadCounter |
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| 218 | * @param IWDGx IWDG Instance |
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| 219 | * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF |
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| 220 | * @retval None |
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| 221 | */ |
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| 222 | __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) |
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| 223 | { |
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| 224 | WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); |
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| 225 | } |
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| 226 | |||
| 227 | /** |
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| 228 | * @brief Get the specified IWDG down-counter reload value |
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| 229 | * @rmtoll RLR RL LL_IWDG_GetReloadCounter |
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| 230 | * @param IWDGx IWDG Instance |
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| 231 | * @retval Value between Min_Data=0 and Max_Data=0x0FFF |
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| 232 | */ |
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| 233 | __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) |
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| 234 | { |
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| 235 | return (READ_REG(IWDGx->RLR)); |
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| 236 | } |
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| 237 | |||
| 238 | /** |
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| 239 | * @} |
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| 240 | */ |
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| 241 | |||
| 242 | /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management |
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| 243 | * @{ |
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| 244 | */ |
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| 245 | |||
| 246 | /** |
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| 247 | * @brief Check if flag Prescaler Value Update is set or not |
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| 248 | * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU |
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| 249 | * @param IWDGx IWDG Instance |
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| 250 | * @retval State of bit (1 or 0). |
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| 251 | */ |
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| 252 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) |
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| 253 | { |
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| 254 | return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); |
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| 255 | } |
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| 256 | |||
| 257 | /** |
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| 258 | * @brief Check if flag Reload Value Update is set or not |
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| 259 | * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU |
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| 260 | * @param IWDGx IWDG Instance |
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| 261 | * @retval State of bit (1 or 0). |
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| 262 | */ |
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| 263 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) |
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| 264 | { |
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| 265 | return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); |
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| 266 | } |
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| 267 | |||
| 268 | /** |
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| 269 | * @brief Check if flags Prescaler & Reload Value Update are reset or not |
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| 270 | * @rmtoll SR PVU LL_IWDG_IsReady\n |
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| 271 | * SR RVU LL_IWDG_IsReady |
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| 272 | * @param IWDGx IWDG Instance |
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| 273 | * @retval State of bits (1 or 0). |
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| 274 | */ |
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| 275 | __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) |
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| 276 | { |
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| 277 | return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL); |
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| 278 | } |
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| 279 | |||
| 280 | /** |
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| 281 | * @} |
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| 282 | */ |
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| 283 | |||
| 284 | /** |
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| 285 | * @} |
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| 286 | */ |
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| 287 | |||
| 288 | /** |
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| 289 | * @} |
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| 290 | */ |
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| 291 | |||
| 292 | #endif /* IWDG */ |
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| 293 | |||
| 294 | /** |
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| 295 | * @} |
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| 296 | */ |
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| 297 | |||
| 298 | #ifdef __cplusplus |
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| 299 | } |
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| 300 | #endif |
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| 301 | |||
| 302 | #endif /* STM32F1xx_LL_IWDG_H */ |