WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_i2c.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_i2c.h
		4	* @author MCD Application Team
		5	* @brief Header file of I2C LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
		10	*
		11	* Redistribution and use in source and binary forms, with or without modification,
		12	* are permitted provided that the following conditions are met:
		13	* 1. Redistributions of source code must retain the above copyright notice,
		14	* this list of conditions and the following disclaimer.
		15	* 2. Redistributions in binary form must reproduce the above copyright notice,
		16	* this list of conditions and the following disclaimer in the documentation
		17	* and/or other materials provided with the distribution.
		18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		19	* may be used to endorse or promote products derived from this software
		20	* without specific prior written permission.
		21	*
		22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		32	*
		33	******************************************************************************
		34	*/
		35
		36	/* Define to prevent recursive inclusion -------------------------------------*/
		37	#ifndef __STM32F1xx_LL_I2C_H
		38	#define __STM32F1xx_LL_I2C_H
		39
		40	#ifdef __cplusplus
		41	extern "C" {
		42	#endif
		43
		44	/* Includes ------------------------------------------------------------------*/
		45	#include "stm32f1xx.h"
		46
		47	/** @addtogroup STM32F1xx_LL_Driver
		48	* @{
		49	*/
		50
		51	#if defined (I2C1) \|\| defined (I2C2)
		52
		53	/** @defgroup I2C_LL I2C
		54	* @{
		55	*/
		56
		57	/* Private types -------------------------------------------------------------*/
		58	/* Private variables ---------------------------------------------------------*/
		59
		60	/* Private constants ---------------------------------------------------------*/
		61	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
		62	* @{
		63	*/
		64
		65	/* Defines used to perform compute and check in the macros */
		66	#define LL_I2C_MAX_SPEED_STANDARD 100000U
		67	#define LL_I2C_MAX_SPEED_FAST 400000U
		68	/**
		69	* @}
		70	*/
		71
		72	/* Private macros ------------------------------------------------------------*/
		73	#if defined(USE_FULL_LL_DRIVER)
		74	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
		75	* @{
		76	*/
		77	/**
		78	* @}
		79	*/
		80	#endif /USE_FULL_LL_DRIVER/
		81
		82	/* Exported types ------------------------------------------------------------*/
		83	#if defined(USE_FULL_LL_DRIVER)
		84	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
		85	* @{
		86	*/
		87	typedef struct
		88	{
		89	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
		90	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
		91
		92	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
		93
		94	uint32_t ClockSpeed; /*!< Specifies the clock frequency.
		95	This parameter must be set to a value lower than 400kHz (in Hz)
		96
		97	This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
		98	or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
		99
		100	uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
		101	This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
		102
		103	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
		104
		105	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
		106	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
		107
		108	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
		109
		110	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
		111	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
		112
		113	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
		114
		115	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
		116	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
		117
		118	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
		119	} LL_I2C_InitTypeDef;
		120	/**
		121	* @}
		122	*/
		123	#endif /USE_FULL_LL_DRIVER/
		124
		125	/* Exported constants --------------------------------------------------------*/
		126	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
		127	* @{
		128	*/
		129
		130	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
		131	* @brief Flags defines which can be used with LL_I2C_ReadReg function
		132	* @{
		133	*/
		134	#define LL_I2C_SR1_SB I2C_SR1_SB /!< Start Bit (master mode) /
		135	#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
		136	Address matched flag (slave mode) */
		137	#define LL_I2C_SR1_BTF I2C_SR1_BTF /!< Byte Transfer Finished flag /
		138	#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /!< 10-bit header sent (master mode) /
		139	#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /!< Stop detection flag (slave mode) /
		140	#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /!< Data register not empty (receivers) /
		141	#define LL_I2C_SR1_TXE I2C_SR1_TXE /!< Data register empty (transmitters) /
		142	#define LL_I2C_SR1_BERR I2C_SR1_BERR /!< Bus error /
		143	#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /!< Arbitration lost /
		144	#define LL_I2C_SR1_AF I2C_SR1_AF /!< Acknowledge failure flag /
		145	#define LL_I2C_SR1_OVR I2C_SR1_OVR /!< Overrun/Underrun /
		146	#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
		147	#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
		148	#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /!< SMBus alert (SMBus mode) /
		149	#define LL_I2C_SR2_MSL I2C_SR2_MSL /!< Master/Slave flag /
		150	#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /!< Bus busy flag /
		151	#define LL_I2C_SR2_TRA I2C_SR2_TRA /!< Transmitter/receiver direction /
		152	#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /!< General call address (Slave mode) /
		153	#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /!< SMBus Device default address (Slave mode) /
		154	#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /!< SMBus Host address (Slave mode) /
		155	#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /!< Dual flag (Slave mode) /
		156	/**
		157	* @}
		158	*/
		159
		160	/** @defgroup I2C_LL_EC_IT IT Defines
		161	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
		162	* @{
		163	*/
		164	#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /!< Events interrupts enable /
		165	#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /!< Buffer interrupts enable /
		166	#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /!< Error interrupts enable /
		167	/**
		168	* @}
		169	*/
		170
		171	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
		172	* @{
		173	*/
		174	#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /!< Own address 1 is a 7-bit address. /
		175	#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE \| 0x00004000U) /!< Own address 1 is a 10-bit address. /
		176	/**
		177	* @}
		178	*/
		179
		180	/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
		181	* @{
		182	*/
		183	#define LL_I2C_DUTYCYCLE_2 0x00000000U /!< I2C fast mode Tlow/Thigh = 2 /
		184	#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /!< I2C fast mode Tlow/Thigh = 16/9 /
		185	/**
		186	* @}
		187	*/
		188
		189	/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
		190	* @{
		191	*/
		192	#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /!< Master clock speed range is standard mode /
		193	#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /!< Master clock speed range is fast mode /
		194	/**
		195	* @}
		196	*/
		197
		198	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
		199	* @{
		200	*/
		201	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
		202	#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP) /!< SMBus Host address acknowledge /
		203	#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /!< SMBus Device default mode (Default address not acknowledge) /
		204	#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_ENARP) /!< SMBus Device Default address acknowledge /
		205	/**
		206	* @}
		207	*/
		208
		209	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
		210	* @{
		211	*/
		212	#define LL_I2C_ACK I2C_CR1_ACK /!< ACK is sent after current received byte. /
		213	#define LL_I2C_NACK 0x00000000U /!< NACK is sent after current received byte./
		214	/**
		215	* @}
		216	*/
		217
		218	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
		219	* @{
		220	*/
		221	#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /!< Bus is in write transfer /
		222	#define LL_I2C_DIRECTION_READ 0x00000000U /!< Bus is in read transfer /
		223	/**
		224	* @}
		225	*/
		226
		227	/**
		228	* @}
		229	*/
		230
		231	/* Exported macro ------------------------------------------------------------*/
		232	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
		233	* @{
		234	*/
		235
		236	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
		237	* @{
		238	*/
		239
		240	/**
		241	* @brief Write a value in I2C register
		242	* @param __INSTANCE__ I2C Instance
		243	* @param __REG__ Register to be written
		244	* @param __VALUE__ Value to be written in the register
		245	* @retval None
		246	*/
		247	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		248
		249	/**
		250	* @brief Read a value in I2C register
		251	* @param __INSTANCE__ I2C Instance
		252	* @param __REG__ Register to be read
		253	* @retval Register value
		254	*/
		255	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		256	/**
		257	* @}
		258	*/
		259
		260	/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
		261	* @{
		262	*/
		263
		264	/**
		265	* @brief Convert Peripheral Clock Frequency in Mhz.
		266	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
		267	* @retval Value of peripheral clock (in Mhz)
		268	*/
		269	#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
		270
		271	/**
		272	* @brief Convert Peripheral Clock Frequency in Hz.
		273	* @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
		274	* @retval Value of peripheral clock (in Hz)
		275	*/
		276	#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
		277
		278	/**
		279	* @brief Compute I2C Clock rising time.
		280	* @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
		281	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
		282	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
		283	*/
		284	#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
		285
		286	/**
		287	* @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
		288	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
		289	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
		290	* @param __DUTYCYCLE__ This parameter can be one of the following values:
		291	* @arg @ref LL_I2C_DUTYCYCLE_2
		292	* @arg @ref LL_I2C_DUTYCYCLE_16_9
		293	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
		294	*/
		295	#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
		296	(__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
		297	(__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
		298
		299	/**
		300	* @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
		301	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
		302	* @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
		303	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
		304	*/
		305	#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
		306
		307	/**
		308	* @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
		309	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
		310	* @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
		311	* @param __DUTYCYCLE__ This parameter can be one of the following values:
		312	* @arg @ref LL_I2C_DUTYCYCLE_2
		313	* @arg @ref LL_I2C_DUTYCYCLE_16_9
		314	* @retval Value between Min_Data=0x001 and Max_Data=0xFFF
		315	*/
		316	#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
		317	(((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
		318	(((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
		319
		320	/**
		321	* @brief Get the Least significant bits of a 10-Bits address.
		322	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
		323	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
		324	*/
		325	#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
		326
		327	/**
		328	* @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
		329	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
		330	* @retval Value between Min_Data=0xF0 and Max_Data=0xF6
		331	*/
		332	#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF0))))
		333
		334	/**
		335	* @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
		336	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
		337	* @retval Value between Min_Data=0xF1 and Max_Data=0xF7
		338	*/
		339	#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF1))))
		340
		341	/**
		342	* @}
		343	*/
		344
		345	/**
		346	* @}
		347	*/
		348
		349	/* Exported functions --------------------------------------------------------*/
		350
		351	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
		352	* @{
		353	*/
		354
		355	/** @defgroup I2C_LL_EF_Configuration Configuration
		356	* @{
		357	*/
		358
		359	/**
		360	* @brief Enable I2C peripheral (PE = 1).
		361	* @rmtoll CR1 PE LL_I2C_Enable
		362	* @param I2Cx I2C Instance.
		363	* @retval None
		364	*/
		365	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
		366	{
		367	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
		368	}
		369
		370	/**
		371	* @brief Disable I2C peripheral (PE = 0).
		372	* @rmtoll CR1 PE LL_I2C_Disable
		373	* @param I2Cx I2C Instance.
		374	* @retval None
		375	*/
		376	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
		377	{
		378	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
		379	}
		380
		381	/**
		382	* @brief Check if the I2C peripheral is enabled or disabled.
		383	* @rmtoll CR1 PE LL_I2C_IsEnabled
		384	* @param I2Cx I2C Instance.
		385	* @retval State of bit (1 or 0).
		386	*/
		387	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
		388	{
		389	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
		390	}
		391
		392
		393	/**
		394	* @brief Enable DMA transmission requests.
		395	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
		396	* @param I2Cx I2C Instance.
		397	* @retval None
		398	*/
		399	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
		400	{
		401	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
		402	}
		403
		404	/**
		405	* @brief Disable DMA transmission requests.
		406	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
		407	* @param I2Cx I2C Instance.
		408	* @retval None
		409	*/
		410	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
		411	{
		412	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
		413	}
		414
		415	/**
		416	* @brief Check if DMA transmission requests are enabled or disabled.
		417	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
		418	* @param I2Cx I2C Instance.
		419	* @retval State of bit (1 or 0).
		420	*/
		421	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
		422	{
		423	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
		424	}
		425
		426	/**
		427	* @brief Enable DMA reception requests.
		428	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
		429	* @param I2Cx I2C Instance.
		430	* @retval None
		431	*/
		432	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
		433	{
		434	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
		435	}
		436
		437	/**
		438	* @brief Disable DMA reception requests.
		439	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
		440	* @param I2Cx I2C Instance.
		441	* @retval None
		442	*/
		443	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
		444	{
		445	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
		446	}
		447
		448	/**
		449	* @brief Check if DMA reception requests are enabled or disabled.
		450	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
		451	* @param I2Cx I2C Instance.
		452	* @retval State of bit (1 or 0).
		453	*/
		454	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
		455	{
		456	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
		457	}
		458
		459	/**
		460	* @brief Get the data register address used for DMA transfer.
		461	* @rmtoll DR DR LL_I2C_DMA_GetRegAddr
		462	* @param I2Cx I2C Instance.
		463	* @retval Address of data register
		464	*/
		465	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
		466	{
		467	return (uint32_t) & (I2Cx->DR);
		468	}
		469
		470	/**
		471	* @brief Enable Clock stretching.
		472	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
		473	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
		474	* @param I2Cx I2C Instance.
		475	* @retval None
		476	*/
		477	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
		478	{
		479	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
		480	}
		481
		482	/**
		483	* @brief Disable Clock stretching.
		484	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
		485	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
		486	* @param I2Cx I2C Instance.
		487	* @retval None
		488	*/
		489	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
		490	{
		491	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
		492	}
		493
		494	/**
		495	* @brief Check if Clock stretching is enabled or disabled.
		496	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
		497	* @param I2Cx I2C Instance.
		498	* @retval State of bit (1 or 0).
		499	*/
		500	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
		501	{
		502	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
		503	}
		504
		505	/**
		506	* @brief Enable General Call.
		507	* @note When enabled the Address 0x00 is ACKed.
		508	* @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
		509	* @param I2Cx I2C Instance.
		510	* @retval None
		511	*/
		512	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
		513	{
		514	SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
		515	}
		516
		517	/**
		518	* @brief Disable General Call.
		519	* @note When disabled the Address 0x00 is NACKed.
		520	* @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
		521	* @param I2Cx I2C Instance.
		522	* @retval None
		523	*/
		524	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
		525	{
		526	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
		527	}
		528
		529	/**
		530	* @brief Check if General Call is enabled or disabled.
		531	* @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
		532	* @param I2Cx I2C Instance.
		533	* @retval State of bit (1 or 0).
		534	*/
		535	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
		536	{
		537	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
		538	}
		539
		540	/**
		541	* @brief Set the Own Address1.
		542	* @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
		543	* OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
		544	* OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
		545	* OAR1 ADDMODE LL_I2C_SetOwnAddress1
		546	* @param I2Cx I2C Instance.
		547	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
		548	* @param OwnAddrSize This parameter can be one of the following values:
		549	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
		550	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
		551	* @retval None
		552	*/
		553	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
		554	{
		555	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 \| I2C_OAR1_ADD1_7 \| I2C_OAR1_ADD8_9 \| I2C_OAR1_ADDMODE, OwnAddress1 \| OwnAddrSize);
		556	}
		557
		558	/**
		559	* @brief Set the 7bits Own Address2.
		560	* @note This action has no effect if own address2 is enabled.
		561	* @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
		562	* @param I2Cx I2C Instance.
		563	* @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
		564	* @retval None
		565	*/
		566	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
		567	{
		568	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
		569	}
		570
		571	/**
		572	* @brief Enable acknowledge on Own Address2 match address.
		573	* @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
		574	* @param I2Cx I2C Instance.
		575	* @retval None
		576	*/
		577	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
		578	{
		579	SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
		580	}
		581
		582	/**
		583	* @brief Disable acknowledge on Own Address2 match address.
		584	* @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
		585	* @param I2Cx I2C Instance.
		586	* @retval None
		587	*/
		588	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
		589	{
		590	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
		591	}
		592
		593	/**
		594	* @brief Check if Own Address1 acknowledge is enabled or disabled.
		595	* @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
		596	* @param I2Cx I2C Instance.
		597	* @retval State of bit (1 or 0).
		598	*/
		599	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
		600	{
		601	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
		602	}
		603
		604	/**
		605	* @brief Configure the Peripheral clock frequency.
		606	* @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
		607	* @param I2Cx I2C Instance.
		608	* @param PeriphClock Peripheral Clock (in Hz)
		609	* @retval None
		610	*/
		611	__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
		612	{
		613	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
		614	}
		615
		616	/**
		617	* @brief Get the Peripheral clock frequency.
		618	* @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
		619	* @param I2Cx I2C Instance.
		620	* @retval Value of Peripheral Clock (in Hz)
		621	*/
		622	__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
		623	{
		624	return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
		625	}
		626
		627	/**
		628	* @brief Configure the Duty cycle (Fast mode only).
		629	* @rmtoll CCR DUTY LL_I2C_SetDutyCycle
		630	* @param I2Cx I2C Instance.
		631	* @param DutyCycle This parameter can be one of the following values:
		632	* @arg @ref LL_I2C_DUTYCYCLE_2
		633	* @arg @ref LL_I2C_DUTYCYCLE_16_9
		634	* @retval None
		635	*/
		636	__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
		637	{
		638	MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
		639	}
		640
		641	/**
		642	* @brief Get the Duty cycle (Fast mode only).
		643	* @rmtoll CCR DUTY LL_I2C_GetDutyCycle
		644	* @param I2Cx I2C Instance.
		645	* @retval Returned value can be one of the following values:
		646	* @arg @ref LL_I2C_DUTYCYCLE_2
		647	* @arg @ref LL_I2C_DUTYCYCLE_16_9
		648	*/
		649	__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
		650	{
		651	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
		652	}
		653
		654	/**
		655	* @brief Configure the I2C master clock speed mode.
		656	* @rmtoll CCR FS LL_I2C_SetClockSpeedMode
		657	* @param I2Cx I2C Instance.
		658	* @param ClockSpeedMode This parameter can be one of the following values:
		659	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
		660	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
		661	* @retval None
		662	*/
		663	__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
		664	{
		665	MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
		666	}
		667
		668	/**
		669	* @brief Get the the I2C master speed mode.
		670	* @rmtoll CCR FS LL_I2C_GetClockSpeedMode
		671	* @param I2Cx I2C Instance.
		672	* @retval Returned value can be one of the following values:
		673	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
		674	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
		675	*/
		676	__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
		677	{
		678	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
		679	}
		680
		681	/**
		682	* @brief Configure the SCL, SDA rising time.
		683	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
		684	* @rmtoll TRISE TRISE LL_I2C_SetRiseTime
		685	* @param I2Cx I2C Instance.
		686	* @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
		687	* @retval None
		688	*/
		689	__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
		690	{
		691	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
		692	}
		693
		694	/**
		695	* @brief Get the SCL, SDA rising time.
		696	* @rmtoll TRISE TRISE LL_I2C_GetRiseTime
		697	* @param I2Cx I2C Instance.
		698	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
		699	*/
		700	__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
		701	{
		702	return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
		703	}
		704
		705	/**
		706	* @brief Configure the SCL high and low period.
		707	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
		708	* @rmtoll CCR CCR LL_I2C_SetClockPeriod
		709	* @param I2Cx I2C Instance.
		710	* @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
		711	* @retval None
		712	*/
		713	__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
		714	{
		715	MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
		716	}
		717
		718	/**
		719	* @brief Get the SCL high and low period.
		720	* @rmtoll CCR CCR LL_I2C_GetClockPeriod
		721	* @param I2Cx I2C Instance.
		722	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
		723	*/
		724	__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
		725	{
		726	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
		727	}
		728
		729	/**
		730	* @brief Configure the SCL speed.
		731	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
		732	* @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
		733	* TRISE TRISE LL_I2C_ConfigSpeed\n
		734	* CCR FS LL_I2C_ConfigSpeed\n
		735	* CCR DUTY LL_I2C_ConfigSpeed\n
		736	* CCR CCR LL_I2C_ConfigSpeed
		737	* @param I2Cx I2C Instance.
		738	* @param PeriphClock Peripheral Clock (in Hz)
		739	* @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
		740	* @param DutyCycle This parameter can be one of the following values:
		741	* @arg @ref LL_I2C_DUTYCYCLE_2
		742	* @arg @ref LL_I2C_DUTYCYCLE_16_9
		743	* @retval None
		744	*/
		745	__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
		746	uint32_t DutyCycle)
		747	{
		748	register uint32_t freqrange = 0x0U;
		749	register uint32_t clockconfig = 0x0U;
		750
		751	/* Compute frequency range */
		752	freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
		753
		754	/* Configure I2Cx: Frequency range register */
		755	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
		756
		757	/* Configure I2Cx: Rise Time register */
		758	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
		759
		760	/* Configure Speed mode, Duty Cycle and Clock control register value */
		761	if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
		762	{
		763	/* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
		764	clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE \| \
		765	__LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) \| \
		766	DutyCycle;
		767	}
		768	else
		769	{
		770	/* Set Speed mode at standard for Clock Speed request in standard clock range */
		771	clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE \| \
		772	__LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
		773	}
		774
		775	/* Configure I2Cx: Clock control register */
		776	MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS \| I2C_CCR_DUTY \| I2C_CCR_CCR), clockconfig);
		777	}
		778
		779	/**
		780	* @brief Configure peripheral mode.
		781	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		782	* SMBus feature is supported by the I2Cx Instance.
		783	* @rmtoll CR1 SMBUS LL_I2C_SetMode\n
		784	* CR1 SMBTYPE LL_I2C_SetMode\n
		785	* CR1 ENARP LL_I2C_SetMode
		786	* @param I2Cx I2C Instance.
		787	* @param PeripheralMode This parameter can be one of the following values:
		788	* @arg @ref LL_I2C_MODE_I2C
		789	* @arg @ref LL_I2C_MODE_SMBUS_HOST
		790	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
		791	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
		792	* @retval None
		793	*/
		794	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
		795	{
		796	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP, PeripheralMode);
		797	}
		798
		799	/**
		800	* @brief Get peripheral mode.
		801	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		802	* SMBus feature is supported by the I2Cx Instance.
		803	* @rmtoll CR1 SMBUS LL_I2C_GetMode\n
		804	* CR1 SMBTYPE LL_I2C_GetMode\n
		805	* CR1 ENARP LL_I2C_GetMode
		806	* @param I2Cx I2C Instance.
		807	* @retval Returned value can be one of the following values:
		808	* @arg @ref LL_I2C_MODE_I2C
		809	* @arg @ref LL_I2C_MODE_SMBUS_HOST
		810	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
		811	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
		812	*/
		813	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
		814	{
		815	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP));
		816	}
		817
		818	/**
		819	* @brief Enable SMBus alert (Host or Device mode)
		820	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		821	* SMBus feature is supported by the I2Cx Instance.
		822	* @note SMBus Device mode:
		823	* - SMBus Alert pin is drived low and
		824	* Alert Response Address Header acknowledge is enabled.
		825	* SMBus Host mode:
		826	* - SMBus Alert pin management is supported.
		827	* @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
		828	* @param I2Cx I2C Instance.
		829	* @retval None
		830	*/
		831	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
		832	{
		833	SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
		834	}
		835
		836	/**
		837	* @brief Disable SMBus alert (Host or Device mode)
		838	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		839	* SMBus feature is supported by the I2Cx Instance.
		840	* @note SMBus Device mode:
		841	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
		842	* Alert Response Address Header acknowledge is disabled.
		843	* SMBus Host mode:
		844	* - SMBus Alert pin management is not supported.
		845	* @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
		846	* @param I2Cx I2C Instance.
		847	* @retval None
		848	*/
		849	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
		850	{
		851	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
		852	}
		853
		854	/**
		855	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
		856	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		857	* SMBus feature is supported by the I2Cx Instance.
		858	* @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
		859	* @param I2Cx I2C Instance.
		860	* @retval State of bit (1 or 0).
		861	*/
		862	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
		863	{
		864	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
		865	}
		866
		867	/**
		868	* @brief Enable SMBus Packet Error Calculation (PEC).
		869	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		870	* SMBus feature is supported by the I2Cx Instance.
		871	* @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
		872	* @param I2Cx I2C Instance.
		873	* @retval None
		874	*/
		875	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
		876	{
		877	SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
		878	}
		879
		880	/**
		881	* @brief Disable SMBus Packet Error Calculation (PEC).
		882	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		883	* SMBus feature is supported by the I2Cx Instance.
		884	* @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
		885	* @param I2Cx I2C Instance.
		886	* @retval None
		887	*/
		888	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
		889	{
		890	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
		891	}
		892
		893	/**
		894	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
		895	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		896	* SMBus feature is supported by the I2Cx Instance.
		897	* @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
		898	* @param I2Cx I2C Instance.
		899	* @retval State of bit (1 or 0).
		900	*/
		901	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
		902	{
		903	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
		904	}
		905
		906	/**
		907	* @}
		908	*/
		909
		910	/** @defgroup I2C_LL_EF_IT_Management IT_Management
		911	* @{
		912	*/
		913
		914	/**
		915	* @brief Enable TXE interrupt.
		916	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
		917	* CR2 ITBUFEN LL_I2C_EnableIT_TX
		918	* @param I2Cx I2C Instance.
		919	* @retval None
		920	*/
		921	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
		922	{
		923	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
		924	}
		925
		926	/**
		927	* @brief Disable TXE interrupt.
		928	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
		929	* CR2 ITBUFEN LL_I2C_DisableIT_TX
		930	* @param I2Cx I2C Instance.
		931	* @retval None
		932	*/
		933	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
		934	{
		935	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
		936	}
		937
		938	/**
		939	* @brief Check if the TXE Interrupt is enabled or disabled.
		940	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
		941	* CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
		942	* @param I2Cx I2C Instance.
		943	* @retval State of bit (1 or 0).
		944	*/
		945	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
		946	{
		947	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
		948	}
		949
		950	/**
		951	* @brief Enable RXNE interrupt.
		952	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
		953	* CR2 ITBUFEN LL_I2C_EnableIT_RX
		954	* @param I2Cx I2C Instance.
		955	* @retval None
		956	*/
		957	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
		958	{
		959	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
		960	}
		961
		962	/**
		963	* @brief Disable RXNE interrupt.
		964	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
		965	* CR2 ITBUFEN LL_I2C_DisableIT_RX
		966	* @param I2Cx I2C Instance.
		967	* @retval None
		968	*/
		969	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
		970	{
		971	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
		972	}
		973
		974	/**
		975	* @brief Check if the RXNE Interrupt is enabled or disabled.
		976	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
		977	* CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
		978	* @param I2Cx I2C Instance.
		979	* @retval State of bit (1 or 0).
		980	*/
		981	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
		982	{
		983	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
		984	}
		985
		986	/**
		987	* @brief Enable Events interrupts.
		988	* @note Any of these events will generate interrupt :
		989	* Start Bit (SB)
		990	* Address sent, Address matched (ADDR)
		991	* 10-bit header sent (ADD10)
		992	* Stop detection (STOPF)
		993	* Byte transfer finished (BTF)
		994	*
		995	* @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
		996	* Receive buffer not empty (RXNE)
		997	* Transmit buffer empty (TXE)
		998	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
		999	* @param I2Cx I2C Instance.
		1000	* @retval None
		1001	*/
		1002	__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
		1003	{
		1004	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
		1005	}
		1006
		1007	/**
		1008	* @brief Disable Events interrupts.
		1009	* @note Any of these events will generate interrupt :
		1010	* Start Bit (SB)
		1011	* Address sent, Address matched (ADDR)
		1012	* 10-bit header sent (ADD10)
		1013	* Stop detection (STOPF)
		1014	* Byte transfer finished (BTF)
		1015	* Receive buffer not empty (RXNE)
		1016	* Transmit buffer empty (TXE)
		1017	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
		1018	* @param I2Cx I2C Instance.
		1019	* @retval None
		1020	*/
		1021	__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
		1022	{
		1023	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
		1024	}
		1025
		1026	/**
		1027	* @brief Check if Events interrupts are enabled or disabled.
		1028	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
		1029	* @param I2Cx I2C Instance.
		1030	* @retval State of bit (1 or 0).
		1031	*/
		1032	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
		1033	{
		1034	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
		1035	}
		1036
		1037	/**
		1038	* @brief Enable Buffer interrupts.
		1039	* @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
		1040	* Receive buffer not empty (RXNE)
		1041	* Transmit buffer empty (TXE)
		1042	* @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
		1043	* @param I2Cx I2C Instance.
		1044	* @retval None
		1045	*/
		1046	__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
		1047	{
		1048	SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
		1049	}
		1050
		1051	/**
		1052	* @brief Disable Buffer interrupts.
		1053	* @note Any of these Buffer events will generate interrupt :
		1054	* Receive buffer not empty (RXNE)
		1055	* Transmit buffer empty (TXE)
		1056	* @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
		1057	* @param I2Cx I2C Instance.
		1058	* @retval None
		1059	*/
		1060	__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
		1061	{
		1062	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
		1063	}
		1064
		1065	/**
		1066	* @brief Check if Buffer interrupts are enabled or disabled.
		1067	* @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
		1068	* @param I2Cx I2C Instance.
		1069	* @retval State of bit (1 or 0).
		1070	*/
		1071	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
		1072	{
		1073	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
		1074	}
		1075
		1076	/**
		1077	* @brief Enable Error interrupts.
		1078	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1079	* SMBus feature is supported by the I2Cx Instance.
		1080	* @note Any of these errors will generate interrupt :
		1081	* Bus Error detection (BERR)
		1082	* Arbitration Loss (ARLO)
		1083	* Acknowledge Failure(AF)
		1084	* Overrun/Underrun (OVR)
		1085	* SMBus Timeout detection (TIMEOUT)
		1086	* SMBus PEC error detection (PECERR)
		1087	* SMBus Alert pin event detection (SMBALERT)
		1088	* @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
		1089	* @param I2Cx I2C Instance.
		1090	* @retval None
		1091	*/
		1092	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
		1093	{
		1094	SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
		1095	}
		1096
		1097	/**
		1098	* @brief Disable Error interrupts.
		1099	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1100	* SMBus feature is supported by the I2Cx Instance.
		1101	* @note Any of these errors will generate interrupt :
		1102	* Bus Error detection (BERR)
		1103	* Arbitration Loss (ARLO)
		1104	* Acknowledge Failure(AF)
		1105	* Overrun/Underrun (OVR)
		1106	* SMBus Timeout detection (TIMEOUT)
		1107	* SMBus PEC error detection (PECERR)
		1108	* SMBus Alert pin event detection (SMBALERT)
		1109	* @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
		1110	* @param I2Cx I2C Instance.
		1111	* @retval None
		1112	*/
		1113	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
		1114	{
		1115	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
		1116	}
		1117
		1118	/**
		1119	* @brief Check if Error interrupts are enabled or disabled.
		1120	* @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
		1121	* @param I2Cx I2C Instance.
		1122	* @retval State of bit (1 or 0).
		1123	*/
		1124	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
		1125	{
		1126	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
		1127	}
		1128
		1129	/**
		1130	* @}
		1131	*/
		1132
		1133	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
		1134	* @{
		1135	*/
		1136
		1137	/**
		1138	* @brief Indicate the status of Transmit data register empty flag.
		1139	* @note RESET: When next data is written in Transmit data register.
		1140	* SET: When Transmit data register is empty.
		1141	* @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
		1142	* @param I2Cx I2C Instance.
		1143	* @retval State of bit (1 or 0).
		1144	*/
		1145	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
		1146	{
		1147	return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
		1148	}
		1149
		1150	/**
		1151	* @brief Indicate the status of Byte Transfer Finished flag.
		1152	* RESET: When Data byte transfer not done.
		1153	* SET: When Data byte transfer succeeded.
		1154	* @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
		1155	* @param I2Cx I2C Instance.
		1156	* @retval State of bit (1 or 0).
		1157	*/
		1158	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
		1159	{
		1160	return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
		1161	}
		1162
		1163	/**
		1164	* @brief Indicate the status of Receive data register not empty flag.
		1165	* @note RESET: When Receive data register is read.
		1166	* SET: When the received data is copied in Receive data register.
		1167	* @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
		1168	* @param I2Cx I2C Instance.
		1169	* @retval State of bit (1 or 0).
		1170	*/
		1171	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
		1172	{
		1173	return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
		1174	}
		1175
		1176	/**
		1177	* @brief Indicate the status of Start Bit (master mode).
		1178	* @note RESET: When No Start condition.
		1179	* SET: When Start condition is generated.
		1180	* @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
		1181	* @param I2Cx I2C Instance.
		1182	* @retval State of bit (1 or 0).
		1183	*/
		1184	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
		1185	{
		1186	return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
		1187	}
		1188
		1189	/**
		1190	* @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
		1191	* @note RESET: Clear default value.
		1192	* SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
		1193	* @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
		1194	* @param I2Cx I2C Instance.
		1195	* @retval State of bit (1 or 0).
		1196	*/
		1197	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
		1198	{
		1199	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
		1200	}
		1201
		1202	/**
		1203	* @brief Indicate the status of 10-bit header sent (master mode).
		1204	* @note RESET: When no ADD10 event occured.
		1205	* SET: When the master has sent the first address byte (header).
		1206	* @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
		1207	* @param I2Cx I2C Instance.
		1208	* @retval State of bit (1 or 0).
		1209	*/
		1210	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
		1211	{
		1212	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
		1213	}
		1214
		1215	/**
		1216	* @brief Indicate the status of Acknowledge failure flag.
		1217	* @note RESET: No acknowledge failure.
		1218	* SET: When an acknowledge failure is received after a byte transmission.
		1219	* @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
		1220	* @param I2Cx I2C Instance.
		1221	* @retval State of bit (1 or 0).
		1222	*/
		1223	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
		1224	{
		1225	return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
		1226	}
		1227
		1228	/**
		1229	* @brief Indicate the status of Stop detection flag (slave mode).
		1230	* @note RESET: Clear default value.
		1231	* SET: When a Stop condition is detected.
		1232	* @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
		1233	* @param I2Cx I2C Instance.
		1234	* @retval State of bit (1 or 0).
		1235	*/
		1236	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
		1237	{
		1238	return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
		1239	}
		1240
		1241	/**
		1242	* @brief Indicate the status of Bus error flag.
		1243	* @note RESET: Clear default value.
		1244	* SET: When a misplaced Start or Stop condition is detected.
		1245	* @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
		1246	* @param I2Cx I2C Instance.
		1247	* @retval State of bit (1 or 0).
		1248	*/
		1249	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
		1250	{
		1251	return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
		1252	}
		1253
		1254	/**
		1255	* @brief Indicate the status of Arbitration lost flag.
		1256	* @note RESET: Clear default value.
		1257	* SET: When arbitration lost.
		1258	* @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
		1259	* @param I2Cx I2C Instance.
		1260	* @retval State of bit (1 or 0).
		1261	*/
		1262	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
		1263	{
		1264	return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
		1265	}
		1266
		1267	/**
		1268	* @brief Indicate the status of Overrun/Underrun flag.
		1269	* @note RESET: Clear default value.
		1270	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
		1271	* @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
		1272	* @param I2Cx I2C Instance.
		1273	* @retval State of bit (1 or 0).
		1274	*/
		1275	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
		1276	{
		1277	return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
		1278	}
		1279
		1280	/**
		1281	* @brief Indicate the status of SMBus PEC error flag in reception.
		1282	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1283	* SMBus feature is supported by the I2Cx Instance.
		1284	* @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
		1285	* @param I2Cx I2C Instance.
		1286	* @retval State of bit (1 or 0).
		1287	*/
		1288	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
		1289	{
		1290	return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
		1291	}
		1292
		1293	/**
		1294	* @brief Indicate the status of SMBus Timeout detection flag.
		1295	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1296	* SMBus feature is supported by the I2Cx Instance.
		1297	* @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
		1298	* @param I2Cx I2C Instance.
		1299	* @retval State of bit (1 or 0).
		1300	*/
		1301	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
		1302	{
		1303	return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
		1304	}
		1305
		1306	/**
		1307	* @brief Indicate the status of SMBus alert flag.
		1308	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1309	* SMBus feature is supported by the I2Cx Instance.
		1310	* @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
		1311	* @param I2Cx I2C Instance.
		1312	* @retval State of bit (1 or 0).
		1313	*/
		1314	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
		1315	{
		1316	return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
		1317	}
		1318
		1319	/**
		1320	* @brief Indicate the status of Bus Busy flag.
		1321	* @note RESET: Clear default value.
		1322	* SET: When a Start condition is detected.
		1323	* @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
		1324	* @param I2Cx I2C Instance.
		1325	* @retval State of bit (1 or 0).
		1326	*/
		1327	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
		1328	{
		1329	return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
		1330	}
		1331
		1332	/**
		1333	* @brief Indicate the status of Dual flag.
		1334	* @note RESET: Received address matched with OAR1.
		1335	* SET: Received address matched with OAR2.
		1336	* @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
		1337	* @param I2Cx I2C Instance.
		1338	* @retval State of bit (1 or 0).
		1339	*/
		1340	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
		1341	{
		1342	return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
		1343	}
		1344
		1345	/**
		1346	* @brief Indicate the status of SMBus Host address reception (Slave mode).
		1347	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1348	* SMBus feature is supported by the I2Cx Instance.
		1349	* @note RESET: No SMBus Host address
		1350	* SET: SMBus Host address received.
		1351	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
		1352	* @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
		1353	* @param I2Cx I2C Instance.
		1354	* @retval State of bit (1 or 0).
		1355	*/
		1356	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
		1357	{
		1358	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
		1359	}
		1360
		1361	/**
		1362	* @brief Indicate the status of SMBus Device default address reception (Slave mode).
		1363	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1364	* SMBus feature is supported by the I2Cx Instance.
		1365	* @note RESET: No SMBus Device default address
		1366	* SET: SMBus Device default address received.
		1367	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
		1368	* @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
		1369	* @param I2Cx I2C Instance.
		1370	* @retval State of bit (1 or 0).
		1371	*/
		1372	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
		1373	{
		1374	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
		1375	}
		1376
		1377	/**
		1378	* @brief Indicate the status of General call address reception (Slave mode).
		1379	* @note RESET: No Generall call address
		1380	* SET: General call address received.
		1381	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
		1382	* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
		1383	* @param I2Cx I2C Instance.
		1384	* @retval State of bit (1 or 0).
		1385	*/
		1386	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
		1387	{
		1388	return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
		1389	}
		1390
		1391	/**
		1392	* @brief Indicate the status of Master/Slave flag.
		1393	* @note RESET: Slave Mode.
		1394	* SET: Master Mode.
		1395	* @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
		1396	* @param I2Cx I2C Instance.
		1397	* @retval State of bit (1 or 0).
		1398	*/
		1399	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
		1400	{
		1401	return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
		1402	}
		1403
		1404	/**
		1405	* @brief Clear Address Matched flag.
		1406	* @note Clearing this flag is done by a read access to the I2Cx_SR1
		1407	* register followed by a read access to the I2Cx_SR2 register.
		1408	* @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
		1409	* @param I2Cx I2C Instance.
		1410	* @retval None
		1411	*/
		1412	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
		1413	{
		1414	__IO uint32_t tmpreg;
		1415	tmpreg = I2Cx->SR1;
		1416	(void) tmpreg;
		1417	tmpreg = I2Cx->SR2;
		1418	(void) tmpreg;
		1419	}
		1420
		1421	/**
		1422	* @brief Clear Acknowledge failure flag.
		1423	* @rmtoll SR1 AF LL_I2C_ClearFlag_AF
		1424	* @param I2Cx I2C Instance.
		1425	* @retval None
		1426	*/
		1427	__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
		1428	{
		1429	CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
		1430	}
		1431
		1432	/**
		1433	* @brief Clear Stop detection flag.
		1434	* @note Clearing this flag is done by a read access to the I2Cx_SR1
		1435	* register followed by a write access to I2Cx_CR1 register.
		1436	* @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
		1437	* CR1 PE LL_I2C_ClearFlag_STOP
		1438	* @param I2Cx I2C Instance.
		1439	* @retval None
		1440	*/
		1441	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
		1442	{
		1443	__IO uint32_t tmpreg;
		1444	tmpreg = I2Cx->SR1;
		1445	(void) tmpreg;
		1446	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
		1447	}
		1448
		1449	/**
		1450	* @brief Clear Bus error flag.
		1451	* @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
		1452	* @param I2Cx I2C Instance.
		1453	* @retval None
		1454	*/
		1455	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
		1456	{
		1457	CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
		1458	}
		1459
		1460	/**
		1461	* @brief Clear Arbitration lost flag.
		1462	* @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
		1463	* @param I2Cx I2C Instance.
		1464	* @retval None
		1465	*/
		1466	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
		1467	{
		1468	CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
		1469	}
		1470
		1471	/**
		1472	* @brief Clear Overrun/Underrun flag.
		1473	* @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
		1474	* @param I2Cx I2C Instance.
		1475	* @retval None
		1476	*/
		1477	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
		1478	{
		1479	CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
		1480	}
		1481
		1482	/**
		1483	* @brief Clear SMBus PEC error flag.
		1484	* @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
		1485	* @param I2Cx I2C Instance.
		1486	* @retval None
		1487	*/
		1488	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
		1489	{
		1490	CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
		1491	}
		1492
		1493	/**
		1494	* @brief Clear SMBus Timeout detection flag.
		1495	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1496	* SMBus feature is supported by the I2Cx Instance.
		1497	* @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
		1498	* @param I2Cx I2C Instance.
		1499	* @retval None
		1500	*/
		1501	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
		1502	{
		1503	CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
		1504	}
		1505
		1506	/**
		1507	* @brief Clear SMBus Alert flag.
		1508	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1509	* SMBus feature is supported by the I2Cx Instance.
		1510	* @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
		1511	* @param I2Cx I2C Instance.
		1512	* @retval None
		1513	*/
		1514	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
		1515	{
		1516	CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
		1517	}
		1518
		1519	/**
		1520	* @}
		1521	*/
		1522
		1523	/** @defgroup I2C_LL_EF_Data_Management Data_Management
		1524	* @{
		1525	*/
		1526
		1527	/**
		1528	* @brief Enable Reset of I2C peripheral.
		1529	* @rmtoll CR1 SWRST LL_I2C_EnableReset
		1530	* @param I2Cx I2C Instance.
		1531	* @retval None
		1532	*/
		1533	__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
		1534	{
		1535	SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
		1536	}
		1537
		1538	/**
		1539	* @brief Disable Reset of I2C peripheral.
		1540	* @rmtoll CR1 SWRST LL_I2C_DisableReset
		1541	* @param I2Cx I2C Instance.
		1542	* @retval None
		1543	*/
		1544	__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
		1545	{
		1546	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
		1547	}
		1548
		1549	/**
		1550	* @brief Check if the I2C peripheral is under reset state or not.
		1551	* @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
		1552	* @param I2Cx I2C Instance.
		1553	* @retval State of bit (1 or 0).
		1554	*/
		1555	__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
		1556	{
		1557	return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
		1558	}
		1559
		1560	/**
		1561	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
		1562	* @note Usage in Slave or Master mode.
		1563	* @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
		1564	* @param I2Cx I2C Instance.
		1565	* @param TypeAcknowledge This parameter can be one of the following values:
		1566	* @arg @ref LL_I2C_ACK
		1567	* @arg @ref LL_I2C_NACK
		1568	* @retval None
		1569	*/
		1570	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
		1571	{
		1572	MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
		1573	}
		1574
		1575	/**
		1576	* @brief Generate a START or RESTART condition
		1577	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
		1578	* This action has no effect when RELOAD is set.
		1579	* @rmtoll CR1 START LL_I2C_GenerateStartCondition
		1580	* @param I2Cx I2C Instance.
		1581	* @retval None
		1582	*/
		1583	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
		1584	{
		1585	SET_BIT(I2Cx->CR1, I2C_CR1_START);
		1586	}
		1587
		1588	/**
		1589	* @brief Generate a STOP condition after the current byte transfer (master mode).
		1590	* @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
		1591	* @param I2Cx I2C Instance.
		1592	* @retval None
		1593	*/
		1594	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
		1595	{
		1596	SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
		1597	}
		1598
		1599	/**
		1600	* @brief Enable bit POS (master/host mode).
		1601	* @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
		1602	* @rmtoll CR1 POS LL_I2C_EnableBitPOS
		1603	* @param I2Cx I2C Instance.
		1604	* @retval None
		1605	*/
		1606	__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
		1607	{
		1608	SET_BIT(I2Cx->CR1, I2C_CR1_POS);
		1609	}
		1610
		1611	/**
		1612	* @brief Disable bit POS (master/host mode).
		1613	* @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
		1614	* @rmtoll CR1 POS LL_I2C_DisableBitPOS
		1615	* @param I2Cx I2C Instance.
		1616	* @retval None
		1617	*/
		1618	__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
		1619	{
		1620	CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
		1621	}
		1622
		1623	/**
		1624	* @brief Check if bit POS is enabled or disabled.
		1625	* @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
		1626	* @param I2Cx I2C Instance.
		1627	* @retval State of bit (1 or 0).
		1628	*/
		1629	__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
		1630	{
		1631	return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
		1632	}
		1633
		1634	/**
		1635	* @brief Indicate the value of transfer direction.
		1636	* @note RESET: Bus is in read transfer (peripheral point of view).
		1637	* SET: Bus is in write transfer (peripheral point of view).
		1638	* @rmtoll SR2 TRA LL_I2C_GetTransferDirection
		1639	* @param I2Cx I2C Instance.
		1640	* @retval Returned value can be one of the following values:
		1641	* @arg @ref LL_I2C_DIRECTION_WRITE
		1642	* @arg @ref LL_I2C_DIRECTION_READ
		1643	*/
		1644	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
		1645	{
		1646	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
		1647	}
		1648
		1649	/**
		1650	* @brief Enable DMA last transfer.
		1651	* @note This action mean that next DMA EOT is the last transfer.
		1652	* @rmtoll CR2 LAST LL_I2C_EnableLastDMA
		1653	* @param I2Cx I2C Instance.
		1654	* @retval None
		1655	*/
		1656	__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
		1657	{
		1658	SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
		1659	}
		1660
		1661	/**
		1662	* @brief Disable DMA last transfer.
		1663	* @note This action mean that next DMA EOT is not the last transfer.
		1664	* @rmtoll CR2 LAST LL_I2C_DisableLastDMA
		1665	* @param I2Cx I2C Instance.
		1666	* @retval None
		1667	*/
		1668	__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
		1669	{
		1670	CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
		1671	}
		1672
		1673	/**
		1674	* @brief Check if DMA last transfer is enabled or disabled.
		1675	* @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
		1676	* @param I2Cx I2C Instance.
		1677	* @retval State of bit (1 or 0).
		1678	*/
		1679	__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
		1680	{
		1681	return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
		1682	}
		1683
		1684	/**
		1685	* @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
		1686	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1687	* SMBus feature is supported by the I2Cx Instance.
		1688	* @note This feature is cleared by hardware when the PEC byte is transferred or compared,
		1689	* or by a START or STOP condition, it is also cleared by software.
		1690	* @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
		1691	* @param I2Cx I2C Instance.
		1692	* @retval None
		1693	*/
		1694	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
		1695	{
		1696	SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
		1697	}
		1698
		1699	/**
		1700	* @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
		1701	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1702	* SMBus feature is supported by the I2Cx Instance.
		1703	* @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
		1704	* @param I2Cx I2C Instance.
		1705	* @retval None
		1706	*/
		1707	__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
		1708	{
		1709	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
		1710	}
		1711
		1712	/**
		1713	* @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
		1714	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1715	* SMBus feature is supported by the I2Cx Instance.
		1716	* @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
		1717	* @param I2Cx I2C Instance.
		1718	* @retval State of bit (1 or 0).
		1719	*/
		1720	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
		1721	{
		1722	return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
		1723	}
		1724
		1725	/**
		1726	* @brief Get the SMBus Packet Error byte calculated.
		1727	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1728	* SMBus feature is supported by the I2Cx Instance.
		1729	* @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
		1730	* @param I2Cx I2C Instance.
		1731	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
		1732	*/
		1733	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
		1734	{
		1735	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
		1736	}
		1737
		1738	/**
		1739	* @brief Read Receive Data register.
		1740	* @rmtoll DR DR LL_I2C_ReceiveData8
		1741	* @param I2Cx I2C Instance.
		1742	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
		1743	*/
		1744	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
		1745	{
		1746	return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
		1747	}
		1748
		1749	/**
		1750	* @brief Write in Transmit Data Register .
		1751	* @rmtoll DR DR LL_I2C_TransmitData8
		1752	* @param I2Cx I2C Instance.
		1753	* @param Data Value between Min_Data=0x0 and Max_Data=0xFF
		1754	* @retval None
		1755	*/
		1756	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
		1757	{
		1758	MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
		1759	}
		1760
		1761	/**
		1762	* @}
		1763	*/
		1764
		1765	#if defined(USE_FULL_LL_DRIVER)
		1766	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
		1767	* @{
		1768	*/
		1769
		1770	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
		1771	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
		1772	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
		1773
		1774
		1775	/**
		1776	* @}
		1777	*/
		1778	#endif /* USE_FULL_LL_DRIVER */
		1779
		1780	/**
		1781	* @}
		1782	*/
		1783
		1784	/**
		1785	* @}
		1786	*/
		1787
		1788	#endif /* I2C1 \|\| I2C2 */
		1789
		1790	/**
		1791	* @}
		1792	*/
		1793
		1794	#ifdef __cplusplus
		1795	}
		1796	#endif
		1797
		1798	#endif /* __STM32F1xx_LL_I2C_H */
		1799
		1800	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories LedShow

(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_i2c.h – Rev 2