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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_gpio.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of GPIO LL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef STM32F1xx_LL_GPIO_H |
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| 22 | #define STM32F1xx_LL_GPIO_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f1xx.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F1xx_LL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) |
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| 36 | |||
| 37 | /** @defgroup GPIO_LL GPIO |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Private types -------------------------------------------------------------*/ |
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| 42 | /* Private variables ---------------------------------------------------------*/ |
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| 43 | /* Private constants ---------------------------------------------------------*/ |
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| 44 | |||
| 45 | /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants |
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| 46 | * @{ |
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| 47 | */ |
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| 48 | /* Defines used for Pin Mask Initialization */ |
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| 49 | #define GPIO_PIN_MASK_POS 8U |
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| 50 | #define GPIO_PIN_NB 16U |
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| 51 | /** |
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| 52 | * @} |
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| 53 | */ |
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| 54 | |||
| 55 | /* Private macros ------------------------------------------------------------*/ |
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| 56 | #if defined(USE_FULL_LL_DRIVER) |
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| 57 | /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros |
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| 58 | * @{ |
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| 59 | */ |
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| 60 | |||
| 61 | /** |
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| 62 | * @} |
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| 63 | */ |
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| 64 | #endif /*USE_FULL_LL_DRIVER*/ |
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| 65 | |||
| 66 | /* Exported types ------------------------------------------------------------*/ |
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| 67 | #if defined(USE_FULL_LL_DRIVER) |
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| 68 | /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures |
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| 69 | * @{ |
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| 70 | */ |
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| 71 | |||
| 72 | /** |
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| 73 | * @brief LL GPIO Init Structure definition |
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| 74 | */ |
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| 75 | typedef struct |
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| 76 | { |
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| 77 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured. |
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| 78 | This parameter can be any value of @ref GPIO_LL_EC_PIN */ |
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| 79 | |||
| 80 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins. |
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| 81 | This parameter can be a value of @ref GPIO_LL_EC_MODE. |
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| 82 | |||
| 83 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ |
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| 84 | |||
| 85 | uint32_t Speed; /*!< Specifies the speed for the selected pins. |
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| 86 | This parameter can be a value of @ref GPIO_LL_EC_SPEED. |
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| 87 | |||
| 88 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ |
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| 89 | |||
| 90 | uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. |
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| 91 | This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. |
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| 92 | |||
| 93 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ |
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| 94 | |||
| 95 | uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. |
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| 96 | This parameter can be a value of @ref GPIO_LL_EC_PULL. |
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| 97 | |||
| 98 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ |
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| 99 | } LL_GPIO_InitTypeDef; |
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| 100 | |||
| 101 | /** |
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| 102 | * @} |
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| 103 | */ |
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| 104 | #endif /* USE_FULL_LL_DRIVER */ |
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| 105 | |||
| 106 | /* Exported constants --------------------------------------------------------*/ |
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| 107 | /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants |
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| 108 | * @{ |
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| 109 | */ |
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| 110 | |||
| 111 | /** @defgroup GPIO_LL_EC_PIN PIN |
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| 112 | * @{ |
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| 113 | */ |
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| 114 | #define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */ |
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| 115 | #define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */ |
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| 116 | #define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */ |
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| 117 | #define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */ |
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| 118 | #define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */ |
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| 119 | #define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */ |
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| 120 | #define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */ |
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| 121 | #define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */ |
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| 122 | #define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */ |
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| 123 | #define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */ |
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| 124 | #define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */ |
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| 125 | #define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */ |
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| 126 | #define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */ |
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| 127 | #define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */ |
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| 128 | #define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */ |
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| 129 | #define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */ |
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| 130 | #define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \ |
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| 131 | LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \ |
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| 132 | LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \ |
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| 133 | LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \ |
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| 134 | LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \ |
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| 135 | LL_GPIO_PIN_15) /*!< Select all pins */ |
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| 136 | /** |
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| 137 | * @} |
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| 138 | */ |
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| 139 | |||
| 140 | /** @defgroup GPIO_LL_EC_MODE Mode |
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| 141 | * @{ |
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| 142 | */ |
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| 143 | #define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */ |
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| 144 | #define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */ |
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| 145 | #define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */ |
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| 146 | #define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */ |
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| 147 | #define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */ |
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| 148 | /** |
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| 149 | * @} |
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| 150 | */ |
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| 151 | |||
| 152 | /** @defgroup GPIO_LL_EC_OUTPUT Output Type |
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| 153 | * @{ |
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| 154 | */ |
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| 155 | #define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */ |
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| 156 | #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */ |
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| 157 | /** |
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| 158 | * @} |
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| 159 | */ |
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| 160 | |||
| 161 | /** @defgroup GPIO_LL_EC_SPEED Output Speed |
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| 162 | * @{ |
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| 163 | */ |
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| 164 | #define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */ |
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| 165 | #define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */ |
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| 166 | #define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */ |
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| 167 | /** |
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| 168 | * @} |
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| 169 | */ |
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| 170 | |||
| 171 | #define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */ |
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| 172 | #define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */ |
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| 173 | #define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */ |
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| 174 | |||
| 175 | /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down |
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| 176 | * @{ |
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| 177 | */ |
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| 178 | #define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */ |
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| 179 | #define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */ |
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| 180 | |||
| 181 | /** |
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| 182 | * @} |
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| 183 | */ |
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| 184 | |||
| 185 | /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin |
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| 186 | * @{ |
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| 187 | */ |
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| 188 | |||
| 189 | #define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ |
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| 190 | #define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ |
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| 191 | #define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ |
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| 192 | #define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ |
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| 193 | #define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ |
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| 194 | #define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ |
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| 195 | #define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ |
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| 196 | #define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ |
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| 197 | #define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ |
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| 198 | #define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ |
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| 199 | #define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ |
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| 200 | #define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ |
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| 201 | #define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ |
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| 202 | #define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ |
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| 203 | #define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ |
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| 204 | #define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ |
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| 205 | |||
| 206 | /** |
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| 207 | * @} |
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| 208 | */ |
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| 209 | |||
| 210 | /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port |
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| 211 | * @{ |
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| 212 | */ |
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| 213 | |||
| 214 | #define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ |
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| 215 | #define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ |
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| 216 | #define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ |
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| 217 | #define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ |
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| 218 | #define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ |
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| 219 | |||
| 220 | /** |
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| 221 | * @} |
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| 222 | */ |
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| 223 | |||
| 224 | /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT |
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| 225 | * @{ |
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| 226 | */ |
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| 227 | #define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */ |
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| 228 | #define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */ |
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| 229 | #define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */ |
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| 230 | #define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */ |
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| 231 | #define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */ |
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| 232 | #define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */ |
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| 233 | #define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */ |
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| 234 | /** |
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| 235 | * @} |
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| 236 | */ |
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| 237 | |||
| 238 | /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE |
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| 239 | * @{ |
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| 240 | */ |
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| 241 | #define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ |
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| 242 | #define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ |
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| 243 | #define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ |
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| 244 | #define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ |
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| 245 | #define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ |
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| 246 | #define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ |
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| 247 | #define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ |
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| 248 | #define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ |
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| 249 | #define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ |
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| 250 | #define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ |
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| 251 | #define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ |
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| 252 | #define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ |
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| 253 | #define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ |
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| 254 | #define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ |
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| 255 | #define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ |
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| 256 | #define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ |
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| 257 | /** |
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| 258 | * @} |
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| 259 | */ |
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| 260 | |||
| 261 | /** |
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| 262 | * @} |
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| 263 | */ |
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| 264 | |||
| 265 | /* Exported macro ------------------------------------------------------------*/ |
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| 266 | /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros |
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| 267 | * @{ |
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| 268 | */ |
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| 269 | |||
| 270 | /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros |
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| 271 | * @{ |
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| 272 | */ |
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| 273 | |||
| 274 | /** |
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| 275 | * @brief Write a value in GPIO register |
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| 276 | * @param __INSTANCE__ GPIO Instance |
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| 277 | * @param __REG__ Register to be written |
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| 278 | * @param __VALUE__ Value to be written in the register |
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| 279 | * @retval None |
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| 280 | */ |
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| 281 | #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
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| 282 | |||
| 283 | /** |
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| 284 | * @brief Read a value in GPIO register |
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| 285 | * @param __INSTANCE__ GPIO Instance |
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| 286 | * @param __REG__ Register to be read |
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| 287 | * @retval Register value |
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| 288 | */ |
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| 289 | #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
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| 290 | /** |
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| 291 | * @} |
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| 292 | */ |
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| 293 | |||
| 294 | /** |
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| 295 | * @} |
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| 296 | */ |
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| 297 | |||
| 298 | /* Exported functions --------------------------------------------------------*/ |
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| 299 | /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions |
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| 300 | * @{ |
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| 301 | */ |
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| 302 | |||
| 303 | /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration |
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| 304 | * @{ |
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| 305 | */ |
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| 306 | |||
| 307 | /** |
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| 308 | * @brief Configure gpio mode for a dedicated pin on dedicated port. |
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| 309 | * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, |
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| 310 | * Alternate function Output. |
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| 311 | * @note Warning: only one pin can be passed as parameter. |
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| 312 | * @rmtoll CRL CNFy LL_GPIO_SetPinMode |
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| 313 | * @rmtoll CRL MODEy LL_GPIO_SetPinMode |
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| 314 | * @rmtoll CRH CNFy LL_GPIO_SetPinMode |
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| 315 | * @rmtoll CRH MODEy LL_GPIO_SetPinMode |
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| 316 | * @param GPIOx GPIO Port |
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| 317 | * @param Pin This parameter can be one of the following values: |
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| 318 | * @arg @ref LL_GPIO_PIN_0 |
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| 319 | * @arg @ref LL_GPIO_PIN_1 |
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| 320 | * @arg @ref LL_GPIO_PIN_2 |
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| 321 | * @arg @ref LL_GPIO_PIN_3 |
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| 322 | * @arg @ref LL_GPIO_PIN_4 |
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| 323 | * @arg @ref LL_GPIO_PIN_5 |
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| 324 | * @arg @ref LL_GPIO_PIN_6 |
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| 325 | * @arg @ref LL_GPIO_PIN_7 |
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| 326 | * @arg @ref LL_GPIO_PIN_8 |
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| 327 | * @arg @ref LL_GPIO_PIN_9 |
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| 328 | * @arg @ref LL_GPIO_PIN_10 |
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| 329 | * @arg @ref LL_GPIO_PIN_11 |
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| 330 | * @arg @ref LL_GPIO_PIN_12 |
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| 331 | * @arg @ref LL_GPIO_PIN_13 |
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| 332 | * @arg @ref LL_GPIO_PIN_14 |
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| 333 | * @arg @ref LL_GPIO_PIN_15 |
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| 334 | * @param Mode This parameter can be one of the following values: |
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| 335 | * @arg @ref LL_GPIO_MODE_ANALOG |
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| 336 | * @arg @ref LL_GPIO_MODE_FLOATING |
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| 337 | * @arg @ref LL_GPIO_MODE_INPUT |
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| 338 | * @arg @ref LL_GPIO_MODE_OUTPUT |
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| 339 | * @arg @ref LL_GPIO_MODE_ALTERNATE |
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| 340 | * @retval None |
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| 341 | */ |
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| 342 | __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) |
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| 343 | { |
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| 344 | register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); |
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| 345 | MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U))); |
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| 346 | } |
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| 347 | |||
| 348 | /** |
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| 349 | * @brief Return gpio mode for a dedicated pin on dedicated port. |
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| 350 | * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, |
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| 351 | * Alternate function Output. |
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| 352 | * @note Warning: only one pin can be passed as parameter. |
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| 353 | * @rmtoll CRL CNFy LL_GPIO_GetPinMode |
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| 354 | * @rmtoll CRL MODEy LL_GPIO_GetPinMode |
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| 355 | * @rmtoll CRH CNFy LL_GPIO_GetPinMode |
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| 356 | * @rmtoll CRH MODEy LL_GPIO_GetPinMode |
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| 357 | * @param GPIOx GPIO Port |
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| 358 | * @param Pin This parameter can be one of the following values: |
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| 359 | * @arg @ref LL_GPIO_PIN_0 |
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| 360 | * @arg @ref LL_GPIO_PIN_1 |
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| 361 | * @arg @ref LL_GPIO_PIN_2 |
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| 362 | * @arg @ref LL_GPIO_PIN_3 |
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| 363 | * @arg @ref LL_GPIO_PIN_4 |
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| 364 | * @arg @ref LL_GPIO_PIN_5 |
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| 365 | * @arg @ref LL_GPIO_PIN_6 |
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| 366 | * @arg @ref LL_GPIO_PIN_7 |
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| 367 | * @arg @ref LL_GPIO_PIN_8 |
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| 368 | * @arg @ref LL_GPIO_PIN_9 |
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| 369 | * @arg @ref LL_GPIO_PIN_10 |
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| 370 | * @arg @ref LL_GPIO_PIN_11 |
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| 371 | * @arg @ref LL_GPIO_PIN_12 |
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| 372 | * @arg @ref LL_GPIO_PIN_13 |
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| 373 | * @arg @ref LL_GPIO_PIN_14 |
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| 374 | * @arg @ref LL_GPIO_PIN_15 |
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| 375 | * @retval Returned value can be one of the following values: |
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| 376 | * @arg @ref LL_GPIO_MODE_ANALOG |
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| 377 | * @arg @ref LL_GPIO_MODE_FLOATING |
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| 378 | * @arg @ref LL_GPIO_MODE_INPUT |
||
| 379 | * @arg @ref LL_GPIO_MODE_OUTPUT |
||
| 380 | * @arg @ref LL_GPIO_MODE_ALTERNATE |
||
| 381 | */ |
||
| 382 | __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) |
||
| 383 | { |
||
| 384 | register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); |
||
| 385 | return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); |
||
| 386 | } |
||
| 387 | |||
| 388 | /** |
||
| 389 | * @brief Configure gpio speed for a dedicated pin on dedicated port. |
||
| 390 | * @note I/O speed can be Low, Medium or Fast speed. |
||
| 391 | * @note Warning: only one pin can be passed as parameter. |
||
| 392 | * @note Refer to datasheet for frequency specifications and the power |
||
| 393 | * supply and load conditions for each speed. |
||
| 394 | * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed |
||
| 395 | * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed |
||
| 396 | * @param GPIOx GPIO Port |
||
| 397 | * @param Pin This parameter can be one of the following values: |
||
| 398 | * @arg @ref LL_GPIO_PIN_0 |
||
| 399 | * @arg @ref LL_GPIO_PIN_1 |
||
| 400 | * @arg @ref LL_GPIO_PIN_2 |
||
| 401 | * @arg @ref LL_GPIO_PIN_3 |
||
| 402 | * @arg @ref LL_GPIO_PIN_4 |
||
| 403 | * @arg @ref LL_GPIO_PIN_5 |
||
| 404 | * @arg @ref LL_GPIO_PIN_6 |
||
| 405 | * @arg @ref LL_GPIO_PIN_7 |
||
| 406 | * @arg @ref LL_GPIO_PIN_8 |
||
| 407 | * @arg @ref LL_GPIO_PIN_9 |
||
| 408 | * @arg @ref LL_GPIO_PIN_10 |
||
| 409 | * @arg @ref LL_GPIO_PIN_11 |
||
| 410 | * @arg @ref LL_GPIO_PIN_12 |
||
| 411 | * @arg @ref LL_GPIO_PIN_13 |
||
| 412 | * @arg @ref LL_GPIO_PIN_14 |
||
| 413 | * @arg @ref LL_GPIO_PIN_15 |
||
| 414 | * @param Speed This parameter can be one of the following values: |
||
| 415 | * @arg @ref LL_GPIO_SPEED_FREQ_LOW |
||
| 416 | * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM |
||
| 417 | * @arg @ref LL_GPIO_SPEED_FREQ_HIGH |
||
| 418 | * @retval None |
||
| 419 | */ |
||
| 420 | __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) |
||
| 421 | { |
||
| 422 | register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); |
||
| 423 | MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)), |
||
| 424 | (Speed << (POSITION_VAL(Pin) * 4U))); |
||
| 425 | } |
||
| 426 | |||
| 427 | /** |
||
| 428 | * @brief Return gpio speed for a dedicated pin on dedicated port. |
||
| 429 | * @note I/O speed can be Low, Medium, Fast or High speed. |
||
| 430 | * @note Warning: only one pin can be passed as parameter. |
||
| 431 | * @note Refer to datasheet for frequency specifications and the power |
||
| 432 | * supply and load conditions for each speed. |
||
| 433 | * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed |
||
| 434 | * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed |
||
| 435 | * @param GPIOx GPIO Port |
||
| 436 | * @param Pin This parameter can be one of the following values: |
||
| 437 | * @arg @ref LL_GPIO_PIN_0 |
||
| 438 | * @arg @ref LL_GPIO_PIN_1 |
||
| 439 | * @arg @ref LL_GPIO_PIN_2 |
||
| 440 | * @arg @ref LL_GPIO_PIN_3 |
||
| 441 | * @arg @ref LL_GPIO_PIN_4 |
||
| 442 | * @arg @ref LL_GPIO_PIN_5 |
||
| 443 | * @arg @ref LL_GPIO_PIN_6 |
||
| 444 | * @arg @ref LL_GPIO_PIN_7 |
||
| 445 | * @arg @ref LL_GPIO_PIN_8 |
||
| 446 | * @arg @ref LL_GPIO_PIN_9 |
||
| 447 | * @arg @ref LL_GPIO_PIN_10 |
||
| 448 | * @arg @ref LL_GPIO_PIN_11 |
||
| 449 | * @arg @ref LL_GPIO_PIN_12 |
||
| 450 | * @arg @ref LL_GPIO_PIN_13 |
||
| 451 | * @arg @ref LL_GPIO_PIN_14 |
||
| 452 | * @arg @ref LL_GPIO_PIN_15 |
||
| 453 | * @retval Returned value can be one of the following values: |
||
| 454 | * @arg @ref LL_GPIO_SPEED_FREQ_LOW |
||
| 455 | * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM |
||
| 456 | * @arg @ref LL_GPIO_SPEED_FREQ_HIGH |
||
| 457 | */ |
||
| 458 | __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) |
||
| 459 | { |
||
| 460 | register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); |
||
| 461 | return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); |
||
| 462 | } |
||
| 463 | |||
| 464 | /** |
||
| 465 | * @brief Configure gpio output type for several pins on dedicated port. |
||
| 466 | * @note Output type as to be set when gpio pin is in output or |
||
| 467 | * alternate modes. Possible type are Push-pull or Open-drain. |
||
| 468 | * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType |
||
| 469 | * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType |
||
| 470 | * @param GPIOx GPIO Port |
||
| 471 | * @param Pin This parameter can be a combination of the following values: |
||
| 472 | * @arg @ref LL_GPIO_PIN_0 |
||
| 473 | * @arg @ref LL_GPIO_PIN_1 |
||
| 474 | * @arg @ref LL_GPIO_PIN_2 |
||
| 475 | * @arg @ref LL_GPIO_PIN_3 |
||
| 476 | * @arg @ref LL_GPIO_PIN_4 |
||
| 477 | * @arg @ref LL_GPIO_PIN_5 |
||
| 478 | * @arg @ref LL_GPIO_PIN_6 |
||
| 479 | * @arg @ref LL_GPIO_PIN_7 |
||
| 480 | * @arg @ref LL_GPIO_PIN_8 |
||
| 481 | * @arg @ref LL_GPIO_PIN_9 |
||
| 482 | * @arg @ref LL_GPIO_PIN_10 |
||
| 483 | * @arg @ref LL_GPIO_PIN_11 |
||
| 484 | * @arg @ref LL_GPIO_PIN_12 |
||
| 485 | * @arg @ref LL_GPIO_PIN_13 |
||
| 486 | * @arg @ref LL_GPIO_PIN_14 |
||
| 487 | * @arg @ref LL_GPIO_PIN_15 |
||
| 488 | * @arg @ref LL_GPIO_PIN_ALL |
||
| 489 | * @param OutputType This parameter can be one of the following values: |
||
| 490 | * @arg @ref LL_GPIO_OUTPUT_PUSHPULL |
||
| 491 | * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN |
||
| 492 | * @retval None |
||
| 493 | */ |
||
| 494 | __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) |
||
| 495 | { |
||
| 496 | register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); |
||
| 497 | MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)), |
||
| 498 | (OutputType << (POSITION_VAL(Pin) * 4U))); |
||
| 499 | } |
||
| 500 | |||
| 501 | /** |
||
| 502 | * @brief Return gpio output type for several pins on dedicated port. |
||
| 503 | * @note Output type as to be set when gpio pin is in output or |
||
| 504 | * alternate modes. Possible type are Push-pull or Open-drain. |
||
| 505 | * @note Warning: only one pin can be passed as parameter. |
||
| 506 | * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType |
||
| 507 | * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType |
||
| 508 | * @param GPIOx GPIO Port |
||
| 509 | * @param Pin This parameter can be one of the following values: |
||
| 510 | * @arg @ref LL_GPIO_PIN_0 |
||
| 511 | * @arg @ref LL_GPIO_PIN_1 |
||
| 512 | * @arg @ref LL_GPIO_PIN_2 |
||
| 513 | * @arg @ref LL_GPIO_PIN_3 |
||
| 514 | * @arg @ref LL_GPIO_PIN_4 |
||
| 515 | * @arg @ref LL_GPIO_PIN_5 |
||
| 516 | * @arg @ref LL_GPIO_PIN_6 |
||
| 517 | * @arg @ref LL_GPIO_PIN_7 |
||
| 518 | * @arg @ref LL_GPIO_PIN_8 |
||
| 519 | * @arg @ref LL_GPIO_PIN_9 |
||
| 520 | * @arg @ref LL_GPIO_PIN_10 |
||
| 521 | * @arg @ref LL_GPIO_PIN_11 |
||
| 522 | * @arg @ref LL_GPIO_PIN_12 |
||
| 523 | * @arg @ref LL_GPIO_PIN_13 |
||
| 524 | * @arg @ref LL_GPIO_PIN_14 |
||
| 525 | * @arg @ref LL_GPIO_PIN_15 |
||
| 526 | * @arg @ref LL_GPIO_PIN_ALL |
||
| 527 | * @retval Returned value can be one of the following values: |
||
| 528 | * @arg @ref LL_GPIO_OUTPUT_PUSHPULL |
||
| 529 | * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN |
||
| 530 | */ |
||
| 531 | __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) |
||
| 532 | { |
||
| 533 | register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); |
||
| 534 | return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); |
||
| 535 | |||
| 536 | } |
||
| 537 | |||
| 538 | /** |
||
| 539 | * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. |
||
| 540 | * @note Warning: only one pin can be passed as parameter. |
||
| 541 | * @rmtoll ODR ODR LL_GPIO_SetPinPull |
||
| 542 | * @param GPIOx GPIO Port |
||
| 543 | * @param Pin This parameter can be one of the following values: |
||
| 544 | * @arg @ref LL_GPIO_PIN_0 |
||
| 545 | * @arg @ref LL_GPIO_PIN_1 |
||
| 546 | * @arg @ref LL_GPIO_PIN_2 |
||
| 547 | * @arg @ref LL_GPIO_PIN_3 |
||
| 548 | * @arg @ref LL_GPIO_PIN_4 |
||
| 549 | * @arg @ref LL_GPIO_PIN_5 |
||
| 550 | * @arg @ref LL_GPIO_PIN_6 |
||
| 551 | * @arg @ref LL_GPIO_PIN_7 |
||
| 552 | * @arg @ref LL_GPIO_PIN_8 |
||
| 553 | * @arg @ref LL_GPIO_PIN_9 |
||
| 554 | * @arg @ref LL_GPIO_PIN_10 |
||
| 555 | * @arg @ref LL_GPIO_PIN_11 |
||
| 556 | * @arg @ref LL_GPIO_PIN_12 |
||
| 557 | * @arg @ref LL_GPIO_PIN_13 |
||
| 558 | * @arg @ref LL_GPIO_PIN_14 |
||
| 559 | * @arg @ref LL_GPIO_PIN_15 |
||
| 560 | * @param Pull This parameter can be one of the following values: |
||
| 561 | * @arg @ref LL_GPIO_PULL_DOWN |
||
| 562 | * @arg @ref LL_GPIO_PULL_UP |
||
| 563 | * @retval None |
||
| 564 | */ |
||
| 565 | __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) |
||
| 566 | { |
||
| 567 | MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); |
||
| 568 | } |
||
| 569 | |||
| 570 | /** |
||
| 571 | * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port |
||
| 572 | * @note Warning: only one pin can be passed as parameter. |
||
| 573 | * @rmtoll ODR ODR LL_GPIO_GetPinPull |
||
| 574 | * @param GPIOx GPIO Port |
||
| 575 | * @param Pin This parameter can be one of the following values: |
||
| 576 | * @arg @ref LL_GPIO_PIN_0 |
||
| 577 | * @arg @ref LL_GPIO_PIN_1 |
||
| 578 | * @arg @ref LL_GPIO_PIN_2 |
||
| 579 | * @arg @ref LL_GPIO_PIN_3 |
||
| 580 | * @arg @ref LL_GPIO_PIN_4 |
||
| 581 | * @arg @ref LL_GPIO_PIN_5 |
||
| 582 | * @arg @ref LL_GPIO_PIN_6 |
||
| 583 | * @arg @ref LL_GPIO_PIN_7 |
||
| 584 | * @arg @ref LL_GPIO_PIN_8 |
||
| 585 | * @arg @ref LL_GPIO_PIN_9 |
||
| 586 | * @arg @ref LL_GPIO_PIN_10 |
||
| 587 | * @arg @ref LL_GPIO_PIN_11 |
||
| 588 | * @arg @ref LL_GPIO_PIN_12 |
||
| 589 | * @arg @ref LL_GPIO_PIN_13 |
||
| 590 | * @arg @ref LL_GPIO_PIN_14 |
||
| 591 | * @arg @ref LL_GPIO_PIN_15 |
||
| 592 | * @retval Returned value can be one of the following values: |
||
| 593 | * @arg @ref LL_GPIO_PULL_DOWN |
||
| 594 | * @arg @ref LL_GPIO_PULL_UP |
||
| 595 | */ |
||
| 596 | __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) |
||
| 597 | { |
||
| 598 | return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); |
||
| 599 | } |
||
| 600 | |||
| 601 | /** |
||
| 602 | * @brief Lock configuration of several pins for a dedicated port. |
||
| 603 | * @note When the lock sequence has been applied on a port bit, the |
||
| 604 | * value of this port bit can no longer be modified until the |
||
| 605 | * next reset. |
||
| 606 | * @note Each lock bit freezes a specific configuration register |
||
| 607 | * (control and alternate function registers). |
||
| 608 | * @rmtoll LCKR LCKK LL_GPIO_LockPin |
||
| 609 | * @param GPIOx GPIO Port |
||
| 610 | * @param PinMask This parameter can be a combination of the following values: |
||
| 611 | * @arg @ref LL_GPIO_PIN_0 |
||
| 612 | * @arg @ref LL_GPIO_PIN_1 |
||
| 613 | * @arg @ref LL_GPIO_PIN_2 |
||
| 614 | * @arg @ref LL_GPIO_PIN_3 |
||
| 615 | * @arg @ref LL_GPIO_PIN_4 |
||
| 616 | * @arg @ref LL_GPIO_PIN_5 |
||
| 617 | * @arg @ref LL_GPIO_PIN_6 |
||
| 618 | * @arg @ref LL_GPIO_PIN_7 |
||
| 619 | * @arg @ref LL_GPIO_PIN_8 |
||
| 620 | * @arg @ref LL_GPIO_PIN_9 |
||
| 621 | * @arg @ref LL_GPIO_PIN_10 |
||
| 622 | * @arg @ref LL_GPIO_PIN_11 |
||
| 623 | * @arg @ref LL_GPIO_PIN_12 |
||
| 624 | * @arg @ref LL_GPIO_PIN_13 |
||
| 625 | * @arg @ref LL_GPIO_PIN_14 |
||
| 626 | * @arg @ref LL_GPIO_PIN_15 |
||
| 627 | * @arg @ref LL_GPIO_PIN_ALL |
||
| 628 | * @retval None |
||
| 629 | */ |
||
| 630 | __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
||
| 631 | { |
||
| 632 | __IO uint32_t temp; |
||
| 633 | WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
||
| 634 | WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
||
| 635 | WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
||
| 636 | temp = READ_REG(GPIOx->LCKR); |
||
| 637 | (void) temp; |
||
| 638 | } |
||
| 639 | |||
| 640 | /** |
||
| 641 | * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. |
||
| 642 | * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked |
||
| 643 | * @param GPIOx GPIO Port |
||
| 644 | * @param PinMask This parameter can be a combination of the following values: |
||
| 645 | * @arg @ref LL_GPIO_PIN_0 |
||
| 646 | * @arg @ref LL_GPIO_PIN_1 |
||
| 647 | * @arg @ref LL_GPIO_PIN_2 |
||
| 648 | * @arg @ref LL_GPIO_PIN_3 |
||
| 649 | * @arg @ref LL_GPIO_PIN_4 |
||
| 650 | * @arg @ref LL_GPIO_PIN_5 |
||
| 651 | * @arg @ref LL_GPIO_PIN_6 |
||
| 652 | * @arg @ref LL_GPIO_PIN_7 |
||
| 653 | * @arg @ref LL_GPIO_PIN_8 |
||
| 654 | * @arg @ref LL_GPIO_PIN_9 |
||
| 655 | * @arg @ref LL_GPIO_PIN_10 |
||
| 656 | * @arg @ref LL_GPIO_PIN_11 |
||
| 657 | * @arg @ref LL_GPIO_PIN_12 |
||
| 658 | * @arg @ref LL_GPIO_PIN_13 |
||
| 659 | * @arg @ref LL_GPIO_PIN_14 |
||
| 660 | * @arg @ref LL_GPIO_PIN_15 |
||
| 661 | * @arg @ref LL_GPIO_PIN_ALL |
||
| 662 | * @retval State of bit (1 or 0). |
||
| 663 | */ |
||
| 664 | __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
||
| 665 | { |
||
| 666 | return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
||
| 667 | } |
||
| 668 | |||
| 669 | /** |
||
| 670 | * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. |
||
| 671 | * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked |
||
| 672 | * @param GPIOx GPIO Port |
||
| 673 | * @retval State of bit (1 or 0). |
||
| 674 | */ |
||
| 675 | __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) |
||
| 676 | { |
||
| 677 | return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); |
||
| 678 | } |
||
| 679 | |||
| 680 | /** |
||
| 681 | * @} |
||
| 682 | */ |
||
| 683 | |||
| 684 | /** @defgroup GPIO_LL_EF_Data_Access Data Access |
||
| 685 | * @{ |
||
| 686 | */ |
||
| 687 | |||
| 688 | /** |
||
| 689 | * @brief Return full input data register value for a dedicated port. |
||
| 690 | * @rmtoll IDR IDy LL_GPIO_ReadInputPort |
||
| 691 | * @param GPIOx GPIO Port |
||
| 692 | * @retval Input data register value of port |
||
| 693 | */ |
||
| 694 | __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) |
||
| 695 | { |
||
| 696 | return (READ_REG(GPIOx->IDR)); |
||
| 697 | } |
||
| 698 | |||
| 699 | /** |
||
| 700 | * @brief Return if input data level for several pins of dedicated port is high or low. |
||
| 701 | * @rmtoll IDR IDy LL_GPIO_IsInputPinSet |
||
| 702 | * @param GPIOx GPIO Port |
||
| 703 | * @param PinMask This parameter can be a combination of the following values: |
||
| 704 | * @arg @ref LL_GPIO_PIN_0 |
||
| 705 | * @arg @ref LL_GPIO_PIN_1 |
||
| 706 | * @arg @ref LL_GPIO_PIN_2 |
||
| 707 | * @arg @ref LL_GPIO_PIN_3 |
||
| 708 | * @arg @ref LL_GPIO_PIN_4 |
||
| 709 | * @arg @ref LL_GPIO_PIN_5 |
||
| 710 | * @arg @ref LL_GPIO_PIN_6 |
||
| 711 | * @arg @ref LL_GPIO_PIN_7 |
||
| 712 | * @arg @ref LL_GPIO_PIN_8 |
||
| 713 | * @arg @ref LL_GPIO_PIN_9 |
||
| 714 | * @arg @ref LL_GPIO_PIN_10 |
||
| 715 | * @arg @ref LL_GPIO_PIN_11 |
||
| 716 | * @arg @ref LL_GPIO_PIN_12 |
||
| 717 | * @arg @ref LL_GPIO_PIN_13 |
||
| 718 | * @arg @ref LL_GPIO_PIN_14 |
||
| 719 | * @arg @ref LL_GPIO_PIN_15 |
||
| 720 | * @arg @ref LL_GPIO_PIN_ALL |
||
| 721 | * @retval State of bit (1 or 0). |
||
| 722 | */ |
||
| 723 | __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
||
| 724 | { |
||
| 725 | return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
||
| 726 | } |
||
| 727 | |||
| 728 | /** |
||
| 729 | * @brief Write output data register for the port. |
||
| 730 | * @rmtoll ODR ODy LL_GPIO_WriteOutputPort |
||
| 731 | * @param GPIOx GPIO Port |
||
| 732 | * @param PortValue Level value for each pin of the port |
||
| 733 | * @retval None |
||
| 734 | */ |
||
| 735 | __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) |
||
| 736 | { |
||
| 737 | WRITE_REG(GPIOx->ODR, PortValue); |
||
| 738 | } |
||
| 739 | |||
| 740 | /** |
||
| 741 | * @brief Return full output data register value for a dedicated port. |
||
| 742 | * @rmtoll ODR ODy LL_GPIO_ReadOutputPort |
||
| 743 | * @param GPIOx GPIO Port |
||
| 744 | * @retval Output data register value of port |
||
| 745 | */ |
||
| 746 | __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) |
||
| 747 | { |
||
| 748 | return (uint32_t)(READ_REG(GPIOx->ODR)); |
||
| 749 | } |
||
| 750 | |||
| 751 | /** |
||
| 752 | * @brief Return if input data level for several pins of dedicated port is high or low. |
||
| 753 | * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet |
||
| 754 | * @param GPIOx GPIO Port |
||
| 755 | * @param PinMask This parameter can be a combination of the following values: |
||
| 756 | * @arg @ref LL_GPIO_PIN_0 |
||
| 757 | * @arg @ref LL_GPIO_PIN_1 |
||
| 758 | * @arg @ref LL_GPIO_PIN_2 |
||
| 759 | * @arg @ref LL_GPIO_PIN_3 |
||
| 760 | * @arg @ref LL_GPIO_PIN_4 |
||
| 761 | * @arg @ref LL_GPIO_PIN_5 |
||
| 762 | * @arg @ref LL_GPIO_PIN_6 |
||
| 763 | * @arg @ref LL_GPIO_PIN_7 |
||
| 764 | * @arg @ref LL_GPIO_PIN_8 |
||
| 765 | * @arg @ref LL_GPIO_PIN_9 |
||
| 766 | * @arg @ref LL_GPIO_PIN_10 |
||
| 767 | * @arg @ref LL_GPIO_PIN_11 |
||
| 768 | * @arg @ref LL_GPIO_PIN_12 |
||
| 769 | * @arg @ref LL_GPIO_PIN_13 |
||
| 770 | * @arg @ref LL_GPIO_PIN_14 |
||
| 771 | * @arg @ref LL_GPIO_PIN_15 |
||
| 772 | * @arg @ref LL_GPIO_PIN_ALL |
||
| 773 | * @retval State of bit (1 or 0). |
||
| 774 | */ |
||
| 775 | __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
||
| 776 | { |
||
| 777 | return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
||
| 778 | } |
||
| 779 | |||
| 780 | /** |
||
| 781 | * @brief Set several pins to high level on dedicated gpio port. |
||
| 782 | * @rmtoll BSRR BSy LL_GPIO_SetOutputPin |
||
| 783 | * @param GPIOx GPIO Port |
||
| 784 | * @param PinMask This parameter can be a combination of the following values: |
||
| 785 | * @arg @ref LL_GPIO_PIN_0 |
||
| 786 | * @arg @ref LL_GPIO_PIN_1 |
||
| 787 | * @arg @ref LL_GPIO_PIN_2 |
||
| 788 | * @arg @ref LL_GPIO_PIN_3 |
||
| 789 | * @arg @ref LL_GPIO_PIN_4 |
||
| 790 | * @arg @ref LL_GPIO_PIN_5 |
||
| 791 | * @arg @ref LL_GPIO_PIN_6 |
||
| 792 | * @arg @ref LL_GPIO_PIN_7 |
||
| 793 | * @arg @ref LL_GPIO_PIN_8 |
||
| 794 | * @arg @ref LL_GPIO_PIN_9 |
||
| 795 | * @arg @ref LL_GPIO_PIN_10 |
||
| 796 | * @arg @ref LL_GPIO_PIN_11 |
||
| 797 | * @arg @ref LL_GPIO_PIN_12 |
||
| 798 | * @arg @ref LL_GPIO_PIN_13 |
||
| 799 | * @arg @ref LL_GPIO_PIN_14 |
||
| 800 | * @arg @ref LL_GPIO_PIN_15 |
||
| 801 | * @arg @ref LL_GPIO_PIN_ALL |
||
| 802 | * @retval None |
||
| 803 | */ |
||
| 804 | __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
||
| 805 | { |
||
| 806 | WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); |
||
| 807 | } |
||
| 808 | |||
| 809 | /** |
||
| 810 | * @brief Set several pins to low level on dedicated gpio port. |
||
| 811 | * @rmtoll BRR BRy LL_GPIO_ResetOutputPin |
||
| 812 | * @param GPIOx GPIO Port |
||
| 813 | * @param PinMask This parameter can be a combination of the following values: |
||
| 814 | * @arg @ref LL_GPIO_PIN_0 |
||
| 815 | * @arg @ref LL_GPIO_PIN_1 |
||
| 816 | * @arg @ref LL_GPIO_PIN_2 |
||
| 817 | * @arg @ref LL_GPIO_PIN_3 |
||
| 818 | * @arg @ref LL_GPIO_PIN_4 |
||
| 819 | * @arg @ref LL_GPIO_PIN_5 |
||
| 820 | * @arg @ref LL_GPIO_PIN_6 |
||
| 821 | * @arg @ref LL_GPIO_PIN_7 |
||
| 822 | * @arg @ref LL_GPIO_PIN_8 |
||
| 823 | * @arg @ref LL_GPIO_PIN_9 |
||
| 824 | * @arg @ref LL_GPIO_PIN_10 |
||
| 825 | * @arg @ref LL_GPIO_PIN_11 |
||
| 826 | * @arg @ref LL_GPIO_PIN_12 |
||
| 827 | * @arg @ref LL_GPIO_PIN_13 |
||
| 828 | * @arg @ref LL_GPIO_PIN_14 |
||
| 829 | * @arg @ref LL_GPIO_PIN_15 |
||
| 830 | * @arg @ref LL_GPIO_PIN_ALL |
||
| 831 | * @retval None |
||
| 832 | */ |
||
| 833 | __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
||
| 834 | { |
||
| 835 | WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); |
||
| 836 | } |
||
| 837 | |||
| 838 | /** |
||
| 839 | * @brief Toggle data value for several pin of dedicated port. |
||
| 840 | * @rmtoll ODR ODy LL_GPIO_TogglePin |
||
| 841 | * @param GPIOx GPIO Port |
||
| 842 | * @param PinMask This parameter can be a combination of the following values: |
||
| 843 | * @arg @ref LL_GPIO_PIN_0 |
||
| 844 | * @arg @ref LL_GPIO_PIN_1 |
||
| 845 | * @arg @ref LL_GPIO_PIN_2 |
||
| 846 | * @arg @ref LL_GPIO_PIN_3 |
||
| 847 | * @arg @ref LL_GPIO_PIN_4 |
||
| 848 | * @arg @ref LL_GPIO_PIN_5 |
||
| 849 | * @arg @ref LL_GPIO_PIN_6 |
||
| 850 | * @arg @ref LL_GPIO_PIN_7 |
||
| 851 | * @arg @ref LL_GPIO_PIN_8 |
||
| 852 | * @arg @ref LL_GPIO_PIN_9 |
||
| 853 | * @arg @ref LL_GPIO_PIN_10 |
||
| 854 | * @arg @ref LL_GPIO_PIN_11 |
||
| 855 | * @arg @ref LL_GPIO_PIN_12 |
||
| 856 | * @arg @ref LL_GPIO_PIN_13 |
||
| 857 | * @arg @ref LL_GPIO_PIN_14 |
||
| 858 | * @arg @ref LL_GPIO_PIN_15 |
||
| 859 | * @arg @ref LL_GPIO_PIN_ALL |
||
| 860 | * @retval None |
||
| 861 | */ |
||
| 862 | __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
||
| 863 | { |
||
| 864 | WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
||
| 865 | } |
||
| 866 | |||
| 867 | /** |
||
| 868 | * @} |
||
| 869 | */ |
||
| 870 | |||
| 871 | /** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping |
||
| 872 | * @brief This section propose definition to remap the alternate function to some other port/pins. |
||
| 873 | * @{ |
||
| 874 | */ |
||
| 875 | |||
| 876 | /** |
||
| 877 | * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
||
| 878 | * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1 |
||
| 879 | * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) |
||
| 880 | * @retval None |
||
| 881 | */ |
||
| 882 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void) |
||
| 883 | { |
||
| 884 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 885 | } |
||
| 886 | |||
| 887 | /** |
||
| 888 | * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
||
| 889 | * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1 |
||
| 890 | * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) |
||
| 891 | * @retval None |
||
| 892 | */ |
||
| 893 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void) |
||
| 894 | { |
||
| 895 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 896 | } |
||
| 897 | |||
| 898 | /** |
||
| 899 | * @brief Check if SPI1 has been remaped or not |
||
| 900 | * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1 |
||
| 901 | * @retval State of bit (1 or 0). |
||
| 902 | */ |
||
| 903 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void) |
||
| 904 | { |
||
| 905 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP)); |
||
| 906 | } |
||
| 907 | |||
| 908 | /** |
||
| 909 | * @brief Enable the remapping of I2C1 alternate function SCL and SDA. |
||
| 910 | * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1 |
||
| 911 | * @note ENABLE: Remap (SCL/PB8, SDA/PB9) |
||
| 912 | * @retval None |
||
| 913 | */ |
||
| 914 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void) |
||
| 915 | { |
||
| 916 | SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 917 | } |
||
| 918 | |||
| 919 | /** |
||
| 920 | * @brief Disable the remapping of I2C1 alternate function SCL and SDA. |
||
| 921 | * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1 |
||
| 922 | * @note DISABLE: No remap (SCL/PB6, SDA/PB7) |
||
| 923 | * @retval None |
||
| 924 | */ |
||
| 925 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void) |
||
| 926 | { |
||
| 927 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 928 | } |
||
| 929 | |||
| 930 | /** |
||
| 931 | * @brief Check if I2C1 has been remaped or not |
||
| 932 | * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1 |
||
| 933 | * @retval State of bit (1 or 0). |
||
| 934 | */ |
||
| 935 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void) |
||
| 936 | { |
||
| 937 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP)); |
||
| 938 | } |
||
| 939 | |||
| 940 | /** |
||
| 941 | * @brief Enable the remapping of USART1 alternate function TX and RX. |
||
| 942 | * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1 |
||
| 943 | * @note ENABLE: Remap (TX/PB6, RX/PB7) |
||
| 944 | * @retval None |
||
| 945 | */ |
||
| 946 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void) |
||
| 947 | { |
||
| 948 | SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 949 | } |
||
| 950 | |||
| 951 | /** |
||
| 952 | * @brief Disable the remapping of USART1 alternate function TX and RX. |
||
| 953 | * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1 |
||
| 954 | * @note DISABLE: No remap (TX/PA9, RX/PA10) |
||
| 955 | * @retval None |
||
| 956 | */ |
||
| 957 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void) |
||
| 958 | { |
||
| 959 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 960 | } |
||
| 961 | |||
| 962 | /** |
||
| 963 | * @brief Check if USART1 has been remaped or not |
||
| 964 | * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1 |
||
| 965 | * @retval State of bit (1 or 0). |
||
| 966 | */ |
||
| 967 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void) |
||
| 968 | { |
||
| 969 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP)); |
||
| 970 | } |
||
| 971 | |||
| 972 | /** |
||
| 973 | * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
||
| 974 | * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2 |
||
| 975 | * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) |
||
| 976 | * @retval None |
||
| 977 | */ |
||
| 978 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void) |
||
| 979 | { |
||
| 980 | SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 981 | } |
||
| 982 | |||
| 983 | /** |
||
| 984 | * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
||
| 985 | * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2 |
||
| 986 | * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) |
||
| 987 | * @retval None |
||
| 988 | */ |
||
| 989 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void) |
||
| 990 | { |
||
| 991 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 992 | } |
||
| 993 | |||
| 994 | /** |
||
| 995 | * @brief Check if USART2 has been remaped or not |
||
| 996 | * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2 |
||
| 997 | * @retval State of bit (1 or 0). |
||
| 998 | */ |
||
| 999 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void) |
||
| 1000 | { |
||
| 1001 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP)); |
||
| 1002 | } |
||
| 1003 | |||
| 1004 | #if defined (AFIO_MAPR_USART3_REMAP) |
||
| 1005 | /** |
||
| 1006 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
||
| 1007 | * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3 |
||
| 1008 | * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) |
||
| 1009 | * @retval None |
||
| 1010 | */ |
||
| 1011 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void) |
||
| 1012 | { |
||
| 1013 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1014 | } |
||
| 1015 | |||
| 1016 | /** |
||
| 1017 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
||
| 1018 | * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3 |
||
| 1019 | * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) |
||
| 1020 | * @retval None |
||
| 1021 | */ |
||
| 1022 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void) |
||
| 1023 | { |
||
| 1024 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1025 | } |
||
| 1026 | |||
| 1027 | /** |
||
| 1028 | * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
||
| 1029 | * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3 |
||
| 1030 | * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) |
||
| 1031 | * @retval None |
||
| 1032 | */ |
||
| 1033 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void) |
||
| 1034 | { |
||
| 1035 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1036 | } |
||
| 1037 | #endif |
||
| 1038 | |||
| 1039 | /** |
||
| 1040 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
||
| 1041 | * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1 |
||
| 1042 | * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) |
||
| 1043 | * @retval None |
||
| 1044 | */ |
||
| 1045 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void) |
||
| 1046 | { |
||
| 1047 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1048 | } |
||
| 1049 | |||
| 1050 | /** |
||
| 1051 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
||
| 1052 | * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1 |
||
| 1053 | * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) |
||
| 1054 | * @retval None |
||
| 1055 | */ |
||
| 1056 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void) |
||
| 1057 | { |
||
| 1058 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1059 | } |
||
| 1060 | |||
| 1061 | /** |
||
| 1062 | * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
||
| 1063 | * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1 |
||
| 1064 | * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) |
||
| 1065 | * @retval None |
||
| 1066 | */ |
||
| 1067 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void) |
||
| 1068 | { |
||
| 1069 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1070 | } |
||
| 1071 | |||
| 1072 | /** |
||
| 1073 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
||
| 1074 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2 |
||
| 1075 | * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) |
||
| 1076 | * @retval None |
||
| 1077 | */ |
||
| 1078 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void) |
||
| 1079 | { |
||
| 1080 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1081 | } |
||
| 1082 | |||
| 1083 | /** |
||
| 1084 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
||
| 1085 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2 |
||
| 1086 | * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) |
||
| 1087 | * @retval None |
||
| 1088 | */ |
||
| 1089 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void) |
||
| 1090 | { |
||
| 1091 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 | AFIO_MAPR_SWJ_CFG)); |
||
| 1092 | } |
||
| 1093 | |||
| 1094 | /** |
||
| 1095 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
||
| 1096 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2 |
||
| 1097 | * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) |
||
| 1098 | * @retval None |
||
| 1099 | */ |
||
| 1100 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void) |
||
| 1101 | { |
||
| 1102 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | AFIO_MAPR_SWJ_CFG)); |
||
| 1103 | } |
||
| 1104 | |||
| 1105 | /** |
||
| 1106 | * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
||
| 1107 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2 |
||
| 1108 | * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) |
||
| 1109 | * @retval None |
||
| 1110 | */ |
||
| 1111 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void) |
||
| 1112 | { |
||
| 1113 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1114 | } |
||
| 1115 | |||
| 1116 | /** |
||
| 1117 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
||
| 1118 | * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3 |
||
| 1119 | * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) |
||
| 1120 | * @note TIM3_ETR on PE0 is not re-mapped. |
||
| 1121 | * @retval None |
||
| 1122 | */ |
||
| 1123 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void) |
||
| 1124 | { |
||
| 1125 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1126 | } |
||
| 1127 | |||
| 1128 | /** |
||
| 1129 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
||
| 1130 | * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3 |
||
| 1131 | * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) |
||
| 1132 | * @note TIM3_ETR on PE0 is not re-mapped. |
||
| 1133 | * @retval None |
||
| 1134 | */ |
||
| 1135 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void) |
||
| 1136 | { |
||
| 1137 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1138 | } |
||
| 1139 | |||
| 1140 | /** |
||
| 1141 | * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 |
||
| 1142 | * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3 |
||
| 1143 | * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) |
||
| 1144 | * @note TIM3_ETR on PE0 is not re-mapped. |
||
| 1145 | * @retval None |
||
| 1146 | */ |
||
| 1147 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void) |
||
| 1148 | { |
||
| 1149 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
||
| 1150 | } |
||
| 1151 | |||
| 1152 | #if defined(AFIO_MAPR_TIM4_REMAP) |
||
| 1153 | /** |
||
| 1154 | * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. |
||
| 1155 | * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4 |
||
| 1156 | * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) |
||
| 1157 | * @note TIM4_ETR on PE0 is not re-mapped. |
||
| 1158 | * @retval None |
||
| 1159 | */ |
||
| 1160 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void) |
||
| 1161 | { |
||
| 1162 | SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1163 | } |
||
| 1164 | /** |
||
| 1165 | * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. |
||
| 1166 | * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4 |
||
| 1167 | * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) |
||
| 1168 | * @note TIM4_ETR on PE0 is not re-mapped. |
||
| 1169 | * @retval None |
||
| 1170 | */ |
||
| 1171 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void) |
||
| 1172 | { |
||
| 1173 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1174 | } |
||
| 1175 | |||
| 1176 | /** |
||
| 1177 | * @brief Check if TIM4 has been remaped or not |
||
| 1178 | * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4 |
||
| 1179 | * @retval State of bit (1 or 0). |
||
| 1180 | */ |
||
| 1181 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void) |
||
| 1182 | { |
||
| 1183 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP)); |
||
| 1184 | } |
||
| 1185 | #endif |
||
| 1186 | |||
| 1187 | #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) |
||
| 1188 | |||
| 1189 | /** |
||
| 1190 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
||
| 1191 | * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1 |
||
| 1192 | * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 |
||
| 1193 | * @retval None |
||
| 1194 | */ |
||
| 1195 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void) |
||
| 1196 | { |
||
| 1197 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP1 | AFIO_MAPR_SWJ_CFG)); |
||
| 1198 | } |
||
| 1199 | |||
| 1200 | /** |
||
| 1201 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
||
| 1202 | * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1 |
||
| 1203 | * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) |
||
| 1204 | * @retval None |
||
| 1205 | */ |
||
| 1206 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void) |
||
| 1207 | { |
||
| 1208 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP2 | AFIO_MAPR_SWJ_CFG)); |
||
| 1209 | } |
||
| 1210 | |||
| 1211 | /** |
||
| 1212 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
||
| 1213 | * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1 |
||
| 1214 | * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 |
||
| 1215 | * @retval None |
||
| 1216 | */ |
||
| 1217 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void) |
||
| 1218 | { |
||
| 1219 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP3 | AFIO_MAPR_SWJ_CFG)); |
||
| 1220 | } |
||
| 1221 | #endif |
||
| 1222 | |||
| 1223 | /** |
||
| 1224 | * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used |
||
| 1225 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
||
| 1226 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
||
| 1227 | * on 100-pin and 144-pin packages, no need for remapping). |
||
| 1228 | * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01 |
||
| 1229 | * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. |
||
| 1230 | * @retval None |
||
| 1231 | */ |
||
| 1232 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void) |
||
| 1233 | { |
||
| 1234 | SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1235 | } |
||
| 1236 | |||
| 1237 | /** |
||
| 1238 | * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used |
||
| 1239 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
||
| 1240 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
||
| 1241 | * on 100-pin and 144-pin packages, no need for remapping). |
||
| 1242 | * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01 |
||
| 1243 | * @note DISABLE: No remapping of PD0 and PD1 |
||
| 1244 | * @retval None |
||
| 1245 | */ |
||
| 1246 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void) |
||
| 1247 | { |
||
| 1248 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1249 | } |
||
| 1250 | |||
| 1251 | /** |
||
| 1252 | * @brief Check if PD01 has been remaped or not |
||
| 1253 | * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01 |
||
| 1254 | * @retval State of bit (1 or 0). |
||
| 1255 | */ |
||
| 1256 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void) |
||
| 1257 | { |
||
| 1258 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP)); |
||
| 1259 | } |
||
| 1260 | |||
| 1261 | #if defined(AFIO_MAPR_TIM5CH4_IREMAP) |
||
| 1262 | /** |
||
| 1263 | * @brief Enable the remapping of TIM5CH4. |
||
| 1264 | * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4 |
||
| 1265 | * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. |
||
| 1266 | * @note This function is available only in high density value line devices. |
||
| 1267 | * @retval None |
||
| 1268 | */ |
||
| 1269 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void) |
||
| 1270 | { |
||
| 1271 | SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1272 | } |
||
| 1273 | |||
| 1274 | /** |
||
| 1275 | * @brief Disable the remapping of TIM5CH4. |
||
| 1276 | * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4 |
||
| 1277 | * @note DISABLE: TIM5_CH4 is connected to PA3 |
||
| 1278 | * @note This function is available only in high density value line devices. |
||
| 1279 | * @retval None |
||
| 1280 | */ |
||
| 1281 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void) |
||
| 1282 | { |
||
| 1283 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1284 | } |
||
| 1285 | |||
| 1286 | /** |
||
| 1287 | * @brief Check if TIM5CH4 has been remaped or not |
||
| 1288 | * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4 |
||
| 1289 | * @retval State of bit (1 or 0). |
||
| 1290 | */ |
||
| 1291 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void) |
||
| 1292 | { |
||
| 1293 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP)); |
||
| 1294 | } |
||
| 1295 | #endif |
||
| 1296 | |||
| 1297 | #if defined(AFIO_MAPR_ETH_REMAP) |
||
| 1298 | /** |
||
| 1299 | * @brief Enable the remapping of Ethernet MAC connections with the PHY. |
||
| 1300 | * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH |
||
| 1301 | * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) |
||
| 1302 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1303 | * @retval None |
||
| 1304 | */ |
||
| 1305 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void) |
||
| 1306 | { |
||
| 1307 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1308 | } |
||
| 1309 | |||
| 1310 | /** |
||
| 1311 | * @brief Disable the remapping of Ethernet MAC connections with the PHY. |
||
| 1312 | * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH |
||
| 1313 | * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) |
||
| 1314 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1315 | * @retval None |
||
| 1316 | */ |
||
| 1317 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void) |
||
| 1318 | { |
||
| 1319 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1320 | } |
||
| 1321 | |||
| 1322 | /** |
||
| 1323 | * @brief Check if ETH has been remaped or not |
||
| 1324 | * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH |
||
| 1325 | * @retval State of bit (1 or 0). |
||
| 1326 | */ |
||
| 1327 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void) |
||
| 1328 | { |
||
| 1329 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP)); |
||
| 1330 | } |
||
| 1331 | #endif |
||
| 1332 | |||
| 1333 | #if defined(AFIO_MAPR_CAN2_REMAP) |
||
| 1334 | |||
| 1335 | /** |
||
| 1336 | * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
||
| 1337 | * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2 |
||
| 1338 | * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) |
||
| 1339 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1340 | * @retval None |
||
| 1341 | */ |
||
| 1342 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void) |
||
| 1343 | { |
||
| 1344 | SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1345 | } |
||
| 1346 | /** |
||
| 1347 | * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
||
| 1348 | * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2 |
||
| 1349 | * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) |
||
| 1350 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1351 | * @retval None |
||
| 1352 | */ |
||
| 1353 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void) |
||
| 1354 | { |
||
| 1355 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1356 | } |
||
| 1357 | |||
| 1358 | /** |
||
| 1359 | * @brief Check if CAN2 has been remaped or not |
||
| 1360 | * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2 |
||
| 1361 | * @retval State of bit (1 or 0). |
||
| 1362 | */ |
||
| 1363 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void) |
||
| 1364 | { |
||
| 1365 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP)); |
||
| 1366 | } |
||
| 1367 | #endif |
||
| 1368 | |||
| 1369 | #if defined(AFIO_MAPR_MII_RMII_SEL) |
||
| 1370 | /** |
||
| 1371 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
||
| 1372 | * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII |
||
| 1373 | * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY |
||
| 1374 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1375 | * @retval None |
||
| 1376 | */ |
||
| 1377 | __STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void) |
||
| 1378 | { |
||
| 1379 | SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG); |
||
| 1380 | } |
||
| 1381 | |||
| 1382 | /** |
||
| 1383 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
||
| 1384 | * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII |
||
| 1385 | * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY |
||
| 1386 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1387 | * @retval None |
||
| 1388 | */ |
||
| 1389 | __STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void) |
||
| 1390 | { |
||
| 1391 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1392 | } |
||
| 1393 | #endif |
||
| 1394 | |||
| 1395 | #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
||
| 1396 | /** |
||
| 1397 | * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
||
| 1398 | * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ |
||
| 1399 | * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. |
||
| 1400 | * @retval None |
||
| 1401 | */ |
||
| 1402 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void) |
||
| 1403 | { |
||
| 1404 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1405 | } |
||
| 1406 | |||
| 1407 | /** |
||
| 1408 | * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
||
| 1409 | * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ |
||
| 1410 | * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 |
||
| 1411 | * @retval None |
||
| 1412 | */ |
||
| 1413 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void) |
||
| 1414 | { |
||
| 1415 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1416 | } |
||
| 1417 | |||
| 1418 | /** |
||
| 1419 | * @brief Check if ADC1_ETRGINJ has been remaped or not |
||
| 1420 | * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ |
||
| 1421 | * @retval State of bit (1 or 0). |
||
| 1422 | */ |
||
| 1423 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void) |
||
| 1424 | { |
||
| 1425 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP)); |
||
| 1426 | } |
||
| 1427 | #endif |
||
| 1428 | |||
| 1429 | #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
||
| 1430 | /** |
||
| 1431 | * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
||
| 1432 | * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG |
||
| 1433 | * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. |
||
| 1434 | * @retval None |
||
| 1435 | */ |
||
| 1436 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void) |
||
| 1437 | { |
||
| 1438 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1439 | } |
||
| 1440 | |||
| 1441 | /** |
||
| 1442 | * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
||
| 1443 | * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG |
||
| 1444 | * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 |
||
| 1445 | * @retval None |
||
| 1446 | */ |
||
| 1447 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void) |
||
| 1448 | { |
||
| 1449 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1450 | } |
||
| 1451 | |||
| 1452 | /** |
||
| 1453 | * @brief Check if ADC1_ETRGREG has been remaped or not |
||
| 1454 | * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG |
||
| 1455 | * @retval State of bit (1 or 0). |
||
| 1456 | */ |
||
| 1457 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void) |
||
| 1458 | { |
||
| 1459 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP)); |
||
| 1460 | } |
||
| 1461 | #endif |
||
| 1462 | |||
| 1463 | #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
||
| 1464 | |||
| 1465 | /** |
||
| 1466 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
||
| 1467 | * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ |
||
| 1468 | * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. |
||
| 1469 | * @retval None |
||
| 1470 | */ |
||
| 1471 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void) |
||
| 1472 | { |
||
| 1473 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1474 | } |
||
| 1475 | |||
| 1476 | /** |
||
| 1477 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
||
| 1478 | * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ |
||
| 1479 | * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 |
||
| 1480 | * @retval None |
||
| 1481 | */ |
||
| 1482 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void) |
||
| 1483 | { |
||
| 1484 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1485 | } |
||
| 1486 | |||
| 1487 | /** |
||
| 1488 | * @brief Check if ADC2_ETRGINJ has been remaped or not |
||
| 1489 | * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ |
||
| 1490 | * @retval State of bit (1 or 0). |
||
| 1491 | */ |
||
| 1492 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void) |
||
| 1493 | { |
||
| 1494 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP)); |
||
| 1495 | } |
||
| 1496 | #endif |
||
| 1497 | |||
| 1498 | #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) |
||
| 1499 | |||
| 1500 | /** |
||
| 1501 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
||
| 1502 | * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG |
||
| 1503 | * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. |
||
| 1504 | * @retval None |
||
| 1505 | */ |
||
| 1506 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void) |
||
| 1507 | { |
||
| 1508 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1509 | } |
||
| 1510 | |||
| 1511 | /** |
||
| 1512 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
||
| 1513 | * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG |
||
| 1514 | * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 |
||
| 1515 | * @retval None |
||
| 1516 | */ |
||
| 1517 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void) |
||
| 1518 | { |
||
| 1519 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1520 | } |
||
| 1521 | |||
| 1522 | /** |
||
| 1523 | * @brief Check if ADC2_ETRGREG has been remaped or not |
||
| 1524 | * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG |
||
| 1525 | * @retval State of bit (1 or 0). |
||
| 1526 | */ |
||
| 1527 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void) |
||
| 1528 | { |
||
| 1529 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP)); |
||
| 1530 | } |
||
| 1531 | #endif |
||
| 1532 | |||
| 1533 | /** |
||
| 1534 | * @brief Enable the Serial wire JTAG configuration |
||
| 1535 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ |
||
| 1536 | * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State |
||
| 1537 | * @retval None |
||
| 1538 | */ |
||
| 1539 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void) |
||
| 1540 | { |
||
| 1541 | CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); |
||
| 1542 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET); |
||
| 1543 | } |
||
| 1544 | |||
| 1545 | /** |
||
| 1546 | * @brief Enable the Serial wire JTAG configuration |
||
| 1547 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST |
||
| 1548 | * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
||
| 1549 | * @retval None |
||
| 1550 | */ |
||
| 1551 | __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void) |
||
| 1552 | { |
||
| 1553 | CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); |
||
| 1554 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST); |
||
| 1555 | } |
||
| 1556 | |||
| 1557 | /** |
||
| 1558 | * @brief Enable the Serial wire JTAG configuration |
||
| 1559 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG |
||
| 1560 | * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled |
||
| 1561 | * @retval None |
||
| 1562 | */ |
||
| 1563 | __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void) |
||
| 1564 | { |
||
| 1565 | CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); |
||
| 1566 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); |
||
| 1567 | } |
||
| 1568 | |||
| 1569 | /** |
||
| 1570 | * @brief Disable the Serial wire JTAG configuration |
||
| 1571 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ |
||
| 1572 | * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled |
||
| 1573 | * @retval None |
||
| 1574 | */ |
||
| 1575 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void) |
||
| 1576 | { |
||
| 1577 | CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); |
||
| 1578 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE); |
||
| 1579 | } |
||
| 1580 | |||
| 1581 | #if defined(AFIO_MAPR_SPI3_REMAP) |
||
| 1582 | |||
| 1583 | /** |
||
| 1584 | * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
||
| 1585 | * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3 |
||
| 1586 | * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) |
||
| 1587 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1588 | * @retval None |
||
| 1589 | */ |
||
| 1590 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void) |
||
| 1591 | { |
||
| 1592 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1593 | } |
||
| 1594 | |||
| 1595 | /** |
||
| 1596 | * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
||
| 1597 | * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3 |
||
| 1598 | * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). |
||
| 1599 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1600 | * @retval None |
||
| 1601 | */ |
||
| 1602 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void) |
||
| 1603 | { |
||
| 1604 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1605 | } |
||
| 1606 | |||
| 1607 | /** |
||
| 1608 | * @brief Check if SPI3 has been remaped or not |
||
| 1609 | * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP |
||
| 1610 | * @retval State of bit (1 or 0). |
||
| 1611 | */ |
||
| 1612 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void) |
||
| 1613 | { |
||
| 1614 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP)); |
||
| 1615 | } |
||
| 1616 | #endif |
||
| 1617 | |||
| 1618 | #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) |
||
| 1619 | |||
| 1620 | /** |
||
| 1621 | * @brief Control of TIM2_ITR1 internal mapping. |
||
| 1622 | * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB |
||
| 1623 | * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. |
||
| 1624 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1625 | * @retval None |
||
| 1626 | */ |
||
| 1627 | __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void) |
||
| 1628 | { |
||
| 1629 | SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1630 | } |
||
| 1631 | |||
| 1632 | /** |
||
| 1633 | * @brief Control of TIM2_ITR1 internal mapping. |
||
| 1634 | * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH |
||
| 1635 | * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. |
||
| 1636 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1637 | * @retval None |
||
| 1638 | */ |
||
| 1639 | __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void) |
||
| 1640 | { |
||
| 1641 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1642 | } |
||
| 1643 | #endif |
||
| 1644 | |||
| 1645 | #if defined(AFIO_MAPR_PTP_PPS_REMAP) |
||
| 1646 | |||
| 1647 | /** |
||
| 1648 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
||
| 1649 | * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS |
||
| 1650 | * @note ENABLE: PTP_PPS is output on PB5 pin. |
||
| 1651 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1652 | * @retval None |
||
| 1653 | */ |
||
| 1654 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void) |
||
| 1655 | { |
||
| 1656 | SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG); |
||
| 1657 | } |
||
| 1658 | |||
| 1659 | /** |
||
| 1660 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
||
| 1661 | * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS |
||
| 1662 | * @note DISABLE: PTP_PPS not output on PB5 pin. |
||
| 1663 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
||
| 1664 | * @retval None |
||
| 1665 | */ |
||
| 1666 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void) |
||
| 1667 | { |
||
| 1668 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
||
| 1669 | } |
||
| 1670 | #endif |
||
| 1671 | |||
| 1672 | #if defined(AFIO_MAPR2_TIM9_REMAP) |
||
| 1673 | |||
| 1674 | /** |
||
| 1675 | * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. |
||
| 1676 | * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9 |
||
| 1677 | * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). |
||
| 1678 | * @retval None |
||
| 1679 | */ |
||
| 1680 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void) |
||
| 1681 | { |
||
| 1682 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); |
||
| 1683 | } |
||
| 1684 | |||
| 1685 | /** |
||
| 1686 | * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. |
||
| 1687 | * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9 |
||
| 1688 | * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). |
||
| 1689 | * @retval None |
||
| 1690 | */ |
||
| 1691 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void) |
||
| 1692 | { |
||
| 1693 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); |
||
| 1694 | } |
||
| 1695 | |||
| 1696 | /** |
||
| 1697 | * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not |
||
| 1698 | * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9 |
||
| 1699 | * @retval State of bit (1 or 0). |
||
| 1700 | */ |
||
| 1701 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void) |
||
| 1702 | { |
||
| 1703 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP)); |
||
| 1704 | } |
||
| 1705 | #endif |
||
| 1706 | |||
| 1707 | #if defined(AFIO_MAPR2_TIM10_REMAP) |
||
| 1708 | |||
| 1709 | /** |
||
| 1710 | * @brief Enable the remapping of TIM10_CH1. |
||
| 1711 | * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10 |
||
| 1712 | * @note ENABLE: Remap (TIM10_CH1 on PF6). |
||
| 1713 | * @retval None |
||
| 1714 | */ |
||
| 1715 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void) |
||
| 1716 | { |
||
| 1717 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); |
||
| 1718 | } |
||
| 1719 | |||
| 1720 | /** |
||
| 1721 | * @brief Disable the remapping of TIM10_CH1. |
||
| 1722 | * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10 |
||
| 1723 | * @note DISABLE: No remap (TIM10_CH1 on PB8). |
||
| 1724 | * @retval None |
||
| 1725 | */ |
||
| 1726 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void) |
||
| 1727 | { |
||
| 1728 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); |
||
| 1729 | } |
||
| 1730 | |||
| 1731 | /** |
||
| 1732 | * @brief Check if TIM10_CH1 has been remaped or not |
||
| 1733 | * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10 |
||
| 1734 | * @retval State of bit (1 or 0). |
||
| 1735 | */ |
||
| 1736 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void) |
||
| 1737 | { |
||
| 1738 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP)); |
||
| 1739 | } |
||
| 1740 | #endif |
||
| 1741 | |||
| 1742 | #if defined(AFIO_MAPR2_TIM11_REMAP) |
||
| 1743 | /** |
||
| 1744 | * @brief Enable the remapping of TIM11_CH1. |
||
| 1745 | * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11 |
||
| 1746 | * @note ENABLE: Remap (TIM11_CH1 on PF7). |
||
| 1747 | * @retval None |
||
| 1748 | */ |
||
| 1749 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void) |
||
| 1750 | { |
||
| 1751 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); |
||
| 1752 | } |
||
| 1753 | |||
| 1754 | /** |
||
| 1755 | * @brief Disable the remapping of TIM11_CH1. |
||
| 1756 | * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11 |
||
| 1757 | * @note DISABLE: No remap (TIM11_CH1 on PB9). |
||
| 1758 | * @retval None |
||
| 1759 | */ |
||
| 1760 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void) |
||
| 1761 | { |
||
| 1762 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); |
||
| 1763 | } |
||
| 1764 | |||
| 1765 | /** |
||
| 1766 | * @brief Check if TIM11_CH1 has been remaped or not |
||
| 1767 | * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11 |
||
| 1768 | * @retval State of bit (1 or 0). |
||
| 1769 | */ |
||
| 1770 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void) |
||
| 1771 | { |
||
| 1772 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP)); |
||
| 1773 | } |
||
| 1774 | #endif |
||
| 1775 | |||
| 1776 | #if defined(AFIO_MAPR2_TIM13_REMAP) |
||
| 1777 | |||
| 1778 | /** |
||
| 1779 | * @brief Enable the remapping of TIM13_CH1. |
||
| 1780 | * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13 |
||
| 1781 | * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). |
||
| 1782 | * @retval None |
||
| 1783 | */ |
||
| 1784 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void) |
||
| 1785 | { |
||
| 1786 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); |
||
| 1787 | } |
||
| 1788 | |||
| 1789 | /** |
||
| 1790 | * @brief Disable the remapping of TIM13_CH1. |
||
| 1791 | * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13 |
||
| 1792 | * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). |
||
| 1793 | * @retval None |
||
| 1794 | */ |
||
| 1795 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void) |
||
| 1796 | { |
||
| 1797 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); |
||
| 1798 | } |
||
| 1799 | |||
| 1800 | /** |
||
| 1801 | * @brief Check if TIM13_CH1 has been remaped or not |
||
| 1802 | * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13 |
||
| 1803 | * @retval State of bit (1 or 0). |
||
| 1804 | */ |
||
| 1805 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void) |
||
| 1806 | { |
||
| 1807 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP)); |
||
| 1808 | } |
||
| 1809 | #endif |
||
| 1810 | |||
| 1811 | #if defined(AFIO_MAPR2_TIM14_REMAP) |
||
| 1812 | |||
| 1813 | /** |
||
| 1814 | * @brief Enable the remapping of TIM14_CH1. |
||
| 1815 | * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14 |
||
| 1816 | * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). |
||
| 1817 | * @retval None |
||
| 1818 | */ |
||
| 1819 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void) |
||
| 1820 | { |
||
| 1821 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); |
||
| 1822 | } |
||
| 1823 | |||
| 1824 | /** |
||
| 1825 | * @brief Disable the remapping of TIM14_CH1. |
||
| 1826 | * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14 |
||
| 1827 | * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). |
||
| 1828 | * @retval None |
||
| 1829 | */ |
||
| 1830 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void) |
||
| 1831 | { |
||
| 1832 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); |
||
| 1833 | } |
||
| 1834 | |||
| 1835 | /** |
||
| 1836 | * @brief Check if TIM14_CH1 has been remaped or not |
||
| 1837 | * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14 |
||
| 1838 | * @retval State of bit (1 or 0). |
||
| 1839 | */ |
||
| 1840 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void) |
||
| 1841 | { |
||
| 1842 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP)); |
||
| 1843 | } |
||
| 1844 | #endif |
||
| 1845 | |||
| 1846 | #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) |
||
| 1847 | |||
| 1848 | /** |
||
| 1849 | * @brief Controls the use of the optional FSMC_NADV signal. |
||
| 1850 | * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV |
||
| 1851 | * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. |
||
| 1852 | * @retval None |
||
| 1853 | */ |
||
| 1854 | __STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void) |
||
| 1855 | { |
||
| 1856 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); |
||
| 1857 | } |
||
| 1858 | |||
| 1859 | /** |
||
| 1860 | * @brief Controls the use of the optional FSMC_NADV signal. |
||
| 1861 | * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV |
||
| 1862 | * @note CONNECTED: The NADV signal is connected to the output (default). |
||
| 1863 | * @retval None |
||
| 1864 | */ |
||
| 1865 | __STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void) |
||
| 1866 | { |
||
| 1867 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); |
||
| 1868 | } |
||
| 1869 | #endif |
||
| 1870 | |||
| 1871 | #if defined(AFIO_MAPR2_TIM15_REMAP) |
||
| 1872 | |||
| 1873 | /** |
||
| 1874 | * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. |
||
| 1875 | * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15 |
||
| 1876 | * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). |
||
| 1877 | * @retval None |
||
| 1878 | */ |
||
| 1879 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void) |
||
| 1880 | { |
||
| 1881 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); |
||
| 1882 | } |
||
| 1883 | /** |
||
| 1884 | * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. |
||
| 1885 | * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15 |
||
| 1886 | * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). |
||
| 1887 | * @retval None |
||
| 1888 | */ |
||
| 1889 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void) |
||
| 1890 | { |
||
| 1891 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); |
||
| 1892 | } |
||
| 1893 | |||
| 1894 | /** |
||
| 1895 | * @brief Check if TIM15_CH1 has been remaped or not |
||
| 1896 | * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15 |
||
| 1897 | * @retval State of bit (1 or 0). |
||
| 1898 | */ |
||
| 1899 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void) |
||
| 1900 | { |
||
| 1901 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP)); |
||
| 1902 | } |
||
| 1903 | #endif |
||
| 1904 | |||
| 1905 | #if defined(AFIO_MAPR2_TIM16_REMAP) |
||
| 1906 | |||
| 1907 | /** |
||
| 1908 | * @brief Enable the remapping of TIM16_CH1. |
||
| 1909 | * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16 |
||
| 1910 | * @note ENABLE: Remap (TIM16_CH1 on PA6). |
||
| 1911 | * @retval None |
||
| 1912 | */ |
||
| 1913 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void) |
||
| 1914 | { |
||
| 1915 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); |
||
| 1916 | } |
||
| 1917 | |||
| 1918 | /** |
||
| 1919 | * @brief Disable the remapping of TIM16_CH1. |
||
| 1920 | * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16 |
||
| 1921 | * @note DISABLE: No remap (TIM16_CH1 on PB8). |
||
| 1922 | * @retval None |
||
| 1923 | */ |
||
| 1924 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void) |
||
| 1925 | { |
||
| 1926 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); |
||
| 1927 | } |
||
| 1928 | |||
| 1929 | /** |
||
| 1930 | * @brief Check if TIM16_CH1 has been remaped or not |
||
| 1931 | * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16 |
||
| 1932 | * @retval State of bit (1 or 0). |
||
| 1933 | */ |
||
| 1934 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void) |
||
| 1935 | { |
||
| 1936 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP)); |
||
| 1937 | } |
||
| 1938 | #endif |
||
| 1939 | |||
| 1940 | #if defined(AFIO_MAPR2_TIM17_REMAP) |
||
| 1941 | |||
| 1942 | /** |
||
| 1943 | * @brief Enable the remapping of TIM17_CH1. |
||
| 1944 | * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17 |
||
| 1945 | * @note ENABLE: Remap (TIM17_CH1 on PA7). |
||
| 1946 | * @retval None |
||
| 1947 | */ |
||
| 1948 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void) |
||
| 1949 | { |
||
| 1950 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); |
||
| 1951 | } |
||
| 1952 | |||
| 1953 | /** |
||
| 1954 | * @brief Disable the remapping of TIM17_CH1. |
||
| 1955 | * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17 |
||
| 1956 | * @note DISABLE: No remap (TIM17_CH1 on PB9). |
||
| 1957 | * @retval None |
||
| 1958 | */ |
||
| 1959 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void) |
||
| 1960 | { |
||
| 1961 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); |
||
| 1962 | } |
||
| 1963 | |||
| 1964 | /** |
||
| 1965 | * @brief Check if TIM17_CH1 has been remaped or not |
||
| 1966 | * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17 |
||
| 1967 | * @retval State of bit (1 or 0). |
||
| 1968 | */ |
||
| 1969 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void) |
||
| 1970 | { |
||
| 1971 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP)); |
||
| 1972 | } |
||
| 1973 | #endif |
||
| 1974 | |||
| 1975 | #if defined(AFIO_MAPR2_CEC_REMAP) |
||
| 1976 | |||
| 1977 | /** |
||
| 1978 | * @brief Enable the remapping of CEC. |
||
| 1979 | * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC |
||
| 1980 | * @note ENABLE: Remap (CEC on PB10). |
||
| 1981 | * @retval None |
||
| 1982 | */ |
||
| 1983 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void) |
||
| 1984 | { |
||
| 1985 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); |
||
| 1986 | } |
||
| 1987 | |||
| 1988 | /** |
||
| 1989 | * @brief Disable the remapping of CEC. |
||
| 1990 | * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC |
||
| 1991 | * @note DISABLE: No remap (CEC on PB8). |
||
| 1992 | * @retval None |
||
| 1993 | */ |
||
| 1994 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void) |
||
| 1995 | { |
||
| 1996 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); |
||
| 1997 | } |
||
| 1998 | |||
| 1999 | /** |
||
| 2000 | * @brief Check if CEC has been remaped or not |
||
| 2001 | * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC |
||
| 2002 | * @retval State of bit (1 or 0). |
||
| 2003 | */ |
||
| 2004 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void) |
||
| 2005 | { |
||
| 2006 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP)); |
||
| 2007 | } |
||
| 2008 | #endif |
||
| 2009 | |||
| 2010 | #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) |
||
| 2011 | |||
| 2012 | /** |
||
| 2013 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
||
| 2014 | * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA |
||
| 2015 | * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) |
||
| 2016 | * @retval None |
||
| 2017 | */ |
||
| 2018 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void) |
||
| 2019 | { |
||
| 2020 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); |
||
| 2021 | } |
||
| 2022 | |||
| 2023 | /** |
||
| 2024 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
||
| 2025 | * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA |
||
| 2026 | * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). |
||
| 2027 | * @retval None |
||
| 2028 | */ |
||
| 2029 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void) |
||
| 2030 | { |
||
| 2031 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); |
||
| 2032 | } |
||
| 2033 | |||
| 2034 | /** |
||
| 2035 | * @brief Check if TIM1DMA has been remaped or not |
||
| 2036 | * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA |
||
| 2037 | * @retval State of bit (1 or 0). |
||
| 2038 | */ |
||
| 2039 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void) |
||
| 2040 | { |
||
| 2041 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP)); |
||
| 2042 | } |
||
| 2043 | #endif |
||
| 2044 | |||
| 2045 | #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
||
| 2046 | |||
| 2047 | /** |
||
| 2048 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
||
| 2049 | * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA |
||
| 2050 | * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) |
||
| 2051 | * @retval None |
||
| 2052 | */ |
||
| 2053 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void) |
||
| 2054 | { |
||
| 2055 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); |
||
| 2056 | } |
||
| 2057 | |||
| 2058 | /** |
||
| 2059 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
||
| 2060 | * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA |
||
| 2061 | * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) |
||
| 2062 | * @retval None |
||
| 2063 | */ |
||
| 2064 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void) |
||
| 2065 | { |
||
| 2066 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); |
||
| 2067 | } |
||
| 2068 | |||
| 2069 | /** |
||
| 2070 | * @brief Check if TIM67DACDMA has been remaped or not |
||
| 2071 | * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA |
||
| 2072 | * @retval State of bit (1 or 0). |
||
| 2073 | */ |
||
| 2074 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void) |
||
| 2075 | { |
||
| 2076 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP)); |
||
| 2077 | } |
||
| 2078 | #endif |
||
| 2079 | |||
| 2080 | #if defined(AFIO_MAPR2_TIM12_REMAP) |
||
| 2081 | |||
| 2082 | /** |
||
| 2083 | * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. |
||
| 2084 | * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12 |
||
| 2085 | * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). |
||
| 2086 | * @note This bit is available only in high density value line devices. |
||
| 2087 | * @retval None |
||
| 2088 | */ |
||
| 2089 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void) |
||
| 2090 | { |
||
| 2091 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); |
||
| 2092 | } |
||
| 2093 | |||
| 2094 | /** |
||
| 2095 | * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. |
||
| 2096 | * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12 |
||
| 2097 | * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). |
||
| 2098 | * @note This bit is available only in high density value line devices. |
||
| 2099 | * @retval None |
||
| 2100 | */ |
||
| 2101 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void) |
||
| 2102 | { |
||
| 2103 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); |
||
| 2104 | } |
||
| 2105 | |||
| 2106 | /** |
||
| 2107 | * @brief Check if TIM12_CH1 has been remaped or not |
||
| 2108 | * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12 |
||
| 2109 | * @retval State of bit (1 or 0). |
||
| 2110 | */ |
||
| 2111 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void) |
||
| 2112 | { |
||
| 2113 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP)); |
||
| 2114 | } |
||
| 2115 | #endif |
||
| 2116 | |||
| 2117 | #if defined(AFIO_MAPR2_MISC_REMAP) |
||
| 2118 | |||
| 2119 | /** |
||
| 2120 | * @brief Miscellaneous features remapping. |
||
| 2121 | * This bit is set and cleared by software. It controls miscellaneous features. |
||
| 2122 | * The DMA2 channel 5 interrupt position in the vector table. |
||
| 2123 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
||
| 2124 | * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC |
||
| 2125 | * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is |
||
| 2126 | * selected as DAC Trigger 3, TIM15 triggers TIM1/3. |
||
| 2127 | * @note This bit is available only in high density value line devices. |
||
| 2128 | * @retval None |
||
| 2129 | */ |
||
| 2130 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void) |
||
| 2131 | { |
||
| 2132 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); |
||
| 2133 | } |
||
| 2134 | |||
| 2135 | /** |
||
| 2136 | * @brief Miscellaneous features remapping. |
||
| 2137 | * This bit is set and cleared by software. It controls miscellaneous features. |
||
| 2138 | * The DMA2 channel 5 interrupt position in the vector table. |
||
| 2139 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
||
| 2140 | * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC |
||
| 2141 | * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO |
||
| 2142 | * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. |
||
| 2143 | * @note This bit is available only in high density value line devices. |
||
| 2144 | * @retval None |
||
| 2145 | */ |
||
| 2146 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void) |
||
| 2147 | { |
||
| 2148 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); |
||
| 2149 | } |
||
| 2150 | |||
| 2151 | /** |
||
| 2152 | * @brief Check if MISC has been remaped or not |
||
| 2153 | * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC |
||
| 2154 | * @retval State of bit (1 or 0). |
||
| 2155 | */ |
||
| 2156 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void) |
||
| 2157 | { |
||
| 2158 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP)); |
||
| 2159 | } |
||
| 2160 | #endif |
||
| 2161 | |||
| 2162 | /** |
||
| 2163 | * @} |
||
| 2164 | */ |
||
| 2165 | |||
| 2166 | /** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration |
||
| 2167 | * @brief This section propose definition to Configure EVENTOUT Cortex feature . |
||
| 2168 | * @{ |
||
| 2169 | */ |
||
| 2170 | |||
| 2171 | /** |
||
| 2172 | * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. |
||
| 2173 | * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n |
||
| 2174 | * EVCR PIN LL_GPIO_AF_ConfigEventout |
||
| 2175 | * @param LL_GPIO_PortSource This parameter can be one of the following values: |
||
| 2176 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A |
||
| 2177 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B |
||
| 2178 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C |
||
| 2179 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D |
||
| 2180 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E |
||
| 2181 | * @param LL_GPIO_PinSource This parameter can be one of the following values: |
||
| 2182 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0 |
||
| 2183 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1 |
||
| 2184 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2 |
||
| 2185 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3 |
||
| 2186 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4 |
||
| 2187 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5 |
||
| 2188 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6 |
||
| 2189 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7 |
||
| 2190 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8 |
||
| 2191 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9 |
||
| 2192 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10 |
||
| 2193 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11 |
||
| 2194 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12 |
||
| 2195 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13 |
||
| 2196 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14 |
||
| 2197 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15 |
||
| 2198 | * @retval None |
||
| 2199 | */ |
||
| 2200 | __STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource) |
||
| 2201 | { |
||
| 2202 | MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource)); |
||
| 2203 | } |
||
| 2204 | |||
| 2205 | /** |
||
| 2206 | * @brief Enables the Event Output. |
||
| 2207 | * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout |
||
| 2208 | * @retval None |
||
| 2209 | */ |
||
| 2210 | __STATIC_INLINE void LL_GPIO_AF_EnableEventout(void) |
||
| 2211 | { |
||
| 2212 | SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
||
| 2213 | } |
||
| 2214 | |||
| 2215 | /** |
||
| 2216 | * @brief Disables the Event Output. |
||
| 2217 | * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout |
||
| 2218 | * @retval None |
||
| 2219 | */ |
||
| 2220 | __STATIC_INLINE void LL_GPIO_AF_DisableEventout(void) |
||
| 2221 | { |
||
| 2222 | CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
||
| 2223 | } |
||
| 2224 | |||
| 2225 | /** |
||
| 2226 | * @} |
||
| 2227 | */ |
||
| 2228 | /** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt |
||
| 2229 | * @brief This section Configure source input for the EXTI external interrupt . |
||
| 2230 | * @{ |
||
| 2231 | */ |
||
| 2232 | |||
| 2233 | /** |
||
| 2234 | * @brief Configure source input for the EXTI external interrupt. |
||
| 2235 | * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n |
||
| 2236 | * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n |
||
| 2237 | * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n |
||
| 2238 | * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource |
||
| 2239 | * @param Port This parameter can be one of the following values: |
||
| 2240 | * @arg @ref LL_GPIO_AF_EXTI_PORTA |
||
| 2241 | * @arg @ref LL_GPIO_AF_EXTI_PORTB |
||
| 2242 | * @arg @ref LL_GPIO_AF_EXTI_PORTC |
||
| 2243 | * @arg @ref LL_GPIO_AF_EXTI_PORTD |
||
| 2244 | * @arg @ref LL_GPIO_AF_EXTI_PORTE |
||
| 2245 | * @arg @ref LL_GPIO_AF_EXTI_PORTF |
||
| 2246 | * @arg @ref LL_GPIO_AF_EXTI_PORTG |
||
| 2247 | * @param Line This parameter can be one of the following values: |
||
| 2248 | * @arg @ref LL_GPIO_AF_EXTI_LINE0 |
||
| 2249 | * @arg @ref LL_GPIO_AF_EXTI_LINE1 |
||
| 2250 | * @arg @ref LL_GPIO_AF_EXTI_LINE2 |
||
| 2251 | * @arg @ref LL_GPIO_AF_EXTI_LINE3 |
||
| 2252 | * @arg @ref LL_GPIO_AF_EXTI_LINE4 |
||
| 2253 | * @arg @ref LL_GPIO_AF_EXTI_LINE5 |
||
| 2254 | * @arg @ref LL_GPIO_AF_EXTI_LINE6 |
||
| 2255 | * @arg @ref LL_GPIO_AF_EXTI_LINE7 |
||
| 2256 | * @arg @ref LL_GPIO_AF_EXTI_LINE8 |
||
| 2257 | * @arg @ref LL_GPIO_AF_EXTI_LINE9 |
||
| 2258 | * @arg @ref LL_GPIO_AF_EXTI_LINE10 |
||
| 2259 | * @arg @ref LL_GPIO_AF_EXTI_LINE11 |
||
| 2260 | * @arg @ref LL_GPIO_AF_EXTI_LINE12 |
||
| 2261 | * @arg @ref LL_GPIO_AF_EXTI_LINE13 |
||
| 2262 | * @arg @ref LL_GPIO_AF_EXTI_LINE14 |
||
| 2263 | * @arg @ref LL_GPIO_AF_EXTI_LINE15 |
||
| 2264 | * @retval None |
||
| 2265 | */ |
||
| 2266 | __STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line) |
||
| 2267 | { |
||
| 2268 | MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); |
||
| 2269 | } |
||
| 2270 | |||
| 2271 | /** |
||
| 2272 | * @brief Get the configured defined for specific EXTI Line |
||
| 2273 | * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n |
||
| 2274 | * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n |
||
| 2275 | * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n |
||
| 2276 | * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource |
||
| 2277 | * @param Line This parameter can be one of the following values: |
||
| 2278 | * @arg @ref LL_GPIO_AF_EXTI_LINE0 |
||
| 2279 | * @arg @ref LL_GPIO_AF_EXTI_LINE1 |
||
| 2280 | * @arg @ref LL_GPIO_AF_EXTI_LINE2 |
||
| 2281 | * @arg @ref LL_GPIO_AF_EXTI_LINE3 |
||
| 2282 | * @arg @ref LL_GPIO_AF_EXTI_LINE4 |
||
| 2283 | * @arg @ref LL_GPIO_AF_EXTI_LINE5 |
||
| 2284 | * @arg @ref LL_GPIO_AF_EXTI_LINE6 |
||
| 2285 | * @arg @ref LL_GPIO_AF_EXTI_LINE7 |
||
| 2286 | * @arg @ref LL_GPIO_AF_EXTI_LINE8 |
||
| 2287 | * @arg @ref LL_GPIO_AF_EXTI_LINE9 |
||
| 2288 | * @arg @ref LL_GPIO_AF_EXTI_LINE10 |
||
| 2289 | * @arg @ref LL_GPIO_AF_EXTI_LINE11 |
||
| 2290 | * @arg @ref LL_GPIO_AF_EXTI_LINE12 |
||
| 2291 | * @arg @ref LL_GPIO_AF_EXTI_LINE13 |
||
| 2292 | * @arg @ref LL_GPIO_AF_EXTI_LINE14 |
||
| 2293 | * @arg @ref LL_GPIO_AF_EXTI_LINE15 |
||
| 2294 | * @retval Returned value can be one of the following values: |
||
| 2295 | * @arg @ref LL_GPIO_AF_EXTI_PORTA |
||
| 2296 | * @arg @ref LL_GPIO_AF_EXTI_PORTB |
||
| 2297 | * @arg @ref LL_GPIO_AF_EXTI_PORTC |
||
| 2298 | * @arg @ref LL_GPIO_AF_EXTI_PORTD |
||
| 2299 | * @arg @ref LL_GPIO_AF_EXTI_PORTE |
||
| 2300 | * @arg @ref LL_GPIO_AF_EXTI_PORTF |
||
| 2301 | * @arg @ref LL_GPIO_AF_EXTI_PORTG |
||
| 2302 | */ |
||
| 2303 | __STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line) |
||
| 2304 | { |
||
| 2305 | return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); |
||
| 2306 | } |
||
| 2307 | |||
| 2308 | /** |
||
| 2309 | * @} |
||
| 2310 | */ |
||
| 2311 | |||
| 2312 | #if defined(USE_FULL_LL_DRIVER) |
||
| 2313 | /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions |
||
| 2314 | * @{ |
||
| 2315 | */ |
||
| 2316 | |||
| 2317 | ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); |
||
| 2318 | ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); |
||
| 2319 | void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); |
||
| 2320 | |||
| 2321 | /** |
||
| 2322 | * @} |
||
| 2323 | */ |
||
| 2324 | #endif /* USE_FULL_LL_DRIVER */ |
||
| 2325 | |||
| 2326 | /** |
||
| 2327 | * @} |
||
| 2328 | */ |
||
| 2329 | |||
| 2330 | /** |
||
| 2331 | * @} |
||
| 2332 | */ |
||
| 2333 | |||
| 2334 | #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */ |
||
| 2335 | /** |
||
| 2336 | * @} |
||
| 2337 | */ |
||
| 2338 | |||
| 2339 | #ifdef __cplusplus |
||
| 2340 | } |
||
| 2341 | #endif |
||
| 2342 | |||
| 2343 | #endif /* STM32F1xx_LL_GPIO_H */ |
||
| 2344 | |||
| 2345 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |