WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_gpio.h
		4	* @author MCD Application Team
		5	* @brief Header file of GPIO LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
		10	*
		11	* Redistribution and use in source and binary forms, with or without modification,
		12	* are permitted provided that the following conditions are met:
		13	* 1. Redistributions of source code must retain the above copyright notice,
		14	* this list of conditions and the following disclaimer.
		15	* 2. Redistributions in binary form must reproduce the above copyright notice,
		16	* this list of conditions and the following disclaimer in the documentation
		17	* and/or other materials provided with the distribution.
		18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		19	* may be used to endorse or promote products derived from this software
		20	* without specific prior written permission.
		21	*
		22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		32	*
		33	******************************************************************************
		34	*/
		35
		36	/* Define to prevent recursive inclusion -------------------------------------*/
		37	#ifndef __STM32F1xx_LL_GPIO_H
		38	#define __STM32F1xx_LL_GPIO_H
		39
		40	#ifdef __cplusplus
		41	extern "C" {
		42	#endif
		43
		44	/* Includes ------------------------------------------------------------------*/
		45	#include "stm32f1xx.h"
		46
		47	/** @addtogroup STM32F1xx_LL_Driver
		48	* @{
		49	*/
		50
		51	#if defined (GPIOA) \|\| defined (GPIOB) \|\| defined (GPIOC) \|\| defined (GPIOD) \|\| defined (GPIOE) \|\| defined (GPIOF) \|\| defined (GPIOG)
		52
		53	/** @defgroup GPIO_LL GPIO
		54	* @{
		55	*/
		56
		57	/* Private types -------------------------------------------------------------*/
		58	/* Private variables ---------------------------------------------------------*/
		59	/* Private constants ---------------------------------------------------------*/
		60
		61	/** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
		62	* @{
		63	*/
		64	/* Defines used for Pin Mask Initialization */
		65	#define GPIO_PIN_MASK_POS 8U
		66	#define GPIO_PIN_NB 16U
		67	/**
		68	* @}
		69	*/
		70
		71	/* Private macros ------------------------------------------------------------*/
		72	#if defined(USE_FULL_LL_DRIVER)
		73	/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
		74	* @{
		75	*/
		76
		77	/**
		78	* @}
		79	*/
		80	#endif /USE_FULL_LL_DRIVER/
		81
		82	/* Exported types ------------------------------------------------------------*/
		83	#if defined(USE_FULL_LL_DRIVER)
		84	/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
		85	* @{
		86	*/
		87
		88	/**
		89	* @brief LL GPIO Init Structure definition
		90	*/
		91	typedef struct
		92	{
		93	uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
		94	This parameter can be any value of @ref GPIO_LL_EC_PIN */
		95
		96	uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
		97	This parameter can be a value of @ref GPIO_LL_EC_MODE.
		98
		99	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
		100
		101	uint32_t Speed; /*!< Specifies the speed for the selected pins.
		102	This parameter can be a value of @ref GPIO_LL_EC_SPEED.
		103
		104	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
		105
		106	uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
		107	This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
		108
		109	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
		110
		111	uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
		112	This parameter can be a value of @ref GPIO_LL_EC_PULL.
		113
		114	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
		115	} LL_GPIO_InitTypeDef;
		116
		117	/**
		118	* @}
		119	*/
		120	#endif /* USE_FULL_LL_DRIVER */
		121
		122	/* Exported constants --------------------------------------------------------*/
		123	/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
		124	* @{
		125	*/
		126
		127	/** @defgroup GPIO_LL_EC_PIN PIN
		128	* @{
		129	*/
		130	#define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) \| 0x00000001U) /!< Select pin 0 /
		131	#define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) \| 0x00000002U) /!< Select pin 1 /
		132	#define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) \| 0x00000004U) /!< Select pin 2 /
		133	#define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) \| 0x00000008U) /!< Select pin 3 /
		134	#define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) \| 0x00000010U) /!< Select pin 4 /
		135	#define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) \| 0x00000020U) /!< Select pin 5 /
		136	#define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) \| 0x00000040U) /!< Select pin 6 /
		137	#define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) \| 0x00000080U) /!< Select pin 7 /
		138	#define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) \| 0x04000001U) /!< Select pin 8 /
		139	#define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) \| 0x04000002U) /!< Select pin 9 /
		140	#define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) \| 0x04000004U) /!< Select pin 10 /
		141	#define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) \| 0x04000008U) /!< Select pin 11 /
		142	#define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) \| 0x04000010U) /!< Select pin 12 /
		143	#define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) \| 0x04000020U) /!< Select pin 13 /
		144	#define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) \| 0x04000040U) /!< Select pin 14 /
		145	#define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) \| 0x04000080U) /!< Select pin 15 /
		146	#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 \| LL_GPIO_PIN_1 \| LL_GPIO_PIN_2 \| \
		147	LL_GPIO_PIN_3 \| LL_GPIO_PIN_4 \| LL_GPIO_PIN_5 \| \
		148	LL_GPIO_PIN_6 \| LL_GPIO_PIN_7 \| LL_GPIO_PIN_8 \| \
		149	LL_GPIO_PIN_9 \| LL_GPIO_PIN_10 \| LL_GPIO_PIN_11 \| \
		150	LL_GPIO_PIN_12 \| LL_GPIO_PIN_13 \| LL_GPIO_PIN_14 \| \
		151	LL_GPIO_PIN_15) /!< Select all pins /
		152	/**
		153	* @}
		154	*/
		155
		156	/** @defgroup GPIO_LL_EC_MODE Mode
		157	* @{
		158	*/
		159	#define LL_GPIO_MODE_ANALOG 0x00000000U /!< Select analog mode /
		160	#define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /!< Select floating mode /
		161	#define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /!< Select input mode /
		162	#define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /!< Select general purpose output mode /
		163	#define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 \| GPIO_CRL_MODE0_0) /!< Select alternate function mode /
		164	/**
		165	* @}
		166	*/
		167
		168	/** @defgroup GPIO_LL_EC_OUTPUT Output Type
		169	* @{
		170	*/
		171	#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /!< Select push-pull as output type /
		172	#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /!< Select open-drain as output type /
		173	/**
		174	* @}
		175	*/
		176
		177	/** @defgroup GPIO_LL_EC_SPEED Output Speed
		178	* @{
		179	*/
		180	#define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /!< Select Output mode, max speed 10 MHz /
		181	#define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /!< Select Output mode, max speed 20 MHz /
		182	#define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /!< Select Output mode, max speed 50 MHz /
		183	/**
		184	* @}
		185	*/
		186
		187	#define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /!< Select I/O low output speed /
		188	#define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /!< Select I/O medium output speed /
		189	#define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /!< Select I/O high output speed /
		190
		191	/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
		192	* @{
		193	*/
		194	#define LL_GPIO_PULL_DOWN 0x00000000U /!< Select I/O pull down /
		195	#define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /!< Select I/O pull up /
		196
		197	/**
		198	* @}
		199	*/
		200
		201	/** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
		202	* @{
		203	*/
		204
		205	#define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /!< EVENTOUT on pin 0 /
		206	#define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /!< EVENTOUT on pin 1 /
		207	#define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /!< EVENTOUT on pin 2 /
		208	#define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /!< EVENTOUT on pin 3 /
		209	#define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /!< EVENTOUT on pin 4 /
		210	#define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /!< EVENTOUT on pin 5 /
		211	#define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /!< EVENTOUT on pin 6 /
		212	#define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /!< EVENTOUT on pin 7 /
		213	#define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /!< EVENTOUT on pin 8 /
		214	#define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /!< EVENTOUT on pin 9 /
		215	#define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /!< EVENTOUT on pin 10 /
		216	#define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /!< EVENTOUT on pin 11 /
		217	#define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /!< EVENTOUT on pin 12 /
		218	#define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /!< EVENTOUT on pin 13 /
		219	#define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /!< EVENTOUT on pin 14 /
		220	#define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /!< EVENTOUT on pin 15 /
		221
		222	/**
		223	* @}
		224	*/
		225
		226	/** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
		227	* @{
		228	*/
		229
		230	#define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /!< EVENTOUT on port A /
		231	#define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /!< EVENTOUT on port B /
		232	#define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /!< EVENTOUT on port C /
		233	#define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /!< EVENTOUT on port D /
		234	#define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /!< EVENTOUT on port E /
		235
		236	/**
		237	* @}
		238	*/
		239
		240	/** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
		241	* @{
		242	*/
		243	#define LL_GPIO_AF_EXTI_PORTA 0U /!< EXTI PORT A /
		244	#define LL_GPIO_AF_EXTI_PORTB 1U /!< EXTI PORT B /
		245	#define LL_GPIO_AF_EXTI_PORTC 2U /!< EXTI PORT C /
		246	#define LL_GPIO_AF_EXTI_PORTD 3U /!< EXTI PORT D /
		247	#define LL_GPIO_AF_EXTI_PORTE 4U /!< EXTI PORT E /
		248	#define LL_GPIO_AF_EXTI_PORTF 5U /!< EXTI PORT F /
		249	#define LL_GPIO_AF_EXTI_PORTG 6U /!< EXTI PORT G /
		250	/**
		251	* @}
		252	*/
		253
		254	/** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
		255	* @{
		256	*/
		257	#define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U \| 0U) /!< EXTI_POSITION_0 \| EXTICR[0] /
		258	#define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U \| 0U) /!< EXTI_POSITION_4 \| EXTICR[0] /
		259	#define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U \| 0U) /!< EXTI_POSITION_8 \| EXTICR[0] /
		260	#define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U \| 0U) /!< EXTI_POSITION_12 \| EXTICR[0] /
		261	#define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U \| 1U) /!< EXTI_POSITION_0 \| EXTICR[1] /
		262	#define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U \| 1U) /!< EXTI_POSITION_4 \| EXTICR[1] /
		263	#define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U \| 1U) /!< EXTI_POSITION_8 \| EXTICR[1] /
		264	#define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U \| 1U) /!< EXTI_POSITION_12 \| EXTICR[1] /
		265	#define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U \| 2U) /!< EXTI_POSITION_0 \| EXTICR[2] /
		266	#define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U \| 2U) /!< EXTI_POSITION_4 \| EXTICR[2] /
		267	#define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U \| 2U) /!< EXTI_POSITION_8 \| EXTICR[2] /
		268	#define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U \| 2U) /!< EXTI_POSITION_12 \| EXTICR[2] /
		269	#define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U \| 3U) /!< EXTI_POSITION_0 \| EXTICR[3] /
		270	#define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U \| 3U) /!< EXTI_POSITION_4 \| EXTICR[3] /
		271	#define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U \| 3U) /!< EXTI_POSITION_8 \| EXTICR[3] /
		272	#define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U \| 3U) /!< EXTI_POSITION_12 \| EXTICR[3] /
		273	/**
		274	* @}
		275	*/
		276
		277	/**
		278	* @}
		279	*/
		280
		281	/* Exported macro ------------------------------------------------------------*/
		282	/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
		283	* @{
		284	*/
		285
		286	/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
		287	* @{
		288	*/
		289
		290	/**
		291	* @brief Write a value in GPIO register
		292	* @param __INSTANCE__ GPIO Instance
		293	* @param __REG__ Register to be written
		294	* @param __VALUE__ Value to be written in the register
		295	* @retval None
		296	*/
		297	#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		298
		299	/**
		300	* @brief Read a value in GPIO register
		301	* @param __INSTANCE__ GPIO Instance
		302	* @param __REG__ Register to be read
		303	* @retval Register value
		304	*/
		305	#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		306	/**
		307	* @}
		308	*/
		309
		310	/**
		311	* @}
		312	*/
		313
		314	/* Exported functions --------------------------------------------------------*/
		315	/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
		316	* @{
		317	*/
		318
		319	/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
		320	* @{
		321	*/
		322
		323	/**
		324	* @brief Configure gpio mode for a dedicated pin on dedicated port.
		325	* @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
		326	* Alternate function Output.
		327	* @note Warning: only one pin can be passed as parameter.
		328	* @rmtoll CRL CNFy LL_GPIO_SetPinMode
		329	* @rmtoll CRL MODEy LL_GPIO_SetPinMode
		330	* @rmtoll CRH CNFy LL_GPIO_SetPinMode
		331	* @rmtoll CRH MODEy LL_GPIO_SetPinMode
		332	* @param GPIOx GPIO Port
		333	* @param Pin This parameter can be one of the following values:
		334	* @arg @ref LL_GPIO_PIN_0
		335	* @arg @ref LL_GPIO_PIN_1
		336	* @arg @ref LL_GPIO_PIN_2
		337	* @arg @ref LL_GPIO_PIN_3
		338	* @arg @ref LL_GPIO_PIN_4
		339	* @arg @ref LL_GPIO_PIN_5
		340	* @arg @ref LL_GPIO_PIN_6
		341	* @arg @ref LL_GPIO_PIN_7
		342	* @arg @ref LL_GPIO_PIN_8
		343	* @arg @ref LL_GPIO_PIN_9
		344	* @arg @ref LL_GPIO_PIN_10
		345	* @arg @ref LL_GPIO_PIN_11
		346	* @arg @ref LL_GPIO_PIN_12
		347	* @arg @ref LL_GPIO_PIN_13
		348	* @arg @ref LL_GPIO_PIN_14
		349	* @arg @ref LL_GPIO_PIN_15
		350	* @param Mode This parameter can be one of the following values:
		351	* @arg @ref LL_GPIO_MODE_ANALOG
		352	* @arg @ref LL_GPIO_MODE_FLOATING
		353	* @arg @ref LL_GPIO_MODE_INPUT
		354	* @arg @ref LL_GPIO_MODE_OUTPUT
		355	* @arg @ref LL_GPIO_MODE_ALTERNATE
		356	* @retval None
		357	*/
		358	__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
		359	{
		360	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
		361	MODIFY_REG(pReg, ((GPIO_CRL_CNF0 \| GPIO_CRL_MODE0) << (POSITION_VAL(Pin) 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
		362	}
		363
		364	/**
		365	* @brief Return gpio mode for a dedicated pin on dedicated port.
		366	* @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
		367	* Alternate function Output.
		368	* @note Warning: only one pin can be passed as parameter.
		369	* @rmtoll CRL CNFy LL_GPIO_GetPinMode
		370	* @rmtoll CRL MODEy LL_GPIO_GetPinMode
		371	* @rmtoll CRH CNFy LL_GPIO_GetPinMode
		372	* @rmtoll CRH MODEy LL_GPIO_GetPinMode
		373	* @param GPIOx GPIO Port
		374	* @param Pin This parameter can be one of the following values:
		375	* @arg @ref LL_GPIO_PIN_0
		376	* @arg @ref LL_GPIO_PIN_1
		377	* @arg @ref LL_GPIO_PIN_2
		378	* @arg @ref LL_GPIO_PIN_3
		379	* @arg @ref LL_GPIO_PIN_4
		380	* @arg @ref LL_GPIO_PIN_5
		381	* @arg @ref LL_GPIO_PIN_6
		382	* @arg @ref LL_GPIO_PIN_7
		383	* @arg @ref LL_GPIO_PIN_8
		384	* @arg @ref LL_GPIO_PIN_9
		385	* @arg @ref LL_GPIO_PIN_10
		386	* @arg @ref LL_GPIO_PIN_11
		387	* @arg @ref LL_GPIO_PIN_12
		388	* @arg @ref LL_GPIO_PIN_13
		389	* @arg @ref LL_GPIO_PIN_14
		390	* @arg @ref LL_GPIO_PIN_15
		391	* @retval Returned value can be one of the following values:
		392	* @arg @ref LL_GPIO_MODE_ANALOG
		393	* @arg @ref LL_GPIO_MODE_FLOATING
		394	* @arg @ref LL_GPIO_MODE_INPUT
		395	* @arg @ref LL_GPIO_MODE_OUTPUT
		396	* @arg @ref LL_GPIO_MODE_ALTERNATE
		397	*/
		398	__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
		399	{
		400	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
		401	return (READ_BIT(pReg, ((GPIO_CRL_CNF0 \| GPIO_CRL_MODE0) << (POSITION_VAL(Pin) 4U))) >> (POSITION_VAL(Pin) * 4U));
		402	}
		403
		404	/**
		405	* @brief Configure gpio speed for a dedicated pin on dedicated port.
		406	* @note I/O speed can be Low, Medium or Fast speed.
		407	* @note Warning: only one pin can be passed as parameter.
		408	* @note Refer to datasheet for frequency specifications and the power
		409	* supply and load conditions for each speed.
		410	* @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
		411	* @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
		412	* @param GPIOx GPIO Port
		413	* @param Pin This parameter can be one of the following values:
		414	* @arg @ref LL_GPIO_PIN_0
		415	* @arg @ref LL_GPIO_PIN_1
		416	* @arg @ref LL_GPIO_PIN_2
		417	* @arg @ref LL_GPIO_PIN_3
		418	* @arg @ref LL_GPIO_PIN_4
		419	* @arg @ref LL_GPIO_PIN_5
		420	* @arg @ref LL_GPIO_PIN_6
		421	* @arg @ref LL_GPIO_PIN_7
		422	* @arg @ref LL_GPIO_PIN_8
		423	* @arg @ref LL_GPIO_PIN_9
		424	* @arg @ref LL_GPIO_PIN_10
		425	* @arg @ref LL_GPIO_PIN_11
		426	* @arg @ref LL_GPIO_PIN_12
		427	* @arg @ref LL_GPIO_PIN_13
		428	* @arg @ref LL_GPIO_PIN_14
		429	* @arg @ref LL_GPIO_PIN_15
		430	* @param Speed This parameter can be one of the following values:
		431	* @arg @ref LL_GPIO_SPEED_FREQ_LOW
		432	* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
		433	* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
		434	* @retval None
		435	*/
		436	__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
		437	{
		438	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
		439	MODIFY_REG(pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) 4U)),
		440	(Speed << (POSITION_VAL(Pin) * 4U)));
		441	}
		442
		443	/**
		444	* @brief Return gpio speed for a dedicated pin on dedicated port.
		445	* @note I/O speed can be Low, Medium, Fast or High speed.
		446	* @note Warning: only one pin can be passed as parameter.
		447	* @note Refer to datasheet for frequency specifications and the power
		448	* supply and load conditions for each speed.
		449	* @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
		450	* @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
		451	* @param GPIOx GPIO Port
		452	* @param Pin This parameter can be one of the following values:
		453	* @arg @ref LL_GPIO_PIN_0
		454	* @arg @ref LL_GPIO_PIN_1
		455	* @arg @ref LL_GPIO_PIN_2
		456	* @arg @ref LL_GPIO_PIN_3
		457	* @arg @ref LL_GPIO_PIN_4
		458	* @arg @ref LL_GPIO_PIN_5
		459	* @arg @ref LL_GPIO_PIN_6
		460	* @arg @ref LL_GPIO_PIN_7
		461	* @arg @ref LL_GPIO_PIN_8
		462	* @arg @ref LL_GPIO_PIN_9
		463	* @arg @ref LL_GPIO_PIN_10
		464	* @arg @ref LL_GPIO_PIN_11
		465	* @arg @ref LL_GPIO_PIN_12
		466	* @arg @ref LL_GPIO_PIN_13
		467	* @arg @ref LL_GPIO_PIN_14
		468	* @arg @ref LL_GPIO_PIN_15
		469	* @retval Returned value can be one of the following values:
		470	* @arg @ref LL_GPIO_SPEED_FREQ_LOW
		471	* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
		472	* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
		473	*/
		474	__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
		475	{
		476	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
		477	return (READ_BIT(pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) 4U))) >> (POSITION_VAL(Pin) * 4U));
		478	}
		479
		480	/**
		481	* @brief Configure gpio output type for several pins on dedicated port.
		482	* @note Output type as to be set when gpio pin is in output or
		483	* alternate modes. Possible type are Push-pull or Open-drain.
		484	* @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
		485	* @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
		486	* @param GPIOx GPIO Port
		487	* @param Pin This parameter can be a combination of the following values:
		488	* @arg @ref LL_GPIO_PIN_0
		489	* @arg @ref LL_GPIO_PIN_1
		490	* @arg @ref LL_GPIO_PIN_2
		491	* @arg @ref LL_GPIO_PIN_3
		492	* @arg @ref LL_GPIO_PIN_4
		493	* @arg @ref LL_GPIO_PIN_5
		494	* @arg @ref LL_GPIO_PIN_6
		495	* @arg @ref LL_GPIO_PIN_7
		496	* @arg @ref LL_GPIO_PIN_8
		497	* @arg @ref LL_GPIO_PIN_9
		498	* @arg @ref LL_GPIO_PIN_10
		499	* @arg @ref LL_GPIO_PIN_11
		500	* @arg @ref LL_GPIO_PIN_12
		501	* @arg @ref LL_GPIO_PIN_13
		502	* @arg @ref LL_GPIO_PIN_14
		503	* @arg @ref LL_GPIO_PIN_15
		504	* @arg @ref LL_GPIO_PIN_ALL
		505	* @param OutputType This parameter can be one of the following values:
		506	* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
		507	* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
		508	* @retval None
		509	*/
		510	__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
		511	{
		512	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
		513	MODIFY_REG(pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) 4U)),
		514	(OutputType << (POSITION_VAL(Pin) * 4U)));
		515	}
		516
		517	/**
		518	* @brief Return gpio output type for several pins on dedicated port.
		519	* @note Output type as to be set when gpio pin is in output or
		520	* alternate modes. Possible type are Push-pull or Open-drain.
		521	* @note Warning: only one pin can be passed as parameter.
		522	* @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
		523	* @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
		524	* @param GPIOx GPIO Port
		525	* @param Pin This parameter can be one of the following values:
		526	* @arg @ref LL_GPIO_PIN_0
		527	* @arg @ref LL_GPIO_PIN_1
		528	* @arg @ref LL_GPIO_PIN_2
		529	* @arg @ref LL_GPIO_PIN_3
		530	* @arg @ref LL_GPIO_PIN_4
		531	* @arg @ref LL_GPIO_PIN_5
		532	* @arg @ref LL_GPIO_PIN_6
		533	* @arg @ref LL_GPIO_PIN_7
		534	* @arg @ref LL_GPIO_PIN_8
		535	* @arg @ref LL_GPIO_PIN_9
		536	* @arg @ref LL_GPIO_PIN_10
		537	* @arg @ref LL_GPIO_PIN_11
		538	* @arg @ref LL_GPIO_PIN_12
		539	* @arg @ref LL_GPIO_PIN_13
		540	* @arg @ref LL_GPIO_PIN_14
		541	* @arg @ref LL_GPIO_PIN_15
		542	* @arg @ref LL_GPIO_PIN_ALL
		543	* @retval Returned value can be one of the following values:
		544	* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
		545	* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
		546	*/
		547	__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
		548	{
		549	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
		550	return (READ_BIT(pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) 4U))) >> (POSITION_VAL(Pin) * 4U));
		551
		552	}
		553
		554	/**
		555	* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
		556	* @note Warning: only one pin can be passed as parameter.
		557	* @rmtoll ODR ODR LL_GPIO_SetPinPull
		558	* @param GPIOx GPIO Port
		559	* @param Pin This parameter can be one of the following values:
		560	* @arg @ref LL_GPIO_PIN_0
		561	* @arg @ref LL_GPIO_PIN_1
		562	* @arg @ref LL_GPIO_PIN_2
		563	* @arg @ref LL_GPIO_PIN_3
		564	* @arg @ref LL_GPIO_PIN_4
		565	* @arg @ref LL_GPIO_PIN_5
		566	* @arg @ref LL_GPIO_PIN_6
		567	* @arg @ref LL_GPIO_PIN_7
		568	* @arg @ref LL_GPIO_PIN_8
		569	* @arg @ref LL_GPIO_PIN_9
		570	* @arg @ref LL_GPIO_PIN_10
		571	* @arg @ref LL_GPIO_PIN_11
		572	* @arg @ref LL_GPIO_PIN_12
		573	* @arg @ref LL_GPIO_PIN_13
		574	* @arg @ref LL_GPIO_PIN_14
		575	* @arg @ref LL_GPIO_PIN_15
		576	* @param Pull This parameter can be one of the following values:
		577	* @arg @ref LL_GPIO_PULL_DOWN
		578	* @arg @ref LL_GPIO_PULL_UP
		579	* @retval None
		580	*/
		581	__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
		582	{
		583	MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
		584	}
		585
		586	/**
		587	* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
		588	* @note Warning: only one pin can be passed as parameter.
		589	* @rmtoll ODR ODR LL_GPIO_GetPinPull
		590	* @param GPIOx GPIO Port
		591	* @param Pin This parameter can be one of the following values:
		592	* @arg @ref LL_GPIO_PIN_0
		593	* @arg @ref LL_GPIO_PIN_1
		594	* @arg @ref LL_GPIO_PIN_2
		595	* @arg @ref LL_GPIO_PIN_3
		596	* @arg @ref LL_GPIO_PIN_4
		597	* @arg @ref LL_GPIO_PIN_5
		598	* @arg @ref LL_GPIO_PIN_6
		599	* @arg @ref LL_GPIO_PIN_7
		600	* @arg @ref LL_GPIO_PIN_8
		601	* @arg @ref LL_GPIO_PIN_9
		602	* @arg @ref LL_GPIO_PIN_10
		603	* @arg @ref LL_GPIO_PIN_11
		604	* @arg @ref LL_GPIO_PIN_12
		605	* @arg @ref LL_GPIO_PIN_13
		606	* @arg @ref LL_GPIO_PIN_14
		607	* @arg @ref LL_GPIO_PIN_15
		608	* @retval Returned value can be one of the following values:
		609	* @arg @ref LL_GPIO_PULL_DOWN
		610	* @arg @ref LL_GPIO_PULL_UP
		611	*/
		612	__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
		613	{
		614	return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
		615	}
		616
		617	/**
		618	* @brief Lock configuration of several pins for a dedicated port.
		619	* @note When the lock sequence has been applied on a port bit, the
		620	* value of this port bit can no longer be modified until the
		621	* next reset.
		622	* @note Each lock bit freezes a specific configuration register
		623	* (control and alternate function registers).
		624	* @rmtoll LCKR LCKK LL_GPIO_LockPin
		625	* @param GPIOx GPIO Port
		626	* @param PinMask This parameter can be a combination of the following values:
		627	* @arg @ref LL_GPIO_PIN_0
		628	* @arg @ref LL_GPIO_PIN_1
		629	* @arg @ref LL_GPIO_PIN_2
		630	* @arg @ref LL_GPIO_PIN_3
		631	* @arg @ref LL_GPIO_PIN_4
		632	* @arg @ref LL_GPIO_PIN_5
		633	* @arg @ref LL_GPIO_PIN_6
		634	* @arg @ref LL_GPIO_PIN_7
		635	* @arg @ref LL_GPIO_PIN_8
		636	* @arg @ref LL_GPIO_PIN_9
		637	* @arg @ref LL_GPIO_PIN_10
		638	* @arg @ref LL_GPIO_PIN_11
		639	* @arg @ref LL_GPIO_PIN_12
		640	* @arg @ref LL_GPIO_PIN_13
		641	* @arg @ref LL_GPIO_PIN_14
		642	* @arg @ref LL_GPIO_PIN_15
		643	* @arg @ref LL_GPIO_PIN_ALL
		644	* @retval None
		645	*/
		646	__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
		647	{
		648	__IO uint32_t temp;
		649	WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK \| ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
		650	WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
		651	WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK \| ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
		652	temp = READ_REG(GPIOx->LCKR);
		653	(void) temp;
		654	}
		655
		656	/**
		657	* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
		658	* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
		659	* @param GPIOx GPIO Port
		660	* @param PinMask This parameter can be a combination of the following values:
		661	* @arg @ref LL_GPIO_PIN_0
		662	* @arg @ref LL_GPIO_PIN_1
		663	* @arg @ref LL_GPIO_PIN_2
		664	* @arg @ref LL_GPIO_PIN_3
		665	* @arg @ref LL_GPIO_PIN_4
		666	* @arg @ref LL_GPIO_PIN_5
		667	* @arg @ref LL_GPIO_PIN_6
		668	* @arg @ref LL_GPIO_PIN_7
		669	* @arg @ref LL_GPIO_PIN_8
		670	* @arg @ref LL_GPIO_PIN_9
		671	* @arg @ref LL_GPIO_PIN_10
		672	* @arg @ref LL_GPIO_PIN_11
		673	* @arg @ref LL_GPIO_PIN_12
		674	* @arg @ref LL_GPIO_PIN_13
		675	* @arg @ref LL_GPIO_PIN_14
		676	* @arg @ref LL_GPIO_PIN_15
		677	* @arg @ref LL_GPIO_PIN_ALL
		678	* @retval State of bit (1 or 0).
		679	*/
		680	__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
		681	{
		682	return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
		683	}
		684
		685	/**
		686	* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
		687	* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
		688	* @param GPIOx GPIO Port
		689	* @retval State of bit (1 or 0).
		690	*/
		691	__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
		692	{
		693	return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
		694	}
		695
		696	/**
		697	* @}
		698	*/
		699
		700	/** @defgroup GPIO_LL_EF_Data_Access Data Access
		701	* @{
		702	*/
		703
		704	/**
		705	* @brief Return full input data register value for a dedicated port.
		706	* @rmtoll IDR IDy LL_GPIO_ReadInputPort
		707	* @param GPIOx GPIO Port
		708	* @retval Input data register value of port
		709	*/
		710	__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
		711	{
		712	return (READ_REG(GPIOx->IDR));
		713	}
		714
		715	/**
		716	* @brief Return if input data level for several pins of dedicated port is high or low.
		717	* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
		718	* @param GPIOx GPIO Port
		719	* @param PinMask This parameter can be a combination of the following values:
		720	* @arg @ref LL_GPIO_PIN_0
		721	* @arg @ref LL_GPIO_PIN_1
		722	* @arg @ref LL_GPIO_PIN_2
		723	* @arg @ref LL_GPIO_PIN_3
		724	* @arg @ref LL_GPIO_PIN_4
		725	* @arg @ref LL_GPIO_PIN_5
		726	* @arg @ref LL_GPIO_PIN_6
		727	* @arg @ref LL_GPIO_PIN_7
		728	* @arg @ref LL_GPIO_PIN_8
		729	* @arg @ref LL_GPIO_PIN_9
		730	* @arg @ref LL_GPIO_PIN_10
		731	* @arg @ref LL_GPIO_PIN_11
		732	* @arg @ref LL_GPIO_PIN_12
		733	* @arg @ref LL_GPIO_PIN_13
		734	* @arg @ref LL_GPIO_PIN_14
		735	* @arg @ref LL_GPIO_PIN_15
		736	* @arg @ref LL_GPIO_PIN_ALL
		737	* @retval State of bit (1 or 0).
		738	*/
		739	__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
		740	{
		741	return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
		742	}
		743
		744	/**
		745	* @brief Write output data register for the port.
		746	* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
		747	* @param GPIOx GPIO Port
		748	* @param PortValue Level value for each pin of the port
		749	* @retval None
		750	*/
		751	__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
		752	{
		753	WRITE_REG(GPIOx->ODR, PortValue);
		754	}
		755
		756	/**
		757	* @brief Return full output data register value for a dedicated port.
		758	* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
		759	* @param GPIOx GPIO Port
		760	* @retval Output data register value of port
		761	*/
		762	__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
		763	{
		764	return (uint32_t)(READ_REG(GPIOx->ODR));
		765	}
		766
		767	/**
		768	* @brief Return if input data level for several pins of dedicated port is high or low.
		769	* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
		770	* @param GPIOx GPIO Port
		771	* @param PinMask This parameter can be a combination of the following values:
		772	* @arg @ref LL_GPIO_PIN_0
		773	* @arg @ref LL_GPIO_PIN_1
		774	* @arg @ref LL_GPIO_PIN_2
		775	* @arg @ref LL_GPIO_PIN_3
		776	* @arg @ref LL_GPIO_PIN_4
		777	* @arg @ref LL_GPIO_PIN_5
		778	* @arg @ref LL_GPIO_PIN_6
		779	* @arg @ref LL_GPIO_PIN_7
		780	* @arg @ref LL_GPIO_PIN_8
		781	* @arg @ref LL_GPIO_PIN_9
		782	* @arg @ref LL_GPIO_PIN_10
		783	* @arg @ref LL_GPIO_PIN_11
		784	* @arg @ref LL_GPIO_PIN_12
		785	* @arg @ref LL_GPIO_PIN_13
		786	* @arg @ref LL_GPIO_PIN_14
		787	* @arg @ref LL_GPIO_PIN_15
		788	* @arg @ref LL_GPIO_PIN_ALL
		789	* @retval State of bit (1 or 0).
		790	*/
		791	__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
		792	{
		793	return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
		794	}
		795
		796	/**
		797	* @brief Set several pins to high level on dedicated gpio port.
		798	* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
		799	* @param GPIOx GPIO Port
		800	* @param PinMask This parameter can be a combination of the following values:
		801	* @arg @ref LL_GPIO_PIN_0
		802	* @arg @ref LL_GPIO_PIN_1
		803	* @arg @ref LL_GPIO_PIN_2
		804	* @arg @ref LL_GPIO_PIN_3
		805	* @arg @ref LL_GPIO_PIN_4
		806	* @arg @ref LL_GPIO_PIN_5
		807	* @arg @ref LL_GPIO_PIN_6
		808	* @arg @ref LL_GPIO_PIN_7
		809	* @arg @ref LL_GPIO_PIN_8
		810	* @arg @ref LL_GPIO_PIN_9
		811	* @arg @ref LL_GPIO_PIN_10
		812	* @arg @ref LL_GPIO_PIN_11
		813	* @arg @ref LL_GPIO_PIN_12
		814	* @arg @ref LL_GPIO_PIN_13
		815	* @arg @ref LL_GPIO_PIN_14
		816	* @arg @ref LL_GPIO_PIN_15
		817	* @arg @ref LL_GPIO_PIN_ALL
		818	* @retval None
		819	*/
		820	__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
		821	{
		822	WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
		823	}
		824
		825	/**
		826	* @brief Set several pins to low level on dedicated gpio port.
		827	* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
		828	* @param GPIOx GPIO Port
		829	* @param PinMask This parameter can be a combination of the following values:
		830	* @arg @ref LL_GPIO_PIN_0
		831	* @arg @ref LL_GPIO_PIN_1
		832	* @arg @ref LL_GPIO_PIN_2
		833	* @arg @ref LL_GPIO_PIN_3
		834	* @arg @ref LL_GPIO_PIN_4
		835	* @arg @ref LL_GPIO_PIN_5
		836	* @arg @ref LL_GPIO_PIN_6
		837	* @arg @ref LL_GPIO_PIN_7
		838	* @arg @ref LL_GPIO_PIN_8
		839	* @arg @ref LL_GPIO_PIN_9
		840	* @arg @ref LL_GPIO_PIN_10
		841	* @arg @ref LL_GPIO_PIN_11
		842	* @arg @ref LL_GPIO_PIN_12
		843	* @arg @ref LL_GPIO_PIN_13
		844	* @arg @ref LL_GPIO_PIN_14
		845	* @arg @ref LL_GPIO_PIN_15
		846	* @arg @ref LL_GPIO_PIN_ALL
		847	* @retval None
		848	*/
		849	__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
		850	{
		851	WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
		852	}
		853
		854	/**
		855	* @brief Toggle data value for several pin of dedicated port.
		856	* @rmtoll ODR ODy LL_GPIO_TogglePin
		857	* @param GPIOx GPIO Port
		858	* @param PinMask This parameter can be a combination of the following values:
		859	* @arg @ref LL_GPIO_PIN_0
		860	* @arg @ref LL_GPIO_PIN_1
		861	* @arg @ref LL_GPIO_PIN_2
		862	* @arg @ref LL_GPIO_PIN_3
		863	* @arg @ref LL_GPIO_PIN_4
		864	* @arg @ref LL_GPIO_PIN_5
		865	* @arg @ref LL_GPIO_PIN_6
		866	* @arg @ref LL_GPIO_PIN_7
		867	* @arg @ref LL_GPIO_PIN_8
		868	* @arg @ref LL_GPIO_PIN_9
		869	* @arg @ref LL_GPIO_PIN_10
		870	* @arg @ref LL_GPIO_PIN_11
		871	* @arg @ref LL_GPIO_PIN_12
		872	* @arg @ref LL_GPIO_PIN_13
		873	* @arg @ref LL_GPIO_PIN_14
		874	* @arg @ref LL_GPIO_PIN_15
		875	* @arg @ref LL_GPIO_PIN_ALL
		876	* @retval None
		877	*/
		878	__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
		879	{
		880	WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
		881	}
		882
		883	/**
		884	* @}
		885	*/
		886
		887	/** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
		888	* @brief This section propose definition to remap the alternate function to some other port/pins.
		889	* @{
		890	*/
		891
		892	/**
		893	* @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
		894	* @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
		895	* @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
		896	* @retval None
		897	*/
		898	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
		899	{
		900	SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
		901	}
		902
		903	/**
		904	* @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
		905	* @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
		906	* @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
		907	* @retval None
		908	*/
		909	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
		910	{
		911	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
		912	}
		913
		914	/**
		915	* @brief Check if SPI1 has been remaped or not
		916	* @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
		917	* @retval State of bit (1 or 0).
		918	*/
		919	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
		920	{
		921	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
		922	}
		923
		924	/**
		925	* @brief Enable the remapping of I2C1 alternate function SCL and SDA.
		926	* @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
		927	* @note ENABLE: Remap (SCL/PB8, SDA/PB9)
		928	* @retval None
		929	*/
		930	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
		931	{
		932	SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
		933	}
		934
		935	/**
		936	* @brief Disable the remapping of I2C1 alternate function SCL and SDA.
		937	* @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
		938	* @note DISABLE: No remap (SCL/PB6, SDA/PB7)
		939	* @retval None
		940	*/
		941	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
		942	{
		943	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
		944	}
		945
		946	/**
		947	* @brief Check if I2C1 has been remaped or not
		948	* @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
		949	* @retval State of bit (1 or 0).
		950	*/
		951	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
		952	{
		953	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
		954	}
		955
		956	/**
		957	* @brief Enable the remapping of USART1 alternate function TX and RX.
		958	* @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
		959	* @note ENABLE: Remap (TX/PB6, RX/PB7)
		960	* @retval None
		961	*/
		962	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
		963	{
		964	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
		965	}
		966
		967	/**
		968	* @brief Disable the remapping of USART1 alternate function TX and RX.
		969	* @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
		970	* @note DISABLE: No remap (TX/PA9, RX/PA10)
		971	* @retval None
		972	*/
		973	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
		974	{
		975	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
		976	}
		977
		978	/**
		979	* @brief Check if USART1 has been remaped or not
		980	* @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
		981	* @retval State of bit (1 or 0).
		982	*/
		983	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
		984	{
		985	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
		986	}
		987
		988	/**
		989	* @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
		990	* @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
		991	* @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
		992	* @retval None
		993	*/
		994	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
		995	{
		996	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
		997	}
		998
		999	/**
		1000	* @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
		1001	* @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
		1002	* @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
		1003	* @retval None
		1004	*/
		1005	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
		1006	{
		1007	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
		1008	}
		1009
		1010	/**
		1011	* @brief Check if USART2 has been remaped or not
		1012	* @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
		1013	* @retval State of bit (1 or 0).
		1014	*/
		1015	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
		1016	{
		1017	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
		1018	}
		1019
		1020	#if defined (AFIO_MAPR_USART3_REMAP)
		1021	/**
		1022	* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
		1023	* @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
		1024	* @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
		1025	* @retval None
		1026	*/
		1027	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
		1028	{
		1029	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
		1030	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);
		1031	}
		1032
		1033	/**
		1034	* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
		1035	* @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
		1036	* @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
		1037	* @retval None
		1038	*/
		1039	__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
		1040	{
		1041	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
		1042	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
		1043	}
		1044
		1045	/**
		1046	* @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
		1047	* @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
		1048	* @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
		1049	* @retval None
		1050	*/
		1051	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
		1052	{
		1053	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
		1054	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP);
		1055	}
		1056	#endif
		1057
		1058	/**
		1059	* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
		1060	* @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
		1061	* @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
		1062	* @retval None
		1063	*/
		1064	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
		1065	{
		1066	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
		1067	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP);
		1068	}
		1069
		1070	/**
		1071	* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
		1072	* @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
		1073	* @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
		1074	* @retval None
		1075	*/
		1076	__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
		1077	{
		1078	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
		1079	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
		1080	}
		1081
		1082	/**
		1083	* @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
		1084	* @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
		1085	* @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
		1086	* @retval None
		1087	*/
		1088	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
		1089	{
		1090	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
		1091	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP);
		1092	}
		1093
		1094	/**
		1095	* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
		1096	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
		1097	* @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
		1098	* @retval None
		1099	*/
		1100	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
		1101	{
		1102	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
		1103	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP);
		1104	}
		1105
		1106	/**
		1107	* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
		1108	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
		1109	* @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
		1110	* @retval None
		1111	*/
		1112	__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
		1113	{
		1114	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
		1115	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
		1116	}
		1117
		1118	/**
		1119	* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
		1120	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
		1121	* @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
		1122	* @retval None
		1123	*/
		1124	__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
		1125	{
		1126	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
		1127	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
		1128	}
		1129
		1130	/**
		1131	* @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
		1132	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
		1133	* @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
		1134	* @retval None
		1135	*/
		1136	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
		1137	{
		1138	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
		1139	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);
		1140	}
		1141
		1142	/**
		1143	* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
		1144	* @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
		1145	* @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
		1146	* @note TIM3_ETR on PE0 is not re-mapped.
		1147	* @retval None
		1148	*/
		1149	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
		1150	{
		1151	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
		1152	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP);
		1153	}
		1154
		1155	/**
		1156	* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
		1157	* @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
		1158	* @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
		1159	* @note TIM3_ETR on PE0 is not re-mapped.
		1160	* @retval None
		1161	*/
		1162	__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
		1163	{
		1164	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
		1165	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
		1166	}
		1167
		1168	/**
		1169	* @brief Disable the remapping of TIM3 alternate function channels 1 to 4
		1170	* @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
		1171	* @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
		1172	* @note TIM3_ETR on PE0 is not re-mapped.
		1173	* @retval None
		1174	*/
		1175	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
		1176	{
		1177	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
		1178	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);
		1179	}
		1180
		1181	#if defined(AFIO_MAPR_TIM4_REMAP)
		1182	/**
		1183	* @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
		1184	* @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
		1185	* @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
		1186	* @note TIM4_ETR on PE0 is not re-mapped.
		1187	* @retval None
		1188	*/
		1189	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
		1190	{
		1191	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
		1192	}
		1193	/**
		1194	* @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
		1195	* @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
		1196	* @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
		1197	* @note TIM4_ETR on PE0 is not re-mapped.
		1198	* @retval None
		1199	*/
		1200	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
		1201	{
		1202	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
		1203	}
		1204
		1205	/**
		1206	* @brief Check if TIM4 has been remaped or not
		1207	* @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
		1208	* @retval State of bit (1 or 0).
		1209	*/
		1210	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
		1211	{
		1212	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
		1213	}
		1214	#endif
		1215
		1216	#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
		1217
		1218	/**
		1219	* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
		1220	* @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
		1221	* @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
		1222	* @retval None
		1223	*/
		1224	__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
		1225	{
		1226	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
		1227	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);
		1228	}
		1229
		1230	/**
		1231	* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
		1232	* @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
		1233	* @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
		1234	* @retval None
		1235	*/
		1236	__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
		1237	{
		1238	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
		1239	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);
		1240	}
		1241
		1242	/**
		1243	* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
		1244	* @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
		1245	* @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
		1246	* @retval None
		1247	*/
		1248	__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
		1249	{
		1250	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
		1251	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);
		1252	}
		1253	#endif
		1254
		1255	/**
		1256	* @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
		1257	* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
		1258	* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
		1259	* on 100-pin and 144-pin packages, no need for remapping).
		1260	* @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
		1261	* @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
		1262	* @retval None
		1263	*/
		1264	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
		1265	{
		1266	SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
		1267	}
		1268
		1269	/**
		1270	* @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
		1271	* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
		1272	* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
		1273	* on 100-pin and 144-pin packages, no need for remapping).
		1274	* @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
		1275	* @note DISABLE: No remapping of PD0 and PD1
		1276	* @retval None
		1277	*/
		1278	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
		1279	{
		1280	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
		1281	}
		1282
		1283	/**
		1284	* @brief Check if PD01 has been remaped or not
		1285	* @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
		1286	* @retval State of bit (1 or 0).
		1287	*/
		1288	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
		1289	{
		1290	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
		1291	}
		1292
		1293	#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
		1294	/**
		1295	* @brief Enable the remapping of TIM5CH4.
		1296	* @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
		1297	* @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
		1298	* @note This function is available only in high density value line devices.
		1299	* @retval None
		1300	*/
		1301	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
		1302	{
		1303	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
		1304	}
		1305
		1306	/**
		1307	* @brief Disable the remapping of TIM5CH4.
		1308	* @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
		1309	* @note DISABLE: TIM5_CH4 is connected to PA3
		1310	* @note This function is available only in high density value line devices.
		1311	* @retval None
		1312	*/
		1313	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
		1314	{
		1315	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
		1316	}
		1317
		1318	/**
		1319	* @brief Check if TIM5CH4 has been remaped or not
		1320	* @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
		1321	* @retval State of bit (1 or 0).
		1322	*/
		1323	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
		1324	{
		1325	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
		1326	}
		1327	#endif
		1328
		1329	#if defined(AFIO_MAPR_ETH_REMAP)
		1330	/**
		1331	* @brief Enable the remapping of Ethernet MAC connections with the PHY.
		1332	* @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
		1333	* @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
		1334	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1335	* @retval None
		1336	*/
		1337	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
		1338	{
		1339	SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
		1340	}
		1341
		1342	/**
		1343	* @brief Disable the remapping of Ethernet MAC connections with the PHY.
		1344	* @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
		1345	* @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
		1346	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1347	* @retval None
		1348	*/
		1349	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
		1350	{
		1351	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
		1352	}
		1353
		1354	/**
		1355	* @brief Check if ETH has been remaped or not
		1356	* @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
		1357	* @retval State of bit (1 or 0).
		1358	*/
		1359	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
		1360	{
		1361	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
		1362	}
		1363	#endif
		1364
		1365	#if defined(AFIO_MAPR_CAN2_REMAP)
		1366
		1367	/**
		1368	* @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
		1369	* @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
		1370	* @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
		1371	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1372	* @retval None
		1373	*/
		1374	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
		1375	{
		1376	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
		1377	}
		1378	/**
		1379	* @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
		1380	* @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
		1381	* @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
		1382	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1383	* @retval None
		1384	*/
		1385	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
		1386	{
		1387	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
		1388	}
		1389
		1390	/**
		1391	* @brief Check if CAN2 has been remaped or not
		1392	* @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
		1393	* @retval State of bit (1 or 0).
		1394	*/
		1395	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
		1396	{
		1397	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
		1398	}
		1399	#endif
		1400
		1401	#if defined(AFIO_MAPR_MII_RMII_SEL)
		1402	/**
		1403	* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
		1404	* @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
		1405	* @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
		1406	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1407	* @retval None
		1408	*/
		1409	__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
		1410	{
		1411	SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
		1412	}
		1413
		1414	/**
		1415	* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
		1416	* @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
		1417	* @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
		1418	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1419	* @retval None
		1420	*/
		1421	__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
		1422	{
		1423	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
		1424	}
		1425	#endif
		1426
		1427	#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
		1428	/**
		1429	* @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
		1430	* @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
		1431	* @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
		1432	* @retval None
		1433	*/
		1434	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
		1435	{
		1436	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
		1437	}
		1438
		1439	/**
		1440	* @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
		1441	* @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
		1442	* @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
		1443	* @retval None
		1444	*/
		1445	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
		1446	{
		1447	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
		1448	}
		1449
		1450	/**
		1451	* @brief Check if ADC1_ETRGINJ has been remaped or not
		1452	* @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
		1453	* @retval State of bit (1 or 0).
		1454	*/
		1455	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
		1456	{
		1457	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
		1458	}
		1459	#endif
		1460
		1461	#if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
		1462	/**
		1463	* @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
		1464	* @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
		1465	* @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
		1466	* @retval None
		1467	*/
		1468	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
		1469	{
		1470	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
		1471	}
		1472
		1473	/**
		1474	* @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
		1475	* @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
		1476	* @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
		1477	* @retval None
		1478	*/
		1479	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
		1480	{
		1481	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
		1482	}
		1483
		1484	/**
		1485	* @brief Check if ADC1_ETRGREG has been remaped or not
		1486	* @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
		1487	* @retval State of bit (1 or 0).
		1488	*/
		1489	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
		1490	{
		1491	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
		1492	}
		1493	#endif
		1494
		1495	#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
		1496
		1497	/**
		1498	* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
		1499	* @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
		1500	* @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
		1501	* @retval None
		1502	*/
		1503	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
		1504	{
		1505	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
		1506	}
		1507
		1508	/**
		1509	* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
		1510	* @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
		1511	* @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
		1512	* @retval None
		1513	*/
		1514	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
		1515	{
		1516	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
		1517	}
		1518
		1519	/**
		1520	* @brief Check if ADC2_ETRGINJ has been remaped or not
		1521	* @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
		1522	* @retval State of bit (1 or 0).
		1523	*/
		1524	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
		1525	{
		1526	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
		1527	}
		1528	#endif
		1529
		1530	#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
		1531
		1532	/**
		1533	* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
		1534	* @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
		1535	* @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
		1536	* @retval None
		1537	*/
		1538	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
		1539	{
		1540	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
		1541	}
		1542
		1543	/**
		1544	* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
		1545	* @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
		1546	* @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
		1547	* @retval None
		1548	*/
		1549	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
		1550	{
		1551	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
		1552	}
		1553
		1554	/**
		1555	* @brief Check if ADC2_ETRGREG has been remaped or not
		1556	* @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
		1557	* @retval State of bit (1 or 0).
		1558	*/
		1559	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
		1560	{
		1561	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
		1562	}
		1563	#endif
		1564
		1565	/**
		1566	* @brief Enable the Serial wire JTAG configuration
		1567	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
		1568	* @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
		1569	* @retval None
		1570	*/
		1571	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
		1572	{
		1573	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
		1574	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
		1575	}
		1576
		1577	/**
		1578	* @brief Enable the Serial wire JTAG configuration
		1579	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
		1580	* @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
		1581	* @retval None
		1582	*/
		1583	__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
		1584	{
		1585	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
		1586	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
		1587	}
		1588
		1589	/**
		1590	* @brief Enable the Serial wire JTAG configuration
		1591	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
		1592	* @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
		1593	* @retval None
		1594	*/
		1595	__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
		1596	{
		1597	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
		1598	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
		1599	}
		1600
		1601	/**
		1602	* @brief Disable the Serial wire JTAG configuration
		1603	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
		1604	* @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
		1605	* @retval None
		1606	*/
		1607	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
		1608	{
		1609	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
		1610	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
		1611	}
		1612
		1613	#if defined(AFIO_MAPR_SPI3_REMAP)
		1614
		1615	/**
		1616	* @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
		1617	* @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
		1618	* @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
		1619	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1620	* @retval None
		1621	*/
		1622	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
		1623	{
		1624	SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
		1625	}
		1626
		1627	/**
		1628	* @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
		1629	* @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
		1630	* @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
		1631	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1632	* @retval None
		1633	*/
		1634	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
		1635	{
		1636	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
		1637	}
		1638
		1639	/**
		1640	* @brief Check if SPI3 has been remaped or not
		1641	* @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
		1642	* @retval State of bit (1 or 0).
		1643	*/
		1644	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
		1645	{
		1646	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
		1647	}
		1648	#endif
		1649
		1650	#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
		1651
		1652	/**
		1653	* @brief Control of TIM2_ITR1 internal mapping.
		1654	* @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
		1655	* @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
		1656	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1657	* @retval None
		1658	*/
		1659	__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
		1660	{
		1661	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
		1662	}
		1663
		1664	/**
		1665	* @brief Control of TIM2_ITR1 internal mapping.
		1666	* @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
		1667	* @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
		1668	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1669	* @retval None
		1670	*/
		1671	__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
		1672	{
		1673	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
		1674	}
		1675	#endif
		1676
		1677	#if defined(AFIO_MAPR_PTP_PPS_REMAP)
		1678
		1679	/**
		1680	* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
		1681	* @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
		1682	* @note ENABLE: PTP_PPS is output on PB5 pin.
		1683	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1684	* @retval None
		1685	*/
		1686	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
		1687	{
		1688	SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
		1689	}
		1690
		1691	/**
		1692	* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
		1693	* @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
		1694	* @note DISABLE: PTP_PPS not output on PB5 pin.
		1695	* @note This bit is available only in connectivity line devices and is reserved otherwise.
		1696	* @retval None
		1697	*/
		1698	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
		1699	{
		1700	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
		1701	}
		1702	#endif
		1703
		1704	#if defined(AFIO_MAPR2_TIM9_REMAP)
		1705
		1706	/**
		1707	* @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
		1708	* @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
		1709	* @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
		1710	* @retval None
		1711	*/
		1712	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
		1713	{
		1714	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
		1715	}
		1716
		1717	/**
		1718	* @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
		1719	* @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
		1720	* @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
		1721	* @retval None
		1722	*/
		1723	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
		1724	{
		1725	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
		1726	}
		1727
		1728	/**
		1729	* @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
		1730	* @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
		1731	* @retval State of bit (1 or 0).
		1732	*/
		1733	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
		1734	{
		1735	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
		1736	}
		1737	#endif
		1738
		1739	#if defined(AFIO_MAPR2_TIM10_REMAP)
		1740
		1741	/**
		1742	* @brief Enable the remapping of TIM10_CH1.
		1743	* @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
		1744	* @note ENABLE: Remap (TIM10_CH1 on PF6).
		1745	* @retval None
		1746	*/
		1747	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
		1748	{
		1749	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
		1750	}
		1751
		1752	/**
		1753	* @brief Disable the remapping of TIM10_CH1.
		1754	* @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
		1755	* @note DISABLE: No remap (TIM10_CH1 on PB8).
		1756	* @retval None
		1757	*/
		1758	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
		1759	{
		1760	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
		1761	}
		1762
		1763	/**
		1764	* @brief Check if TIM10_CH1 has been remaped or not
		1765	* @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
		1766	* @retval State of bit (1 or 0).
		1767	*/
		1768	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
		1769	{
		1770	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
		1771	}
		1772	#endif
		1773
		1774	#if defined(AFIO_MAPR2_TIM11_REMAP)
		1775	/**
		1776	* @brief Enable the remapping of TIM11_CH1.
		1777	* @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
		1778	* @note ENABLE: Remap (TIM11_CH1 on PF7).
		1779	* @retval None
		1780	*/
		1781	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
		1782	{
		1783	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
		1784	}
		1785
		1786	/**
		1787	* @brief Disable the remapping of TIM11_CH1.
		1788	* @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
		1789	* @note DISABLE: No remap (TIM11_CH1 on PB9).
		1790	* @retval None
		1791	*/
		1792	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
		1793	{
		1794	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
		1795	}
		1796
		1797	/**
		1798	* @brief Check if TIM11_CH1 has been remaped or not
		1799	* @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
		1800	* @retval State of bit (1 or 0).
		1801	*/
		1802	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
		1803	{
		1804	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
		1805	}
		1806	#endif
		1807
		1808	#if defined(AFIO_MAPR2_TIM13_REMAP)
		1809
		1810	/**
		1811	* @brief Enable the remapping of TIM13_CH1.
		1812	* @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
		1813	* @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
		1814	* @retval None
		1815	*/
		1816	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
		1817	{
		1818	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
		1819	}
		1820
		1821	/**
		1822	* @brief Disable the remapping of TIM13_CH1.
		1823	* @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
		1824	* @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
		1825	* @retval None
		1826	*/
		1827	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
		1828	{
		1829	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
		1830	}
		1831
		1832	/**
		1833	* @brief Check if TIM13_CH1 has been remaped or not
		1834	* @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
		1835	* @retval State of bit (1 or 0).
		1836	*/
		1837	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
		1838	{
		1839	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
		1840	}
		1841	#endif
		1842
		1843	#if defined(AFIO_MAPR2_TIM14_REMAP)
		1844
		1845	/**
		1846	* @brief Enable the remapping of TIM14_CH1.
		1847	* @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
		1848	* @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
		1849	* @retval None
		1850	*/
		1851	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
		1852	{
		1853	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
		1854	}
		1855
		1856	/**
		1857	* @brief Disable the remapping of TIM14_CH1.
		1858	* @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
		1859	* @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
		1860	* @retval None
		1861	*/
		1862	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
		1863	{
		1864	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
		1865	}
		1866
		1867	/**
		1868	* @brief Check if TIM14_CH1 has been remaped or not
		1869	* @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
		1870	* @retval State of bit (1 or 0).
		1871	*/
		1872	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
		1873	{
		1874	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
		1875	}
		1876	#endif
		1877
		1878	#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
		1879
		1880	/**
		1881	* @brief Controls the use of the optional FSMC_NADV signal.
		1882	* @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
		1883	* @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
		1884	* @retval None
		1885	*/
		1886	__STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
		1887	{
		1888	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
		1889	}
		1890
		1891	/**
		1892	* @brief Controls the use of the optional FSMC_NADV signal.
		1893	* @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
		1894	* @note CONNECTED: The NADV signal is connected to the output (default).
		1895	* @retval None
		1896	*/
		1897	__STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
		1898	{
		1899	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
		1900	}
		1901	#endif
		1902
		1903	#if defined(AFIO_MAPR2_TIM15_REMAP)
		1904
		1905	/**
		1906	* @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
		1907	* @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
		1908	* @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
		1909	* @retval None
		1910	*/
		1911	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
		1912	{
		1913	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
		1914	}
		1915	/**
		1916	* @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
		1917	* @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
		1918	* @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
		1919	* @retval None
		1920	*/
		1921	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
		1922	{
		1923	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
		1924	}
		1925
		1926	/**
		1927	* @brief Check if TIM15_CH1 has been remaped or not
		1928	* @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
		1929	* @retval State of bit (1 or 0).
		1930	*/
		1931	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
		1932	{
		1933	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
		1934	}
		1935	#endif
		1936
		1937	#if defined(AFIO_MAPR2_TIM16_REMAP)
		1938
		1939	/**
		1940	* @brief Enable the remapping of TIM16_CH1.
		1941	* @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
		1942	* @note ENABLE: Remap (TIM16_CH1 on PA6).
		1943	* @retval None
		1944	*/
		1945	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
		1946	{
		1947	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
		1948	}
		1949
		1950	/**
		1951	* @brief Disable the remapping of TIM16_CH1.
		1952	* @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
		1953	* @note DISABLE: No remap (TIM16_CH1 on PB8).
		1954	* @retval None
		1955	*/
		1956	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
		1957	{
		1958	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
		1959	}
		1960
		1961	/**
		1962	* @brief Check if TIM16_CH1 has been remaped or not
		1963	* @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
		1964	* @retval State of bit (1 or 0).
		1965	*/
		1966	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
		1967	{
		1968	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
		1969	}
		1970	#endif
		1971
		1972	#if defined(AFIO_MAPR2_TIM17_REMAP)
		1973
		1974	/**
		1975	* @brief Enable the remapping of TIM17_CH1.
		1976	* @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
		1977	* @note ENABLE: Remap (TIM17_CH1 on PA7).
		1978	* @retval None
		1979	*/
		1980	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
		1981	{
		1982	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
		1983	}
		1984
		1985	/**
		1986	* @brief Disable the remapping of TIM17_CH1.
		1987	* @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
		1988	* @note DISABLE: No remap (TIM17_CH1 on PB9).
		1989	* @retval None
		1990	*/
		1991	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
		1992	{
		1993	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
		1994	}
		1995
		1996	/**
		1997	* @brief Check if TIM17_CH1 has been remaped or not
		1998	* @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
		1999	* @retval State of bit (1 or 0).
		2000	*/
		2001	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
		2002	{
		2003	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
		2004	}
		2005	#endif
		2006
		2007	#if defined(AFIO_MAPR2_CEC_REMAP)
		2008
		2009	/**
		2010	* @brief Enable the remapping of CEC.
		2011	* @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
		2012	* @note ENABLE: Remap (CEC on PB10).
		2013	* @retval None
		2014	*/
		2015	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
		2016	{
		2017	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
		2018	}
		2019
		2020	/**
		2021	* @brief Disable the remapping of CEC.
		2022	* @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
		2023	* @note DISABLE: No remap (CEC on PB8).
		2024	* @retval None
		2025	*/
		2026	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
		2027	{
		2028	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
		2029	}
		2030
		2031	/**
		2032	* @brief Check if CEC has been remaped or not
		2033	* @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
		2034	* @retval State of bit (1 or 0).
		2035	*/
		2036	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
		2037	{
		2038	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
		2039	}
		2040	#endif
		2041
		2042	#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
		2043
		2044	/**
		2045	* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
		2046	* @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
		2047	* @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
		2048	* @retval None
		2049	*/
		2050	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
		2051	{
		2052	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
		2053	}
		2054
		2055	/**
		2056	* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
		2057	* @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
		2058	* @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
		2059	* @retval None
		2060	*/
		2061	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
		2062	{
		2063	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
		2064	}
		2065
		2066	/**
		2067	* @brief Check if TIM1DMA has been remaped or not
		2068	* @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
		2069	* @retval State of bit (1 or 0).
		2070	*/
		2071	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
		2072	{
		2073	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
		2074	}
		2075	#endif
		2076
		2077	#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
		2078
		2079	/**
		2080	* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
		2081	* @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
		2082	* @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
		2083	* @retval None
		2084	*/
		2085	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
		2086	{
		2087	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
		2088	}
		2089
		2090	/**
		2091	* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
		2092	* @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
		2093	* @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
		2094	* @retval None
		2095	*/
		2096	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
		2097	{
		2098	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
		2099	}
		2100
		2101	/**
		2102	* @brief Check if TIM67DACDMA has been remaped or not
		2103	* @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
		2104	* @retval State of bit (1 or 0).
		2105	*/
		2106	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
		2107	{
		2108	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
		2109	}
		2110	#endif
		2111
		2112	#if defined(AFIO_MAPR2_TIM12_REMAP)
		2113
		2114	/**
		2115	* @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
		2116	* @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
		2117	* @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
		2118	* @note This bit is available only in high density value line devices.
		2119	* @retval None
		2120	*/
		2121	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
		2122	{
		2123	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
		2124	}
		2125
		2126	/**
		2127	* @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
		2128	* @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
		2129	* @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
		2130	* @note This bit is available only in high density value line devices.
		2131	* @retval None
		2132	*/
		2133	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
		2134	{
		2135	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
		2136	}
		2137
		2138	/**
		2139	* @brief Check if TIM12_CH1 has been remaped or not
		2140	* @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
		2141	* @retval State of bit (1 or 0).
		2142	*/
		2143	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
		2144	{
		2145	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
		2146	}
		2147	#endif
		2148
		2149	#if defined(AFIO_MAPR2_MISC_REMAP)
		2150
		2151	/**
		2152	* @brief Miscellaneous features remapping.
		2153	* This bit is set and cleared by software. It controls miscellaneous features.
		2154	* The DMA2 channel 5 interrupt position in the vector table.
		2155	* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
		2156	* @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
		2157	* @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
		2158	* selected as DAC Trigger 3, TIM15 triggers TIM1/3.
		2159	* @note This bit is available only in high density value line devices.
		2160	* @retval None
		2161	*/
		2162	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
		2163	{
		2164	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
		2165	}
		2166
		2167	/**
		2168	* @brief Miscellaneous features remapping.
		2169	* This bit is set and cleared by software. It controls miscellaneous features.
		2170	* The DMA2 channel 5 interrupt position in the vector table.
		2171	* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
		2172	* @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
		2173	* @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
		2174	* event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
		2175	* @note This bit is available only in high density value line devices.
		2176	* @retval None
		2177	*/
		2178	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
		2179	{
		2180	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
		2181	}
		2182
		2183	/**
		2184	* @brief Check if MISC has been remaped or not
		2185	* @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
		2186	* @retval State of bit (1 or 0).
		2187	*/
		2188	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
		2189	{
		2190	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
		2191	}
		2192	#endif
		2193
		2194	/**
		2195	* @}
		2196	*/
		2197
		2198	/** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
		2199	* @brief This section propose definition to Configure EVENTOUT Cortex feature .
		2200	* @{
		2201	*/
		2202
		2203	/**
		2204	* @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
		2205	* @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
		2206	* EVCR PIN LL_GPIO_AF_ConfigEventout
		2207	* @param LL_GPIO_PortSource This parameter can be one of the following values:
		2208	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
		2209	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
		2210	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
		2211	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
		2212	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
		2213	* @param LL_GPIO_PinSource This parameter can be one of the following values:
		2214	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
		2215	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
		2216	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
		2217	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
		2218	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
		2219	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
		2220	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
		2221	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
		2222	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
		2223	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
		2224	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
		2225	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
		2226	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
		2227	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
		2228	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
		2229	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
		2230	* @retval None
		2231	*/
		2232	__STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
		2233	{
		2234	MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) \| (AFIO_EVCR_PIN), (LL_GPIO_PortSource) \| (LL_GPIO_PinSource));
		2235	}
		2236
		2237	/**
		2238	* @brief Enables the Event Output.
		2239	* @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
		2240	* @retval None
		2241	*/
		2242	__STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
		2243	{
		2244	SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
		2245	}
		2246
		2247	/**
		2248	* @brief Disables the Event Output.
		2249	* @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
		2250	* @retval None
		2251	*/
		2252	__STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
		2253	{
		2254	CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
		2255	}
		2256
		2257	/**
		2258	* @}
		2259	*/
		2260	/** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
		2261	* @brief This section Configure source input for the EXTI external interrupt .
		2262	* @{
		2263	*/
		2264
		2265	/**
		2266	* @brief Configure source input for the EXTI external interrupt.
		2267	* @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
		2268	* AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
		2269	* AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
		2270	* AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
		2271	* @param Port This parameter can be one of the following values:
		2272	* @arg @ref LL_GPIO_AF_EXTI_PORTA
		2273	* @arg @ref LL_GPIO_AF_EXTI_PORTB
		2274	* @arg @ref LL_GPIO_AF_EXTI_PORTC
		2275	* @arg @ref LL_GPIO_AF_EXTI_PORTD
		2276	* @arg @ref LL_GPIO_AF_EXTI_PORTE
		2277	* @arg @ref LL_GPIO_AF_EXTI_PORTF
		2278	* @arg @ref LL_GPIO_AF_EXTI_PORTG
		2279	* @param Line This parameter can be one of the following values:
		2280	* @arg @ref LL_GPIO_AF_EXTI_LINE0
		2281	* @arg @ref LL_GPIO_AF_EXTI_LINE1
		2282	* @arg @ref LL_GPIO_AF_EXTI_LINE2
		2283	* @arg @ref LL_GPIO_AF_EXTI_LINE3
		2284	* @arg @ref LL_GPIO_AF_EXTI_LINE4
		2285	* @arg @ref LL_GPIO_AF_EXTI_LINE5
		2286	* @arg @ref LL_GPIO_AF_EXTI_LINE6
		2287	* @arg @ref LL_GPIO_AF_EXTI_LINE7
		2288	* @arg @ref LL_GPIO_AF_EXTI_LINE8
		2289	* @arg @ref LL_GPIO_AF_EXTI_LINE9
		2290	* @arg @ref LL_GPIO_AF_EXTI_LINE10
		2291	* @arg @ref LL_GPIO_AF_EXTI_LINE11
		2292	* @arg @ref LL_GPIO_AF_EXTI_LINE12
		2293	* @arg @ref LL_GPIO_AF_EXTI_LINE13
		2294	* @arg @ref LL_GPIO_AF_EXTI_LINE14
		2295	* @arg @ref LL_GPIO_AF_EXTI_LINE15
		2296	* @retval None
		2297	*/
		2298	__STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
		2299	{
		2300	MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
		2301	}
		2302
		2303	/**
		2304	* @brief Get the configured defined for specific EXTI Line
		2305	* @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
		2306	* AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
		2307	* AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
		2308	* AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
		2309	* @param Line This parameter can be one of the following values:
		2310	* @arg @ref LL_GPIO_AF_EXTI_LINE0
		2311	* @arg @ref LL_GPIO_AF_EXTI_LINE1
		2312	* @arg @ref LL_GPIO_AF_EXTI_LINE2
		2313	* @arg @ref LL_GPIO_AF_EXTI_LINE3
		2314	* @arg @ref LL_GPIO_AF_EXTI_LINE4
		2315	* @arg @ref LL_GPIO_AF_EXTI_LINE5
		2316	* @arg @ref LL_GPIO_AF_EXTI_LINE6
		2317	* @arg @ref LL_GPIO_AF_EXTI_LINE7
		2318	* @arg @ref LL_GPIO_AF_EXTI_LINE8
		2319	* @arg @ref LL_GPIO_AF_EXTI_LINE9
		2320	* @arg @ref LL_GPIO_AF_EXTI_LINE10
		2321	* @arg @ref LL_GPIO_AF_EXTI_LINE11
		2322	* @arg @ref LL_GPIO_AF_EXTI_LINE12
		2323	* @arg @ref LL_GPIO_AF_EXTI_LINE13
		2324	* @arg @ref LL_GPIO_AF_EXTI_LINE14
		2325	* @arg @ref LL_GPIO_AF_EXTI_LINE15
		2326	* @retval Returned value can be one of the following values:
		2327	* @arg @ref LL_GPIO_AF_EXTI_PORTA
		2328	* @arg @ref LL_GPIO_AF_EXTI_PORTB
		2329	* @arg @ref LL_GPIO_AF_EXTI_PORTC
		2330	* @arg @ref LL_GPIO_AF_EXTI_PORTD
		2331	* @arg @ref LL_GPIO_AF_EXTI_PORTE
		2332	* @arg @ref LL_GPIO_AF_EXTI_PORTF
		2333	* @arg @ref LL_GPIO_AF_EXTI_PORTG
		2334	*/
		2335	__STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
		2336	{
		2337	return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
		2338	}
		2339
		2340	/**
		2341	* @}
		2342	*/
		2343
		2344	#if defined(USE_FULL_LL_DRIVER)
		2345	/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
		2346	* @{
		2347	*/
		2348
		2349	ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
		2350	ErrorStatus LL_GPIO_Init(GPIO_TypeDef GPIOx, LL_GPIO_InitTypeDef GPIO_InitStruct);
		2351	void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
		2352
		2353	/**
		2354	* @}
		2355	*/
		2356	#endif /* USE_FULL_LL_DRIVER */
		2357
		2358	/**
		2359	* @}
		2360	*/
		2361
		2362	/**
		2363	* @}
		2364	*/
		2365
		2366	#endif /* defined (GPIOA) \|\| defined (GPIOB) \|\| defined (GPIOC) \|\| defined (GPIOD) \|\| defined (GPIOE) \|\| defined (GPIOF) \|\| defined (GPIOG) */
		2367	/**
		2368	* @}
		2369	*/
		2370
		2371	#ifdef __cplusplus
		2372	}
		2373	#endif
		2374
		2375	#endif /* __STM32F1xx_LL_GPIO_H */
		2376
		2377	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h – Rev 2