WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_fsmc.h
		4	* @author MCD Application Team
		5	* @brief Header file of FSMC HAL module.
		6	******************************************************************************
		7	* @attention
		8	*
9	mjames	9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
2	mjames	11	*
9	mjames	12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
2	mjames	16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
9	mjames	21	#ifndef STM32F1xx_LL_FSMC_H
		22	#define STM32F1xx_LL_FSMC_H
2	mjames	23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f1xx_hal_def.h"
		30
		31	/** @addtogroup STM32F1xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup FSMC_LL
		36	* @{
		37	*/
		38
9	mjames	39	/** @addtogroup FSMC_LL_Private_Macros
		40	* @{
		41	*/
		42	#if defined FSMC_BANK1
2	mjames	43
9	mjames	44	#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) \|\| \
		45	((__BANK__) == FSMC_NORSRAM_BANK2) \|\| \
		46	((__BANK__) == FSMC_NORSRAM_BANK3) \|\| \
		47	((__BANK__) == FSMC_NORSRAM_BANK4))
		48	#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
		49	((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
		50	#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) \|\| \
		51	((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
		52	((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
		53	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
		54	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
		55	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
		56	#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) \|\| \
		57	((__SIZE__) == FSMC_PAGE_SIZE_128) \|\| \
		58	((__SIZE__) == FSMC_PAGE_SIZE_256) \|\| \
		59	((__SIZE__) == FSMC_PAGE_SIZE_512) \|\| \
		60	((__SIZE__) == FSMC_PAGE_SIZE_1024))
		61	#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) \|\| \
		62	((__MODE__) == FSMC_ACCESS_MODE_B) \|\| \
		63	((__MODE__) == FSMC_ACCESS_MODE_C) \|\| \
		64	((__MODE__) == FSMC_ACCESS_MODE_D))
		65	#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
		66	((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
		67	#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
		68	((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
		69	#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) \|\| \
		70	((__MODE__) == FSMC_WRAP_MODE_ENABLE))
		71	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
		72	((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
		73	#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
		74	((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
		75	#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
		76	((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
		77	#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
		78	((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
		79	#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
		80	((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
		81	#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
		82	#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) \|\| \
		83	((__BURST__) == FSMC_WRITE_BURST_ENABLE))
		84	#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
		85	((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
		86	#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
		87	#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
		88	#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
		89	#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
		90	#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
		91	#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
		92	#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
		93	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
		94
		95	#endif /* FSMC_BANK1 */
		96	#if defined(FSMC_BANK3)
		97
		98	#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
		99	#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
		100	((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
		101	#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
		102	((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
		103	#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) \|\| \
		104	((__STATE__) == FSMC_NAND_ECC_ENABLE))
		105
		106	#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
		107	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
		108	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
		109	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
		110	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
		111	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
		112	#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
		113	#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
		114	#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
		115	#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
		116	#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
		117	#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
		118	#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
		119
		120	#endif /* FSMC_BANK3 */
		121	#if defined(FSMC_BANK4)
		122	#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
		123
		124	#endif /* FSMC_BANK4 */
		125
		126	/**
		127	* @}
		128	*/
		129
2	mjames	130	/* Exported typedef ----------------------------------------------------------*/
		131
9	mjames	132	/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
2	mjames	133	* @{
		134	*/
		135
9	mjames	136	#if defined FSMC_BANK1
		137	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
		138	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
		139	#endif /* FSMC_BANK1 */
		140	#if defined(FSMC_BANK3)
		141	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
		142	#endif /* FSMC_BANK3 */
		143	#if defined(FSMC_BANK4)
		144	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
		145	#endif /* FSMC_BANK4 */
		146
		147	#if defined FSMC_BANK1
		148	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
		149	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
		150	#endif /* FSMC_BANK1 */
		151	#if defined(FSMC_BANK3)
		152	#define FSMC_NAND_DEVICE FSMC_Bank2_3
		153	#endif /* FSMC_BANK3 */
		154	#if defined(FSMC_BANK4)
		155	#define FSMC_PCCARD_DEVICE FSMC_Bank4
		156	#endif /* FSMC_BANK4 */
		157
		158	#if defined FSMC_BANK1
2	mjames	159	/**
9	mjames	160	* @brief FSMC NORSRAM Configuration Structure definition
2	mjames	161	*/
		162	typedef struct
		163	{
		164	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
		165	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
		166
		167	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
		168	multiplexed on the data bus or not.
		169	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
		170
		171	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
		172	the corresponding memory device.
		173	This parameter can be a value of @ref FSMC_Memory_Type */
		174
		175	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
		176	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
		177
		178	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
		179	valid only with synchronous burst Flash memories.
		180	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
		181
		182	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
		183	the Flash memory in burst mode.
		184	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
		185
		186	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
		187	memory, valid only when accessing Flash memories in burst mode.
		188	This parameter can be a value of @ref FSMC_Wrap_Mode */
		189
		190	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
		191	clock cycle before the wait state or during the wait state,
		192	valid only when accessing memories in burst mode.
		193	This parameter can be a value of @ref FSMC_Wait_Timing */
		194
		195	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
		196	This parameter can be a value of @ref FSMC_Write_Operation */
		197
		198	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
		199	signal, valid for Flash memory access in burst mode.
		200	This parameter can be a value of @ref FSMC_Wait_Signal */
		201
		202	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
		203	This parameter can be a value of @ref FSMC_Extended_Mode */
		204
		205	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
		206	valid only with asynchronous Flash memories.
		207	This parameter can be a value of @ref FSMC_AsynchronousWait */
		208
		209	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
		210	This parameter can be a value of @ref FSMC_Write_Burst */
		211
		212
9	mjames	213	uint32_t PageSize; /*!< Specifies the memory page size.
		214	This parameter can be a value of @ref FSMC_Page_Size */
		215	} FSMC_NORSRAM_InitTypeDef;
		216
2	mjames	217	/**
9	mjames	218	* @brief FSMC NORSRAM Timing parameters structure definition
2	mjames	219	*/
		220	typedef struct
		221	{
		222	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
		223	the duration of the address setup time.
		224	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
		225	@note This parameter is not used with synchronous NOR Flash memories. */
		226
		227	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
		228	the duration of the address hold time.
		229	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
		230	@note This parameter is not used with synchronous NOR Flash memories. */
		231
		232	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
		233	the duration of the data setup time.
		234	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
		235	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
		236	NOR Flash memories. */
		237
		238	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
		239	the duration of the bus turnaround.
		240	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
		241	@note This parameter is only used for multiplexed NOR Flash memories. */
		242
		243	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
		244	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
		245	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
		246	accesses. */
		247
		248	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
		249	to the memory before getting the first data.
		250	The parameter value depends on the memory type as shown below:
		251	- It must be set to 0 in case of a CRAM
		252	- It is don't care in asynchronous NOR, SRAM or ROM accesses
		253	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
		254	with synchronous burst mode enable */
		255
		256	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
9	mjames	257	This parameter can be a value of @ref FSMC_Access_Mode */
		258	} FSMC_NORSRAM_TimingTypeDef;
		259	#endif /* FSMC_BANK1 */
2	mjames	260
9	mjames	261	#if defined(FSMC_BANK3)
2	mjames	262	/**
9	mjames	263	* @brief FSMC NAND Configuration Structure definition
2	mjames	264	*/
		265	typedef struct
		266	{
		267	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
9	mjames	268	This parameter can be a value of @ref FSMC_NAND_Bank */
2	mjames	269
		270	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
9	mjames	271	This parameter can be any value of @ref FSMC_Wait_feature */
2	mjames	272
		273	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
9	mjames	274	This parameter can be any value of @ref FSMC_NAND_Data_Width */
2	mjames	275
		276	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
9	mjames	277	This parameter can be any value of @ref FSMC_ECC */
2	mjames	278
		279	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
9	mjames	280	This parameter can be any value of @ref FSMC_ECC_Page_Size */
2	mjames	281
		282	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
		283	delay between CLE low and RE low.
		284	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
		285
		286	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
		287	delay between ALE low and RE low.
		288	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
9	mjames	289	} FSMC_NAND_InitTypeDef;
		290	#endif
2	mjames	291
9	mjames	292	#if defined(FSMC_BANK3)\|\|defined(FSMC_BANK4)
2	mjames	293	/**
9	mjames	294	* @brief FSMC NAND Timing parameters structure definition
2	mjames	295	*/
		296	typedef struct
		297	{
		298	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
		299	the command assertion for NAND-Flash read or write access
		300	to common/Attribute or I/O memory space (depending on
		301	the memory space timing to be configured).
9	mjames	302	This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
2	mjames	303
		304	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
		305	command for NAND-Flash read or write access to
		306	common/Attribute or I/O memory space (depending on the
		307	memory space timing to be configured).
9	mjames	308	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
2	mjames	309
		310	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
		311	(and data for write access) after the command de-assertion
		312	for NAND-Flash read or write access to common/Attribute
		313	or I/O memory space (depending on the memory space timing
		314	to be configured).
9	mjames	315	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
2	mjames	316
		317	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
		318	data bus is kept in HiZ after the start of a NAND-Flash
		319	write access to common/Attribute or I/O memory space (depending
		320	on the memory space timing to be configured).
9	mjames	321	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
		322	} FSMC_NAND_PCC_TimingTypeDef;
		323	#endif /* FSMC_BANK3 */
2	mjames	324
9	mjames	325	#if defined(FSMC_BANK4)
2	mjames	326	/**
9	mjames	327	* @brief FSMC PCCARD Configuration Structure definition
2	mjames	328	*/
		329	typedef struct
		330	{
		331	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
9	mjames	332	This parameter can be any value of @ref FSMC_Wait_feature */
2	mjames	333
		334	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
		335	delay between CLE low and RE low.
		336	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
		337
		338	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
		339	delay between ALE low and RE low.
		340	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
9	mjames	341	}FSMC_PCCARD_InitTypeDef;
		342	#endif
2	mjames	343
		344	/**
		345	* @}
		346	*/
		347
		348	/* Exported constants --------------------------------------------------------*/
9	mjames	349	/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
2	mjames	350	* @{
		351	*/
9	mjames	352	#if defined FSMC_BANK1
2	mjames	353
9	mjames	354	/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
2	mjames	355	* @{
		356	*/
9	mjames	357
2	mjames	358	/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
		359	* @{
		360	*/
9	mjames	361	#define FSMC_NORSRAM_BANK1 (0x00000000U)
		362	#define FSMC_NORSRAM_BANK2 (0x00000002U)
		363	#define FSMC_NORSRAM_BANK3 (0x00000004U)
		364	#define FSMC_NORSRAM_BANK4 (0x00000006U)
2	mjames	365	/**
		366	* @}
		367	*/
		368
		369	/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
		370	* @{
		371	*/
9	mjames	372	#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
		373	#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
2	mjames	374	/**
		375	* @}
		376	*/
		377
		378	/** @defgroup FSMC_Memory_Type FSMC Memory Type
		379	* @{
		380	*/
9	mjames	381	#define FSMC_MEMORY_TYPE_SRAM (0x00000000U)
		382	#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U)
		383	#define FSMC_MEMORY_TYPE_NOR (0x00000008U)
2	mjames	384	/**
		385	* @}
		386	*/
		387
9	mjames	388	/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
2	mjames	389	* @{
		390	*/
9	mjames	391	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
		392	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
		393	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
2	mjames	394	/**
		395	* @}
		396	*/
		397
		398	/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
		399	* @{
		400	*/
9	mjames	401	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
		402	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
2	mjames	403	/**
		404	* @}
		405	*/
		406
		407	/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
		408	* @{
		409	*/
9	mjames	410	#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
		411	#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
2	mjames	412	/**
		413	* @}
		414	*/
		415
		416	/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
		417	* @{
		418	*/
9	mjames	419	#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
		420	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
2	mjames	421	/**
		422	* @}
		423	*/
		424
		425	/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
		426	* @{
		427	*/
9	mjames	428	#define FSMC_WRAP_MODE_DISABLE (0x00000000U)
		429	#define FSMC_WRAP_MODE_ENABLE (0x00000400U)
2	mjames	430	/**
		431	* @}
		432	*/
		433
		434	/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
		435	* @{
		436	*/
9	mjames	437	#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
		438	#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U)
2	mjames	439	/**
		440	* @}
		441	*/
		442
		443	/** @defgroup FSMC_Write_Operation FSMC Write Operation
		444	* @{
		445	*/
9	mjames	446	#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U)
		447	#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U)
2	mjames	448	/**
		449	* @}
		450	*/
		451
		452	/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
		453	* @{
		454	*/
9	mjames	455	#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U)
		456	#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U)
2	mjames	457	/**
		458	* @}
		459	*/
		460
		461	/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
		462	* @{
		463	*/
9	mjames	464	#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U)
		465	#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U)
2	mjames	466	/**
		467	* @}
		468	*/
		469
		470	/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
		471	* @{
		472	*/
9	mjames	473	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
		474	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
2	mjames	475	/**
		476	* @}
		477	*/
		478
9	mjames	479	/** @defgroup FSMC_Page_Size FSMC Page Size
		480	* @{
		481	*/
		482	#define FSMC_PAGE_SIZE_NONE (0x00000000U)
		483	#define FSMC_PAGE_SIZE_128 (0x00010000U)
		484	#define FSMC_PAGE_SIZE_256 (0x00020000U)
		485	#define FSMC_PAGE_SIZE_512 (0x00030000U)
		486	#define FSMC_PAGE_SIZE_1024 (0x00040000U)
		487	/**
		488	* @}
		489	*/
		490
2	mjames	491	/** @defgroup FSMC_Write_Burst FSMC Write Burst
		492	* @{
		493	*/
9	mjames	494	#define FSMC_WRITE_BURST_DISABLE (0x00000000U)
		495	#define FSMC_WRITE_BURST_ENABLE (0x00080000U)
2	mjames	496	/**
		497	* @}
		498	*/
		499
9	mjames	500	/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
		501	* @{
		502	*/
		503	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
		504	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
		505	/**
		506	* @}
		507	*/
		508
2	mjames	509	/** @defgroup FSMC_Access_Mode FSMC Access Mode
		510	* @{
		511	*/
9	mjames	512	#define FSMC_ACCESS_MODE_A (0x00000000U)
		513	#define FSMC_ACCESS_MODE_B (0x10000000U)
		514	#define FSMC_ACCESS_MODE_C (0x20000000U)
		515	#define FSMC_ACCESS_MODE_D (0x30000000U)
2	mjames	516	/**
		517	* @}
		518	*/
		519
		520	/**
		521	* @}
		522	*/
9	mjames	523	#endif /* FSMC_BANK1 */
2	mjames	524
9	mjames	525	#if defined(FSMC_BANK3)\|\|defined(FSMC_BANK4)
		526
		527	/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
2	mjames	528	* @{
		529	*/
		530	/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
		531	* @{
		532	*/
9	mjames	533	#define FSMC_NAND_BANK2 (0x00000010U)
		534	#define FSMC_NAND_BANK3 (0x00000100U)
2	mjames	535	/**
		536	* @}
		537	*/
		538
		539	/** @defgroup FSMC_Wait_feature FSMC Wait feature
		540	* @{
		541	*/
9	mjames	542	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
		543	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
2	mjames	544	/**
		545	* @}
		546	*/
		547
		548	/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
		549	* @{
		550	*/
9	mjames	551	#if defined(FSMC_BANK4)
		552	#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
		553	#endif
		554	#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
2	mjames	555	/**
		556	* @}
		557	*/
		558
		559	/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
		560	* @{
		561	*/
9	mjames	562	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
		563	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
2	mjames	564	/**
		565	* @}
		566	*/
		567
9	mjames	568	/** @defgroup FSMC_ECC FSMC ECC
2	mjames	569	* @{
		570	*/
9	mjames	571	#define FSMC_NAND_ECC_DISABLE (0x00000000U)
		572	#define FSMC_NAND_ECC_ENABLE (0x00000040U)
2	mjames	573	/**
		574	* @}
		575	*/
		576
		577	/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
		578	* @{
		579	*/
9	mjames	580	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
		581	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
		582	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
		583	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
		584	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
		585	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
2	mjames	586	/**
		587	* @}
		588	*/
		589
		590	/**
		591	* @}
		592	*/
9	mjames	593	#endif /* FSMC_BANK3 */
2	mjames	594
9	mjames	595
		596	/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
2	mjames	597	* @{
		598	*/
9	mjames	599	#if defined(FSMC_BANK3)\|\|defined(FSMC_BANK4)
		600	#define FSMC_IT_RISING_EDGE (0x00000008U)
		601	#define FSMC_IT_LEVEL (0x00000010U)
		602	#define FSMC_IT_FALLING_EDGE (0x00000020U)
		603	#endif /* FSMC_BANK3 */
2	mjames	604	/**
		605	* @}
		606	*/
		607
9	mjames	608	/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
2	mjames	609	* @{
		610	*/
9	mjames	611	#if defined(FSMC_BANK3)\|\|defined(FSMC_BANK4)
		612	#define FSMC_FLAG_RISING_EDGE (0x00000001U)
		613	#define FSMC_FLAG_LEVEL (0x00000002U)
		614	#define FSMC_FLAG_FALLING_EDGE (0x00000004U)
		615	#define FSMC_FLAG_FEMPT (0x00000040U)
		616	#endif /* FSMC_BANK3 */
2	mjames	617	/**
		618	* @}
		619	*/
		620
		621	/**
		622	* @}
		623	*/
		624
		625	/**
		626	* @}
		627	*/
		628
9	mjames	629	/* Private macro -------------------------------------------------------------*/
		630	/** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros
2	mjames	631	* @{
		632	*/
9	mjames	633	#if defined FSMC_BANK1
		634	/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
		635	* @brief macros to handle NOR device enable/disable and read/write operations
		636	* @{
2	mjames	637	*/
		638
		639	/**
		640	* @brief Enable the NORSRAM device access.
9	mjames	641	* @param __INSTANCE__ FSMC_NORSRAM Instance
		642	* @param __BANK__ FSMC_NORSRAM Bank
		643	* @retval None
2	mjames	644	*/
9	mjames	645	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
		646	\|= FSMC_BCRx_MBKEN)
2	mjames	647
		648	/**
		649	* @brief Disable the NORSRAM device access.
9	mjames	650	* @param __INSTANCE__ FSMC_NORSRAM Instance
		651	* @param __BANK__ FSMC_NORSRAM Bank
		652	* @retval None
2	mjames	653	*/
9	mjames	654	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
		655	&= ~FSMC_BCRx_MBKEN)
2	mjames	656
		657	/**
		658	* @}
		659	*/
9	mjames	660	#endif /* FSMC_BANK1 */
2	mjames	661
9	mjames	662	#if defined(FSMC_BANK3)
2	mjames	663	/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
		664	* @brief macros to handle NAND device enable/disable
		665	* @{
		666	*/
		667
		668	/**
		669	* @brief Enable the NAND device access.
9	mjames	670	* @param __INSTANCE__ FSMC_NAND Instance
		671	* @param __BANK__ FSMC_NAND Bank
2	mjames	672	* @retval None
		673	*/
9	mjames	674	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCRx_PBKEN): \
		675	((__INSTANCE__)->PCR3 \|= FSMC_PCRx_PBKEN))
2	mjames	676
		677	/**
		678	* @brief Disable the NAND device access.
9	mjames	679	* @param __INSTANCE__ FSMC_NAND Instance
		680	* @param __BANK__ FSMC_NAND Bank
2	mjames	681	* @retval None
		682	*/
		683	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
9	mjames	684	CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
		685
2	mjames	686	/**
		687	* @}
		688	*/
9	mjames	689	#endif
2	mjames	690
9	mjames	691	#if defined(FSMC_BANK4)
		692	/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
2	mjames	693	* @brief macros to handle PCCARD read/write operations
		694	* @{
		695	*/
		696	/**
		697	* @brief Enable the PCCARD device access.
9	mjames	698	* @param __INSTANCE__ FSMC_PCCARD Instance
2	mjames	699	* @retval None
		700	*/
9	mjames	701	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCRx_PBKEN)
2	mjames	702
		703	/**
		704	* @brief Disable the PCCARD device access.
9	mjames	705	* @param __INSTANCE__ FSMC_PCCARD Instance
2	mjames	706	* @retval None
		707	*/
9	mjames	708	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN)
2	mjames	709	/**
		710	* @}
		711	*/
		712
9	mjames	713	#endif
		714	#if defined(FSMC_BANK3)
		715	/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
		716	* @brief macros to handle NAND interrupts
2	mjames	717	* @{
		718	*/
		719
		720	/**
		721	* @brief Enable the NAND device interrupt.
9	mjames	722	* @param __INSTANCE__ FSMC_NAND instance
		723	* @param __BANK__ FSMC_NAND Bank
		724	* @param __INTERRUPT__ FSMC_NAND interrupt
2	mjames	725	* This parameter can be any combination of the following values:
		726	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
		727	* @arg FSMC_IT_LEVEL: Interrupt level.
		728	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
		729	* @retval None
		730	*/
9	mjames	731	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
		732	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
2	mjames	733
		734	/**
		735	* @brief Disable the NAND device interrupt.
9	mjames	736	* @param __INSTANCE__ FSMC_NAND Instance
		737	* @param __BANK__ FSMC_NAND Bank
		738	* @param __INTERRUPT__ FSMC_NAND interrupt
2	mjames	739	* This parameter can be any combination of the following values:
		740	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
		741	* @arg FSMC_IT_LEVEL: Interrupt level.
		742	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
		743	* @retval None
		744	*/
9	mjames	745	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
		746	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
2	mjames	747
		748	/**
		749	* @brief Get flag status of the NAND device.
9	mjames	750	* @param __INSTANCE__ FSMC_NAND Instance
		751	* @param __BANK__ FSMC_NAND Bank
		752	* @param __FLAG__ FSMC_NAND flag
2	mjames	753	* This parameter can be any combination of the following values:
		754	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
		755	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
		756	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
		757	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
		758	* @retval The state of FLAG (SET or RESET).
		759	*/
		760	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
9	mjames	761	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
		762
2	mjames	763	/**
		764	* @brief Clear flag status of the NAND device.
9	mjames	765	* @param __INSTANCE__ FSMC_NAND Instance
		766	* @param __BANK__ FSMC_NAND Bank
		767	* @param __FLAG__ FSMC_NAND flag
2	mjames	768	* This parameter can be any combination of the following values:
		769	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
		770	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
		771	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
		772	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
		773	* @retval None
		774	*/
9	mjames	775	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
		776	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
2	mjames	777
		778	/**
9	mjames	779	* @}
		780	*/
		781	#endif /* FSMC_BANK3 */
		782
		783	#if defined(FSMC_BANK4)
		784	/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
		785	* @brief macros to handle PCCARD interrupts
		786	* @{
		787	*/
		788
		789	/**
2	mjames	790	* @brief Enable the PCCARD device interrupt.
9	mjames	791	* @param __INSTANCE__ FSMC_PCCARD instance
		792	* @param __INTERRUPT__ FSMC_PCCARD interrupt
2	mjames	793	* This parameter can be any combination of the following values:
		794	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
		795	* @arg FSMC_IT_LEVEL: Interrupt level.
		796	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
		797	* @retval None
		798	*/
9	mjames	799	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
2	mjames	800
		801	/**
		802	* @brief Disable the PCCARD device interrupt.
9	mjames	803	* @param __INSTANCE__ FSMC_PCCARD instance
		804	* @param __INTERRUPT__ FSMC_PCCARD interrupt
2	mjames	805	* This parameter can be any combination of the following values:
		806	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
		807	* @arg FSMC_IT_LEVEL: Interrupt level.
		808	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
		809	* @retval None
		810	*/
9	mjames	811	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
2	mjames	812
		813	/**
		814	* @brief Get flag status of the PCCARD device.
9	mjames	815	* @param __INSTANCE__ FSMC_PCCARD instance
		816	* @param __FLAG__ FSMC_PCCARD flag
2	mjames	817	* This parameter can be any combination of the following values:
9	mjames	818	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
		819	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
		820	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
		821	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
2	mjames	822	* @retval The state of FLAG (SET or RESET).
		823	*/
		824	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
		825
		826	/**
		827	* @brief Clear flag status of the PCCARD device.
9	mjames	828	* @param __INSTANCE__ FSMC_PCCARD instance
		829	* @param __FLAG__ FSMC_PCCARD flag
2	mjames	830	* This parameter can be any combination of the following values:
9	mjames	831	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
		832	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
		833	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
		834	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
2	mjames	835	* @retval None
		836	*/
9	mjames	837	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
2	mjames	838
		839	/**
		840	* @}
		841	*/
9	mjames	842	#endif
2	mjames	843
		844	/**
		845	* @}
		846	*/
		847
		848	/**
		849	* @}
		850	*/
		851
9	mjames	852	/* Private functions ---------------------------------------------------------*/
		853	/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
		854	* @{
2	mjames	855	*/
		856
9	mjames	857	#if defined FSMC_BANK1
		858	/** @defgroup FSMC_LL_NORSRAM NOR SRAM
		859	* @{
2	mjames	860	*/
9	mjames	861	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
		862	* @{
2	mjames	863	*/
9	mjames	864	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
		865	FSMC_NORSRAM_InitTypeDef *Init);
		866	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
		867	FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
		868	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
		869	FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
		870	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
		871	FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
2	mjames	872	/**
		873	* @}
		874	*/
		875
9	mjames	876	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
		877	* @{
2	mjames	878	*/
		879	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
		880	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
		881	/**
		882	* @}
		883	*/
		884	/**
		885	* @}
		886	*/
9	mjames	887	#endif /* FSMC_BANK1 */
2	mjames	888
9	mjames	889	#if defined(FSMC_BANK3)
		890	/** @defgroup FSMC_LL_NAND NAND
		891	* @{
2	mjames	892	*/
9	mjames	893	/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
		894	* @{
2	mjames	895	*/
		896	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
9	mjames	897	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
		898	FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
		899	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
		900	FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
2	mjames	901	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
		902	/**
		903	* @}
		904	*/
		905
9	mjames	906	/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
		907	* @{
2	mjames	908	*/
		909	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
		910	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
9	mjames	911	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank,
		912	uint32_t Timeout);
2	mjames	913	/**
		914	* @}
		915	*/
		916	/**
		917	* @}
		918	*/
9	mjames	919	#endif /* FSMC_BANK3 */
2	mjames	920
9	mjames	921	#if defined(FSMC_BANK4)
		922	/** @defgroup FSMC_LL_PCCARD PCCARD
		923	* @{
2	mjames	924	*/
9	mjames	925	/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
		926	* @{
2	mjames	927	*/
		928	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
9	mjames	929	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
		930	FSMC_NAND_PCC_TimingTypeDef *Timing);
		931	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
		932	FSMC_NAND_PCC_TimingTypeDef *Timing);
		933	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
		934	FSMC_NAND_PCC_TimingTypeDef *Timing);
2	mjames	935	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
		936	/**
		937	* @}
		938	*/
		939	/**
		940	* @}
		941	*/
9	mjames	942	#endif /* FSMC_BANK4 */
2	mjames	943
9	mjames	944
2	mjames	945	/**
		946	* @}
		947	*/
		948
		949	/**
		950	* @}
		951	*/
		952
		953	/**
		954	* @}
		955	*/
		956
		957	#ifdef __cplusplus
		958	}
		959	#endif
		960
9	mjames	961	#endif /* STM32F1xx_LL_FSMC_H */
2	mjames	962
		963	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h – Rev 9