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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_fsmc.h
		4	* @author MCD Application Team
		5	* @brief Header file of FSMC HAL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
		10	*
		11	* Redistribution and use in source and binary forms, with or without modification,
		12	* are permitted provided that the following conditions are met:
		13	* 1. Redistributions of source code must retain the above copyright notice,
		14	* this list of conditions and the following disclaimer.
		15	* 2. Redistributions in binary form must reproduce the above copyright notice,
		16	* this list of conditions and the following disclaimer in the documentation
		17	* and/or other materials provided with the distribution.
		18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		19	* may be used to endorse or promote products derived from this software
		20	* without specific prior written permission.
		21	*
		22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		32	*
		33	******************************************************************************
		34	*/
		35
		36	/* Define to prevent recursive inclusion -------------------------------------*/
		37	#ifndef __STM32F1xx_LL_FSMC_H
		38	#define __STM32F1xx_LL_FSMC_H
		39
		40	#ifdef __cplusplus
		41	extern "C" {
		42	#endif
		43
		44	/* Includes ------------------------------------------------------------------*/
		45	#include "stm32f1xx_hal_def.h"
		46
		47	/** @addtogroup STM32F1xx_HAL_Driver
		48	* @{
		49	*/
		50
		51	#if defined(FSMC_BANK1)
		52
		53	/** @addtogroup FSMC_LL
		54	* @{
		55	*/
		56
		57
		58	/* Exported typedef ----------------------------------------------------------*/
		59
		60	/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
		61	* @{
		62	*/
		63
		64	/**
		65	* @brief FSMC NORSRAM Configuration Structure definition
		66	*/
		67	typedef struct
		68	{
		69	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
		70	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
		71
		72	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
		73	multiplexed on the data bus or not.
		74	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
		75
		76	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
		77	the corresponding memory device.
		78	This parameter can be a value of @ref FSMC_Memory_Type */
		79
		80	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
		81	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
		82
		83	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
		84	valid only with synchronous burst Flash memories.
		85	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
		86
		87	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
		88	the Flash memory in burst mode.
		89	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
		90
		91	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
		92	memory, valid only when accessing Flash memories in burst mode.
		93	This parameter can be a value of @ref FSMC_Wrap_Mode */
		94
		95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
		96	clock cycle before the wait state or during the wait state,
		97	valid only when accessing memories in burst mode.
		98	This parameter can be a value of @ref FSMC_Wait_Timing */
		99
		100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
		101	This parameter can be a value of @ref FSMC_Write_Operation */
		102
		103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
		104	signal, valid for Flash memory access in burst mode.
		105	This parameter can be a value of @ref FSMC_Wait_Signal */
		106
		107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
		108	This parameter can be a value of @ref FSMC_Extended_Mode */
		109
		110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
		111	valid only with asynchronous Flash memories.
		112	This parameter can be a value of @ref FSMC_AsynchronousWait */
		113
		114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
		115	This parameter can be a value of @ref FSMC_Write_Burst */
		116
		117	}FSMC_NORSRAM_InitTypeDef;
		118
		119	/**
		120	* @brief FSMC NORSRAM Timing parameters structure definition
		121	*/
		122	typedef struct
		123	{
		124	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
		125	the duration of the address setup time.
		126	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
		127	@note This parameter is not used with synchronous NOR Flash memories. */
		128
		129	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
		130	the duration of the address hold time.
		131	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
		132	@note This parameter is not used with synchronous NOR Flash memories. */
		133
		134	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
		135	the duration of the data setup time.
		136	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
		137	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
		138	NOR Flash memories. */
		139
		140	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
		141	the duration of the bus turnaround.
		142	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
		143	@note This parameter is only used for multiplexed NOR Flash memories. */
		144
		145	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
		146	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
		147	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
		148	accesses. */
		149
		150	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
		151	to the memory before getting the first data.
		152	The parameter value depends on the memory type as shown below:
		153	- It must be set to 0 in case of a CRAM
		154	- It is don't care in asynchronous NOR, SRAM or ROM accesses
		155	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
		156	with synchronous burst mode enable */
		157
		158	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
		159	This parameter can be a value of @ref FSMC_Access_Mode */
		160
		161	}FSMC_NORSRAM_TimingTypeDef;
		162
		163	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
		164	/**
		165	* @brief FSMC NAND Configuration Structure definition
		166	*/
		167	typedef struct
		168	{
		169	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
		170	This parameter can be a value of @ref FSMC_NAND_Bank */
		171
		172	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
		173	This parameter can be any value of @ref FSMC_Wait_feature */
		174
		175	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
		176	This parameter can be any value of @ref FSMC_NAND_Data_Width */
		177
		178	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
		179	This parameter can be any value of @ref FSMC_ECC */
		180
		181	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
		182	This parameter can be any value of @ref FSMC_ECC_Page_Size */
		183
		184	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
		185	delay between CLE low and RE low.
		186	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
		187
		188	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
		189	delay between ALE low and RE low.
		190	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
		191
		192	}FSMC_NAND_InitTypeDef;
		193
		194	/**
		195	* @brief FSMC NAND/PCCARD Timing parameters structure definition
		196	*/
		197	typedef struct
		198	{
		199	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
		200	the command assertion for NAND-Flash read or write access
		201	to common/Attribute or I/O memory space (depending on
		202	the memory space timing to be configured).
		203	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
		204
		205	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
		206	command for NAND-Flash read or write access to
		207	common/Attribute or I/O memory space (depending on the
		208	memory space timing to be configured).
		209	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
		210
		211	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
		212	(and data for write access) after the command de-assertion
		213	for NAND-Flash read or write access to common/Attribute
		214	or I/O memory space (depending on the memory space timing
		215	to be configured).
		216	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
		217
		218	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
		219	data bus is kept in HiZ after the start of a NAND-Flash
		220	write access to common/Attribute or I/O memory space (depending
		221	on the memory space timing to be configured).
		222	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
		223
		224	}FSMC_NAND_PCC_TimingTypeDef;
		225
		226	/**
		227	* @brief FSMC NAND Configuration Structure definition
		228	*/
		229	typedef struct
		230	{
		231	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
		232	This parameter can be any value of @ref FSMC_Wait_feature */
		233
		234	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
		235	delay between CLE low and RE low.
		236	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
		237
		238	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
		239	delay between ALE low and RE low.
		240	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
		241
		242	}FSMC_PCCARD_InitTypeDef;
		243	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
		244	/**
		245	* @}
		246	*/
		247
		248	/* Exported constants --------------------------------------------------------*/
		249
		250	/** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
		251	* @{
		252	*/
		253
		254	/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
		255	* @{
		256	*/
		257	/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
		258	* @{
		259	*/
		260	#define FSMC_NORSRAM_BANK1 0x00000000U
		261	#define FSMC_NORSRAM_BANK2 0x00000002U
		262	#define FSMC_NORSRAM_BANK3 0x00000004U
		263	#define FSMC_NORSRAM_BANK4 0x00000006U
		264	/**
		265	* @}
		266	*/
		267
		268	/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
		269	* @{
		270	*/
		271	#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
		272	#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN)
		273	/**
		274	* @}
		275	*/
		276
		277	/** @defgroup FSMC_Memory_Type FSMC Memory Type
		278	* @{
		279	*/
		280	#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
		281	#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0)
		282	#define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1)
		283	/**
		284	* @}
		285	*/
		286
		287	/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
		288	* @{
		289	*/
		290	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
		291	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0)
		292	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1)
		293	/**
		294	* @}
		295	*/
		296
		297	/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
		298	* @{
		299	*/
		300	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN)
		301	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
		302	/**
		303	* @}
		304	*/
		305
		306	/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
		307	* @{
		308	*/
		309	#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
		310	#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN)
		311	/**
		312	* @}
		313	*/
		314
		315	/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
		316	* @{
		317	*/
		318	#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
		319	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL)
		320	/**
		321	* @}
		322	*/
		323
		324	/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
		325	* @{
		326	*/
		327	#define FSMC_WRAP_MODE_DISABLE 0x00000000U
		328	#define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD)
		329	/**
		330	* @}
		331	*/
		332
		333	/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
		334	* @{
		335	*/
		336	#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
		337	#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG)
		338	/**
		339	* @}
		340	*/
		341
		342	/** @defgroup FSMC_Write_Operation FSMC Write Operation
		343	* @{
		344	*/
		345	#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
		346	#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN)
		347	/**
		348	* @}
		349	*/
		350
		351	/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
		352	* @{
		353	*/
		354	#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
		355	#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN)
		356	/**
		357	* @}
		358	*/
		359
		360	/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
		361	* @{
		362	*/
		363	#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
		364	#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD)
		365	/**
		366	* @}
		367	*/
		368
		369	/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
		370	* @{
		371	*/
		372	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
		373	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT)
		374	/**
		375	* @}
		376	*/
		377
		378	/** @defgroup FSMC_Write_Burst FSMC Write Burst
		379	* @{
		380	*/
		381	#define FSMC_WRITE_BURST_DISABLE 0x00000000U
		382	#define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW)
		383	/**
		384	* @}
		385	*/
		386
		387	/** @defgroup FSMC_Access_Mode FSMC Access Mode
		388	* @{
		389	*/
		390	#define FSMC_ACCESS_MODE_A 0x00000000U
		391	#define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0)
		392	#define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1)
		393	#define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 \| FSMC_BTRx_ACCMOD_1))
		394	/**
		395	* @}
		396	*/
		397
		398	/**
		399	* @}
		400	*/
		401
		402	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
		403	/** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
		404	* @{
		405	*/
		406	/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
		407	* @{
		408	*/
		409	#define FSMC_NAND_BANK2 0x00000010U
		410	#define FSMC_NAND_BANK3 0x00000100U
		411	/**
		412	* @}
		413	*/
		414
		415	/** @defgroup FSMC_Wait_feature FSMC Wait feature
		416	* @{
		417	*/
		418	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
		419	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FSMC_PCRx_PWAITEN)
		420	/**
		421	* @}
		422	*/
		423
		424	/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
		425	* @{
		426	*/
		427	#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
		428	#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FSMC_PCRx_PTYP)
		429	/**
		430	* @}
		431	*/
		432
		433	/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
		434	* @{
		435	*/
		436	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
		437	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_PCRx_PWID_0)
		438	/**
		439	* @}
		440	*/
		441
		442	/** @defgroup FSMC_ECC FSMC NAND ECC
		443	* @{
		444	*/
		445	#define FSMC_NAND_ECC_DISABLE 0x00000000U
		446	#define FSMC_NAND_ECC_ENABLE ((uint32_t)FSMC_PCRx_ECCEN)
		447	/**
		448	* @}
		449	*/
		450
		451	/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
		452	* @{
		453	*/
		454	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
		455	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FSMC_PCRx_ECCPS_0)
		456	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FSMC_PCRx_ECCPS_1)
		457	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FSMC_PCRx_ECCPS_0\|FSMC_PCRx_ECCPS_1)
		458	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FSMC_PCRx_ECCPS_2)
		459	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FSMC_PCRx_ECCPS_0\|FSMC_PCRx_ECCPS_2)
		460	/**
		461	* @}
		462	*/
		463
		464	/**
		465	* @}
		466	*/
		467	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
		468
		469	/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
		470	* @brief FSMC Interrupt definition
		471	* @{
		472	*/
		473	#define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN)
		474	#define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN)
		475	#define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN)
		476	/**
		477	* @}
		478	*/
		479
		480	/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
		481	* @brief FSMC Flag definition
		482	* @{
		483	*/
		484	#define FSMC_FLAG_RISING_EDGE ((uint32_t)FSMC_SRx_IRS)
		485	#define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS)
		486	#define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS)
		487	#define FSMC_FLAG_FEMPT ((uint32_t)FSMC_SRx_FEMPT)
		488	/**
		489	* @}
		490	*/
		491
		492	/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
		493	* @{
		494	*/
		495	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
		496	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
		497	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
		498	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
		499
		500	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
		501	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
		502	#define FSMC_NAND_DEVICE FSMC_Bank2_3
		503	#define FSMC_PCCARD_DEVICE FSMC_Bank4
		504	/**
		505	* @}
		506	*/
		507
		508	/**
		509	* @}
		510	*/
		511
		512	/* Exported macro ------------------------------------------------------------*/
		513	/** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
		514	* @{
		515	*/
		516
		517	/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
		518	* @brief macros to handle NOR device enable/disable and read/write operations
		519	* @{
		520	*/
		521
		522	/**
		523	* @brief Enable the NORSRAM device access.
		524	* @param __INSTANCE__: FSMC_NORSRAM Instance
		525	* @param __BANK__: FSMC_NORSRAM Bank
		526	* @retval none
		527	*/
		528	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
		529
		530	/**
		531	* @brief Disable the NORSRAM device access.
		532	* @param __INSTANCE__: FSMC_NORSRAM Instance
		533	* @param __BANK__: FSMC_NORSRAM Bank
		534	* @retval none
		535	*/
		536	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
		537
		538	/**
		539	* @}
		540	*/
		541
		542	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
		543	/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
		544	* @brief macros to handle NAND device enable/disable
		545	* @{
		546	*/
		547
		548	/**
		549	* @brief Enable the NAND device access.
		550	* @param __INSTANCE__: FSMC_NAND Instance
		551	* @param __BANK__: FSMC_NAND Bank
		552	* @retval None
		553	*/
		554	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
		555	SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
		556
		557	/**
		558	* @brief Disable the NAND device access.
		559	* @param __INSTANCE__: FSMC_NAND Instance
		560	* @param __BANK__: FSMC_NAND Bank
		561	* @retval None
		562	*/
		563	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
		564	CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
		565	/**
		566	* @}
		567	*/
		568
		569	/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
		570	* @brief macros to handle PCCARD read/write operations
		571	* @{
		572	*/
		573	/**
		574	* @brief Enable the PCCARD device access.
		575	* @param __INSTANCE__: FSMC_PCCARD Instance
		576	* @retval None
		577	*/
		578	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
		579
		580	/**
		581	* @brief Disable the PCCARD device access.
		582	* @param __INSTANCE__: FSMC_PCCARD Instance
		583	* @retval None
		584	*/
		585	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
		586	/**
		587	* @}
		588	*/
		589
		590	/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
		591	* @brief macros to handle FSMC flags and interrupts
		592	* @{
		593	*/
		594
		595	/**
		596	* @brief Enable the NAND device interrupt.
		597	* @param __INSTANCE__: FSMC_NAND Instance
		598	* @param __BANK__: FSMC_NAND Bank
		599	* @param __INTERRUPT__: FSMC_NAND interrupt
		600	* This parameter can be any combination of the following values:
		601	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
		602	* @arg FSMC_IT_LEVEL: Interrupt level.
		603	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
		604	* @retval None
		605	*/
		606	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
		607	SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
		608
		609	/**
		610	* @brief Disable the NAND device interrupt.
		611	* @param __INSTANCE__: FSMC_NAND Instance
		612	* @param __BANK__: FSMC_NAND Bank
		613	* @param __INTERRUPT__: FSMC_NAND interrupt
		614	* This parameter can be any combination of the following values:
		615	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
		616	* @arg FSMC_IT_LEVEL: Interrupt level.
		617	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
		618	* @retval None
		619	*/
		620	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
		621	CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
		622
		623	/**
		624	* @brief Get flag status of the NAND device.
		625	* @param __INSTANCE__: FSMC_NAND Instance
		626	* @param __BANK__ : FSMC_NAND Bank
		627	* @param __FLAG__ : FSMC_NAND flag
		628	* This parameter can be any combination of the following values:
		629	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
		630	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
		631	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
		632	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
		633	* @retval The state of FLAG (SET or RESET).
		634	*/
		635	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
		636	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
		637	/**
		638	* @brief Clear flag status of the NAND device.
		639	* @param __INSTANCE__: FSMC_NAND Instance
		640	* @param __BANK__: FSMC_NAND Bank
		641	* @param __FLAG__: FSMC_NAND flag
		642	* This parameter can be any combination of the following values:
		643	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
		644	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
		645	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
		646	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
		647	* @retval None
		648	*/
		649	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
		650	CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
		651
		652	/**
		653	* @brief Enable the PCCARD device interrupt.
		654	* @param __INSTANCE__: FSMC_PCCARD Instance
		655	* @param __INTERRUPT__: FSMC_PCCARD interrupt
		656	* This parameter can be any combination of the following values:
		657	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
		658	* @arg FSMC_IT_LEVEL: Interrupt level.
		659	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
		660	* @retval None
		661	*/
		662	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
		663
		664	/**
		665	* @brief Disable the PCCARD device interrupt.
		666	* @param __INSTANCE__: FSMC_PCCARD Instance
		667	* @param __INTERRUPT__: FSMC_PCCARD interrupt
		668	* This parameter can be any combination of the following values:
		669	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
		670	* @arg FSMC_IT_LEVEL: Interrupt level.
		671	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
		672	* @retval None
		673	*/
		674	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
		675
		676	/**
		677	* @brief Get flag status of the PCCARD device.
		678	* @param __INSTANCE__: FSMC_PCCARD Instance
		679	* @param __FLAG__: FSMC_PCCARD flag
		680	* This parameter can be any combination of the following values:
		681	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
		682	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
		683	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
		684	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
		685	* @retval The state of FLAG (SET or RESET).
		686	*/
		687	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
		688
		689	/**
		690	* @brief Clear flag status of the PCCARD device.
		691	* @param __INSTANCE__: FSMC_PCCARD Instance
		692	* @param __FLAG__: FSMC_PCCARD flag
		693	* This parameter can be any combination of the following values:
		694	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
		695	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
		696	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
		697	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
		698	* @retval None
		699	*/
		700	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
		701
		702	/**
		703	* @}
		704	*/
		705	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
		706
		707	/**
		708	* @}
		709	*/
		710
		711	/** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
		712	* @{
		713	*/
		714	#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) \|\| \
		715	((__BANK__) == FSMC_NORSRAM_BANK2) \|\| \
		716	((__BANK__) == FSMC_NORSRAM_BANK3) \|\| \
		717	((__BANK__) == FSMC_NORSRAM_BANK4))
		718
		719	#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
		720	((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
		721
		722	#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) \|\| \
		723	((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
		724	((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
		725
		726	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
		727	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
		728	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
		729
		730	#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) \|\| \
		731	((__BURST__) == FSMC_WRITE_BURST_ENABLE))
		732
		733	#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) \|\| \
		734	((__MODE__) == FSMC_ACCESS_MODE_B) \|\| \
		735	((__MODE__) == FSMC_ACCESS_MODE_C) \|\| \
		736	((__MODE__) == FSMC_ACCESS_MODE_D))
		737
		738	#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) \|\| \
		739	((__BANK__) == FSMC_NAND_BANK3))
		740
		741	#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
		742	((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
		743
		744	#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
		745	((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
		746
		747	#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) \|\| \
		748	((__STATE__) == FSMC_NAND_ECC_ENABLE))
		749
		750	#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
		751	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
		752	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
		753	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
		754	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
		755	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
		756
		757	/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
		758	* @{
		759	*/
		760	#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
		761	/**
		762	* @}
		763	*/
		764
		765	/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
		766	* @{
		767	*/
		768	#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
		769	/**
		770	* @}
		771	*/
		772
		773	/** @defgroup FSMC_Setup_Time FSMC_Setup_Time
		774	* @{
		775	*/
		776	#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255U)
		777	/**
		778	* @}
		779	*/
		780
		781	/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
		782	* @{
		783	*/
		784	#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255U)
		785	/**
		786	* @}
		787	*/
		788
		789	/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
		790	* @{
		791	*/
		792	#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255U)
		793	/**
		794	* @}
		795	*/
		796
		797	/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
		798	* @{
		799	*/
		800	#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255U)
		801	/**
		802	* @}
		803	*/
		804
		805	/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
		806	* @{
		807	*/
		808	#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
		809	/**
		810	* @}
		811	*/
		812
		813	/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
		814	* @{
		815	*/
		816	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
		817	/**
		818	* @}
		819	*/
		820
		821	/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
		822	* @{
		823	*/
		824	#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
		825	/**
		826	* @}
		827	*/
		828
		829	/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
		830	* @{
		831	*/
		832	#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
		833
		834	/**
		835	* @}
		836	*/
		837	#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
		838	((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
		839
		840	#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
		841	((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
		842
		843	#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) \|\| \
		844	((__MODE__) == FSMC_WRAP_MODE_ENABLE))
		845
		846	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
		847	((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
		848
		849	#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
		850	((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
		851
		852	#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
		853	((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
		854
		855	#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
		856	((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
		857
		858	#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
		859	((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
		860
		861	#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
		862
		863	/** @defgroup FSMC_Data_Latency FSMC Data Latency
		864	* @{
		865	*/
		866	#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
		867	/**
		868	* @}
		869	*/
		870
		871	/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
		872	* @{
		873	*/
		874	#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
		875	/**
		876	* @}
		877	*/
		878
		879	/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
		880	* @{
		881	*/
		882	#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
		883	/**
		884	* @}
		885	*/
		886
		887	/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
		888	* @{
		889	*/
		890	#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
		891	/**
		892	* @}
		893	*/
		894
		895	/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
		896	* @{
		897	*/
		898	#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
		899	/**
		900	* @}
		901	*/
		902
		903	/**
		904	* @}
		905	*/
		906
		907	/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
		908	* @{
		909	*/
		910
		911	/* ----------------------- FSMC registers bit mask --------------------------- */
		912	#if (defined (STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
		913	/* --- PCR Register ---*/
		914	/* PCR register clear mask */
		915	#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN \| FSMC_PCRx_PBKEN \| \
		916	FSMC_PCRx_PTYP \| FSMC_PCRx_PWID \| \
		917	FSMC_PCRx_ECCEN \| FSMC_PCRx_TCLR \| \
		918	FSMC_PCRx_TAR \| FSMC_PCRx_ECCPS))
		919
		920	/* --- PMEM Register ---*/
		921	/* PMEM register clear mask */
		922	#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx \| FSMC_PMEMx_MEMWAITx \|\
		923	FSMC_PMEMx_MEMHOLDx \| FSMC_PMEMx_MEMHIZx))
		924
		925	/* --- PATT Register ---*/
		926	/* PATT register clear mask */
		927	#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx \| FSMC_PATTx_ATTWAITx \|\
		928	FSMC_PATTx_ATTHOLDx \| FSMC_PATTx_ATTHIZx))
		929
		930	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
		931	/* --- BCR Register ---*/
		932	/* BCR register clear mask */
		933	#define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN \| FSMC_BCRx_MUXEN \| \
		934	FSMC_BCRx_MTYP \| FSMC_BCRx_MWID \| \
		935	FSMC_BCRx_BURSTEN \| FSMC_BCRx_WAITPOL \| \
		936	FSMC_BCRx_WRAPMOD \| FSMC_BCRx_WAITCFG \| \
		937	FSMC_BCRx_WREN \| FSMC_BCRx_WAITEN \| \
		938	FSMC_BCRx_EXTMOD \| FSMC_BCRx_ASYNCWAIT \| \
		939	FSMC_BCRx_CBURSTRW))
		940	/* --- BTR Register ---*/
		941	/* BTR register clear mask */
		942	#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET \| FSMC_BTRx_ADDHLD \|\
		943	FSMC_BTRx_DATAST \| FSMC_BTRx_BUSTURN \|\
		944	FSMC_BTRx_CLKDIV \| FSMC_BTRx_DATLAT \|\
		945	FSMC_BTRx_ACCMOD))
		946
		947	/* --- BWTR Register ---*/
		948	/* BWTR register clear mask */
		949	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
		950	#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET \| FSMC_BWTRx_ADDHLD \| \
		951	FSMC_BWTRx_DATAST \| FSMC_BWTRx_ACCMOD \| \
		952	FSMC_BWTRx_BUSTURN))
		953	#else
		954	#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET \| FSMC_BWTRx_ADDHLD \| \
		955	FSMC_BWTRx_DATAST \| FSMC_BWTRx_ACCMOD \| \
		956	FSMC_BWTRx_CLKDIV \| FSMC_BWTRx_DATLAT))
		957	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
		958
		959	/* --- PIO4 Register ---*/
		960	/* PIO4 register clear mask */
		961	#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 \| FSMC_PIO4_IOWAIT4 \| \
		962	FSMC_PIO4_IOHOLD4 \| FSMC_PIO4_IOHIZ4))
		963	/**
		964	* @}
		965	*/
		966	/* Exported functions --------------------------------------------------------*/
		967
		968	/** @addtogroup FSMC_LL_Exported_Functions
		969	* @{
		970	*/
		971
		972	/** @addtogroup FSMC_NORSRAM
		973	* @{
		974	*/
		975
		976	/** @addtogroup FSMC_NORSRAM_Group1
		977	* @{
		978	*/
		979	/* FSMC_NORSRAM Controller functions ******************************************/
		980	/* Initialization/de-initialization functions */
		981	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
		982	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
		983	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
		984	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
		985	/**
		986	* @}
		987	*/
		988
		989	/** @addtogroup FSMC_NORSRAM_Group2
		990	* @{
		991	*/
		992	/* FSMC_NORSRAM Control functions */
		993	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
		994	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
		995	/**
		996	* @}
		997	*/
		998
		999	/**
		1000	* @}
		1001	*/
		1002
		1003	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
		1004	/** @addtogroup FSMC_NAND
		1005	* @{
		1006	*/
		1007
		1008	/* FSMC_NAND Controller functions **********************************************/
		1009	/* Initialization/de-initialization functions */
		1010	/** @addtogroup FSMC_NAND_Exported_Functions_Group1
		1011	* @{
		1012	*/
		1013	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
		1014	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
		1015	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
		1016	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
		1017	/**
		1018	* @}
		1019	*/
		1020
		1021	/* FSMC_NAND Control functions */
		1022	/** @addtogroup FSMC_NAND_Exported_Functions_Group2
		1023	* @{
		1024	*/
		1025	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
		1026	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
		1027	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
		1028	/**
		1029	* @}
		1030	*/
		1031
		1032	/**
		1033	* @}
		1034	*/
		1035
		1036	/** @addtogroup FSMC_PCCARD
		1037	* @{
		1038	*/
		1039
		1040	/* FSMC_PCCARD Controller functions ********************************************/
		1041	/* Initialization/de-initialization functions */
		1042	/** @addtogroup FSMC_PCCARD_Exported_Functions_Group1
		1043	* @{
		1044	*/
		1045	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
		1046	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
		1047	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
		1048	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
		1049	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
		1050	/**
		1051	* @}
		1052	*/
		1053
		1054	/**
		1055	* @}
		1056	*/
		1057	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
		1058
		1059	/**
		1060	* @}
		1061	*/
		1062
		1063	/**
		1064	* @}
		1065	*/
		1066	#endif /* FSMC_BANK1 */
		1067
		1068	/**
		1069	* @}
		1070	*/
		1071
		1072	#ifdef __cplusplus
		1073	}
		1074	#endif
		1075
		1076	#endif /* __STM32F1xx_LL_FSMC_H */
		1077
		1078	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
		1079

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h – Rev 2