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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f1xx_ll_dac.h |
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4 | * @author MCD Application Team |
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5 | * @brief Header file of DAC LL module. |
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6 | ****************************************************************************** |
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7 | * @attention |
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8 | * |
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9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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10 | * |
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11 | * Redistribution and use in source and binary forms, with or without modification, |
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12 | * are permitted provided that the following conditions are met: |
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13 | * 1. Redistributions of source code must retain the above copyright notice, |
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14 | * this list of conditions and the following disclaimer. |
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15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 | * this list of conditions and the following disclaimer in the documentation |
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17 | * and/or other materials provided with the distribution. |
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18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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19 | * may be used to endorse or promote products derived from this software |
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20 | * without specific prior written permission. |
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21 | * |
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22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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32 | * |
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33 | ****************************************************************************** |
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34 | */ |
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35 | |||
36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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37 | #ifndef __STM32F1xx_LL_DAC_H |
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38 | #define __STM32F1xx_LL_DAC_H |
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39 | |||
40 | #ifdef __cplusplus |
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41 | extern "C" { |
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42 | #endif |
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43 | |||
44 | /* Includes ------------------------------------------------------------------*/ |
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45 | #include "stm32f1xx.h" |
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46 | |||
47 | /** @addtogroup STM32F1xx_LL_Driver |
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48 | * @{ |
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49 | */ |
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50 | |||
51 | #if defined (DAC) |
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52 | |||
53 | /** @defgroup DAC_LL DAC |
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54 | * @{ |
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55 | */ |
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56 | |||
57 | /* Private types -------------------------------------------------------------*/ |
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58 | /* Private variables ---------------------------------------------------------*/ |
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59 | |||
60 | /* Private constants ---------------------------------------------------------*/ |
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61 | /** @defgroup DAC_LL_Private_Constants DAC Private Constants |
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62 | * @{ |
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63 | */ |
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64 | |||
65 | /* Internal masks for DAC channels definition */ |
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66 | /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ |
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67 | /* - channel bits position into register CR */ |
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68 | /* - channel bits position into register SWTRIG */ |
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69 | /* - channel register offset of data holding register DHRx */ |
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70 | /* - channel register offset of data output register DORx */ |
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71 | #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
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72 | #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
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73 | #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) |
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74 | |||
75 | #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
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76 | #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
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77 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
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78 | |||
79 | #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ |
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80 | #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
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81 | #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
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82 | #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
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83 | #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
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84 | #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
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85 | #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U |
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86 | #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U |
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87 | #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U |
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88 | #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
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89 | |||
90 | #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ |
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91 | #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ |
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92 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) |
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93 | |||
94 | /* DAC registers bits positions */ |
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95 | #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ |
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96 | #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ |
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97 | #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ |
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98 | |||
99 | /* Miscellaneous data */ |
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100 | #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ |
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101 | |||
102 | /** |
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103 | * @} |
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104 | */ |
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105 | |||
106 | |||
107 | /* Private macros ------------------------------------------------------------*/ |
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108 | /** @defgroup DAC_LL_Private_Macros DAC Private Macros |
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109 | * @{ |
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110 | */ |
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111 | |||
112 | /** |
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113 | * @brief Driver macro reserved for internal use: isolate bits with the |
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114 | * selected mask and shift them to the register LSB |
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115 | * (shift mask on register position bit 0). |
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116 | * @param __BITS__ Bits in register 32 bits |
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117 | * @param __MASK__ Mask in register 32 bits |
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118 | * @retval Bits in register 32 bits |
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119 | */ |
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120 | #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ |
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121 | (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) |
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122 | |||
123 | /** |
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124 | * @brief Driver macro reserved for internal use: set a pointer to |
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125 | * a register from a register basis from which an offset |
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126 | * is applied. |
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127 | * @param __REG__ Register basis from which the offset is applied. |
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128 | * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). |
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129 | * @retval Pointer to register address |
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130 | */ |
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131 | #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ |
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132 | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) |
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133 | |||
134 | /** |
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135 | * @} |
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136 | */ |
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137 | |||
138 | |||
139 | /* Exported types ------------------------------------------------------------*/ |
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140 | #if defined(USE_FULL_LL_DRIVER) |
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141 | /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure |
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142 | * @{ |
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143 | */ |
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144 | |||
145 | /** |
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146 | * @brief Structure definition of some features of DAC instance. |
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147 | */ |
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148 | typedef struct |
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149 | { |
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150 | uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). |
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151 | This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE |
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152 | |||
153 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ |
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154 | |||
155 | uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
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156 | This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE |
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157 | |||
158 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ |
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159 | |||
160 | uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
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161 | If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS |
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162 | If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE |
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163 | @note If waveform automatic generation mode is disabled, this parameter is discarded. |
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164 | |||
165 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ |
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166 | |||
167 | uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. |
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168 | This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER |
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169 | |||
170 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ |
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171 | |||
172 | } LL_DAC_InitTypeDef; |
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173 | |||
174 | /** |
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175 | * @} |
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176 | */ |
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177 | #endif /* USE_FULL_LL_DRIVER */ |
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178 | |||
179 | /* Exported constants --------------------------------------------------------*/ |
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180 | /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants |
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181 | * @{ |
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182 | */ |
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183 | |||
184 | /** @defgroup DAC_LL_EC_GET_FLAG DAC flags |
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185 | * @brief Flags defines which can be used with LL_DAC_ReadReg function |
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186 | * @{ |
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187 | */ |
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188 | /* DAC channel 1 flags */ |
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189 | #if defined(DAC_SR_DMAUDR1) |
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190 | #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ |
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191 | #endif /* DAC_SR_DMAUDR1 */ |
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192 | |||
193 | /* DAC channel 2 flags */ |
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194 | #if defined(DAC_SR_DMAUDR2) |
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195 | #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ |
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196 | #endif /* DAC_SR_DMAUDR2 */ |
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197 | /** |
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198 | * @} |
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199 | */ |
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200 | |||
201 | /** @defgroup DAC_LL_EC_IT DAC interruptions |
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202 | * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions |
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203 | * @{ |
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204 | */ |
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205 | #if defined(DAC_CR_DMAUDRIE1) |
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206 | #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ |
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207 | #endif /* DAC_CR_DMAUDRIE1 */ |
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208 | #if defined(DAC_CR_DMAUDRIE2) |
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209 | #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ |
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210 | #endif /* DAC_CR_DMAUDRIE2 */ |
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211 | /** |
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212 | * @} |
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213 | */ |
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214 | |||
215 | /** @defgroup DAC_LL_EC_CHANNEL DAC channels |
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216 | * @{ |
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217 | */ |
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218 | #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ |
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219 | #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ |
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220 | /** |
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221 | * @} |
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222 | */ |
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223 | |||
224 | /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source |
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225 | * @{ |
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226 | */ |
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227 | #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ |
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228 | #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ |
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229 | #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ |
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230 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ |
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231 | #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ |
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232 | #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ |
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233 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ |
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234 | #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ |
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235 | #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ |
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236 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ |
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237 | /** |
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238 | * @} |
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239 | */ |
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240 | |||
241 | /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode |
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242 | * @{ |
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243 | */ |
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244 | #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ |
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245 | #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ |
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246 | #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ |
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247 | /** |
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248 | * @} |
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249 | */ |
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250 | |||
251 | /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits |
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252 | * @{ |
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253 | */ |
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254 | #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ |
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255 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ |
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256 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ |
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257 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ |
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258 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ |
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259 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ |
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260 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ |
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261 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ |
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262 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ |
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263 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ |
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264 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ |
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265 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ |
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266 | /** |
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267 | * @} |
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268 | */ |
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269 | |||
270 | /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude |
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271 | * @{ |
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272 | */ |
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273 | #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ |
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274 | #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ |
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275 | #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ |
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276 | #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ |
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277 | #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ |
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278 | #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ |
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279 | #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ |
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280 | #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ |
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281 | #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ |
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282 | #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ |
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283 | #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ |
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284 | #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ |
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285 | /** |
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286 | * @} |
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287 | */ |
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288 | |||
289 | /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer |
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290 | * @{ |
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291 | */ |
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292 | #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ |
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293 | #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ |
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294 | /** |
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295 | * @} |
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296 | */ |
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297 | |||
298 | |||
299 | /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution |
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300 | * @{ |
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301 | */ |
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302 | #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ |
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303 | #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ |
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304 | /** |
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305 | * @} |
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306 | */ |
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307 | |||
308 | /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose |
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309 | * @{ |
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310 | */ |
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311 | /* List of DAC registers intended to be used (most commonly) with */ |
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312 | /* DMA transfer. */ |
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313 | /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ |
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314 | #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ |
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315 | #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ |
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316 | #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ |
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317 | /** |
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318 | * @} |
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319 | */ |
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320 | |||
321 | /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays |
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322 | * @note Only DAC IP HW delays are defined in DAC LL driver driver, |
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323 | * not timeout values. |
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324 | * For details on delays values, refer to descriptions in source code |
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325 | * above each literal definition. |
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326 | * @{ |
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327 | */ |
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328 | |||
329 | /* Delay for DAC channel voltage settling time from DAC channel startup */ |
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330 | /* (transition from disable to enable). */ |
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331 | /* Note: DAC channel startup time depends on board application environment: */ |
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332 | /* impedance connected to DAC channel output. */ |
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333 | /* The delay below is specified under conditions: */ |
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334 | /* - voltage maximum transition (lowest to highest value) */ |
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335 | /* - until voltage reaches final value +-1LSB */ |
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336 | /* - DAC channel output buffer enabled */ |
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337 | /* - load impedance of 5kOhm (min), 50pF (max) */ |
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338 | /* Literal set to maximum value (refer to device datasheet, */ |
||
339 | /* parameter "tWAKEUP"). */ |
||
340 | /* Unit: us */ |
||
341 | #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ |
||
342 | |||
343 | /* Delay for DAC channel voltage settling time. */ |
||
344 | /* Note: DAC channel startup time depends on board application environment: */ |
||
345 | /* impedance connected to DAC channel output. */ |
||
346 | /* The delay below is specified under conditions: */ |
||
347 | /* - voltage maximum transition (lowest to highest value) */ |
||
348 | /* - until voltage reaches final value +-1LSB */ |
||
349 | /* - DAC channel output buffer enabled */ |
||
350 | /* - load impedance of 5kOhm min, 50pF max */ |
||
351 | /* Literal set to maximum value (refer to device datasheet, */ |
||
352 | /* parameter "tSETTLING"). */ |
||
353 | /* Unit: us */ |
||
354 | #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ |
||
355 | /** |
||
356 | * @} |
||
357 | */ |
||
358 | |||
359 | /** |
||
360 | * @} |
||
361 | */ |
||
362 | |||
363 | /* Exported macro ------------------------------------------------------------*/ |
||
364 | /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros |
||
365 | * @{ |
||
366 | */ |
||
367 | |||
368 | /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros |
||
369 | * @{ |
||
370 | */ |
||
371 | |||
372 | /** |
||
373 | * @brief Write a value in DAC register |
||
374 | * @param __INSTANCE__ DAC Instance |
||
375 | * @param __REG__ Register to be written |
||
376 | * @param __VALUE__ Value to be written in the register |
||
377 | * @retval None |
||
378 | */ |
||
379 | #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
||
380 | |||
381 | /** |
||
382 | * @brief Read a value in DAC register |
||
383 | * @param __INSTANCE__ DAC Instance |
||
384 | * @param __REG__ Register to be read |
||
385 | * @retval Register value |
||
386 | */ |
||
387 | #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
||
388 | |||
389 | /** |
||
390 | * @} |
||
391 | */ |
||
392 | |||
393 | /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro |
||
394 | * @{ |
||
395 | */ |
||
396 | |||
397 | /** |
||
398 | * @brief Helper macro to get DAC channel number in decimal format |
||
399 | * from literals LL_DAC_CHANNEL_x. |
||
400 | * Example: |
||
401 | * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) |
||
402 | * will return decimal number "1". |
||
403 | * @note The input can be a value from functions where a channel |
||
404 | * number is returned. |
||
405 | * @param __CHANNEL__ This parameter can be one of the following values: |
||
406 | * @arg @ref LL_DAC_CHANNEL_1 |
||
407 | * @arg @ref LL_DAC_CHANNEL_2 |
||
408 | * @retval 1...2 |
||
409 | */ |
||
410 | #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ |
||
411 | ((__CHANNEL__) & DAC_SWTR_CHX_MASK) |
||
412 | |||
413 | /** |
||
414 | * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x |
||
415 | * from number in decimal format. |
||
416 | * Example: |
||
417 | * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) |
||
418 | * will return a data equivalent to "LL_DAC_CHANNEL_1". |
||
419 | * @note If the input parameter does not correspond to a DAC channel, |
||
420 | * this macro returns value '0'. |
||
421 | * @param __DECIMAL_NB__ 1...2 |
||
422 | * @retval Returned value can be one of the following values: |
||
423 | * @arg @ref LL_DAC_CHANNEL_1 |
||
424 | * @arg @ref LL_DAC_CHANNEL_2 |
||
425 | */ |
||
426 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
||
427 | (((__DECIMAL_NB__) == 1U) \ |
||
428 | ? ( \ |
||
429 | LL_DAC_CHANNEL_1 \ |
||
430 | ) \ |
||
431 | : \ |
||
432 | (((__DECIMAL_NB__) == 2U) \ |
||
433 | ? ( \ |
||
434 | LL_DAC_CHANNEL_2 \ |
||
435 | ) \ |
||
436 | : \ |
||
437 | ( \ |
||
438 | |||
439 | ) \ |
||
440 | ) \ |
||
441 | ) |
||
442 | |||
443 | /** |
||
444 | * @brief Helper macro to define the DAC conversion data full-scale digital |
||
445 | * value corresponding to the selected DAC resolution. |
||
446 | * @note DAC conversion data full-scale corresponds to voltage range |
||
447 | * determined by analog voltage references Vref+ and Vref- |
||
448 | * (refer to reference manual). |
||
449 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
||
450 | * @arg @ref LL_DAC_RESOLUTION_12B |
||
451 | * @arg @ref LL_DAC_RESOLUTION_8B |
||
452 | * @retval ADC conversion data equivalent voltage value (unit: mVolt) |
||
453 | */ |
||
454 | #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
||
455 | ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) |
||
456 | |||
457 | /** |
||
458 | * @brief Helper macro to calculate the DAC conversion data (unit: digital |
||
459 | * value) corresponding to a voltage (unit: mVolt). |
||
460 | * @note This helper macro is intended to provide input data in voltage |
||
461 | * rather than digital value, |
||
462 | * to be used with LL DAC functions such as |
||
463 | * @ref LL_DAC_ConvertData12RightAligned(). |
||
464 | * @note Analog reference voltage (Vref+) must be either known from |
||
465 | * user board environment or can be calculated using ADC measurement |
||
466 | * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
||
467 | * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) |
||
468 | * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel |
||
469 | * (unit: mVolt). |
||
470 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
||
471 | * @arg @ref LL_DAC_RESOLUTION_12B |
||
472 | * @arg @ref LL_DAC_RESOLUTION_8B |
||
473 | * @retval DAC conversion data (unit: digital value) |
||
474 | */ |
||
475 | #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ |
||
476 | __DAC_VOLTAGE__,\ |
||
477 | __DAC_RESOLUTION__) \ |
||
478 | ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
||
479 | / (__VREFANALOG_VOLTAGE__) \ |
||
480 | ) |
||
481 | |||
482 | /** |
||
483 | * @} |
||
484 | */ |
||
485 | |||
486 | /** |
||
487 | * @} |
||
488 | */ |
||
489 | |||
490 | |||
491 | /* Exported functions --------------------------------------------------------*/ |
||
492 | /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions |
||
493 | * @{ |
||
494 | */ |
||
495 | /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels |
||
496 | * @{ |
||
497 | */ |
||
498 | |||
499 | /** |
||
500 | * @brief Set the conversion trigger source for the selected DAC channel. |
||
501 | * @note For conversion trigger source to be effective, DAC trigger |
||
502 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
||
503 | * @note To set conversion trigger source, DAC channel must be disabled. |
||
504 | * Otherwise, the setting is discarded. |
||
505 | * @note Availability of parameters of trigger sources from timer |
||
506 | * depends on timers availability on the selected device. |
||
507 | * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n |
||
508 | * CR TSEL2 LL_DAC_SetTriggerSource |
||
509 | * @param DACx DAC instance |
||
510 | * @param DAC_Channel This parameter can be one of the following values: |
||
511 | * @arg @ref LL_DAC_CHANNEL_1 |
||
512 | * @arg @ref LL_DAC_CHANNEL_2 |
||
513 | * @param TriggerSource This parameter can be one of the following values: |
||
514 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
||
515 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO |
||
516 | * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO |
||
517 | * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO |
||
518 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
||
519 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
||
520 | * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO |
||
521 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
||
522 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
||
523 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
||
524 | * @retval None |
||
525 | */ |
||
526 | __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) |
||
527 | { |
||
528 | MODIFY_REG(DACx->CR, |
||
529 | DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
530 | TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
531 | } |
||
532 | |||
533 | /** |
||
534 | * @brief Get the conversion trigger source for the selected DAC channel. |
||
535 | * @note For conversion trigger source to be effective, DAC trigger |
||
536 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
||
537 | * @note Availability of parameters of trigger sources from timer |
||
538 | * depends on timers availability on the selected device. |
||
539 | * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n |
||
540 | * CR TSEL2 LL_DAC_GetTriggerSource |
||
541 | * @param DACx DAC instance |
||
542 | * @param DAC_Channel This parameter can be one of the following values: |
||
543 | * @arg @ref LL_DAC_CHANNEL_1 |
||
544 | * @arg @ref LL_DAC_CHANNEL_2 |
||
545 | * @retval Returned value can be one of the following values: |
||
546 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
||
547 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO |
||
548 | * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO |
||
549 | * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO |
||
550 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
||
551 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
||
552 | * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO |
||
553 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
||
554 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
||
555 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
||
556 | */ |
||
557 | __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
558 | { |
||
559 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
560 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
561 | ); |
||
562 | } |
||
563 | |||
564 | /** |
||
565 | * @brief Set the waveform automatic generation mode |
||
566 | * for the selected DAC channel. |
||
567 | * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n |
||
568 | * CR WAVE2 LL_DAC_SetWaveAutoGeneration |
||
569 | * @param DACx DAC instance |
||
570 | * @param DAC_Channel This parameter can be one of the following values: |
||
571 | * @arg @ref LL_DAC_CHANNEL_1 |
||
572 | * @arg @ref LL_DAC_CHANNEL_2 |
||
573 | * @param WaveAutoGeneration This parameter can be one of the following values: |
||
574 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
||
575 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
||
576 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
||
577 | * @retval None |
||
578 | */ |
||
579 | __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) |
||
580 | { |
||
581 | MODIFY_REG(DACx->CR, |
||
582 | DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
583 | WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
584 | } |
||
585 | |||
586 | /** |
||
587 | * @brief Get the waveform automatic generation mode |
||
588 | * for the selected DAC channel. |
||
589 | * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n |
||
590 | * CR WAVE2 LL_DAC_GetWaveAutoGeneration |
||
591 | * @param DACx DAC instance |
||
592 | * @param DAC_Channel This parameter can be one of the following values: |
||
593 | * @arg @ref LL_DAC_CHANNEL_1 |
||
594 | * @arg @ref LL_DAC_CHANNEL_2 |
||
595 | * @retval Returned value can be one of the following values: |
||
596 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
||
597 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
||
598 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
||
599 | */ |
||
600 | __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
601 | { |
||
602 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
603 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
604 | ); |
||
605 | } |
||
606 | |||
607 | /** |
||
608 | * @brief Set the noise waveform generation for the selected DAC channel: |
||
609 | * Noise mode and parameters LFSR (linear feedback shift register). |
||
610 | * @note For wave generation to be effective, DAC channel |
||
611 | * wave generation mode must be enabled using |
||
612 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
||
613 | * @note This setting can be set when the selected DAC channel is disabled |
||
614 | * (otherwise, the setting operation is ignored). |
||
615 | * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n |
||
616 | * CR MAMP2 LL_DAC_SetWaveNoiseLFSR |
||
617 | * @param DACx DAC instance |
||
618 | * @param DAC_Channel This parameter can be one of the following values: |
||
619 | * @arg @ref LL_DAC_CHANNEL_1 |
||
620 | * @arg @ref LL_DAC_CHANNEL_2 |
||
621 | * @param NoiseLFSRMask This parameter can be one of the following values: |
||
622 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
||
623 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
||
624 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
||
625 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
||
626 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
||
627 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
||
628 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
||
629 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
||
630 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
||
631 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
||
632 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
||
633 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
||
634 | * @retval None |
||
635 | */ |
||
636 | __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) |
||
637 | { |
||
638 | MODIFY_REG(DACx->CR, |
||
639 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
640 | NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
641 | } |
||
642 | |||
643 | /** |
||
644 | * @brief Set the noise waveform generation for the selected DAC channel: |
||
645 | * Noise mode and parameters LFSR (linear feedback shift register). |
||
646 | * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n |
||
647 | * CR MAMP2 LL_DAC_GetWaveNoiseLFSR |
||
648 | * @param DACx DAC instance |
||
649 | * @param DAC_Channel This parameter can be one of the following values: |
||
650 | * @arg @ref LL_DAC_CHANNEL_1 |
||
651 | * @arg @ref LL_DAC_CHANNEL_2 |
||
652 | * @retval Returned value can be one of the following values: |
||
653 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
||
654 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
||
655 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
||
656 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
||
657 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
||
658 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
||
659 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
||
660 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
||
661 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
||
662 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
||
663 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
||
664 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
||
665 | */ |
||
666 | __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
667 | { |
||
668 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
669 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
670 | ); |
||
671 | } |
||
672 | |||
673 | /** |
||
674 | * @brief Set the triangle waveform generation for the selected DAC channel: |
||
675 | * triangle mode and amplitude. |
||
676 | * @note For wave generation to be effective, DAC channel |
||
677 | * wave generation mode must be enabled using |
||
678 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
||
679 | * @note This setting can be set when the selected DAC channel is disabled |
||
680 | * (otherwise, the setting operation is ignored). |
||
681 | * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n |
||
682 | * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude |
||
683 | * @param DACx DAC instance |
||
684 | * @param DAC_Channel This parameter can be one of the following values: |
||
685 | * @arg @ref LL_DAC_CHANNEL_1 |
||
686 | * @arg @ref LL_DAC_CHANNEL_2 |
||
687 | * @param TriangleAmplitude This parameter can be one of the following values: |
||
688 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
||
689 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
||
690 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
||
691 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
||
692 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
||
693 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
||
694 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
||
695 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
||
696 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
||
697 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
||
698 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
||
699 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
||
700 | * @retval None |
||
701 | */ |
||
702 | __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) |
||
703 | { |
||
704 | MODIFY_REG(DACx->CR, |
||
705 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
706 | TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
707 | } |
||
708 | |||
709 | /** |
||
710 | * @brief Set the triangle waveform generation for the selected DAC channel: |
||
711 | * triangle mode and amplitude. |
||
712 | * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n |
||
713 | * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude |
||
714 | * @param DACx DAC instance |
||
715 | * @param DAC_Channel This parameter can be one of the following values: |
||
716 | * @arg @ref LL_DAC_CHANNEL_1 |
||
717 | * @arg @ref LL_DAC_CHANNEL_2 |
||
718 | * @retval Returned value can be one of the following values: |
||
719 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
||
720 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
||
721 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
||
722 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
||
723 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
||
724 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
||
725 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
||
726 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
||
727 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
||
728 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
||
729 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
||
730 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
||
731 | */ |
||
732 | __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
733 | { |
||
734 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
735 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
736 | ); |
||
737 | } |
||
738 | |||
739 | /** |
||
740 | * @brief Set the output buffer for the selected DAC channel. |
||
741 | * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n |
||
742 | * CR BOFF2 LL_DAC_SetOutputBuffer |
||
743 | * @param DACx DAC instance |
||
744 | * @param DAC_Channel This parameter can be one of the following values: |
||
745 | * @arg @ref LL_DAC_CHANNEL_1 |
||
746 | * @arg @ref LL_DAC_CHANNEL_2 |
||
747 | * @param OutputBuffer This parameter can be one of the following values: |
||
748 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
||
749 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
||
750 | * @retval None |
||
751 | */ |
||
752 | __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) |
||
753 | { |
||
754 | MODIFY_REG(DACx->CR, |
||
755 | DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
756 | OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
757 | } |
||
758 | |||
759 | /** |
||
760 | * @brief Get the output buffer state for the selected DAC channel. |
||
761 | * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n |
||
762 | * CR BOFF2 LL_DAC_GetOutputBuffer |
||
763 | * @param DACx DAC instance |
||
764 | * @param DAC_Channel This parameter can be one of the following values: |
||
765 | * @arg @ref LL_DAC_CHANNEL_1 |
||
766 | * @arg @ref LL_DAC_CHANNEL_2 |
||
767 | * @retval Returned value can be one of the following values: |
||
768 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
||
769 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
||
770 | */ |
||
771 | __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
772 | { |
||
773 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
774 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
775 | ); |
||
776 | } |
||
777 | |||
778 | /** |
||
779 | * @} |
||
780 | */ |
||
781 | |||
782 | /** @defgroup DAC_LL_EF_DMA_Management DMA Management |
||
783 | * @{ |
||
784 | */ |
||
785 | |||
786 | /** |
||
787 | * @brief Enable DAC DMA transfer request of the selected channel. |
||
788 | * @note To configure DMA source address (peripheral address), |
||
789 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
||
790 | * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n |
||
791 | * CR DMAEN2 LL_DAC_EnableDMAReq |
||
792 | * @param DACx DAC instance |
||
793 | * @param DAC_Channel This parameter can be one of the following values: |
||
794 | * @arg @ref LL_DAC_CHANNEL_1 |
||
795 | * @arg @ref LL_DAC_CHANNEL_2 |
||
796 | * @retval None |
||
797 | */ |
||
798 | __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
799 | { |
||
800 | SET_BIT(DACx->CR, |
||
801 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
802 | } |
||
803 | |||
804 | /** |
||
805 | * @brief Disable DAC DMA transfer request of the selected channel. |
||
806 | * @note To configure DMA source address (peripheral address), |
||
807 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
||
808 | * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n |
||
809 | * CR DMAEN2 LL_DAC_DisableDMAReq |
||
810 | * @param DACx DAC instance |
||
811 | * @param DAC_Channel This parameter can be one of the following values: |
||
812 | * @arg @ref LL_DAC_CHANNEL_1 |
||
813 | * @arg @ref LL_DAC_CHANNEL_2 |
||
814 | * @retval None |
||
815 | */ |
||
816 | __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
817 | { |
||
818 | CLEAR_BIT(DACx->CR, |
||
819 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
820 | } |
||
821 | |||
822 | /** |
||
823 | * @brief Get DAC DMA transfer request state of the selected channel. |
||
824 | * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) |
||
825 | * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n |
||
826 | * CR DMAEN2 LL_DAC_IsDMAReqEnabled |
||
827 | * @param DACx DAC instance |
||
828 | * @param DAC_Channel This parameter can be one of the following values: |
||
829 | * @arg @ref LL_DAC_CHANNEL_1 |
||
830 | * @arg @ref LL_DAC_CHANNEL_2 |
||
831 | * @retval State of bit (1 or 0). |
||
832 | */ |
||
833 | __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
834 | { |
||
835 | return (READ_BIT(DACx->CR, |
||
836 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
837 | == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
||
838 | } |
||
839 | |||
840 | /** |
||
841 | * @brief Function to help to configure DMA transfer to DAC: retrieve the |
||
842 | * DAC register address from DAC instance and a list of DAC registers |
||
843 | * intended to be used (most commonly) with DMA transfer. |
||
844 | * @note These DAC registers are data holding registers: |
||
845 | * when DAC conversion is requested, DAC generates a DMA transfer |
||
846 | * request to have data available in DAC data holding registers. |
||
847 | * @note This macro is intended to be used with LL DMA driver, refer to |
||
848 | * function "LL_DMA_ConfigAddresses()". |
||
849 | * Example: |
||
850 | * LL_DMA_ConfigAddresses(DMA1, |
||
851 | * LL_DMA_CHANNEL_1, |
||
852 | * (uint32_t)&< array or variable >, |
||
853 | * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), |
||
854 | * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); |
||
855 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
||
856 | * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
||
857 | * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
||
858 | * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
||
859 | * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
||
860 | * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr |
||
861 | * @param DACx DAC instance |
||
862 | * @param DAC_Channel This parameter can be one of the following values: |
||
863 | * @arg @ref LL_DAC_CHANNEL_1 |
||
864 | * @arg @ref LL_DAC_CHANNEL_2 |
||
865 | * @param Register This parameter can be one of the following values: |
||
866 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED |
||
867 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED |
||
868 | * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED |
||
869 | * @retval DAC register address |
||
870 | */ |
||
871 | __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) |
||
872 | { |
||
873 | /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ |
||
874 | /* DAC channel selected. */ |
||
875 | return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); |
||
876 | } |
||
877 | /** |
||
878 | * @} |
||
879 | */ |
||
880 | |||
881 | /** @defgroup DAC_LL_EF_Operation Operation on DAC channels |
||
882 | * @{ |
||
883 | */ |
||
884 | |||
885 | /** |
||
886 | * @brief Enable DAC selected channel. |
||
887 | * @rmtoll CR EN1 LL_DAC_Enable\n |
||
888 | * CR EN2 LL_DAC_Enable |
||
889 | * @note After enable from off state, DAC channel requires a delay |
||
890 | * for output voltage to reach accuracy +/- 1 LSB. |
||
891 | * Refer to device datasheet, parameter "tWAKEUP". |
||
892 | * @param DACx DAC instance |
||
893 | * @param DAC_Channel This parameter can be one of the following values: |
||
894 | * @arg @ref LL_DAC_CHANNEL_1 |
||
895 | * @arg @ref LL_DAC_CHANNEL_2 |
||
896 | * @retval None |
||
897 | */ |
||
898 | __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
899 | { |
||
900 | SET_BIT(DACx->CR, |
||
901 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
902 | } |
||
903 | |||
904 | /** |
||
905 | * @brief Disable DAC selected channel. |
||
906 | * @rmtoll CR EN1 LL_DAC_Disable\n |
||
907 | * CR EN2 LL_DAC_Disable |
||
908 | * @param DACx DAC instance |
||
909 | * @param DAC_Channel This parameter can be one of the following values: |
||
910 | * @arg @ref LL_DAC_CHANNEL_1 |
||
911 | * @arg @ref LL_DAC_CHANNEL_2 |
||
912 | * @retval None |
||
913 | */ |
||
914 | __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
915 | { |
||
916 | CLEAR_BIT(DACx->CR, |
||
917 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
918 | } |
||
919 | |||
920 | /** |
||
921 | * @brief Get DAC enable state of the selected channel. |
||
922 | * (0: DAC channel is disabled, 1: DAC channel is enabled) |
||
923 | * @rmtoll CR EN1 LL_DAC_IsEnabled\n |
||
924 | * CR EN2 LL_DAC_IsEnabled |
||
925 | * @param DACx DAC instance |
||
926 | * @param DAC_Channel This parameter can be one of the following values: |
||
927 | * @arg @ref LL_DAC_CHANNEL_1 |
||
928 | * @arg @ref LL_DAC_CHANNEL_2 |
||
929 | * @retval State of bit (1 or 0). |
||
930 | */ |
||
931 | __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
932 | { |
||
933 | return (READ_BIT(DACx->CR, |
||
934 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
935 | == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
||
936 | } |
||
937 | |||
938 | /** |
||
939 | * @brief Enable DAC trigger of the selected channel. |
||
940 | * @note - If DAC trigger is disabled, DAC conversion is performed |
||
941 | * automatically once the data holding register is updated, |
||
942 | * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
||
943 | * @ref LL_DAC_ConvertData12RightAligned(), ... |
||
944 | * - If DAC trigger is enabled, DAC conversion is performed |
||
945 | * only when a hardware of software trigger event is occurring. |
||
946 | * Select trigger source using |
||
947 | * function @ref LL_DAC_SetTriggerSource(). |
||
948 | * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n |
||
949 | * CR TEN2 LL_DAC_EnableTrigger |
||
950 | * @param DACx DAC instance |
||
951 | * @param DAC_Channel This parameter can be one of the following values: |
||
952 | * @arg @ref LL_DAC_CHANNEL_1 |
||
953 | * @arg @ref LL_DAC_CHANNEL_2 |
||
954 | * @retval None |
||
955 | */ |
||
956 | __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
957 | { |
||
958 | SET_BIT(DACx->CR, |
||
959 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
960 | } |
||
961 | |||
962 | /** |
||
963 | * @brief Disable DAC trigger of the selected channel. |
||
964 | * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n |
||
965 | * CR TEN2 LL_DAC_DisableTrigger |
||
966 | * @param DACx DAC instance |
||
967 | * @param DAC_Channel This parameter can be one of the following values: |
||
968 | * @arg @ref LL_DAC_CHANNEL_1 |
||
969 | * @arg @ref LL_DAC_CHANNEL_2 |
||
970 | * @retval None |
||
971 | */ |
||
972 | __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
973 | { |
||
974 | CLEAR_BIT(DACx->CR, |
||
975 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
976 | } |
||
977 | |||
978 | /** |
||
979 | * @brief Get DAC trigger state of the selected channel. |
||
980 | * (0: DAC trigger is disabled, 1: DAC trigger is enabled) |
||
981 | * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n |
||
982 | * CR TEN2 LL_DAC_IsTriggerEnabled |
||
983 | * @param DACx DAC instance |
||
984 | * @param DAC_Channel This parameter can be one of the following values: |
||
985 | * @arg @ref LL_DAC_CHANNEL_1 |
||
986 | * @arg @ref LL_DAC_CHANNEL_2 |
||
987 | * @retval State of bit (1 or 0). |
||
988 | */ |
||
989 | __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
990 | { |
||
991 | return (READ_BIT(DACx->CR, |
||
992 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
993 | == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
||
994 | } |
||
995 | |||
996 | /** |
||
997 | * @brief Trig DAC conversion by software for the selected DAC channel. |
||
998 | * @note Preliminarily, DAC trigger must be set to software trigger |
||
999 | * using function @ref LL_DAC_SetTriggerSource() |
||
1000 | * with parameter "LL_DAC_TRIGGER_SOFTWARE". |
||
1001 | * and DAC trigger must be enabled using |
||
1002 | * function @ref LL_DAC_EnableTrigger(). |
||
1003 | * @note For devices featuring DAC with 2 channels: this function |
||
1004 | * can perform a SW start of both DAC channels simultaneously. |
||
1005 | * Two channels can be selected as parameter. |
||
1006 | * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) |
||
1007 | * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n |
||
1008 | * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion |
||
1009 | * @param DACx DAC instance |
||
1010 | * @param DAC_Channel This parameter can a combination of the following values: |
||
1011 | * @arg @ref LL_DAC_CHANNEL_1 |
||
1012 | * @arg @ref LL_DAC_CHANNEL_2 |
||
1013 | * @retval None |
||
1014 | */ |
||
1015 | __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
1016 | { |
||
1017 | SET_BIT(DACx->SWTRIGR, |
||
1018 | (DAC_Channel & DAC_SWTR_CHX_MASK)); |
||
1019 | } |
||
1020 | |||
1021 | /** |
||
1022 | * @brief Set the data to be loaded in the data holding register |
||
1023 | * in format 12 bits left alignment (LSB aligned on bit 0), |
||
1024 | * for the selected DAC channel. |
||
1025 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n |
||
1026 | * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned |
||
1027 | * @param DACx DAC instance |
||
1028 | * @param DAC_Channel This parameter can be one of the following values: |
||
1029 | * @arg @ref LL_DAC_CHANNEL_1 |
||
1030 | * @arg @ref LL_DAC_CHANNEL_2 |
||
1031 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
||
1032 | * @retval None |
||
1033 | */ |
||
1034 | __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
||
1035 | { |
||
1036 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); |
||
1037 | |||
1038 | MODIFY_REG(*preg, |
||
1039 | DAC_DHR12R1_DACC1DHR, |
||
1040 | Data); |
||
1041 | } |
||
1042 | |||
1043 | /** |
||
1044 | * @brief Set the data to be loaded in the data holding register |
||
1045 | * in format 12 bits left alignment (MSB aligned on bit 15), |
||
1046 | * for the selected DAC channel. |
||
1047 | * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n |
||
1048 | * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned |
||
1049 | * @param DACx DAC instance |
||
1050 | * @param DAC_Channel This parameter can be one of the following values: |
||
1051 | * @arg @ref LL_DAC_CHANNEL_1 |
||
1052 | * @arg @ref LL_DAC_CHANNEL_2 |
||
1053 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
||
1054 | * @retval None |
||
1055 | */ |
||
1056 | __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
||
1057 | { |
||
1058 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); |
||
1059 | |||
1060 | MODIFY_REG(*preg, |
||
1061 | DAC_DHR12L1_DACC1DHR, |
||
1062 | Data); |
||
1063 | } |
||
1064 | |||
1065 | /** |
||
1066 | * @brief Set the data to be loaded in the data holding register |
||
1067 | * in format 8 bits left alignment (LSB aligned on bit 0), |
||
1068 | * for the selected DAC channel. |
||
1069 | * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n |
||
1070 | * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned |
||
1071 | * @param DACx DAC instance |
||
1072 | * @param DAC_Channel This parameter can be one of the following values: |
||
1073 | * @arg @ref LL_DAC_CHANNEL_1 |
||
1074 | * @arg @ref LL_DAC_CHANNEL_2 |
||
1075 | * @param Data Value between Min_Data=0x00 and Max_Data=0xFF |
||
1076 | * @retval None |
||
1077 | */ |
||
1078 | __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
||
1079 | { |
||
1080 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); |
||
1081 | |||
1082 | MODIFY_REG(*preg, |
||
1083 | DAC_DHR8R1_DACC1DHR, |
||
1084 | Data); |
||
1085 | } |
||
1086 | |||
1087 | /** |
||
1088 | * @brief Set the data to be loaded in the data holding register |
||
1089 | * in format 12 bits left alignment (LSB aligned on bit 0), |
||
1090 | * for both DAC channels. |
||
1091 | * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n |
||
1092 | * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned |
||
1093 | * @param DACx DAC instance |
||
1094 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
||
1095 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
||
1096 | * @retval None |
||
1097 | */ |
||
1098 | __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
||
1099 | { |
||
1100 | MODIFY_REG(DACx->DHR12RD, |
||
1101 | (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), |
||
1102 | ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
||
1103 | } |
||
1104 | |||
1105 | /** |
||
1106 | * @brief Set the data to be loaded in the data holding register |
||
1107 | * in format 12 bits left alignment (MSB aligned on bit 15), |
||
1108 | * for both DAC channels. |
||
1109 | * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n |
||
1110 | * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned |
||
1111 | * @param DACx DAC instance |
||
1112 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
||
1113 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
||
1114 | * @retval None |
||
1115 | */ |
||
1116 | __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
||
1117 | { |
||
1118 | /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ |
||
1119 | /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ |
||
1120 | /* the 4 LSB must be taken into account for the shift value. */ |
||
1121 | MODIFY_REG(DACx->DHR12LD, |
||
1122 | (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), |
||
1123 | ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); |
||
1124 | } |
||
1125 | |||
1126 | /** |
||
1127 | * @brief Set the data to be loaded in the data holding register |
||
1128 | * in format 8 bits left alignment (LSB aligned on bit 0), |
||
1129 | * for both DAC channels. |
||
1130 | * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n |
||
1131 | * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned |
||
1132 | * @param DACx DAC instance |
||
1133 | * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF |
||
1134 | * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF |
||
1135 | * @retval None |
||
1136 | */ |
||
1137 | __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
||
1138 | { |
||
1139 | MODIFY_REG(DACx->DHR8RD, |
||
1140 | (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), |
||
1141 | ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
||
1142 | } |
||
1143 | |||
1144 | /** |
||
1145 | * @brief Retrieve output data currently generated for the selected DAC channel. |
||
1146 | * @note Whatever alignment and resolution settings |
||
1147 | * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
||
1148 | * @ref LL_DAC_ConvertData12RightAligned(), ...), |
||
1149 | * output data format is 12 bits right aligned (LSB aligned on bit 0). |
||
1150 | * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n |
||
1151 | * DOR2 DACC2DOR LL_DAC_RetrieveOutputData |
||
1152 | * @param DACx DAC instance |
||
1153 | * @param DAC_Channel This parameter can be one of the following values: |
||
1154 | * @arg @ref LL_DAC_CHANNEL_1 |
||
1155 | * @arg @ref LL_DAC_CHANNEL_2 |
||
1156 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
||
1157 | */ |
||
1158 | __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
1159 | { |
||
1160 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); |
||
1161 | |||
1162 | return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); |
||
1163 | } |
||
1164 | |||
1165 | /** |
||
1166 | * @} |
||
1167 | */ |
||
1168 | |||
1169 | /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management |
||
1170 | * @{ |
||
1171 | */ |
||
1172 | #if defined(DAC_SR_DMAUDR1) |
||
1173 | /** |
||
1174 | * @brief Get DAC underrun flag for DAC channel 1 |
||
1175 | * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 |
||
1176 | * @param DACx DAC instance |
||
1177 | * @retval State of bit (1 or 0). |
||
1178 | */ |
||
1179 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) |
||
1180 | { |
||
1181 | return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); |
||
1182 | } |
||
1183 | #endif /* DAC_SR_DMAUDR1 */ |
||
1184 | |||
1185 | #if defined(DAC_SR_DMAUDR2) |
||
1186 | /** |
||
1187 | * @brief Get DAC underrun flag for DAC channel 2 |
||
1188 | * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 |
||
1189 | * @param DACx DAC instance |
||
1190 | * @retval State of bit (1 or 0). |
||
1191 | */ |
||
1192 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) |
||
1193 | { |
||
1194 | return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); |
||
1195 | } |
||
1196 | #endif /* DAC_SR_DMAUDR2 */ |
||
1197 | |||
1198 | #if defined(DAC_SR_DMAUDR1) |
||
1199 | /** |
||
1200 | * @brief Clear DAC underrun flag for DAC channel 1 |
||
1201 | * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 |
||
1202 | * @param DACx DAC instance |
||
1203 | * @retval None |
||
1204 | */ |
||
1205 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) |
||
1206 | { |
||
1207 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); |
||
1208 | } |
||
1209 | #endif /* DAC_SR_DMAUDR1 */ |
||
1210 | |||
1211 | #if defined(DAC_SR_DMAUDR2) |
||
1212 | /** |
||
1213 | * @brief Clear DAC underrun flag for DAC channel 2 |
||
1214 | * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 |
||
1215 | * @param DACx DAC instance |
||
1216 | * @retval None |
||
1217 | */ |
||
1218 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) |
||
1219 | { |
||
1220 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); |
||
1221 | } |
||
1222 | #endif /* DAC_SR_DMAUDR2 */ |
||
1223 | |||
1224 | /** |
||
1225 | * @} |
||
1226 | */ |
||
1227 | /** @defgroup DAC_LL_EF_IT_Management IT management |
||
1228 | * @{ |
||
1229 | */ |
||
1230 | |||
1231 | #if defined(DAC_CR_DMAUDRIE1) |
||
1232 | /** |
||
1233 | * @brief Enable DMA underrun interrupt for DAC channel 1 |
||
1234 | * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 |
||
1235 | * @param DACx DAC instance |
||
1236 | * @retval None |
||
1237 | */ |
||
1238 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) |
||
1239 | { |
||
1240 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
||
1241 | } |
||
1242 | #endif /* DAC_CR_DMAUDRIE1 */ |
||
1243 | |||
1244 | #if defined(DAC_CR_DMAUDRIE2) |
||
1245 | /** |
||
1246 | * @brief Enable DMA underrun interrupt for DAC channel 2 |
||
1247 | * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 |
||
1248 | * @param DACx DAC instance |
||
1249 | * @retval None |
||
1250 | */ |
||
1251 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) |
||
1252 | { |
||
1253 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
||
1254 | } |
||
1255 | #endif /* DAC_CR_DMAUDRIE2 */ |
||
1256 | |||
1257 | #if defined(DAC_CR_DMAUDRIE1) |
||
1258 | /** |
||
1259 | * @brief Disable DMA underrun interrupt for DAC channel 1 |
||
1260 | * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 |
||
1261 | * @param DACx DAC instance |
||
1262 | * @retval None |
||
1263 | */ |
||
1264 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) |
||
1265 | { |
||
1266 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
||
1267 | } |
||
1268 | #endif /* DAC_CR_DMAUDRIE1 */ |
||
1269 | |||
1270 | #if defined(DAC_CR_DMAUDRIE2) |
||
1271 | /** |
||
1272 | * @brief Disable DMA underrun interrupt for DAC channel 2 |
||
1273 | * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 |
||
1274 | * @param DACx DAC instance |
||
1275 | * @retval None |
||
1276 | */ |
||
1277 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) |
||
1278 | { |
||
1279 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
||
1280 | } |
||
1281 | #endif /* DAC_CR_DMAUDRIE2 */ |
||
1282 | |||
1283 | #if defined(DAC_CR_DMAUDRIE1) |
||
1284 | /** |
||
1285 | * @brief Get DMA underrun interrupt for DAC channel 1 |
||
1286 | * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 |
||
1287 | * @param DACx DAC instance |
||
1288 | * @retval State of bit (1 or 0). |
||
1289 | */ |
||
1290 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) |
||
1291 | { |
||
1292 | return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); |
||
1293 | } |
||
1294 | #endif /* DAC_CR_DMAUDRIE1 */ |
||
1295 | |||
1296 | #if defined(DAC_CR_DMAUDRIE2) |
||
1297 | /** |
||
1298 | * @brief Get DMA underrun interrupt for DAC channel 2 |
||
1299 | * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 |
||
1300 | * @param DACx DAC instance |
||
1301 | * @retval State of bit (1 or 0). |
||
1302 | */ |
||
1303 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) |
||
1304 | { |
||
1305 | return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); |
||
1306 | } |
||
1307 | #endif /* DAC_CR_DMAUDRIE2 */ |
||
1308 | |||
1309 | /** |
||
1310 | * @} |
||
1311 | */ |
||
1312 | |||
1313 | #if defined(USE_FULL_LL_DRIVER) |
||
1314 | /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions |
||
1315 | * @{ |
||
1316 | */ |
||
1317 | |||
1318 | ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); |
||
1319 | ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); |
||
1320 | void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); |
||
1321 | |||
1322 | /** |
||
1323 | * @} |
||
1324 | */ |
||
1325 | #endif /* USE_FULL_LL_DRIVER */ |
||
1326 | |||
1327 | /** |
||
1328 | * @} |
||
1329 | */ |
||
1330 | |||
1331 | /** |
||
1332 | * @} |
||
1333 | */ |
||
1334 | |||
1335 | #endif /* DAC */ |
||
1336 | |||
1337 | /** |
||
1338 | * @} |
||
1339 | */ |
||
1340 | |||
1341 | #ifdef __cplusplus |
||
1342 | } |
||
1343 | #endif |
||
1344 | |||
1345 | #endif /* __STM32F1xx_LL_DAC_H */ |
||
1346 | |||
1347 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |