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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_cortex.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of CORTEX LL module. |
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| 6 | @verbatim |
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| 7 | ============================================================================== |
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| 8 | ##### How to use this driver ##### |
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| 9 | ============================================================================== |
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| 10 | [..] |
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| 11 | The LL CORTEX driver contains a set of generic APIs that can be |
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| 12 | used by user: |
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| 13 | (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick |
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| 14 | functions |
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| 15 | (+) Low power mode configuration (SCB register of Cortex-MCU) |
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| 16 | (+) MPU API to configure and enable regions |
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| 17 | (MPU services provided only on some devices) |
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| 18 | (+) API to access to MCU info (CPUID register) |
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| 19 | (+) API to enable fault handler (SHCSR accesses) |
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| 20 | |||
| 21 | @endverbatim |
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| 22 | ****************************************************************************** |
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| 23 | * @attention |
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| 24 | * |
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| 25 | * Copyright (c) 2017 STMicroelectronics. |
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| 26 | * All rights reserved. |
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| 27 | * |
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| 28 | * This software is licensed under terms that can be found in the LICENSE file in |
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| 29 | * the root directory of this software component. |
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| 30 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 31 | * |
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| 32 | ****************************************************************************** |
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| 33 | */ |
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| 34 | |||
| 35 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 36 | #ifndef __STM32F1xx_LL_CORTEX_H |
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| 37 | #define __STM32F1xx_LL_CORTEX_H |
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| 38 | |||
| 39 | #ifdef __cplusplus |
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| 40 | extern "C" { |
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| 41 | #endif |
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| 42 | |||
| 43 | /* Includes ------------------------------------------------------------------*/ |
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| 44 | #include "stm32f1xx.h" |
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| 45 | |||
| 46 | /** @addtogroup STM32F1xx_LL_Driver |
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| 47 | * @{ |
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| 48 | */ |
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| 49 | |||
| 50 | /** @defgroup CORTEX_LL CORTEX |
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| 51 | * @{ |
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| 52 | */ |
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| 53 | |||
| 54 | /* Private types -------------------------------------------------------------*/ |
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| 55 | /* Private variables ---------------------------------------------------------*/ |
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| 56 | |||
| 57 | /* Private constants ---------------------------------------------------------*/ |
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| 58 | |||
| 59 | /* Private macros ------------------------------------------------------------*/ |
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| 60 | |||
| 61 | /* Exported types ------------------------------------------------------------*/ |
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| 62 | /* Exported constants --------------------------------------------------------*/ |
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| 63 | /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants |
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| 64 | * @{ |
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| 65 | */ |
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| 66 | |||
| 67 | /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source |
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| 68 | * @{ |
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| 69 | */ |
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| 70 | #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ |
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| 71 | #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ |
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| 72 | /** |
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| 73 | * @} |
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| 74 | */ |
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| 75 | |||
| 76 | /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type |
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| 77 | * @{ |
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| 78 | */ |
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| 79 | #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ |
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| 80 | #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ |
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| 81 | #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ |
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| 82 | /** |
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| 83 | * @} |
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| 84 | */ |
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| 85 | |||
| 86 | #if __MPU_PRESENT |
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| 87 | |||
| 88 | /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control |
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| 89 | * @{ |
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| 90 | */ |
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| 91 | #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ |
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| 92 | #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ |
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| 93 | #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ |
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| 94 | #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ |
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| 95 | /** |
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| 96 | * @} |
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| 97 | */ |
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| 98 | |||
| 99 | /** @defgroup CORTEX_LL_EC_REGION MPU Region Number |
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| 100 | * @{ |
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| 101 | */ |
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| 102 | #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ |
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| 103 | #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ |
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| 104 | #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ |
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| 105 | #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ |
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| 106 | #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ |
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| 107 | #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ |
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| 108 | #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ |
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| 109 | #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ |
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| 110 | /** |
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| 111 | * @} |
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| 112 | */ |
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| 113 | |||
| 114 | /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size |
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| 115 | * @{ |
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| 116 | */ |
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| 117 | #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ |
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| 118 | #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ |
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| 119 | #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ |
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| 120 | #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ |
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| 121 | #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ |
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| 122 | #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ |
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| 123 | #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ |
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| 124 | #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ |
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| 125 | #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ |
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| 126 | #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ |
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| 127 | #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ |
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| 128 | #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ |
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| 129 | #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ |
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| 130 | #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ |
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| 131 | #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ |
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| 132 | #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ |
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| 133 | #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ |
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| 134 | #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ |
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| 135 | #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ |
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| 136 | #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ |
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| 137 | #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ |
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| 138 | #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ |
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| 139 | #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ |
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| 140 | #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ |
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| 141 | #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ |
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| 142 | #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ |
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| 143 | #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ |
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| 144 | #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ |
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| 145 | /** |
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| 146 | * @} |
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| 147 | */ |
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| 148 | |||
| 149 | /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges |
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| 150 | * @{ |
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| 151 | */ |
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| 152 | #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ |
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| 153 | #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ |
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| 154 | #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ |
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| 155 | #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ |
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| 156 | #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ |
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| 157 | #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ |
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| 158 | /** |
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| 159 | * @} |
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| 160 | */ |
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| 161 | |||
| 162 | /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level |
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| 163 | * @{ |
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| 164 | */ |
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| 165 | #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ |
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| 166 | #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ |
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| 167 | #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ |
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| 168 | #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ |
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| 169 | /** |
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| 170 | * @} |
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| 171 | */ |
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| 172 | |||
| 173 | /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access |
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| 174 | * @{ |
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| 175 | */ |
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| 176 | #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ |
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| 177 | #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ |
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| 178 | /** |
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| 179 | * @} |
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| 180 | */ |
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| 181 | |||
| 182 | /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access |
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| 183 | * @{ |
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| 184 | */ |
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| 185 | #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ |
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| 186 | #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ |
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| 187 | /** |
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| 188 | * @} |
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| 189 | */ |
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| 190 | |||
| 191 | /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access |
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| 192 | * @{ |
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| 193 | */ |
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| 194 | #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ |
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| 195 | #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ |
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| 196 | /** |
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| 197 | * @} |
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| 198 | */ |
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| 199 | |||
| 200 | /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access |
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| 201 | * @{ |
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| 202 | */ |
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| 203 | #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ |
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| 204 | #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ |
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| 205 | /** |
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| 206 | * @} |
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| 207 | */ |
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| 208 | #endif /* __MPU_PRESENT */ |
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| 209 | /** |
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| 210 | * @} |
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| 211 | */ |
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| 212 | |||
| 213 | /* Exported macro ------------------------------------------------------------*/ |
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| 214 | |||
| 215 | /* Exported functions --------------------------------------------------------*/ |
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| 216 | /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions |
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| 217 | * @{ |
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| 218 | */ |
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| 219 | |||
| 220 | /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK |
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| 221 | * @{ |
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| 222 | */ |
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| 223 | |||
| 224 | /** |
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| 225 | * @brief This function checks if the Systick counter flag is active or not. |
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| 226 | * @note It can be used in timeout function on application side. |
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| 227 | * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag |
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| 228 | * @retval State of bit (1 or 0). |
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| 229 | */ |
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| 230 | __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) |
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| 231 | { |
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| 232 | return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); |
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| 233 | } |
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| 234 | |||
| 235 | /** |
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| 236 | * @brief Configures the SysTick clock source |
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| 237 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource |
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| 238 | * @param Source This parameter can be one of the following values: |
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| 239 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
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| 240 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
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| 241 | * @retval None |
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| 242 | */ |
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| 243 | __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) |
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| 244 | { |
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| 245 | if (Source == LL_SYSTICK_CLKSOURCE_HCLK) |
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| 246 | { |
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| 247 | SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
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| 248 | } |
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| 249 | else |
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| 250 | { |
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| 251 | CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
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| 252 | } |
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| 253 | } |
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| 254 | |||
| 255 | /** |
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| 256 | * @brief Get the SysTick clock source |
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| 257 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource |
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| 258 | * @retval Returned value can be one of the following values: |
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| 259 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
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| 260 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
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| 261 | */ |
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| 262 | __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) |
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| 263 | { |
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| 264 | return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
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| 265 | } |
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| 266 | |||
| 267 | /** |
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| 268 | * @brief Enable SysTick exception request |
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| 269 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT |
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| 270 | * @retval None |
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| 271 | */ |
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| 272 | __STATIC_INLINE void LL_SYSTICK_EnableIT(void) |
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| 273 | { |
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| 274 | SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
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| 275 | } |
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| 276 | |||
| 277 | /** |
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| 278 | * @brief Disable SysTick exception request |
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| 279 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT |
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| 280 | * @retval None |
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| 281 | */ |
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| 282 | __STATIC_INLINE void LL_SYSTICK_DisableIT(void) |
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| 283 | { |
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| 284 | CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
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| 285 | } |
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| 286 | |||
| 287 | /** |
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| 288 | * @brief Checks if the SYSTICK interrupt is enabled or disabled. |
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| 289 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT |
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| 290 | * @retval State of bit (1 or 0). |
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| 291 | */ |
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| 292 | __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) |
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| 293 | { |
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| 294 | return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); |
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| 295 | } |
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| 296 | |||
| 297 | /** |
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| 298 | * @} |
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| 299 | */ |
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| 300 | |||
| 301 | /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE |
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| 302 | * @{ |
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| 303 | */ |
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| 304 | |||
| 305 | /** |
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| 306 | * @brief Processor uses sleep as its low power mode |
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| 307 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep |
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| 308 | * @retval None |
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| 309 | */ |
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| 310 | __STATIC_INLINE void LL_LPM_EnableSleep(void) |
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| 311 | { |
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| 312 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
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| 313 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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| 314 | } |
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| 315 | |||
| 316 | /** |
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| 317 | * @brief Processor uses deep sleep as its low power mode |
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| 318 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep |
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| 319 | * @retval None |
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| 320 | */ |
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| 321 | __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) |
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| 322 | { |
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| 323 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
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| 324 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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| 325 | } |
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| 326 | |||
| 327 | /** |
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| 328 | * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. |
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| 329 | * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an |
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| 330 | * empty main application. |
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| 331 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit |
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| 332 | * @retval None |
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| 333 | */ |
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| 334 | __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) |
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| 335 | { |
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| 336 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
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| 337 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
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| 338 | } |
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| 339 | |||
| 340 | /** |
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| 341 | * @brief Do not sleep when returning to Thread mode. |
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| 342 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit |
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| 343 | * @retval None |
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| 344 | */ |
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| 345 | __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) |
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| 346 | { |
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| 347 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
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| 348 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
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| 349 | } |
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| 350 | |||
| 351 | /** |
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| 352 | * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the |
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| 353 | * processor. |
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| 354 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend |
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| 355 | * @retval None |
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| 356 | */ |
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| 357 | __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) |
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| 358 | { |
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| 359 | /* Set SEVEONPEND bit of Cortex System Control Register */ |
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| 360 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
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| 361 | } |
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| 362 | |||
| 363 | /** |
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| 364 | * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are |
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| 365 | * excluded |
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| 366 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend |
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| 367 | * @retval None |
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| 368 | */ |
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| 369 | __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) |
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| 370 | { |
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| 371 | /* Clear SEVEONPEND bit of Cortex System Control Register */ |
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| 372 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
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| 373 | } |
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| 374 | |||
| 375 | /** |
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| 376 | * @} |
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| 377 | */ |
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| 378 | |||
| 379 | /** @defgroup CORTEX_LL_EF_HANDLER HANDLER |
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| 380 | * @{ |
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| 381 | */ |
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| 382 | |||
| 383 | /** |
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| 384 | * @brief Enable a fault in System handler control register (SHCSR) |
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| 385 | * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault |
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| 386 | * @param Fault This parameter can be a combination of the following values: |
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| 387 | * @arg @ref LL_HANDLER_FAULT_USG |
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| 388 | * @arg @ref LL_HANDLER_FAULT_BUS |
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| 389 | * @arg @ref LL_HANDLER_FAULT_MEM |
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| 390 | * @retval None |
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| 391 | */ |
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| 392 | __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) |
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| 393 | { |
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| 394 | /* Enable the system handler fault */ |
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| 395 | SET_BIT(SCB->SHCSR, Fault); |
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| 396 | } |
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| 397 | |||
| 398 | /** |
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| 399 | * @brief Disable a fault in System handler control register (SHCSR) |
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| 400 | * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault |
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| 401 | * @param Fault This parameter can be a combination of the following values: |
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| 402 | * @arg @ref LL_HANDLER_FAULT_USG |
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| 403 | * @arg @ref LL_HANDLER_FAULT_BUS |
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| 404 | * @arg @ref LL_HANDLER_FAULT_MEM |
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| 405 | * @retval None |
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| 406 | */ |
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| 407 | __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) |
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| 408 | { |
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| 409 | /* Disable the system handler fault */ |
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| 410 | CLEAR_BIT(SCB->SHCSR, Fault); |
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| 411 | } |
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| 412 | |||
| 413 | /** |
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| 414 | * @} |
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| 415 | */ |
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| 416 | |||
| 417 | /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO |
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| 418 | * @{ |
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| 419 | */ |
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| 420 | |||
| 421 | /** |
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| 422 | * @brief Get Implementer code |
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| 423 | * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer |
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| 424 | * @retval Value should be equal to 0x41 for ARM |
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| 425 | */ |
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| 426 | __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) |
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| 427 | { |
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| 428 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); |
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| 429 | } |
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| 430 | |||
| 431 | /** |
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| 432 | * @brief Get Variant number (The r value in the rnpn product revision identifier) |
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| 433 | * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant |
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| 434 | * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2) |
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| 435 | */ |
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| 436 | __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) |
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| 437 | { |
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| 438 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); |
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| 439 | } |
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| 440 | |||
| 441 | /** |
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| 442 | * @brief Get Constant number |
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| 443 | * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant |
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| 444 | * @retval Value should be equal to 0xF for Cortex-M3 devices |
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| 445 | */ |
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| 446 | __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) |
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| 447 | { |
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| 448 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); |
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| 449 | } |
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| 450 | |||
| 451 | /** |
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| 452 | * @brief Get Part number |
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| 453 | * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo |
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| 454 | * @retval Value should be equal to 0xC23 for Cortex-M3 |
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| 455 | */ |
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| 456 | __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) |
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| 457 | { |
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| 458 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); |
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| 459 | } |
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| 460 | |||
| 461 | /** |
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| 462 | * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) |
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| 463 | * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision |
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| 464 | * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1) |
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| 465 | */ |
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| 466 | __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) |
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| 467 | { |
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| 468 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); |
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| 469 | } |
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| 470 | |||
| 471 | /** |
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| 472 | * @} |
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| 473 | */ |
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| 474 | |||
| 475 | #if __MPU_PRESENT |
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| 476 | /** @defgroup CORTEX_LL_EF_MPU MPU |
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| 477 | * @{ |
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| 478 | */ |
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| 479 | |||
| 480 | /** |
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| 481 | * @brief Enable MPU with input options |
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| 482 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable |
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| 483 | * @param Options This parameter can be one of the following values: |
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| 484 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE |
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| 485 | * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI |
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| 486 | * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT |
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| 487 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF |
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| 488 | * @retval None |
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| 489 | */ |
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| 490 | __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) |
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| 491 | { |
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| 492 | /* Enable the MPU*/ |
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| 493 | WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); |
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| 494 | /* Ensure MPU settings take effects */ |
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| 495 | __DSB(); |
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| 496 | /* Sequence instruction fetches using update settings */ |
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| 497 | __ISB(); |
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| 498 | } |
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| 499 | |||
| 500 | /** |
||
| 501 | * @brief Disable MPU |
||
| 502 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable |
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| 503 | * @retval None |
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| 504 | */ |
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| 505 | __STATIC_INLINE void LL_MPU_Disable(void) |
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| 506 | { |
||
| 507 | /* Make sure outstanding transfers are done */ |
||
| 508 | __DMB(); |
||
| 509 | /* Disable MPU*/ |
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| 510 | WRITE_REG(MPU->CTRL, 0U); |
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| 511 | } |
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| 512 | |||
| 513 | /** |
||
| 514 | * @brief Check if MPU is enabled or not |
||
| 515 | * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled |
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| 516 | * @retval State of bit (1 or 0). |
||
| 517 | */ |
||
| 518 | __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) |
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| 519 | { |
||
| 520 | return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); |
||
| 521 | } |
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| 522 | |||
| 523 | /** |
||
| 524 | * @brief Enable a MPU region |
||
| 525 | * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion |
||
| 526 | * @param Region This parameter can be one of the following values: |
||
| 527 | * @arg @ref LL_MPU_REGION_NUMBER0 |
||
| 528 | * @arg @ref LL_MPU_REGION_NUMBER1 |
||
| 529 | * @arg @ref LL_MPU_REGION_NUMBER2 |
||
| 530 | * @arg @ref LL_MPU_REGION_NUMBER3 |
||
| 531 | * @arg @ref LL_MPU_REGION_NUMBER4 |
||
| 532 | * @arg @ref LL_MPU_REGION_NUMBER5 |
||
| 533 | * @arg @ref LL_MPU_REGION_NUMBER6 |
||
| 534 | * @arg @ref LL_MPU_REGION_NUMBER7 |
||
| 535 | * @retval None |
||
| 536 | */ |
||
| 537 | __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) |
||
| 538 | { |
||
| 539 | /* Set Region number */ |
||
| 540 | WRITE_REG(MPU->RNR, Region); |
||
| 541 | /* Enable the MPU region */ |
||
| 542 | SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
||
| 543 | } |
||
| 544 | |||
| 545 | /** |
||
| 546 | * @brief Configure and enable a region |
||
| 547 | * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n |
||
| 548 | * MPU_RBAR REGION LL_MPU_ConfigRegion\n |
||
| 549 | * MPU_RBAR ADDR LL_MPU_ConfigRegion\n |
||
| 550 | * MPU_RASR XN LL_MPU_ConfigRegion\n |
||
| 551 | * MPU_RASR AP LL_MPU_ConfigRegion\n |
||
| 552 | * MPU_RASR S LL_MPU_ConfigRegion\n |
||
| 553 | * MPU_RASR C LL_MPU_ConfigRegion\n |
||
| 554 | * MPU_RASR B LL_MPU_ConfigRegion\n |
||
| 555 | * MPU_RASR SIZE LL_MPU_ConfigRegion |
||
| 556 | * @param Region This parameter can be one of the following values: |
||
| 557 | * @arg @ref LL_MPU_REGION_NUMBER0 |
||
| 558 | * @arg @ref LL_MPU_REGION_NUMBER1 |
||
| 559 | * @arg @ref LL_MPU_REGION_NUMBER2 |
||
| 560 | * @arg @ref LL_MPU_REGION_NUMBER3 |
||
| 561 | * @arg @ref LL_MPU_REGION_NUMBER4 |
||
| 562 | * @arg @ref LL_MPU_REGION_NUMBER5 |
||
| 563 | * @arg @ref LL_MPU_REGION_NUMBER6 |
||
| 564 | * @arg @ref LL_MPU_REGION_NUMBER7 |
||
| 565 | * @param Address Value of region base address |
||
| 566 | * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF |
||
| 567 | * @param Attributes This parameter can be a combination of the following values: |
||
| 568 | * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B |
||
| 569 | * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB |
||
| 570 | * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB |
||
| 571 | * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB |
||
| 572 | * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB |
||
| 573 | * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB |
||
| 574 | * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS |
||
| 575 | * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO |
||
| 576 | * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 |
||
| 577 | * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE |
||
| 578 | * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE |
||
| 579 | * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE |
||
| 580 | * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE |
||
| 581 | * @retval None |
||
| 582 | */ |
||
| 583 | __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) |
||
| 584 | { |
||
| 585 | /* Set Region number */ |
||
| 586 | WRITE_REG(MPU->RNR, Region); |
||
| 587 | /* Set base address */ |
||
| 588 | WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); |
||
| 589 | /* Configure MPU */ |
||
| 590 | WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); |
||
| 591 | } |
||
| 592 | |||
| 593 | /** |
||
| 594 | * @brief Disable a region |
||
| 595 | * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n |
||
| 596 | * MPU_RASR ENABLE LL_MPU_DisableRegion |
||
| 597 | * @param Region This parameter can be one of the following values: |
||
| 598 | * @arg @ref LL_MPU_REGION_NUMBER0 |
||
| 599 | * @arg @ref LL_MPU_REGION_NUMBER1 |
||
| 600 | * @arg @ref LL_MPU_REGION_NUMBER2 |
||
| 601 | * @arg @ref LL_MPU_REGION_NUMBER3 |
||
| 602 | * @arg @ref LL_MPU_REGION_NUMBER4 |
||
| 603 | * @arg @ref LL_MPU_REGION_NUMBER5 |
||
| 604 | * @arg @ref LL_MPU_REGION_NUMBER6 |
||
| 605 | * @arg @ref LL_MPU_REGION_NUMBER7 |
||
| 606 | * @retval None |
||
| 607 | */ |
||
| 608 | __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) |
||
| 609 | { |
||
| 610 | /* Set Region number */ |
||
| 611 | WRITE_REG(MPU->RNR, Region); |
||
| 612 | /* Disable the MPU region */ |
||
| 613 | CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
||
| 614 | } |
||
| 615 | |||
| 616 | /** |
||
| 617 | * @} |
||
| 618 | */ |
||
| 619 | |||
| 620 | #endif /* __MPU_PRESENT */ |
||
| 621 | /** |
||
| 622 | * @} |
||
| 623 | */ |
||
| 624 | |||
| 625 | /** |
||
| 626 | * @} |
||
| 627 | */ |
||
| 628 | |||
| 629 | /** |
||
| 630 | * @} |
||
| 631 | */ |
||
| 632 | |||
| 633 | #ifdef __cplusplus |
||
| 634 | } |
||
| 635 | #endif |
||
| 636 | |||
| 637 | #endif /* __STM32F1xx_LL_CORTEX_H */ |
||
| 638 |