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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_bus.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of BUS LL module. |
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| 6 | |||
| 7 | @verbatim |
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| 8 | ##### RCC Limitations ##### |
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| 9 | ============================================================================== |
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| 10 | [..] |
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| 11 | A delay between an RCC peripheral clock enable and the effective peripheral |
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| 12 | enabling should be taken into account in order to manage the peripheral read/write |
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| 13 | from/to registers. |
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| 14 | (+) This delay depends on the peripheral mapping. |
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| 15 | (++) AHB & APB peripherals, 1 dummy read is necessary |
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| 16 | |||
| 17 | [..] |
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| 18 | Workarounds: |
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| 19 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
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| 20 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
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| 21 | |||
| 22 | @endverbatim |
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| 23 | ****************************************************************************** |
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| 24 | * @attention |
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| 25 | * |
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| 26 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 27 | * All rights reserved.</center></h2> |
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| 28 | * |
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| 29 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 30 | * the "License"; You may not use this file except in compliance with the |
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| 31 | * License. You may obtain a copy of the License at: |
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| 32 | * opensource.org/licenses/BSD-3-Clause |
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| 33 | * |
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| 34 | ****************************************************************************** |
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| 35 | */ |
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| 36 | |||
| 37 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 38 | #ifndef __STM32F1xx_LL_BUS_H |
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| 39 | #define __STM32F1xx_LL_BUS_H |
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| 40 | |||
| 41 | #ifdef __cplusplus |
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| 42 | extern "C" { |
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| 43 | #endif |
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| 44 | |||
| 45 | /* Includes ------------------------------------------------------------------*/ |
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| 46 | #include "stm32f1xx.h" |
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| 47 | |||
| 48 | /** @addtogroup STM32F1xx_LL_Driver |
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| 49 | * @{ |
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| 50 | */ |
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| 51 | |||
| 52 | #if defined(RCC) |
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| 53 | |||
| 54 | /** @defgroup BUS_LL BUS |
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| 55 | * @{ |
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| 56 | */ |
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| 57 | |||
| 58 | /* Private types -------------------------------------------------------------*/ |
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| 59 | /* Private variables ---------------------------------------------------------*/ |
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| 60 | |||
| 61 | /* Private constants ---------------------------------------------------------*/ |
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| 62 | #if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST) |
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| 63 | #define RCC_AHBRSTR_SUPPORT |
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| 64 | #endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */ |
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| 65 | |||
| 66 | /* Private macros ------------------------------------------------------------*/ |
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| 67 | |||
| 68 | /* Exported types ------------------------------------------------------------*/ |
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| 69 | /* Exported constants --------------------------------------------------------*/ |
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| 70 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
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| 71 | * @{ |
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| 72 | */ |
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| 73 | |||
| 74 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
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| 75 | * @{ |
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| 76 | */ |
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| 77 | #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
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| 78 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN |
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| 79 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN |
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| 80 | #if defined(DMA2) |
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| 81 | #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN |
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| 82 | #endif /*DMA2*/ |
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| 83 | #if defined(ETH) |
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| 84 | #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN |
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| 85 | #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN |
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| 86 | #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN |
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| 87 | #endif /*ETH*/ |
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| 88 | #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN |
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| 89 | #if defined(FSMC_Bank1) |
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| 90 | #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN |
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| 91 | #endif /*FSMC_Bank1*/ |
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| 92 | #if defined(USB_OTG_FS) |
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| 93 | #define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN |
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| 94 | #endif /*USB_OTG_FS*/ |
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| 95 | #if defined(SDIO) |
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| 96 | #define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN |
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| 97 | #endif /*SDIO*/ |
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| 98 | #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN |
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| 99 | /** |
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| 100 | * @} |
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| 101 | */ |
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| 102 | |||
| 103 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
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| 104 | * @{ |
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| 105 | */ |
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| 106 | #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
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| 107 | #define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN |
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| 108 | #if defined(CAN1) |
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| 109 | #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN |
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| 110 | #endif /*CAN1*/ |
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| 111 | #if defined(CAN2) |
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| 112 | #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN |
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| 113 | #endif /*CAN2*/ |
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| 114 | #if defined(CEC) |
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| 115 | #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN |
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| 116 | #endif /*CEC*/ |
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| 117 | #if defined(DAC) |
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| 118 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN |
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| 119 | #endif /*DAC*/ |
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| 120 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN |
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| 121 | #if defined(I2C2) |
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| 122 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN |
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| 123 | #endif /*I2C2*/ |
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| 124 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN |
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| 125 | #if defined(SPI2) |
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| 126 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN |
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| 127 | #endif /*SPI2*/ |
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| 128 | #if defined(SPI3) |
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| 129 | #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN |
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| 130 | #endif /*SPI3*/ |
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| 131 | #if defined(TIM12) |
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| 132 | #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN |
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| 133 | #endif /*TIM12*/ |
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| 134 | #if defined(TIM13) |
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| 135 | #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN |
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| 136 | #endif /*TIM13*/ |
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| 137 | #if defined(TIM14) |
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| 138 | #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN |
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| 139 | #endif /*TIM14*/ |
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| 140 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN |
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| 141 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN |
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| 142 | #if defined(TIM4) |
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| 143 | #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN |
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| 144 | #endif /*TIM4*/ |
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| 145 | #if defined(TIM5) |
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| 146 | #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN |
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| 147 | #endif /*TIM5*/ |
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| 148 | #if defined(TIM6) |
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| 149 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN |
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| 150 | #endif /*TIM6*/ |
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| 151 | #if defined(TIM7) |
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| 152 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN |
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| 153 | #endif /*TIM7*/ |
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| 154 | #if defined(UART4) |
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| 155 | #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN |
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| 156 | #endif /*UART4*/ |
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| 157 | #if defined(UART5) |
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| 158 | #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN |
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| 159 | #endif /*UART5*/ |
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| 160 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN |
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| 161 | #if defined(USART3) |
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| 162 | #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN |
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| 163 | #endif /*USART3*/ |
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| 164 | #if defined(USB) |
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| 165 | #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN |
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| 166 | #endif /*USB*/ |
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| 167 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN |
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| 168 | /** |
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| 169 | * @} |
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| 170 | */ |
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| 171 | |||
| 172 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
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| 173 | * @{ |
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| 174 | */ |
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| 175 | #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
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| 176 | #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN |
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| 177 | #if defined(ADC2) |
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| 178 | #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN |
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| 179 | #endif /*ADC2*/ |
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| 180 | #if defined(ADC3) |
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| 181 | #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN |
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| 182 | #endif /*ADC3*/ |
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| 183 | #define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN |
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| 184 | #define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN |
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| 185 | #define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN |
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| 186 | #define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN |
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| 187 | #define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN |
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| 188 | #if defined(GPIOE) |
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| 189 | #define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN |
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| 190 | #endif /*GPIOE*/ |
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| 191 | #if defined(GPIOF) |
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| 192 | #define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN |
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| 193 | #endif /*GPIOF*/ |
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| 194 | #if defined(GPIOG) |
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| 195 | #define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN |
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| 196 | #endif /*GPIOG*/ |
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| 197 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN |
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| 198 | #if defined(TIM10) |
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| 199 | #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN |
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| 200 | #endif /*TIM10*/ |
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| 201 | #if defined(TIM11) |
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| 202 | #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN |
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| 203 | #endif /*TIM11*/ |
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| 204 | #if defined(TIM15) |
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| 205 | #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN |
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| 206 | #endif /*TIM15*/ |
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| 207 | #if defined(TIM16) |
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| 208 | #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN |
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| 209 | #endif /*TIM16*/ |
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| 210 | #if defined(TIM17) |
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| 211 | #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN |
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| 212 | #endif /*TIM17*/ |
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| 213 | #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN |
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| 214 | #if defined(TIM8) |
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| 215 | #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN |
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| 216 | #endif /*TIM8*/ |
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| 217 | #if defined(TIM9) |
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| 218 | #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN |
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| 219 | #endif /*TIM9*/ |
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| 220 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN |
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| 221 | /** |
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| 222 | * @} |
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| 223 | */ |
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| 224 | |||
| 225 | /** |
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| 226 | * @} |
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| 227 | */ |
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| 228 | |||
| 229 | /* Exported macro ------------------------------------------------------------*/ |
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| 230 | |||
| 231 | /* Exported functions --------------------------------------------------------*/ |
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| 232 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
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| 233 | * @{ |
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| 234 | */ |
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| 235 | |||
| 236 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
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| 237 | * @{ |
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| 238 | */ |
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| 239 | |||
| 240 | /** |
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| 241 | * @brief Enable AHB1 peripherals clock. |
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| 242 | * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n |
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| 243 | * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n |
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| 244 | * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n |
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| 245 | * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n |
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| 246 | * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n |
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| 247 | * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n |
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| 248 | * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n |
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| 249 | * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n |
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| 250 | * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n |
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| 251 | * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n |
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| 252 | * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock |
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| 253 | * @param Periphs This parameter can be a combination of the following values: |
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| 254 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
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| 255 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
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| 256 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
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| 257 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
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| 258 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
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| 259 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
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| 260 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
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| 261 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
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| 262 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) |
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| 263 | * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) |
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| 264 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
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| 265 | * |
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| 266 | * (*) value not defined in all devices. |
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| 267 | * @retval None |
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| 268 | */ |
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| 269 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
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| 270 | { |
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| 271 | __IO uint32_t tmpreg; |
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| 272 | SET_BIT(RCC->AHBENR, Periphs); |
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| 273 | /* Delay after an RCC peripheral clock enabling */ |
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| 274 | tmpreg = READ_BIT(RCC->AHBENR, Periphs); |
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| 275 | (void)tmpreg; |
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| 276 | } |
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| 277 | |||
| 278 | /** |
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| 279 | * @brief Check if AHB1 peripheral clock is enabled or not |
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| 280 | * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
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| 281 | * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n |
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| 282 | * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n |
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| 283 | * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n |
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| 284 | * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n |
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| 285 | * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n |
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| 286 | * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n |
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| 287 | * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n |
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| 288 | * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n |
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| 289 | * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n |
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| 290 | * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock |
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| 291 | * @param Periphs This parameter can be a combination of the following values: |
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| 292 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
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| 293 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
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| 294 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
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| 295 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
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| 296 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
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| 297 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
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| 298 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
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| 299 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
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| 300 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) |
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| 301 | * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) |
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| 302 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
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| 303 | * |
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| 304 | * (*) value not defined in all devices. |
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| 305 | * @retval State of Periphs (1 or 0). |
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| 306 | */ |
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| 307 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
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| 308 | { |
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| 309 | return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); |
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| 310 | } |
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| 311 | |||
| 312 | /** |
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| 313 | * @brief Disable AHB1 peripherals clock. |
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| 314 | * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n |
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| 315 | * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n |
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| 316 | * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n |
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| 317 | * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n |
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| 318 | * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n |
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| 319 | * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n |
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| 320 | * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n |
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| 321 | * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n |
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| 322 | * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n |
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| 323 | * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n |
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| 324 | * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock |
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| 325 | * @param Periphs This parameter can be a combination of the following values: |
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| 326 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
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| 327 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
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| 328 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
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| 329 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
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| 330 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
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| 331 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
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| 332 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
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| 333 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
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| 334 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) |
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| 335 | * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) |
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| 336 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
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| 337 | * |
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| 338 | * (*) value not defined in all devices. |
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| 339 | * @retval None |
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| 340 | */ |
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| 341 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
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| 342 | { |
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| 343 | CLEAR_BIT(RCC->AHBENR, Periphs); |
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| 344 | } |
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| 345 | |||
| 346 | #if defined(RCC_AHBRSTR_SUPPORT) |
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| 347 | /** |
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| 348 | * @brief Force AHB1 peripherals reset. |
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| 349 | * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n |
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| 350 | * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset |
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| 351 | * @param Periphs This parameter can be a combination of the following values: |
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| 352 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
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| 353 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
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| 354 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) |
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| 355 | * |
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| 356 | * (*) value not defined in all devices. |
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| 357 | * @retval None |
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| 358 | */ |
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| 359 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
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| 360 | { |
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| 361 | SET_BIT(RCC->AHBRSTR, Periphs); |
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| 362 | } |
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| 363 | |||
| 364 | /** |
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| 365 | * @brief Release AHB1 peripherals reset. |
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| 366 | * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n |
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| 367 | * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset |
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| 368 | * @param Periphs This parameter can be a combination of the following values: |
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| 369 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
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| 370 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
||
| 371 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) |
||
| 372 | * |
||
| 373 | * (*) value not defined in all devices. |
||
| 374 | * @retval None |
||
| 375 | */ |
||
| 376 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
||
| 377 | { |
||
| 378 | CLEAR_BIT(RCC->AHBRSTR, Periphs); |
||
| 379 | } |
||
| 380 | #endif /* RCC_AHBRSTR_SUPPORT */ |
||
| 381 | |||
| 382 | /** |
||
| 383 | * @} |
||
| 384 | */ |
||
| 385 | |||
| 386 | /** @defgroup BUS_LL_EF_APB1 APB1 |
||
| 387 | * @{ |
||
| 388 | */ |
||
| 389 | |||
| 390 | /** |
||
| 391 | * @brief Enable APB1 peripherals clock. |
||
| 392 | * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n |
||
| 393 | * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n |
||
| 394 | * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n |
||
| 395 | * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n |
||
| 396 | * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n |
||
| 397 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
||
| 398 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
||
| 399 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
||
| 400 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
||
| 401 | * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n |
||
| 402 | * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n |
||
| 403 | * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n |
||
| 404 | * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n |
||
| 405 | * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
||
| 406 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
||
| 407 | * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n |
||
| 408 | * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n |
||
| 409 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
||
| 410 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
||
| 411 | * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n |
||
| 412 | * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n |
||
| 413 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
||
| 414 | * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n |
||
| 415 | * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n |
||
| 416 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock |
||
| 417 | * @param Periphs This parameter can be a combination of the following values: |
||
| 418 | * @arg @ref LL_APB1_GRP1_PERIPH_BKP |
||
| 419 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
||
| 420 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
||
| 421 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
||
| 422 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
||
| 423 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
||
| 424 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
||
| 425 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
||
| 426 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
||
| 427 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
||
| 428 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
||
| 429 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
||
| 430 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
||
| 431 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
||
| 432 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
||
| 433 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
||
| 434 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
||
| 435 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
||
| 436 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
||
| 437 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
||
| 438 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
||
| 439 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
||
| 440 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
||
| 441 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
||
| 442 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
||
| 443 | * |
||
| 444 | * (*) value not defined in all devices. |
||
| 445 | * @retval None |
||
| 446 | */ |
||
| 447 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
||
| 448 | { |
||
| 449 | __IO uint32_t tmpreg; |
||
| 450 | SET_BIT(RCC->APB1ENR, Periphs); |
||
| 451 | /* Delay after an RCC peripheral clock enabling */ |
||
| 452 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
||
| 453 | (void)tmpreg; |
||
| 454 | } |
||
| 455 | |||
| 456 | /** |
||
| 457 | * @brief Check if APB1 peripheral clock is enabled or not |
||
| 458 | * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n |
||
| 459 | * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 460 | * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 461 | * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n |
||
| 462 | * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n |
||
| 463 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 464 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 465 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
||
| 466 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 467 | * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 468 | * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 469 | * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 470 | * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 471 | * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 472 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 473 | * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 474 | * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 475 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 476 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 477 | * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 478 | * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 479 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 480 | * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n |
||
| 481 | * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n |
||
| 482 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock |
||
| 483 | * @param Periphs This parameter can be a combination of the following values: |
||
| 484 | * @arg @ref LL_APB1_GRP1_PERIPH_BKP |
||
| 485 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
||
| 486 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
||
| 487 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
||
| 488 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
||
| 489 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
||
| 490 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
||
| 491 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
||
| 492 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
||
| 493 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
||
| 494 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
||
| 495 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
||
| 496 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
||
| 497 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
||
| 498 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
||
| 499 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
||
| 500 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
||
| 501 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
||
| 502 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
||
| 503 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
||
| 504 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
||
| 505 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
||
| 506 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
||
| 507 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
||
| 508 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
||
| 509 | * |
||
| 510 | * (*) value not defined in all devices. |
||
| 511 | * @retval State of Periphs (1 or 0). |
||
| 512 | */ |
||
| 513 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
||
| 514 | { |
||
| 515 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
||
| 516 | } |
||
| 517 | |||
| 518 | /** |
||
| 519 | * @brief Disable APB1 peripherals clock. |
||
| 520 | * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n |
||
| 521 | * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n |
||
| 522 | * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n |
||
| 523 | * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n |
||
| 524 | * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n |
||
| 525 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
||
| 526 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
||
| 527 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
||
| 528 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
||
| 529 | * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n |
||
| 530 | * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n |
||
| 531 | * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n |
||
| 532 | * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n |
||
| 533 | * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
||
| 534 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
||
| 535 | * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n |
||
| 536 | * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n |
||
| 537 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
||
| 538 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
||
| 539 | * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n |
||
| 540 | * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n |
||
| 541 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
||
| 542 | * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n |
||
| 543 | * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n |
||
| 544 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock |
||
| 545 | * @param Periphs This parameter can be a combination of the following values: |
||
| 546 | * @arg @ref LL_APB1_GRP1_PERIPH_BKP |
||
| 547 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
||
| 548 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
||
| 549 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
||
| 550 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
||
| 551 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
||
| 552 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
||
| 553 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
||
| 554 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
||
| 555 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
||
| 556 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
||
| 557 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
||
| 558 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
||
| 559 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
||
| 560 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
||
| 561 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
||
| 562 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
||
| 563 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
||
| 564 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
||
| 565 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
||
| 566 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
||
| 567 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
||
| 568 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
||
| 569 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
||
| 570 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
||
| 571 | * |
||
| 572 | * (*) value not defined in all devices. |
||
| 573 | * @retval None |
||
| 574 | */ |
||
| 575 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
||
| 576 | { |
||
| 577 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
||
| 578 | } |
||
| 579 | |||
| 580 | /** |
||
| 581 | * @brief Force APB1 peripherals reset. |
||
| 582 | * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n |
||
| 583 | * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n |
||
| 584 | * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n |
||
| 585 | * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n |
||
| 586 | * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n |
||
| 587 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
||
| 588 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
||
| 589 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
||
| 590 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
||
| 591 | * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n |
||
| 592 | * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n |
||
| 593 | * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n |
||
| 594 | * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n |
||
| 595 | * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
||
| 596 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
||
| 597 | * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n |
||
| 598 | * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n |
||
| 599 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
||
| 600 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
||
| 601 | * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n |
||
| 602 | * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n |
||
| 603 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
||
| 604 | * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n |
||
| 605 | * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n |
||
| 606 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset |
||
| 607 | * @param Periphs This parameter can be a combination of the following values: |
||
| 608 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
||
| 609 | * @arg @ref LL_APB1_GRP1_PERIPH_BKP |
||
| 610 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
||
| 611 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
||
| 612 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
||
| 613 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
||
| 614 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
||
| 615 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
||
| 616 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
||
| 617 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
||
| 618 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
||
| 619 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
||
| 620 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
||
| 621 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
||
| 622 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
||
| 623 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
||
| 624 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
||
| 625 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
||
| 626 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
||
| 627 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
||
| 628 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
||
| 629 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
||
| 630 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
||
| 631 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
||
| 632 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
||
| 633 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
||
| 634 | * |
||
| 635 | * (*) value not defined in all devices. |
||
| 636 | * @retval None |
||
| 637 | */ |
||
| 638 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
||
| 639 | { |
||
| 640 | SET_BIT(RCC->APB1RSTR, Periphs); |
||
| 641 | } |
||
| 642 | |||
| 643 | /** |
||
| 644 | * @brief Release APB1 peripherals reset. |
||
| 645 | * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n |
||
| 646 | * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n |
||
| 647 | * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n |
||
| 648 | * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n |
||
| 649 | * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n |
||
| 650 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
||
| 651 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
||
| 652 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
||
| 653 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
||
| 654 | * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n |
||
| 655 | * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n |
||
| 656 | * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n |
||
| 657 | * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n |
||
| 658 | * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
||
| 659 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
||
| 660 | * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n |
||
| 661 | * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n |
||
| 662 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
||
| 663 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
||
| 664 | * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n |
||
| 665 | * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n |
||
| 666 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
||
| 667 | * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n |
||
| 668 | * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n |
||
| 669 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset |
||
| 670 | * @param Periphs This parameter can be a combination of the following values: |
||
| 671 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
||
| 672 | * @arg @ref LL_APB1_GRP1_PERIPH_BKP |
||
| 673 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
||
| 674 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
||
| 675 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
||
| 676 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
||
| 677 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
||
| 678 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
||
| 679 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
||
| 680 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
||
| 681 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
||
| 682 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
||
| 683 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
||
| 684 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
||
| 685 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
||
| 686 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
||
| 687 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
||
| 688 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
||
| 689 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
||
| 690 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
||
| 691 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
||
| 692 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
||
| 693 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
||
| 694 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
||
| 695 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
||
| 696 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
||
| 697 | * |
||
| 698 | * (*) value not defined in all devices. |
||
| 699 | * @retval None |
||
| 700 | */ |
||
| 701 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
||
| 702 | { |
||
| 703 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
||
| 704 | } |
||
| 705 | |||
| 706 | /** |
||
| 707 | * @} |
||
| 708 | */ |
||
| 709 | |||
| 710 | /** @defgroup BUS_LL_EF_APB2 APB2 |
||
| 711 | * @{ |
||
| 712 | */ |
||
| 713 | |||
| 714 | /** |
||
| 715 | * @brief Enable APB2 peripherals clock. |
||
| 716 | * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n |
||
| 717 | * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n |
||
| 718 | * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n |
||
| 719 | * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n |
||
| 720 | * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n |
||
| 721 | * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n |
||
| 722 | * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n |
||
| 723 | * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n |
||
| 724 | * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n |
||
| 725 | * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n |
||
| 726 | * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n |
||
| 727 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
||
| 728 | * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n |
||
| 729 | * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n |
||
| 730 | * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n |
||
| 731 | * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n |
||
| 732 | * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n |
||
| 733 | * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n |
||
| 734 | * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n |
||
| 735 | * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n |
||
| 736 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock |
||
| 737 | * @param Periphs This parameter can be a combination of the following values: |
||
| 738 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
||
| 739 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
||
| 740 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
||
| 741 | * @arg @ref LL_APB2_GRP1_PERIPH_AFIO |
||
| 742 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA |
||
| 743 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB |
||
| 744 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC |
||
| 745 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD |
||
| 746 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) |
||
| 747 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) |
||
| 748 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) |
||
| 749 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
||
| 750 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
||
| 751 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) |
||
| 752 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) |
||
| 753 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) |
||
| 754 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
||
| 755 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
||
| 756 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
||
| 757 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) |
||
| 758 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
||
| 759 | * |
||
| 760 | * (*) value not defined in all devices. |
||
| 761 | * @retval None |
||
| 762 | */ |
||
| 763 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
||
| 764 | { |
||
| 765 | __IO uint32_t tmpreg; |
||
| 766 | SET_BIT(RCC->APB2ENR, Periphs); |
||
| 767 | /* Delay after an RCC peripheral clock enabling */ |
||
| 768 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
||
| 769 | (void)tmpreg; |
||
| 770 | } |
||
| 771 | |||
| 772 | /** |
||
| 773 | * @brief Check if APB2 peripheral clock is enabled or not |
||
| 774 | * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 775 | * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 776 | * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 777 | * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n |
||
| 778 | * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n |
||
| 779 | * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n |
||
| 780 | * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n |
||
| 781 | * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n |
||
| 782 | * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n |
||
| 783 | * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n |
||
| 784 | * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n |
||
| 785 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 786 | * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 787 | * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 788 | * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 789 | * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 790 | * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 791 | * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 792 | * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 793 | * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n |
||
| 794 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock |
||
| 795 | * @param Periphs This parameter can be a combination of the following values: |
||
| 796 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
||
| 797 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
||
| 798 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
||
| 799 | * @arg @ref LL_APB2_GRP1_PERIPH_AFIO |
||
| 800 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA |
||
| 801 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB |
||
| 802 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC |
||
| 803 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD |
||
| 804 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) |
||
| 805 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) |
||
| 806 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) |
||
| 807 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
||
| 808 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
||
| 809 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) |
||
| 810 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) |
||
| 811 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) |
||
| 812 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
||
| 813 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
||
| 814 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
||
| 815 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) |
||
| 816 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
||
| 817 | * |
||
| 818 | * (*) value not defined in all devices. |
||
| 819 | * @retval State of Periphs (1 or 0). |
||
| 820 | */ |
||
| 821 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
||
| 822 | { |
||
| 823 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
||
| 824 | } |
||
| 825 | |||
| 826 | /** |
||
| 827 | * @brief Disable APB2 peripherals clock. |
||
| 828 | * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n |
||
| 829 | * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n |
||
| 830 | * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n |
||
| 831 | * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n |
||
| 832 | * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n |
||
| 833 | * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n |
||
| 834 | * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n |
||
| 835 | * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n |
||
| 836 | * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n |
||
| 837 | * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n |
||
| 838 | * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n |
||
| 839 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
||
| 840 | * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n |
||
| 841 | * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n |
||
| 842 | * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n |
||
| 843 | * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n |
||
| 844 | * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n |
||
| 845 | * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n |
||
| 846 | * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n |
||
| 847 | * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n |
||
| 848 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock |
||
| 849 | * @param Periphs This parameter can be a combination of the following values: |
||
| 850 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
||
| 851 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
||
| 852 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
||
| 853 | * @arg @ref LL_APB2_GRP1_PERIPH_AFIO |
||
| 854 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA |
||
| 855 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB |
||
| 856 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC |
||
| 857 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD |
||
| 858 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) |
||
| 859 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) |
||
| 860 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) |
||
| 861 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
||
| 862 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
||
| 863 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) |
||
| 864 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) |
||
| 865 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) |
||
| 866 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
||
| 867 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
||
| 868 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
||
| 869 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) |
||
| 870 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
||
| 871 | * |
||
| 872 | * (*) value not defined in all devices. |
||
| 873 | * @retval None |
||
| 874 | */ |
||
| 875 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
||
| 876 | { |
||
| 877 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
||
| 878 | } |
||
| 879 | |||
| 880 | /** |
||
| 881 | * @brief Force APB2 peripherals reset. |
||
| 882 | * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n |
||
| 883 | * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n |
||
| 884 | * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n |
||
| 885 | * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n |
||
| 886 | * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n |
||
| 887 | * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n |
||
| 888 | * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n |
||
| 889 | * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n |
||
| 890 | * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n |
||
| 891 | * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n |
||
| 892 | * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n |
||
| 893 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
||
| 894 | * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n |
||
| 895 | * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n |
||
| 896 | * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n |
||
| 897 | * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n |
||
| 898 | * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n |
||
| 899 | * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n |
||
| 900 | * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n |
||
| 901 | * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n |
||
| 902 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset |
||
| 903 | * @param Periphs This parameter can be a combination of the following values: |
||
| 904 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
||
| 905 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
||
| 906 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
||
| 907 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
||
| 908 | * @arg @ref LL_APB2_GRP1_PERIPH_AFIO |
||
| 909 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA |
||
| 910 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB |
||
| 911 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC |
||
| 912 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD |
||
| 913 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) |
||
| 914 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) |
||
| 915 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) |
||
| 916 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
||
| 917 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
||
| 918 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) |
||
| 919 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) |
||
| 920 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) |
||
| 921 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
||
| 922 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
||
| 923 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
||
| 924 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) |
||
| 925 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
||
| 926 | * |
||
| 927 | * (*) value not defined in all devices. |
||
| 928 | * @retval None |
||
| 929 | */ |
||
| 930 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
||
| 931 | { |
||
| 932 | SET_BIT(RCC->APB2RSTR, Periphs); |
||
| 933 | } |
||
| 934 | |||
| 935 | /** |
||
| 936 | * @brief Release APB2 peripherals reset. |
||
| 937 | * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n |
||
| 938 | * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n |
||
| 939 | * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n |
||
| 940 | * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n |
||
| 941 | * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n |
||
| 942 | * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n |
||
| 943 | * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n |
||
| 944 | * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n |
||
| 945 | * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n |
||
| 946 | * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n |
||
| 947 | * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n |
||
| 948 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
||
| 949 | * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n |
||
| 950 | * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n |
||
| 951 | * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n |
||
| 952 | * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n |
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| 953 | * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n |
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| 954 | * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n |
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| 955 | * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n |
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| 956 | * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n |
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| 957 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset |
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| 958 | * @param Periphs This parameter can be a combination of the following values: |
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| 959 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
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| 960 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
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| 961 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
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| 962 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
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| 963 | * @arg @ref LL_APB2_GRP1_PERIPH_AFIO |
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| 964 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA |
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| 965 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB |
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| 966 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC |
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| 967 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD |
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| 968 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) |
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| 969 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) |
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| 970 | * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) |
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| 971 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
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| 972 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
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| 973 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) |
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| 974 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) |
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| 975 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) |
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| 976 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
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| 977 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
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| 978 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
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| 979 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) |
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| 980 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
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| 981 | * |
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| 982 | * (*) value not defined in all devices. |
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| 983 | * @retval None |
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| 984 | */ |
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| 985 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
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| 986 | { |
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| 987 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
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| 988 | } |
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| 989 | |||
| 990 | /** |
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| 991 | * @} |
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| 992 | */ |
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| 993 | |||
| 994 | |||
| 995 | /** |
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| 996 | * @} |
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| 997 | */ |
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| 998 | |||
| 999 | /** |
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| 1000 | * @} |
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| 1001 | */ |
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| 1002 | |||
| 1003 | #endif /* defined(RCC) */ |
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| 1004 | |||
| 1005 | /** |
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| 1006 | * @} |
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| 1007 | */ |
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| 1008 | |||
| 1009 | #ifdef __cplusplus |
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| 1010 | } |
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| 1011 | #endif |
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| 1012 | |||
| 1013 | #endif /* __STM32F1xx_LL_BUS_H */ |
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| 1014 | |||
| 1015 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |