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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_ll_adc.h
		4	* @author MCD Application Team
		5	* @brief Header file of ADC LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
		10	*
		11	* Redistribution and use in source and binary forms, with or without modification,
		12	* are permitted provided that the following conditions are met:
		13	* 1. Redistributions of source code must retain the above copyright notice,
		14	* this list of conditions and the following disclaimer.
		15	* 2. Redistributions in binary form must reproduce the above copyright notice,
		16	* this list of conditions and the following disclaimer in the documentation
		17	* and/or other materials provided with the distribution.
		18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		19	* may be used to endorse or promote products derived from this software
		20	* without specific prior written permission.
		21	*
		22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		32	*
		33	******************************************************************************
		34	*/
		35
		36	/* Define to prevent recursive inclusion -------------------------------------*/
		37	#ifndef __STM32F1xx_LL_ADC_H
		38	#define __STM32F1xx_LL_ADC_H
		39
		40	#ifdef __cplusplus
		41	extern "C" {
		42	#endif
		43
		44	/* Includes ------------------------------------------------------------------*/
		45	#include "stm32f1xx.h"
		46
		47	/** @addtogroup STM32F1xx_LL_Driver
		48	* @{
		49	*/
		50
		51	#if defined (ADC1) \|\| defined (ADC2) \|\| defined (ADC3)
		52
		53	/** @defgroup ADC_LL ADC
		54	* @{
		55	*/
		56
		57	/* Private types -------------------------------------------------------------*/
		58	/* Private variables ---------------------------------------------------------*/
		59
		60	/* Private constants ---------------------------------------------------------*/
		61	/** @defgroup ADC_LL_Private_Constants ADC Private Constants
		62	* @{
		63	*/
		64
		65	/* Internal mask for ADC group regular sequencer: */
		66	/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
		67	/* - sequencer register offset */
		68	/* - sequencer rank bits position into the selected register */
		69
		70	/* Internal register offset for ADC group regular sequencer configuration */
		71	/* (offset placed into a spare area of literal definition) */
		72	#define ADC_SQR1_REGOFFSET 0x00000000U
		73	#define ADC_SQR2_REGOFFSET 0x00000100U
		74	#define ADC_SQR3_REGOFFSET 0x00000200U
		75	#define ADC_SQR4_REGOFFSET 0x00000300U
		76
		77	#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET)
		78	#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
		79
		80	/* Definition of ADC group regular sequencer bits information to be inserted */
		81	/* into ADC group regular sequencer ranks literals definition. */
		82	#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
		83	#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
		84	#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
		85	#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
		86	#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
		87	#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
		88	#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
		89	#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
		90	#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
		91	#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
		92	#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
		93	#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
		94	#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
		95	#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
		96	#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
		97	#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
		98
		99	/* Internal mask for ADC group injected sequencer: */
		100	/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
		101	/* - data register offset */
		102	/* - offset register offset */
		103	/* - sequencer rank bits position into the selected register */
		104
		105	/* Internal register offset for ADC group injected data register */
		106	/* (offset placed into a spare area of literal definition) */
		107	#define ADC_JDR1_REGOFFSET 0x00000000U
		108	#define ADC_JDR2_REGOFFSET 0x00000100U
		109	#define ADC_JDR3_REGOFFSET 0x00000200U
		110	#define ADC_JDR4_REGOFFSET 0x00000300U
		111
		112	/* Internal register offset for ADC group injected offset configuration */
		113	/* (offset placed into a spare area of literal definition) */
		114	#define ADC_JOFR1_REGOFFSET 0x00000000U
		115	#define ADC_JOFR2_REGOFFSET 0x00001000U
		116	#define ADC_JOFR3_REGOFFSET 0x00002000U
		117	#define ADC_JOFR4_REGOFFSET 0x00003000U
		118
		119	#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET \| ADC_JDR2_REGOFFSET \| ADC_JDR3_REGOFFSET \| ADC_JDR4_REGOFFSET)
		120	#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET \| ADC_JOFR2_REGOFFSET \| ADC_JOFR3_REGOFFSET \| ADC_JOFR4_REGOFFSET)
		121	#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
		122
		123	/* Internal mask for ADC channel: */
		124	/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
		125	/* - channel identifier defined by number */
		126	/* - channel differentiation between external channels (connected to */
		127	/* GPIO pins) and internal channels (connected to internal paths) */
		128	/* - channel sampling time defined by SMPRx register offset */
		129	/* and SMPx bits positions into SMPRx register */
		130	#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
		131	#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
		132	#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
		133	/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
		134	#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
		135
		136	/* Channel differentiation between external and internal channels */
		137	#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
		138	#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
		139	#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2)
		140
		141	/* Internal register offset for ADC channel sampling time configuration */
		142	/* (offset placed into a spare area of literal definition) */
		143	#define ADC_SMPR1_REGOFFSET 0x00000000U
		144	#define ADC_SMPR2_REGOFFSET 0x02000000U
		145	#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET)
		146
		147	#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
		148	#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
		149
		150	/* Definition of channels ID number information to be inserted into */
		151	/* channels literals definition. */
		152	#define ADC_CHANNEL_0_NUMBER 0x00000000U
		153	#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
		154	#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
		155	#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
		156	#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
		157	#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
		158	#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
		159	#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
		160	#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
		161	#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0)
		162	#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 )
		163	#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
		164	#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 )
		165	#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
		166	#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
		167	#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
		168	#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
		169	#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_0)
		170
		171	/* Definition of channels sampling time information to be inserted into */
		172	/* channels literals definition. */
		173	#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
		174	#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
		175	#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
		176	#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
		177	#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
		178	#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
		179	#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
		180	#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
		181	#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET \| ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
		182	#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET \| ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
		183	#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
		184	#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
		185	#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
		186	#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
		187	#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
		188	#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
		189	#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
		190	#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
		191
		192	/* Internal mask for ADC analog watchdog: */
		193	/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
		194	/* (concatenation of multiple bits used in different analog watchdogs, */
		195	/* (feature of several watchdogs not available on all STM32 families)). */
		196	/* - analog watchdog 1: monitored channel defined by number, */
		197	/* selection of ADC group (ADC groups regular and-or injected). */
		198
		199	/* Internal register offset for ADC analog watchdog channel configuration */
		200	#define ADC_AWD_CR1_REGOFFSET 0x00000000U
		201
		202	#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
		203
		204	#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
		205	#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
		206
		207	/* Internal register offset for ADC analog watchdog threshold configuration */
		208	#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
		209	#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
		210	#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET \| ADC_AWD_TR1_LOW_REGOFFSET)
		211
		212	/* ADC registers bits positions */
		213	#define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
		214
		215	/**
		216	* @}
		217	*/
		218
		219
		220	/* Private macros ------------------------------------------------------------*/
		221	/** @defgroup ADC_LL_Private_Macros ADC Private Macros
		222	* @{
		223	*/
		224
		225	/**
		226	* @brief Driver macro reserved for internal use: isolate bits with the
		227	* selected mask and shift them to the register LSB
		228	* (shift mask on register position bit 0).
		229	* @param __BITS__ Bits in register 32 bits
		230	* @param __MASK__ Mask in register 32 bits
		231	* @retval Bits in register 32 bits
		232	*/
		233	#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
		234	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
		235
		236	/**
		237	* @brief Driver macro reserved for internal use: set a pointer to
		238	* a register from a register basis from which an offset
		239	* is applied.
		240	* @param __REG__ Register basis from which the offset is applied.
		241	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
		242	* @retval Pointer to register address
		243	*/
		244	#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
		245	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
		246
		247	/**
		248	* @}
		249	*/
		250
		251
		252	/* Exported types ------------------------------------------------------------*/
		253	#if defined(USE_FULL_LL_DRIVER)
		254	/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
		255	* @{
		256	*/
		257
		258	/**
		259	* @brief Structure definition of some features of ADC common parameters
		260	* and multimode
		261	* (all ADC instances belonging to the same ADC common instance).
		262	* @note The setting of these parameters by function @ref LL_ADC_CommonInit()
		263	* is conditioned to ADC instances state (all ADC instances
		264	* sharing the same ADC common instance):
		265	* All ADC instances sharing the same ADC common instance must be
		266	* disabled.
		267	*/
		268	typedef struct
		269	{
		270	uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
		271	This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
		272
		273	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
		274	} LL_ADC_CommonInitTypeDef;
		275	/**
		276	* @brief Structure definition of some features of ADC instance.
		277	* @note These parameters have an impact on ADC scope: ADC instance.
		278	* Affects both group regular and group injected (availability
		279	* of ADC group injected depends on STM32 families).
		280	* Refer to corresponding unitary functions into
		281	* @ref ADC_LL_EF_Configuration_ADC_Instance .
		282	* @note The setting of these parameters by function @ref LL_ADC_Init()
		283	* is conditioned to ADC state:
		284	* ADC instance must be disabled.
		285	* This condition is applied to all ADC features, for efficiency
		286	* and compatibility over all STM32 families. However, the different
		287	* features can be set under different ADC state conditions
		288	* (setting possible with ADC enabled without conversion on going,
		289	* ADC enabled with conversion on going, ...)
		290	* Each feature can be updated afterwards with a unitary function
		291	* and potentially with ADC in a different state than disabled,
		292	* refer to description of each function for setting
		293	* conditioned to ADC state.
		294	*/
		295	typedef struct
		296	{
		297	uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
		298	This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
		299
		300	This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
		301
		302	uint32_t SequencersScanMode; /*!< Set ADC scan selection.
		303	This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
		304
		305	This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
		306
		307	} LL_ADC_InitTypeDef;
		308
		309	/**
		310	* @brief Structure definition of some features of ADC group regular.
		311	* @note These parameters have an impact on ADC scope: ADC group regular.
		312	* Refer to corresponding unitary functions into
		313	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
		314	* (functions with prefix "REG").
		315	* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
		316	* is conditioned to ADC state:
		317	* ADC instance must be disabled.
		318	* This condition is applied to all ADC features, for efficiency
		319	* and compatibility over all STM32 families. However, the different
		320	* features can be set under different ADC state conditions
		321	* (setting possible with ADC enabled without conversion on going,
		322	* ADC enabled with conversion on going, ...)
		323	* Each feature can be updated afterwards with a unitary function
		324	* and potentially with ADC in a different state than disabled,
		325	* refer to description of each function for setting
		326	* conditioned to ADC state.
		327	*/
		328	typedef struct
		329	{
		330	uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
		331	This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
		332	@note On this STM32 serie, external trigger is set with trigger polarity: rising edge
		333	(only trigger polarity available on this STM32 serie).
		334
		335	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
		336
		337	uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
		338	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
		339	@note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
		340
		341	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
		342
		343	uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
		344	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
		345	@note This parameter has an effect only if group regular sequencer is enabled
		346	(scan length of 2 ranks or more).
		347
		348	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
		349
		350	uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
		351	This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
		352	Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
		353
		354	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
		355
		356	uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
		357	This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
		358
		359	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
		360
		361	} LL_ADC_REG_InitTypeDef;
		362
		363	/**
		364	* @brief Structure definition of some features of ADC group injected.
		365	* @note These parameters have an impact on ADC scope: ADC group injected.
		366	* Refer to corresponding unitary functions into
		367	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
		368	* (functions with prefix "INJ").
		369	* @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
		370	* is conditioned to ADC state:
		371	* ADC instance must be disabled.
		372	* This condition is applied to all ADC features, for efficiency
		373	* and compatibility over all STM32 families. However, the different
		374	* features can be set under different ADC state conditions
		375	* (setting possible with ADC enabled without conversion on going,
		376	* ADC enabled with conversion on going, ...)
		377	* Each feature can be updated afterwards with a unitary function
		378	* and potentially with ADC in a different state than disabled,
		379	* refer to description of each function for setting
		380	* conditioned to ADC state.
		381	*/
		382	typedef struct
		383	{
		384	uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
		385	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
		386	@note On this STM32 serie, external trigger is set with trigger polarity: rising edge
		387	(only trigger polarity available on this STM32 serie).
		388
		389	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
		390
		391	uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
		392	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
		393	@note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
		394
		395	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
		396
		397	uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
		398	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
		399	@note This parameter has an effect only if group injected sequencer is enabled
		400	(scan length of 2 ranks or more).
		401
		402	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
		403
		404	uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
		405	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
		406	Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
		407
		408	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
		409
		410	} LL_ADC_INJ_InitTypeDef;
		411
		412	/**
		413	* @}
		414	*/
		415	#endif /* USE_FULL_LL_DRIVER */
		416
		417	/* Exported constants --------------------------------------------------------*/
		418	/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
		419	* @{
		420	*/
		421
		422	/** @defgroup ADC_LL_EC_FLAG ADC flags
		423	* @brief Flags defines which can be used with LL_ADC_ReadReg function
		424	* @{
		425	*/
		426	#define LL_ADC_FLAG_STRT ADC_SR_STRT /!< ADC flag ADC group regular conversion start /
		427	#define LL_ADC_FLAG_EOS ADC_SR_EOC /!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) /
		428	#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC flag ADC group injected conversion start /
		429	#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
		430	#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /!< ADC flag ADC analog watchdog 1 /
		431	#if defined(ADC_MULTIMODE_SUPPORT)
		432	#define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) /
		433	#define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) /
		434	#define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
		435	#define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) /
		436	#define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /!< ADC flag ADC multimode master analog watchdog 1 of the ADC master /
		437	#define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) /
		438	#endif
		439	/**
		440	* @}
		441	*/
		442
		443	/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
		444	* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
		445	* @{
		446	*/
		447	#define LL_ADC_IT_EOS ADC_CR1_EOCIE /!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) /
		448	#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
		449	#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /!< ADC interruption ADC analog watchdog 1 /
		450	/**
		451	* @}
		452	*/
		453
		454	/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
		455	* @{
		456	*/
		457	/* List of ADC registers intended to be used (most commonly) with */
		458	/* DMA transfer. */
		459	/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
		460	#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
		461	#if defined(ADC_MULTIMODE_SUPPORT)
		462	#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
		463	#endif
		464	/**
		465	* @}
		466	*/
		467
		468	/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
		469	* @{
		470	*/
		471	/* Note: Other measurement paths to internal channels may be available */
		472	/* (connections to other peripherals). */
		473	/* If they are not listed below, they do not require any specific */
		474	/* path enable. In this case, Access to measurement path is done */
		475	/* only by selecting the corresponding ADC internal channel. */
		476	#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /!< ADC measurement pathes all disabled /
		477	#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /!< ADC measurement path to internal channel VrefInt /
		478	#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /!< ADC measurement path to internal channel temperature sensor /
		479	/**
		480	* @}
		481	*/
		482
		483	/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
		484	* @{
		485	*/
		486	#define LL_ADC_RESOLUTION_12B 0x00000000U /!< ADC resolution 12 bits /
		487	/**
		488	* @}
		489	*/
		490
		491	/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
		492	* @{
		493	*/
		494	#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)/
		495	#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)/
		496	/**
		497	* @}
		498	*/
		499
		500	/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
		501	* @{
		502	*/
		503	#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank./
		504	#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). /
		505	/**
		506	* @}
		507	*/
		508
		509	/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
		510	* @{
		511	*/
		512	#define LL_ADC_GROUP_REGULAR 0x00000001U /!< ADC group regular (available on all STM32 devices) /
		513	#define LL_ADC_GROUP_INJECTED 0x00000002U /!< ADC group injected (not available on all STM32 devices)/
		514	#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /!< ADC both groups regular and injected /
		515	/**
		516	* @}
		517	*/
		518
		519	/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
		520	* @{
		521	*/
		522	#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 /
		523	#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 /
		524	#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 /
		525	#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 /
		526	#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 /
		527	#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 /
		528	#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 /
		529	#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 /
		530	#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 /
		531	#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 /
		532	#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 /
		533	#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 /
		534	#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 /
		535	#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 /
		536	#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 /
		537	#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 /
		538	#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 /
		539	#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 /
		540	#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. /
		541	#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Temperature sensor. /
		542	/**
		543	* @}
		544	*/
		545
		546	/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
		547	* @{
		548	*/
		549	/* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
		550	#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0) /!< ADC group regular conversion trigger internal: SW start. /
		551	#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		552	/* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
		553	#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		554	#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		555	#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0) /!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		556	#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). /
		557	#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0) /!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		558	#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1) /!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). /
		559	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
		560	/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
		561	/* XL-density devices. */
		562	/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
		563	/* A remap of trigger must be done at top level (refer to */
		564	/* AFIO peripheral). */
		565	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral)./
		566	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
		567	#if defined (STM32F103xE) \|\| defined (STM32F103xG)
		568	/* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
		569	#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		570	#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		571	#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		572	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). /
		573	#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		574	#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		575	#endif
		576	/**
		577	* @}
		578	*/
		579
		580	/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
		581	* @{
		582	*/
		583	#define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /!< ADC group regular conversion trigger polarity set to rising edge /
		584	/**
		585	* @}
		586	*/
		587
		588	/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
		589	* @{
		590	*/
		591	#define LL_ADC_REG_CONV_SINGLE 0x00000000U /!< ADC conversions are performed in single mode: one conversion per trigger /
		592	#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically /
		593	/**
		594	* @}
		595	*/
		596
		597	/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
		598	* @{
		599	*/
		600	#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /!< ADC conversions are not transferred by DMA /
		601	#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. /
		602	/**
		603	* @}
		604	*/
		605
		606	/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
		607	* @{
		608	*/
		609	#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
		610	#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 2 ranks in the sequence /
		611	#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 3 ranks in the sequence /
		612	#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 4 ranks in the sequence /
		613	#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 5 ranks in the sequence /
		614	#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 6 ranks in the sequence /
		615	#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 7 ranks in the sequence /
		616	#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 8 ranks in the sequence /
		617	#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /!< ADC group regular sequencer enable with 9 ranks in the sequence /
		618	#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 10 ranks in the sequence /
		619	#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 11 ranks in the sequence /
		620	#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 12 ranks in the sequence /
		621	#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 13 ranks in the sequence /
		622	#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 14 ranks in the sequence /
		623	#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 15 ranks in the sequence /
		624	#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 16 ranks in the sequence /
		625	/**
		626	* @}
		627	*/
		628
		629	/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
		630	* @{
		631	*/
		632	#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /!< ADC group regular sequencer discontinuous mode disable /
		633	#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank /
		634	#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks /
		635	#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks /
		636	#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks /
		637	#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks /
		638	#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks /
		639	#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks /
		640	#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks /
		641	/**
		642	* @}
		643	*/
		644
		645	/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
		646	* @{
		647	*/
		648	#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 1 /
		649	#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 2 /
		650	#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 3 /
		651	#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 4 /
		652	#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 5 /
		653	#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 6 /
		654	#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 7 /
		655	#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 8 /
		656	#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 9 /
		657	#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 10 /
		658	#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 11 /
		659	#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 12 /
		660	#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 13 /
		661	#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 14 /
		662	#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 15 /
		663	#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 16 /
		664	/**
		665	* @}
		666	*/
		667
		668	/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
		669	* @{
		670	*/
		671	/* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
		672	#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0) /!< ADC group injected conversion trigger internal: SW start. /
		673	#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
		674	#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		675	/* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
		676	#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
		677	#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0) /!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		678	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		679	#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_0) /!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
		680	#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1) /!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). /
		681	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
		682	/* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */
		683	/* XL-density devices. */
		684	/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
		685	/* A remap of trigger must be done at top level (refer to */
		686	/* AFIO peripheral). */
		687	#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). /
		688	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
		689	#if defined (STM32F103xE) \|\| defined (STM32F103xG)
		690	/* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
		691	#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		692	#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		693	#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		694	#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). /
		695	#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		696	#endif
		697	/**
		698	* @}
		699	*/
		700
		701	/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
		702	* @{
		703	*/
		704	#define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /!< ADC group injected conversion trigger polarity set to rising edge /
		705	/**
		706	* @}
		707	*/
		708
		709	/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
		710	* @{
		711	*/
		712	#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. /
		713	#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. /
		714	/**
		715	* @}
		716	*/
		717
		718
		719	/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
		720	* @{
		721	*/
		722	#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
		723	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 2 ranks in the sequence /
		724	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /!< ADC group injected sequencer enable with 3 ranks in the sequence /
		725	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 \| ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 4 ranks in the sequence /
		726	/**
		727	* @}
		728	*/
		729
		730	/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
		731	* @{
		732	*/
		733	#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /!< ADC group injected sequencer discontinuous mode disable /
		734	#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank /
		735	/**
		736	* @}
		737	*/
		738
		739	/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
		740	* @{
		741	*/
		742	#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \| ADC_JOFR1_REGOFFSET \| 0x00000001U) /!< ADC group injected sequencer rank 1 /
		743	#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \| ADC_JOFR2_REGOFFSET \| 0x00000002U) /!< ADC group injected sequencer rank 2 /
		744	#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \| ADC_JOFR3_REGOFFSET \| 0x00000003U) /!< ADC group injected sequencer rank 3 /
		745	#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \| ADC_JOFR4_REGOFFSET \| 0x00000004U) /!< ADC group injected sequencer rank 4 /
		746	/**
		747	* @}
		748	*/
		749
		750	/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
		751	* @{
		752	*/
		753	#define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /!< Sampling time 1.5 ADC clock cycle /
		754	#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /!< Sampling time 7.5 ADC clock cycles /
		755	#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /!< Sampling time 13.5 ADC clock cycles /
		756	#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0) /!< Sampling time 28.5 ADC clock cycles /
		757	#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /!< Sampling time 41.5 ADC clock cycles /
		758	#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_0) /!< Sampling time 55.5 ADC clock cycles /
		759	#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1) /!< Sampling time 71.5 ADC clock cycles /
		760	#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0) /!< Sampling time 239.5 ADC clock cycles /
		761	/**
		762	* @}
		763	*/
		764
		765	/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
		766	* @{
		767	*/
		768	#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /!< ADC analog watchdog number 1 /
		769	/**
		770	* @}
		771	*/
		772
		773	/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
		774	* @{
		775	*/
		776	#define LL_ADC_AWD_DISABLE 0x00000000U /!< ADC analog watchdog monitoring disabled /
		777	#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group regular only /
		778	#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group injected only /
		779	#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN \| ADC_CR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected /
		780	#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only /
		781	#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only /
		782	#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected /
		783	#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only /
		784	#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only /
		785	#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected /
		786	#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only /
		787	#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only /
		788	#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected /
		789	#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only /
		790	#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only /
		791	#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected /
		792	#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only /
		793	#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only /
		794	#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected /
		795	#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only /
		796	#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only /
		797	#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected /
		798	#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only /
		799	#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only /
		800	#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected /
		801	#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only /
		802	#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only /
		803	#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected /
		804	#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only /
		805	#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only /
		806	#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected /
		807	#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only /
		808	#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only /
		809	#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected /
		810	#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only /
		811	#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only /
		812	#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected /
		813	#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only /
		814	#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only /
		815	#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected /
		816	#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only /
		817	#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only /
		818	#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected /
		819	#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only /
		820	#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only /
		821	#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected /
		822	#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only /
		823	#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only /
		824	#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected /
		825	#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only /
		826	#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only /
		827	#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected /
		828	#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only /
		829	#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only /
		830	#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected /
		831	#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only /
		832	#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only /
		833	#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected /
		834	#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only /
		835	#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only /
		836	#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected /
		837	#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only /
		838	#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only /
		839	#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected /
		840	/**
		841	* @}
		842	*/
		843
		844	/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
		845	* @{
		846	*/
		847	#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /!< ADC analog watchdog threshold high /
		848	#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /!< ADC analog watchdog threshold low /
		849	/**
		850	* @}
		851	*/
		852
		853	#if !defined(ADC_MULTIMODE_SUPPORT)
		854	/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
		855	* @{
		856	*/
		857	#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /!< ADC dual mode disabled (ADC independent mode) /
		858	/**
		859	* @}
		860	*/
		861	#endif
		862	#if defined(ADC_MULTIMODE_SUPPORT)
		863	/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
		864	* @{
		865	*/
		866	#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /!< ADC dual mode disabled (ADC independent mode) /
		867	#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 \| ADC_CR1_DUALMOD_1 ) /!< ADC dual mode enabled: group regular simultaneous /
		868	#define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 \| ADC_CR1_DUALMOD_1 \| ADC_CR1_DUALMOD_0) /!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) /
		869	#define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) /
		870	#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 \| ADC_CR1_DUALMOD_0) /!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) /
		871	#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 \| ADC_CR1_DUALMOD_0) /!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) /
		872	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous /
		873	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger /
		874	#define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 \| ADC_CR1_DUALMOD_0) /!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous /
		875	#define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous /
		876
		877	/**
		878	* @}
		879	*/
		880
		881	/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
		882	* @{
		883	*/
		884	#define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /!< In multimode, selection among several ADC instances: ADC master /
		885	#define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /!< In multimode, selection among several ADC instances: ADC slave /
		886	#define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA \| ADC_DR_DATA) /!< In multimode, selection among several ADC instances: both ADC master and ADC slave /
		887	/**
		888	* @}
		889	*/
		890
		891	#endif /* ADC_MULTIMODE_SUPPORT */
		892
		893
		894	/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
		895	* @note Only ADC IP HW delays are defined in ADC LL driver driver,
		896	* not timeout values.
		897	* For details on delays values, refer to descriptions in source code
		898	* above each literal definition.
		899	* @{
		900	*/
		901
		902	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
		903	/* not timeout values. */
		904	/* Timeout values for ADC operations are dependent to device clock */
		905	/* configuration (system clock versus ADC clock), */
		906	/* and therefore must be defined in user application. */
		907	/* Indications for estimation of ADC timeout delays, for this */
		908	/* STM32 serie: */
		909	/* - ADC enable time: maximum delay is 1us */
		910	/* (refer to device datasheet, parameter "tSTAB") */
		911	/* - ADC conversion time: duration depending on ADC clock and ADC */
		912	/* configuration. */
		913	/* (refer to device reference manual, section "Timing") */
		914
		915	/* Delay for temperature sensor stabilization time. */
		916	/* Literal set to maximum value (refer to device datasheet, */
		917	/* parameter "tSTART"). */
		918	/* Unit: us */
		919	#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /!< Delay for internal voltage reference stabilization time /
		920
		921	/* Delay required between ADC disable and ADC calibration start. */
		922	/* Note: On this STM32 serie, before starting a calibration, */
		923	/* ADC must be disabled. */
		924	/* A minimum number of ADC clock cycles are required */
		925	/* between ADC disable state and calibration start. */
		926	/* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */
		927	/* Wait time can be computed in user application by waiting for the */
		928	/* equivalent number of CPU cycles, by taking into account */
		929	/* ratio of CPU clock versus ADC clock prescalers. */
		930	/* Unit: ADC clock cycles. */
		931	#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /!< Delay required between ADC disable and ADC calibration start /
		932
		933	/* Delay required between end of ADC Enable and the start of ADC calibration. */
		934	/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
		935	/* are required between the end of ADC enable and the start of ADC */
		936	/* calibration. */
		937	/* Wait time can be computed in user application by waiting for the */
		938	/* equivalent number of CPU cycles, by taking into account */
		939	/* ratio of CPU clock versus ADC clock prescalers. */
		940	/* Unit: ADC clock cycles. */
		941	#define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /!< Delay required between end of ADC enable and the start of ADC calibration /
		942
		943	/**
		944	* @}
		945	*/
		946
		947	/**
		948	* @}
		949	*/
		950
		951
		952	/* Exported macro ------------------------------------------------------------*/
		953	/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
		954	* @{
		955	*/
		956
		957	/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
		958	* @{
		959	*/
		960
		961	/**
		962	* @brief Write a value in ADC register
		963	* @param __INSTANCE__ ADC Instance
		964	* @param __REG__ Register to be written
		965	* @param __VALUE__ Value to be written in the register
		966	* @retval None
		967	*/
		968	#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		969
		970	/**
		971	* @brief Read a value in ADC register
		972	* @param __INSTANCE__ ADC Instance
		973	* @param __REG__ Register to be read
		974	* @retval Register value
		975	*/
		976	#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		977	/**
		978	* @}
		979	*/
		980
		981	/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
		982	* @{
		983	*/
		984
		985	/**
		986	* @brief Helper macro to get ADC channel number in decimal format
		987	* from literals LL_ADC_CHANNEL_x.
		988	* @note Example:
		989	* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
		990	* will return decimal number "4".
		991	* @note The input can be a value from functions where a channel
		992	* number is returned, either defined with number
		993	* or with bitfield (only one bit must be set).
		994	* @param __CHANNEL__ This parameter can be one of the following values:
		995	* @arg @ref LL_ADC_CHANNEL_0
		996	* @arg @ref LL_ADC_CHANNEL_1
		997	* @arg @ref LL_ADC_CHANNEL_2
		998	* @arg @ref LL_ADC_CHANNEL_3
		999	* @arg @ref LL_ADC_CHANNEL_4
		1000	* @arg @ref LL_ADC_CHANNEL_5
		1001	* @arg @ref LL_ADC_CHANNEL_6
		1002	* @arg @ref LL_ADC_CHANNEL_7
		1003	* @arg @ref LL_ADC_CHANNEL_8
		1004	* @arg @ref LL_ADC_CHANNEL_9
		1005	* @arg @ref LL_ADC_CHANNEL_10
		1006	* @arg @ref LL_ADC_CHANNEL_11
		1007	* @arg @ref LL_ADC_CHANNEL_12
		1008	* @arg @ref LL_ADC_CHANNEL_13
		1009	* @arg @ref LL_ADC_CHANNEL_14
		1010	* @arg @ref LL_ADC_CHANNEL_15
		1011	* @arg @ref LL_ADC_CHANNEL_16
		1012	* @arg @ref LL_ADC_CHANNEL_17
		1013	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		1014	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		1015	*
		1016	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		1017	* @retval Value between Min_Data=0 and Max_Data=18
		1018	*/
		1019	#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
		1020	(((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
		1021
		1022	/**
		1023	* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
		1024	* from number in decimal format.
		1025	* @note Example:
		1026	* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
		1027	* will return a data equivalent to "LL_ADC_CHANNEL_4".
		1028	* @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
		1029	* @retval Returned value can be one of the following values:
		1030	* @arg @ref LL_ADC_CHANNEL_0
		1031	* @arg @ref LL_ADC_CHANNEL_1
		1032	* @arg @ref LL_ADC_CHANNEL_2
		1033	* @arg @ref LL_ADC_CHANNEL_3
		1034	* @arg @ref LL_ADC_CHANNEL_4
		1035	* @arg @ref LL_ADC_CHANNEL_5
		1036	* @arg @ref LL_ADC_CHANNEL_6
		1037	* @arg @ref LL_ADC_CHANNEL_7
		1038	* @arg @ref LL_ADC_CHANNEL_8
		1039	* @arg @ref LL_ADC_CHANNEL_9
		1040	* @arg @ref LL_ADC_CHANNEL_10
		1041	* @arg @ref LL_ADC_CHANNEL_11
		1042	* @arg @ref LL_ADC_CHANNEL_12
		1043	* @arg @ref LL_ADC_CHANNEL_13
		1044	* @arg @ref LL_ADC_CHANNEL_14
		1045	* @arg @ref LL_ADC_CHANNEL_15
		1046	* @arg @ref LL_ADC_CHANNEL_16
		1047	* @arg @ref LL_ADC_CHANNEL_17
		1048	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		1049	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		1050	*
		1051	* (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
		1052	* (1) For ADC channel read back from ADC register,
		1053	* comparison with internal channel parameter to be done
		1054	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
		1055	*/
		1056	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
		1057	(((__DECIMAL_NB__) <= 9U) \
		1058	? ( \
		1059	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
		1060	(ADC_SMPR2_REGOFFSET \| (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
		1061	) \
		1062	: \
		1063	( \
		1064	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
		1065	(ADC_SMPR1_REGOFFSET \| (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
		1066	) \
		1067	)
		1068
		1069	/**
		1070	* @brief Helper macro to determine whether the selected channel
		1071	* corresponds to literal definitions of driver.
		1072	* @note The different literal definitions of ADC channels are:
		1073	* - ADC internal channel:
		1074	* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
		1075	* - ADC external channel (channel connected to a GPIO pin):
		1076	* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
		1077	* @note The channel parameter must be a value defined from literal
		1078	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
		1079	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
		1080	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
		1081	* must not be a value from functions where a channel number is
		1082	* returned from ADC registers,
		1083	* because internal and external channels share the same channel
		1084	* number in ADC registers. The differentiation is made only with
		1085	* parameters definitions of driver.
		1086	* @param __CHANNEL__ This parameter can be one of the following values:
		1087	* @arg @ref LL_ADC_CHANNEL_0
		1088	* @arg @ref LL_ADC_CHANNEL_1
		1089	* @arg @ref LL_ADC_CHANNEL_2
		1090	* @arg @ref LL_ADC_CHANNEL_3
		1091	* @arg @ref LL_ADC_CHANNEL_4
		1092	* @arg @ref LL_ADC_CHANNEL_5
		1093	* @arg @ref LL_ADC_CHANNEL_6
		1094	* @arg @ref LL_ADC_CHANNEL_7
		1095	* @arg @ref LL_ADC_CHANNEL_8
		1096	* @arg @ref LL_ADC_CHANNEL_9
		1097	* @arg @ref LL_ADC_CHANNEL_10
		1098	* @arg @ref LL_ADC_CHANNEL_11
		1099	* @arg @ref LL_ADC_CHANNEL_12
		1100	* @arg @ref LL_ADC_CHANNEL_13
		1101	* @arg @ref LL_ADC_CHANNEL_14
		1102	* @arg @ref LL_ADC_CHANNEL_15
		1103	* @arg @ref LL_ADC_CHANNEL_16
		1104	* @arg @ref LL_ADC_CHANNEL_17
		1105	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		1106	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		1107	*
		1108	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		1109	* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
		1110	* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
		1111	*/
		1112	#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
		1113	(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
		1114
		1115	/**
		1116	* @brief Helper macro to convert a channel defined from parameter
		1117	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
		1118	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
		1119	* to its equivalent parameter definition of a ADC external channel
		1120	* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
		1121	* @note The channel parameter can be, additionally to a value
		1122	* defined from parameter definition of a ADC internal channel
		1123	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
		1124	* a value defined from parameter definition of
		1125	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
		1126	* or a value from functions where a channel number is returned
		1127	* from ADC registers.
		1128	* @param __CHANNEL__ This parameter can be one of the following values:
		1129	* @arg @ref LL_ADC_CHANNEL_0
		1130	* @arg @ref LL_ADC_CHANNEL_1
		1131	* @arg @ref LL_ADC_CHANNEL_2
		1132	* @arg @ref LL_ADC_CHANNEL_3
		1133	* @arg @ref LL_ADC_CHANNEL_4
		1134	* @arg @ref LL_ADC_CHANNEL_5
		1135	* @arg @ref LL_ADC_CHANNEL_6
		1136	* @arg @ref LL_ADC_CHANNEL_7
		1137	* @arg @ref LL_ADC_CHANNEL_8
		1138	* @arg @ref LL_ADC_CHANNEL_9
		1139	* @arg @ref LL_ADC_CHANNEL_10
		1140	* @arg @ref LL_ADC_CHANNEL_11
		1141	* @arg @ref LL_ADC_CHANNEL_12
		1142	* @arg @ref LL_ADC_CHANNEL_13
		1143	* @arg @ref LL_ADC_CHANNEL_14
		1144	* @arg @ref LL_ADC_CHANNEL_15
		1145	* @arg @ref LL_ADC_CHANNEL_16
		1146	* @arg @ref LL_ADC_CHANNEL_17
		1147	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		1148	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		1149	*
		1150	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		1151	* @retval Returned value can be one of the following values:
		1152	* @arg @ref LL_ADC_CHANNEL_0
		1153	* @arg @ref LL_ADC_CHANNEL_1
		1154	* @arg @ref LL_ADC_CHANNEL_2
		1155	* @arg @ref LL_ADC_CHANNEL_3
		1156	* @arg @ref LL_ADC_CHANNEL_4
		1157	* @arg @ref LL_ADC_CHANNEL_5
		1158	* @arg @ref LL_ADC_CHANNEL_6
		1159	* @arg @ref LL_ADC_CHANNEL_7
		1160	* @arg @ref LL_ADC_CHANNEL_8
		1161	* @arg @ref LL_ADC_CHANNEL_9
		1162	* @arg @ref LL_ADC_CHANNEL_10
		1163	* @arg @ref LL_ADC_CHANNEL_11
		1164	* @arg @ref LL_ADC_CHANNEL_12
		1165	* @arg @ref LL_ADC_CHANNEL_13
		1166	* @arg @ref LL_ADC_CHANNEL_14
		1167	* @arg @ref LL_ADC_CHANNEL_15
		1168	* @arg @ref LL_ADC_CHANNEL_16
		1169	* @arg @ref LL_ADC_CHANNEL_17
		1170	*/
		1171	#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
		1172	((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
		1173
		1174	/**
		1175	* @brief Helper macro to determine whether the internal channel
		1176	* selected is available on the ADC instance selected.
		1177	* @note The channel parameter must be a value defined from parameter
		1178	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
		1179	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
		1180	* must not be a value defined from parameter definition of
		1181	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
		1182	* or a value from functions where a channel number is
		1183	* returned from ADC registers,
		1184	* because internal and external channels share the same channel
		1185	* number in ADC registers. The differentiation is made only with
		1186	* parameters definitions of driver.
		1187	* @param __ADC_INSTANCE__ ADC instance
		1188	* @param __CHANNEL__ This parameter can be one of the following values:
		1189	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		1190	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		1191	*
		1192	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		1193	* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
		1194	* Value "1" if the internal channel selected is available on the ADC instance selected.
		1195	*/
		1196	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
		1197	(((__ADC_INSTANCE__) == ADC1) \
		1198	? ( \
		1199	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
		1200	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
		1201	) \
		1202	: \
		1203	(0U) \
		1204	)
		1205
		1206	/**
		1207	* @brief Helper macro to define ADC analog watchdog parameter:
		1208	* define a single channel to monitor with analog watchdog
		1209	* from sequencer channel and groups definition.
		1210	* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
		1211	* Example:
		1212	* LL_ADC_SetAnalogWDMonitChannels(
		1213	* ADC1, LL_ADC_AWD1,
		1214	* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
		1215	* @param __CHANNEL__ This parameter can be one of the following values:
		1216	* @arg @ref LL_ADC_CHANNEL_0
		1217	* @arg @ref LL_ADC_CHANNEL_1
		1218	* @arg @ref LL_ADC_CHANNEL_2
		1219	* @arg @ref LL_ADC_CHANNEL_3
		1220	* @arg @ref LL_ADC_CHANNEL_4
		1221	* @arg @ref LL_ADC_CHANNEL_5
		1222	* @arg @ref LL_ADC_CHANNEL_6
		1223	* @arg @ref LL_ADC_CHANNEL_7
		1224	* @arg @ref LL_ADC_CHANNEL_8
		1225	* @arg @ref LL_ADC_CHANNEL_9
		1226	* @arg @ref LL_ADC_CHANNEL_10
		1227	* @arg @ref LL_ADC_CHANNEL_11
		1228	* @arg @ref LL_ADC_CHANNEL_12
		1229	* @arg @ref LL_ADC_CHANNEL_13
		1230	* @arg @ref LL_ADC_CHANNEL_14
		1231	* @arg @ref LL_ADC_CHANNEL_15
		1232	* @arg @ref LL_ADC_CHANNEL_16
		1233	* @arg @ref LL_ADC_CHANNEL_17
		1234	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		1235	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		1236	*
		1237	* (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
		1238	* (1) For ADC channel read back from ADC register,
		1239	* comparison with internal channel parameter to be done
		1240	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
		1241	* @param __GROUP__ This parameter can be one of the following values:
		1242	* @arg @ref LL_ADC_GROUP_REGULAR
		1243	* @arg @ref LL_ADC_GROUP_INJECTED
		1244	* @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
		1245	* @retval Returned value can be one of the following values:
		1246	* @arg @ref LL_ADC_AWD_DISABLE
		1247	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
		1248	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
		1249	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
		1250	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
		1251	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
		1252	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
		1253	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
		1254	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
		1255	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
		1256	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
		1257	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
		1258	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
		1259	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
		1260	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
		1261	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
		1262	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
		1263	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
		1264	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
		1265	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
		1266	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
		1267	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
		1268	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
		1269	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
		1270	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
		1271	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
		1272	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
		1273	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
		1274	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
		1275	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
		1276	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
		1277	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
		1278	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
		1279	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
		1280	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
		1281	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
		1282	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
		1283	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
		1284	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
		1285	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
		1286	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
		1287	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
		1288	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
		1289	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
		1290	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
		1291	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
		1292	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
		1293	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
		1294	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
		1295	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
		1296	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
		1297	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
		1298	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
		1299	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
		1300	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
		1301	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
		1302	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
		1303	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
		1304	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
		1305	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
		1306	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
		1307	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
		1308	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
		1309	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
		1310	*
		1311	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		1312	*/
		1313	#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
		1314	(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
		1315	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) \
		1316	: \
		1317	((__GROUP__) == LL_ADC_GROUP_INJECTED) \
		1318	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) \
		1319	: \
		1320	(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) \
		1321	)
		1322
		1323	/**
		1324	* @brief Helper macro to set the value of ADC analog watchdog threshold high
		1325	* or low in function of ADC resolution, when ADC resolution is
		1326	* different of 12 bits.
		1327	* @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
		1328	* Example, with a ADC resolution of 8 bits, to set the value of
		1329	* analog watchdog threshold high (on 8 bits):
		1330	* LL_ADC_SetAnalogWDThresholds
		1331	* (< ADCx param >,
		1332	* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
		1333	* );
		1334	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
		1335	* @arg @ref LL_ADC_RESOLUTION_12B
		1336	* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
		1337	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		1338	*/
		1339	/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
		1340	/* This macro has been kept anyway for compatibility with other */
		1341	/* STM32 families featuring different ADC resolutions. */
		1342	#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
		1343	((__AWD_THRESHOLD__) << (0U))
		1344
		1345	/**
		1346	* @brief Helper macro to get the value of ADC analog watchdog threshold high
		1347	* or low in function of ADC resolution, when ADC resolution is
		1348	* different of 12 bits.
		1349	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
		1350	* Example, with a ADC resolution of 8 bits, to get the value of
		1351	* analog watchdog threshold high (on 8 bits):
		1352	* < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
		1353	* (LL_ADC_RESOLUTION_8B,
		1354	* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
		1355	* );
		1356	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
		1357	* @arg @ref LL_ADC_RESOLUTION_12B
		1358	* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
		1359	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		1360	*/
		1361	/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
		1362	/* This macro has been kept anyway for compatibility with other */
		1363	/* STM32 families featuring different ADC resolutions. */
		1364	#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
		1365	(__AWD_THRESHOLD_12_BITS__)
		1366
		1367	#if defined(ADC_MULTIMODE_SUPPORT)
		1368	/**
		1369	* @brief Helper macro to get the ADC multimode conversion data of ADC master
		1370	* or ADC slave from raw value with both ADC conversion data concatenated.
		1371	* @note This macro is intended to be used when multimode transfer by DMA
		1372	* is enabled.
		1373	* In this case the transferred data need to processed with this macro
		1374	* to separate the conversion data of ADC master and ADC slave.
		1375	* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
		1376	* @arg @ref LL_ADC_MULTI_MASTER
		1377	* @arg @ref LL_ADC_MULTI_SLAVE
		1378	* @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
		1379	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		1380	*/
		1381	#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
		1382	(((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)
		1383	#endif
		1384
		1385	/**
		1386	* @brief Helper macro to select the ADC common instance
		1387	* to which is belonging the selected ADC instance.
		1388	* @note ADC common register instance can be used for:
		1389	* - Set parameters common to several ADC instances
		1390	* - Multimode (for devices with several ADC instances)
		1391	* Refer to functions having argument "ADCxy_COMMON" as parameter.
		1392	* @note On STM32F1, there is no common ADC instance.
		1393	* However, ADC instance ADC1 has a role of common ADC instance
		1394	* for ADC1 and ADC2:
		1395	* this instance is used to manage internal channels
		1396	* and multimode (these features are managed in ADC common
		1397	* instances on some other STM32 devices).
		1398	* ADC instance ADC3 (if available on the selected device)
		1399	* has no ADC common instance.
		1400	* @param __ADCx__ ADC instance
		1401	* @retval ADC common register instance
		1402	*/
		1403	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
		1404	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
		1405	((((__ADCx__) == ADC1) \|\| ((__ADCx__) == ADC2)) \
		1406	? ( \
		1407	(ADC12_COMMON) \
		1408	) \
		1409	: \
		1410	( \
		1411	(0U) \
		1412	) \
		1413	)
		1414	#elif defined(ADC1) && defined(ADC2)
		1415	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
		1416	(ADC12_COMMON)
		1417	#else
		1418	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
		1419	(ADC1_COMMON)
		1420	#endif
		1421
		1422	/**
		1423	* @brief Helper macro to check if all ADC instances sharing the same
		1424	* ADC common instance are disabled.
		1425	* @note This check is required by functions with setting conditioned to
		1426	* ADC state:
		1427	* All ADC instances of the ADC common group must be disabled.
		1428	* Refer to functions having argument "ADCxy_COMMON" as parameter.
		1429	* @note On devices with only 1 ADC common instance, parameter of this macro
		1430	* is useless and can be ignored (parameter kept for compatibility
		1431	* with devices featuring several ADC common instances).
		1432	* @note On STM32F1, there is no common ADC instance.
		1433	* However, ADC instance ADC1 has a role of common ADC instance
		1434	* for ADC1 and ADC2:
		1435	* this instance is used to manage internal channels
		1436	* and multimode (these features are managed in ADC common
		1437	* instances on some other STM32 devices).
		1438	* ADC instance ADC3 (if available on the selected device)
		1439	* has no ADC common instance.
		1440	* @param __ADCXY_COMMON__ ADC common instance
		1441	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		1442	* @retval Value "0" if all ADC instances sharing the same ADC common instance
		1443	* are disabled.
		1444	* Value "1" if at least one ADC instance sharing the same ADC common instance
		1445	* is enabled.
		1446	*/
		1447	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
		1448	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
		1449	(((__ADCXY_COMMON__) == ADC12_COMMON) \
		1450	? ( \
		1451	(LL_ADC_IsEnabled(ADC1) \| \
		1452	LL_ADC_IsEnabled(ADC2) ) \
		1453	) \
		1454	: \
		1455	( \
		1456	LL_ADC_IsEnabled(ADC3) \
		1457	) \
		1458	)
		1459	#elif defined(ADC1) && defined(ADC2)
		1460	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
		1461	(LL_ADC_IsEnabled(ADC1) \| \
		1462	LL_ADC_IsEnabled(ADC2) )
		1463	#else
		1464	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
		1465	LL_ADC_IsEnabled(ADC1)
		1466	#endif
		1467
		1468	/**
		1469	* @brief Helper macro to define the ADC conversion data full-scale digital
		1470	* value corresponding to the selected ADC resolution.
		1471	* @note ADC conversion data full-scale corresponds to voltage range
		1472	* determined by analog voltage references Vref+ and Vref-
		1473	* (refer to reference manual).
		1474	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
		1475	* @arg @ref LL_ADC_RESOLUTION_12B
		1476	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
		1477	*/
		1478	#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
		1479	(0xFFFU)
		1480
		1481
		1482	/**
		1483	* @brief Helper macro to calculate the voltage (unit: mVolt)
		1484	* corresponding to a ADC conversion data (unit: digital value).
		1485	* @note Analog reference voltage (Vref+) must be known from
		1486	* user board environment or can be calculated using ADC measurement.
		1487	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
		1488	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
		1489	* (unit: digital value).
		1490	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
		1491	* @arg @ref LL_ADC_RESOLUTION_12B
		1492	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
		1493	*/
		1494	#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
		1495	__ADC_DATA__,\
		1496	__ADC_RESOLUTION__) \
		1497	((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
		1498	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
		1499	)
		1500
		1501
		1502	/**
		1503	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
		1504	* from ADC conversion data of internal temperature sensor.
		1505	* @note Computation is using temperature sensor typical values
		1506	* (refer to device datasheet).
		1507	* @note Calculation formula:
		1508	* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
		1509	* / Avg_Slope + CALx_TEMP
		1510	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
		1511	* (unit: digital value)
		1512	* Avg_Slope = temperature sensor slope
		1513	* (unit: uV/Degree Celsius)
		1514	* TS_TYP_CALx_VOLT = temperature sensor digital value at
		1515	* temperature CALx_TEMP (unit: mV)
		1516	* Caution: Calculation relevancy under reserve the temperature sensor
		1517	* of the current device has characteristics in line with
		1518	* datasheet typical values.
		1519	* If temperature sensor calibration values are available on
		1520	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
		1521	* temperature calculation will be more accurate using
		1522	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
		1523	* @note As calculation input, the analog reference voltage (Vref+) must be
		1524	* defined as it impacts the ADC LSB equivalent voltage.
		1525	* @note Analog reference voltage (Vref+) must be known from
		1526	* user board environment or can be calculated using ADC measurement.
		1527	* @note ADC measurement data must correspond to a resolution of 12bits
		1528	* (full scale digital value 4095). If not the case, the data must be
		1529	* preliminarily rescaled to an equivalent resolution of 12 bits.
		1530	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
		1531	* On STM32F1, refer to device datasheet parameter "Avg_Slope".
		1532	* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
		1533	* On STM32F1, refer to device datasheet parameter "V25".
		1534	* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
		1535	* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
		1536	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
		1537	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
		1538	* This parameter can be one of the following values:
		1539	* @arg @ref LL_ADC_RESOLUTION_12B
		1540	* @retval Temperature (unit: degree Celsius)
		1541	*/
		1542	#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
		1543	__TEMPSENSOR_TYP_CALX_V__,\
		1544	__TEMPSENSOR_CALX_TEMP__,\
		1545	__VREFANALOG_VOLTAGE__,\
		1546	__TEMPSENSOR_ADC_DATA__,\
		1547	__ADC_RESOLUTION__) \
		1548	((( ( \
		1549	(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
		1550	* 1000) \
		1551	- \
		1552	(int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
		1553	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
		1554	* 1000) \
		1555	) \
		1556	) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
		1557	) + (__TEMPSENSOR_CALX_TEMP__) \
		1558	)
		1559
		1560	/**
		1561	* @}
		1562	*/
		1563
		1564	/**
		1565	* @}
		1566	*/
		1567
		1568
		1569	/* Exported functions --------------------------------------------------------*/
		1570	/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
		1571	* @{
		1572	*/
		1573
		1574	/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
		1575	* @{
		1576	*/
		1577	/* Note: LL ADC functions to set DMA transfer are located into sections of */
		1578	/* configuration of ADC instance, groups and multimode (if available): */
		1579	/* @ref LL_ADC_REG_SetDMATransfer(), ... */
		1580
		1581	/**
		1582	* @brief Function to help to configure DMA transfer from ADC: retrieve the
		1583	* ADC register address from ADC instance and a list of ADC registers
		1584	* intended to be used (most commonly) with DMA transfer.
		1585	* @note These ADC registers are data registers:
		1586	* when ADC conversion data is available in ADC data registers,
		1587	* ADC generates a DMA transfer request.
		1588	* @note This macro is intended to be used with LL DMA driver, refer to
		1589	* function "LL_DMA_ConfigAddresses()".
		1590	* Example:
		1591	* LL_DMA_ConfigAddresses(DMA1,
		1592	* LL_DMA_CHANNEL_1,
		1593	* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
		1594	* (uint32_t)&< array or variable >,
		1595	* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
		1596	* @note For devices with several ADC: in multimode, some devices
		1597	* use a different data register outside of ADC instance scope
		1598	* (common data register). This macro manages this register difference,
		1599	* only ADC instance has to be set as parameter.
		1600	* @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer
		1601	* capability, not ADC2 (ADC2 and ADC3 instances not available on
		1602	* all devices).
		1603	* @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3.
		1604	* Therefore, the corresponding parameter of data transfer
		1605	* for multimode can be used only with ADC1 and ADC2.
		1606	* (ADC2 and ADC3 instances not available on all devices).
		1607	* @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
		1608	* @param ADCx ADC instance
		1609	* @param Register This parameter can be one of the following values:
		1610	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
		1611	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
		1612	*
		1613	* (1) Available on devices with several ADC instances.
		1614	* @retval ADC register address
		1615	*/
		1616	#if defined(ADC_MULTIMODE_SUPPORT)
		1617	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
		1618	{
		1619	register uint32_t data_reg_addr = 0U;
		1620
		1621	if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
		1622	{
		1623	/* Retrieve address of register DR */
		1624	data_reg_addr = (uint32_t)&(ADCx->DR);
		1625	}
		1626	else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
		1627	{
		1628	/* Retrieve address of register of multimode data */
		1629	data_reg_addr = (uint32_t)&(ADC12_COMMON->DR);
		1630	}
		1631
		1632	return data_reg_addr;
		1633	}
		1634	#else
		1635	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
		1636	{
		1637	/* Retrieve address of register DR */
		1638	return (uint32_t)&(ADCx->DR);
		1639	}
		1640	#endif
		1641
		1642	/**
		1643	* @}
		1644	*/
		1645
		1646	/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
		1647	* @{
		1648	*/
		1649
		1650	/**
		1651	* @brief Set parameter common to several ADC: measurement path to internal
		1652	* channels (VrefInt, temperature sensor, ...).
		1653	* @note One or several values can be selected.
		1654	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
		1655	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
		1656	* @note Stabilization time of measurement path to internal channel:
		1657	* After enabling internal paths, before starting ADC conversion,
		1658	* a delay is required for internal voltage reference and
		1659	* temperature sensor stabilization time.
		1660	* Refer to device datasheet.
		1661	* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
		1662	* @note ADC internal channel sampling time constraint:
		1663	* For ADC conversion of internal channels,
		1664	* a sampling time minimum value is required.
		1665	* Refer to device datasheet.
		1666	* @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
		1667	* @param ADCxy_COMMON ADC common instance
		1668	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		1669	* @param PathInternal This parameter can be a combination of the following values:
		1670	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
		1671	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
		1672	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
		1673	* @retval None
		1674	*/
		1675	__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
		1676	{
		1677	MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
		1678	}
		1679
		1680	/**
		1681	* @brief Get parameter common to several ADC: measurement path to internal
		1682	* channels (VrefInt, temperature sensor, ...).
		1683	* @note One or several values can be selected.
		1684	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
		1685	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
		1686	* @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
		1687	* @param ADCxy_COMMON ADC common instance
		1688	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		1689	* @retval Returned value can be a combination of the following values:
		1690	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
		1691	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
		1692	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
		1693	*/
		1694	__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
		1695	{
		1696	return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
		1697	}
		1698
		1699	/**
		1700	* @}
		1701	*/
		1702
		1703	/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
		1704	* @{
		1705	*/
		1706
		1707	/**
		1708	* @brief Set ADC conversion data alignment.
		1709	* @note Refer to reference manual for alignments formats
		1710	* dependencies to ADC resolutions.
		1711	* @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
		1712	* @param ADCx ADC instance
		1713	* @param DataAlignment This parameter can be one of the following values:
		1714	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
		1715	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
		1716	* @retval None
		1717	*/
		1718	__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
		1719	{
		1720	MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
		1721	}
		1722
		1723	/**
		1724	* @brief Get ADC conversion data alignment.
		1725	* @note Refer to reference manual for alignments formats
		1726	* dependencies to ADC resolutions.
		1727	* @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
		1728	* @param ADCx ADC instance
		1729	* @retval Returned value can be one of the following values:
		1730	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
		1731	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
		1732	*/
		1733	__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
		1734	{
		1735	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
		1736	}
		1737
		1738	/**
		1739	* @brief Set ADC sequencers scan mode, for all ADC groups
		1740	* (group regular, group injected).
		1741	* @note According to sequencers scan mode :
		1742	* - If disabled: ADC conversion is performed in unitary conversion
		1743	* mode (one channel converted, that defined in rank 1).
		1744	* Configuration of sequencers of all ADC groups
		1745	* (sequencer scan length, ...) is discarded: equivalent to
		1746	* scan length of 1 rank.
		1747	* - If enabled: ADC conversions are performed in sequence conversions
		1748	* mode, according to configuration of sequencers of
		1749	* each ADC group (sequencer scan length, ...).
		1750	* Refer to function @ref LL_ADC_REG_SetSequencerLength()
		1751	* and to function @ref LL_ADC_INJ_SetSequencerLength().
		1752	* @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
		1753	* @param ADCx ADC instance
		1754	* @param ScanMode This parameter can be one of the following values:
		1755	* @arg @ref LL_ADC_SEQ_SCAN_DISABLE
		1756	* @arg @ref LL_ADC_SEQ_SCAN_ENABLE
		1757	* @retval None
		1758	*/
		1759	__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
		1760	{
		1761	MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
		1762	}
		1763
		1764	/**
		1765	* @brief Get ADC sequencers scan mode, for all ADC groups
		1766	* (group regular, group injected).
		1767	* @note According to sequencers scan mode :
		1768	* - If disabled: ADC conversion is performed in unitary conversion
		1769	* mode (one channel converted, that defined in rank 1).
		1770	* Configuration of sequencers of all ADC groups
		1771	* (sequencer scan length, ...) is discarded: equivalent to
		1772	* scan length of 1 rank.
		1773	* - If enabled: ADC conversions are performed in sequence conversions
		1774	* mode, according to configuration of sequencers of
		1775	* each ADC group (sequencer scan length, ...).
		1776	* Refer to function @ref LL_ADC_REG_SetSequencerLength()
		1777	* and to function @ref LL_ADC_INJ_SetSequencerLength().
		1778	* @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
		1779	* @param ADCx ADC instance
		1780	* @retval Returned value can be one of the following values:
		1781	* @arg @ref LL_ADC_SEQ_SCAN_DISABLE
		1782	* @arg @ref LL_ADC_SEQ_SCAN_ENABLE
		1783	*/
		1784	__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
		1785	{
		1786	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
		1787	}
		1788
		1789	/**
		1790	* @}
		1791	*/
		1792
		1793	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
		1794	* @{
		1795	*/
		1796
		1797	/**
		1798	* @brief Set ADC group regular conversion trigger source:
		1799	* internal (SW start) or from external IP (timer event,
		1800	* external interrupt line).
		1801	* @note On this STM32 serie, external trigger is set with trigger polarity:
		1802	* rising edge (only trigger polarity available on this STM32 serie).
		1803	* @note Availability of parameters of trigger sources from timer
		1804	* depends on timers availability on the selected device.
		1805	* @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
		1806	* @param ADCx ADC instance
		1807	* @param TriggerSource This parameter can be one of the following values:
		1808	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
		1809	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
		1810	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
		1811	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
		1812	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
		1813	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
		1814	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
		1815	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
		1816	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
		1817	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
		1818	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
		1819	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
		1820	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
		1821	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
		1822	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
		1823	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
		1824	*
		1825	* (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
		1826	* (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
		1827	* (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
		1828	* (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
		1829	* @retval None
		1830	*/
		1831	__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
		1832	{
		1833	/* Note: On this STM32 serie, ADC group regular external trigger edge */
		1834	/* is used to perform a ADC conversion start. */
		1835	/* This function does not set external trigger edge. */
		1836	/* This feature is set using function */
		1837	/* @ref LL_ADC_REG_StartConversionExtTrig(). */
		1838	MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
		1839	}
		1840
		1841	/**
		1842	* @brief Get ADC group regular conversion trigger source:
		1843	* internal (SW start) or from external IP (timer event,
		1844	* external interrupt line).
		1845	* @note To determine whether group regular trigger source is
		1846	* internal (SW start) or external, without detail
		1847	* of which peripheral is selected as external trigger,
		1848	* (equivalent to
		1849	* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
		1850	* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
		1851	* @note Availability of parameters of trigger sources from timer
		1852	* depends on timers availability on the selected device.
		1853	* @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
		1854	* @param ADCx ADC instance
		1855	* @retval Returned value can be one of the following values:
		1856	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
		1857	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
		1858	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
		1859	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
		1860	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
		1861	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
		1862	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
		1863	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
		1864	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
		1865	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
		1866	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
		1867	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
		1868	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
		1869	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
		1870	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
		1871	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
		1872	*
		1873	* (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
		1874	* (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
		1875	* (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
		1876	* (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
		1877	*/
		1878	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
		1879	{
		1880	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
		1881	}
		1882
		1883	/**
		1884	* @brief Get ADC group regular conversion trigger source internal (SW start)
		1885	or external.
		1886	* @note In case of group regular trigger source set to external trigger,
		1887	* to determine which peripheral is selected as external trigger,
		1888	* use function @ref LL_ADC_REG_GetTriggerSource().
		1889	* @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
		1890	* @param ADCx ADC instance
		1891	* @retval Value "0" if trigger source external trigger
		1892	* Value "1" if trigger source SW start.
		1893	*/
		1894	__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
		1895	{
		1896	return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
		1897	}
		1898
		1899
		1900	/**
		1901	* @brief Set ADC group regular sequencer length and scan direction.
		1902	* @note Description of ADC group regular sequencer features:
		1903	* - For devices with sequencer fully configurable
		1904	* (function "LL_ADC_REG_SetSequencerRanks()" available):
		1905	* sequencer length and each rank affectation to a channel
		1906	* are configurable.
		1907	* This function performs configuration of:
		1908	* - Sequence length: Number of ranks in the scan sequence.
		1909	* - Sequence direction: Unless specified in parameters, sequencer
		1910	* scan direction is forward (from rank 1 to rank n).
		1911	* Sequencer ranks are selected using
		1912	* function "LL_ADC_REG_SetSequencerRanks()".
		1913	* - For devices with sequencer not fully configurable
		1914	* (function "LL_ADC_REG_SetSequencerChannels()" available):
		1915	* sequencer length and each rank affectation to a channel
		1916	* are defined by channel number.
		1917	* This function performs configuration of:
		1918	* - Sequence length: Number of ranks in the scan sequence is
		1919	* defined by number of channels set in the sequence,
		1920	* rank of each channel is fixed by channel HW number.
		1921	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
		1922	* - Sequence direction: Unless specified in parameters, sequencer
		1923	* scan direction is forward (from lowest channel number to
		1924	* highest channel number).
		1925	* Sequencer ranks are selected using
		1926	* function "LL_ADC_REG_SetSequencerChannels()".
		1927	* @note On this STM32 serie, group regular sequencer configuration
		1928	* is conditioned to ADC instance sequencer mode.
		1929	* If ADC instance sequencer mode is disabled, sequencers of
		1930	* all groups (group regular, group injected) can be configured
		1931	* but their execution is disabled (limited to rank 1).
		1932	* Refer to function @ref LL_ADC_SetSequencersScanMode().
		1933	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
		1934	* ADC conversion on only 1 channel.
		1935	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
		1936	* @param ADCx ADC instance
		1937	* @param SequencerNbRanks This parameter can be one of the following values:
		1938	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
		1939	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
		1940	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
		1941	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
		1942	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
		1943	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
		1944	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
		1945	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
		1946	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
		1947	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
		1948	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
		1949	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
		1950	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
		1951	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
		1952	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
		1953	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
		1954	* @retval None
		1955	*/
		1956	__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
		1957	{
		1958	MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
		1959	}
		1960
		1961	/**
		1962	* @brief Get ADC group regular sequencer length and scan direction.
		1963	* @note Description of ADC group regular sequencer features:
		1964	* - For devices with sequencer fully configurable
		1965	* (function "LL_ADC_REG_SetSequencerRanks()" available):
		1966	* sequencer length and each rank affectation to a channel
		1967	* are configurable.
		1968	* This function retrieves:
		1969	* - Sequence length: Number of ranks in the scan sequence.
		1970	* - Sequence direction: Unless specified in parameters, sequencer
		1971	* scan direction is forward (from rank 1 to rank n).
		1972	* Sequencer ranks are selected using
		1973	* function "LL_ADC_REG_SetSequencerRanks()".
		1974	* - For devices with sequencer not fully configurable
		1975	* (function "LL_ADC_REG_SetSequencerChannels()" available):
		1976	* sequencer length and each rank affectation to a channel
		1977	* are defined by channel number.
		1978	* This function retrieves:
		1979	* - Sequence length: Number of ranks in the scan sequence is
		1980	* defined by number of channels set in the sequence,
		1981	* rank of each channel is fixed by channel HW number.
		1982	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
		1983	* - Sequence direction: Unless specified in parameters, sequencer
		1984	* scan direction is forward (from lowest channel number to
		1985	* highest channel number).
		1986	* Sequencer ranks are selected using
		1987	* function "LL_ADC_REG_SetSequencerChannels()".
		1988	* @note On this STM32 serie, group regular sequencer configuration
		1989	* is conditioned to ADC instance sequencer mode.
		1990	* If ADC instance sequencer mode is disabled, sequencers of
		1991	* all groups (group regular, group injected) can be configured
		1992	* but their execution is disabled (limited to rank 1).
		1993	* Refer to function @ref LL_ADC_SetSequencersScanMode().
		1994	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
		1995	* ADC conversion on only 1 channel.
		1996	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
		1997	* @param ADCx ADC instance
		1998	* @retval Returned value can be one of the following values:
		1999	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
		2000	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
		2001	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
		2002	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
		2003	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
		2004	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
		2005	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
		2006	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
		2007	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
		2008	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
		2009	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
		2010	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
		2011	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
		2012	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
		2013	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
		2014	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
		2015	*/
		2016	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
		2017	{
		2018	return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
		2019	}
		2020
		2021	/**
		2022	* @brief Set ADC group regular sequencer discontinuous mode:
		2023	* sequence subdivided and scan conversions interrupted every selected
		2024	* number of ranks.
		2025	* @note It is not possible to enable both ADC group regular
		2026	* continuous mode and sequencer discontinuous mode.
		2027	* @note It is not possible to enable both ADC auto-injected mode
		2028	* and ADC group regular sequencer discontinuous mode.
		2029	* @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
		2030	* CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
		2031	* @param ADCx ADC instance
		2032	* @param SeqDiscont This parameter can be one of the following values:
		2033	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
		2034	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
		2035	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
		2036	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
		2037	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
		2038	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
		2039	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
		2040	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
		2041	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
		2042	* @retval None
		2043	*/
		2044	__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
		2045	{
		2046	MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN \| ADC_CR1_DISCNUM, SeqDiscont);
		2047	}
		2048
		2049	/**
		2050	* @brief Get ADC group regular sequencer discontinuous mode:
		2051	* sequence subdivided and scan conversions interrupted every selected
		2052	* number of ranks.
		2053	* @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
		2054	* CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
		2055	* @param ADCx ADC instance
		2056	* @retval Returned value can be one of the following values:
		2057	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
		2058	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
		2059	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
		2060	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
		2061	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
		2062	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
		2063	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
		2064	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
		2065	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
		2066	*/
		2067	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
		2068	{
		2069	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN \| ADC_CR1_DISCNUM));
		2070	}
		2071
		2072	/**
		2073	* @brief Set ADC group regular sequence: channel on the selected
		2074	* scan sequence rank.
		2075	* @note This function performs configuration of:
		2076	* - Channels ordering into each rank of scan sequence:
		2077	* whatever channel can be placed into whatever rank.
		2078	* @note On this STM32 serie, ADC group regular sequencer is
		2079	* fully configurable: sequencer length and each rank
		2080	* affectation to a channel are configurable.
		2081	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
		2082	* @note Depending on devices and packages, some channels may not be available.
		2083	* Refer to device datasheet for channels availability.
		2084	* @note On this STM32 serie, to measure internal channels (VrefInt,
		2085	* TempSensor, ...), measurement paths to internal channels must be
		2086	* enabled separately.
		2087	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
		2088	* @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
		2089	* SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
		2090	* SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
		2091	* SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
		2092	* SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
		2093	* SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
		2094	* SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
		2095	* SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
		2096	* SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
		2097	* SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
		2098	* SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
		2099	* SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
		2100	* SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
		2101	* SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
		2102	* SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
		2103	* SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
		2104	* @param ADCx ADC instance
		2105	* @param Rank This parameter can be one of the following values:
		2106	* @arg @ref LL_ADC_REG_RANK_1
		2107	* @arg @ref LL_ADC_REG_RANK_2
		2108	* @arg @ref LL_ADC_REG_RANK_3
		2109	* @arg @ref LL_ADC_REG_RANK_4
		2110	* @arg @ref LL_ADC_REG_RANK_5
		2111	* @arg @ref LL_ADC_REG_RANK_6
		2112	* @arg @ref LL_ADC_REG_RANK_7
		2113	* @arg @ref LL_ADC_REG_RANK_8
		2114	* @arg @ref LL_ADC_REG_RANK_9
		2115	* @arg @ref LL_ADC_REG_RANK_10
		2116	* @arg @ref LL_ADC_REG_RANK_11
		2117	* @arg @ref LL_ADC_REG_RANK_12
		2118	* @arg @ref LL_ADC_REG_RANK_13
		2119	* @arg @ref LL_ADC_REG_RANK_14
		2120	* @arg @ref LL_ADC_REG_RANK_15
		2121	* @arg @ref LL_ADC_REG_RANK_16
		2122	* @param Channel This parameter can be one of the following values:
		2123	* @arg @ref LL_ADC_CHANNEL_0
		2124	* @arg @ref LL_ADC_CHANNEL_1
		2125	* @arg @ref LL_ADC_CHANNEL_2
		2126	* @arg @ref LL_ADC_CHANNEL_3
		2127	* @arg @ref LL_ADC_CHANNEL_4
		2128	* @arg @ref LL_ADC_CHANNEL_5
		2129	* @arg @ref LL_ADC_CHANNEL_6
		2130	* @arg @ref LL_ADC_CHANNEL_7
		2131	* @arg @ref LL_ADC_CHANNEL_8
		2132	* @arg @ref LL_ADC_CHANNEL_9
		2133	* @arg @ref LL_ADC_CHANNEL_10
		2134	* @arg @ref LL_ADC_CHANNEL_11
		2135	* @arg @ref LL_ADC_CHANNEL_12
		2136	* @arg @ref LL_ADC_CHANNEL_13
		2137	* @arg @ref LL_ADC_CHANNEL_14
		2138	* @arg @ref LL_ADC_CHANNEL_15
		2139	* @arg @ref LL_ADC_CHANNEL_16
		2140	* @arg @ref LL_ADC_CHANNEL_17
		2141	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		2142	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		2143	*
		2144	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		2145	* @retval None
		2146	*/
		2147	__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
		2148	{
		2149	/* Set bits with content of parameter "Channel" with bits position */
		2150	/* in register and register position depending on parameter "Rank". */
		2151	/* Parameters "Rank" and "Channel" are used with masks because containing */
		2152	/* other bits reserved for other purpose. */
		2153	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
		2154
		2155	MODIFY_REG(*preg,
		2156	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
		2157	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
		2158	}
		2159
		2160	/**
		2161	* @brief Get ADC group regular sequence: channel on the selected
		2162	* scan sequence rank.
		2163	* @note On this STM32 serie, ADC group regular sequencer is
		2164	* fully configurable: sequencer length and each rank
		2165	* affectation to a channel are configurable.
		2166	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
		2167	* @note Depending on devices and packages, some channels may not be available.
		2168	* Refer to device datasheet for channels availability.
		2169	* @note Usage of the returned channel number:
		2170	* - To reinject this channel into another function LL_ADC_xxx:
		2171	* the returned channel number is only partly formatted on definition
		2172	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
		2173	* with parts of literals LL_ADC_CHANNEL_x or using
		2174	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
		2175	* Then the selected literal LL_ADC_CHANNEL_x can be used
		2176	* as parameter for another function.
		2177	* - To get the channel number in decimal format:
		2178	* process the returned value with the helper macro
		2179	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
		2180	* @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
		2181	* SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
		2182	* SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
		2183	* SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
		2184	* SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
		2185	* SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
		2186	* SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
		2187	* SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
		2188	* SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
		2189	* SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
		2190	* SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
		2191	* SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
		2192	* SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
		2193	* SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
		2194	* SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
		2195	* SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
		2196	* @param ADCx ADC instance
		2197	* @param Rank This parameter can be one of the following values:
		2198	* @arg @ref LL_ADC_REG_RANK_1
		2199	* @arg @ref LL_ADC_REG_RANK_2
		2200	* @arg @ref LL_ADC_REG_RANK_3
		2201	* @arg @ref LL_ADC_REG_RANK_4
		2202	* @arg @ref LL_ADC_REG_RANK_5
		2203	* @arg @ref LL_ADC_REG_RANK_6
		2204	* @arg @ref LL_ADC_REG_RANK_7
		2205	* @arg @ref LL_ADC_REG_RANK_8
		2206	* @arg @ref LL_ADC_REG_RANK_9
		2207	* @arg @ref LL_ADC_REG_RANK_10
		2208	* @arg @ref LL_ADC_REG_RANK_11
		2209	* @arg @ref LL_ADC_REG_RANK_12
		2210	* @arg @ref LL_ADC_REG_RANK_13
		2211	* @arg @ref LL_ADC_REG_RANK_14
		2212	* @arg @ref LL_ADC_REG_RANK_15
		2213	* @arg @ref LL_ADC_REG_RANK_16
		2214	* @retval Returned value can be one of the following values:
		2215	* @arg @ref LL_ADC_CHANNEL_0
		2216	* @arg @ref LL_ADC_CHANNEL_1
		2217	* @arg @ref LL_ADC_CHANNEL_2
		2218	* @arg @ref LL_ADC_CHANNEL_3
		2219	* @arg @ref LL_ADC_CHANNEL_4
		2220	* @arg @ref LL_ADC_CHANNEL_5
		2221	* @arg @ref LL_ADC_CHANNEL_6
		2222	* @arg @ref LL_ADC_CHANNEL_7
		2223	* @arg @ref LL_ADC_CHANNEL_8
		2224	* @arg @ref LL_ADC_CHANNEL_9
		2225	* @arg @ref LL_ADC_CHANNEL_10
		2226	* @arg @ref LL_ADC_CHANNEL_11
		2227	* @arg @ref LL_ADC_CHANNEL_12
		2228	* @arg @ref LL_ADC_CHANNEL_13
		2229	* @arg @ref LL_ADC_CHANNEL_14
		2230	* @arg @ref LL_ADC_CHANNEL_15
		2231	* @arg @ref LL_ADC_CHANNEL_16
		2232	* @arg @ref LL_ADC_CHANNEL_17
		2233	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		2234	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		2235	*
		2236	* (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
		2237	* (1) For ADC channel read back from ADC register,
		2238	* comparison with internal channel parameter to be done
		2239	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
		2240	*/
		2241	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
		2242	{
		2243	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
		2244
		2245	return (uint32_t) (READ_BIT(*preg,
		2246	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
		2247	>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
		2248	);
		2249	}
		2250
		2251	/**
		2252	* @brief Set ADC continuous conversion mode on ADC group regular.
		2253	* @note Description of ADC continuous conversion mode:
		2254	* - single mode: one conversion per trigger
		2255	* - continuous mode: after the first trigger, following
		2256	* conversions launched successively automatically.
		2257	* @note It is not possible to enable both ADC group regular
		2258	* continuous mode and sequencer discontinuous mode.
		2259	* @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
		2260	* @param ADCx ADC instance
		2261	* @param Continuous This parameter can be one of the following values:
		2262	* @arg @ref LL_ADC_REG_CONV_SINGLE
		2263	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
		2264	* @retval None
		2265	*/
		2266	__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
		2267	{
		2268	MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
		2269	}
		2270
		2271	/**
		2272	* @brief Get ADC continuous conversion mode on ADC group regular.
		2273	* @note Description of ADC continuous conversion mode:
		2274	* - single mode: one conversion per trigger
		2275	* - continuous mode: after the first trigger, following
		2276	* conversions launched successively automatically.
		2277	* @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
		2278	* @param ADCx ADC instance
		2279	* @retval Returned value can be one of the following values:
		2280	* @arg @ref LL_ADC_REG_CONV_SINGLE
		2281	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
		2282	*/
		2283	__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
		2284	{
		2285	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
		2286	}
		2287
		2288	/**
		2289	* @brief Set ADC group regular conversion data transfer: no transfer or
		2290	* transfer by DMA, and DMA requests mode.
		2291	* @note If transfer by DMA selected, specifies the DMA requests
		2292	* mode:
		2293	* - Limited mode (One shot mode): DMA transfer requests are stopped
		2294	* when number of DMA data transfers (number of
		2295	* ADC conversions) is reached.
		2296	* This ADC mode is intended to be used with DMA mode non-circular.
		2297	* - Unlimited mode: DMA transfer requests are unlimited,
		2298	* whatever number of DMA data transfers (number of
		2299	* ADC conversions).
		2300	* This ADC mode is intended to be used with DMA mode circular.
		2301	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
		2302	* mode non-circular:
		2303	* when DMA transfers size will be reached, DMA will stop transfers of
		2304	* ADC conversions data ADC will raise an overrun error
		2305	* (overrun flag and interruption if enabled).
		2306	* @note To configure DMA source address (peripheral address),
		2307	* use function @ref LL_ADC_DMA_GetRegAddr().
		2308	* @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
		2309	* @param ADCx ADC instance
		2310	* @param DMATransfer This parameter can be one of the following values:
		2311	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
		2312	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
		2313	* @retval None
		2314	*/
		2315	__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
		2316	{
		2317	MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
		2318	}
		2319
		2320	/**
		2321	* @brief Get ADC group regular conversion data transfer: no transfer or
		2322	* transfer by DMA, and DMA requests mode.
		2323	* @note If transfer by DMA selected, specifies the DMA requests
		2324	* mode:
		2325	* - Limited mode (One shot mode): DMA transfer requests are stopped
		2326	* when number of DMA data transfers (number of
		2327	* ADC conversions) is reached.
		2328	* This ADC mode is intended to be used with DMA mode non-circular.
		2329	* - Unlimited mode: DMA transfer requests are unlimited,
		2330	* whatever number of DMA data transfers (number of
		2331	* ADC conversions).
		2332	* This ADC mode is intended to be used with DMA mode circular.
		2333	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
		2334	* mode non-circular:
		2335	* when DMA transfers size will be reached, DMA will stop transfers of
		2336	* ADC conversions data ADC will raise an overrun error
		2337	* (overrun flag and interruption if enabled).
		2338	* @note To configure DMA source address (peripheral address),
		2339	* use function @ref LL_ADC_DMA_GetRegAddr().
		2340	* @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
		2341	* @param ADCx ADC instance
		2342	* @retval Returned value can be one of the following values:
		2343	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
		2344	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
		2345	*/
		2346	__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
		2347	{
		2348	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
		2349	}
		2350
		2351	/**
		2352	* @}
		2353	*/
		2354
		2355	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
		2356	* @{
		2357	*/
		2358
		2359	/**
		2360	* @brief Set ADC group injected conversion trigger source:
		2361	* internal (SW start) or from external IP (timer event,
		2362	* external interrupt line).
		2363	* @note On this STM32 serie, external trigger is set with trigger polarity:
		2364	* rising edge (only trigger polarity available on this STM32 serie).
		2365	* @note Availability of parameters of trigger sources from timer
		2366	* depends on timers availability on the selected device.
		2367	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
		2368	* @param ADCx ADC instance
		2369	* @param TriggerSource This parameter can be one of the following values:
		2370	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
		2371	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
		2372	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
		2373	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
		2374	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
		2375	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
		2376	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
		2377	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
		2378	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
		2379	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
		2380	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
		2381	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
		2382	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
		2383	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
		2384	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
		2385	*
		2386	* (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
		2387	* (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
		2388	* (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
		2389	* (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
		2390	* @retval None
		2391	*/
		2392	__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
		2393	{
		2394	/* Note: On this STM32 serie, ADC group injected external trigger edge */
		2395	/* is used to perform a ADC conversion start. */
		2396	/* This function does not set external trigger edge. */
		2397	/* This feature is set using function */
		2398	/* @ref LL_ADC_INJ_StartConversionExtTrig(). */
		2399	MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
		2400	}
		2401
		2402	/**
		2403	* @brief Get ADC group injected conversion trigger source:
		2404	* internal (SW start) or from external IP (timer event,
		2405	* external interrupt line).
		2406	* @note To determine whether group injected trigger source is
		2407	* internal (SW start) or external, without detail
		2408	* of which peripheral is selected as external trigger,
		2409	* (equivalent to
		2410	* "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
		2411	* use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
		2412	* @note Availability of parameters of trigger sources from timer
		2413	* depends on timers availability on the selected device.
		2414	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
		2415	* @param ADCx ADC instance
		2416	* @retval Returned value can be one of the following values:
		2417	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
		2418	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
		2419	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
		2420	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
		2421	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
		2422	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
		2423	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
		2424	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
		2425	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
		2426	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
		2427	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
		2428	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
		2429	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
		2430	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
		2431	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
		2432	*
		2433	* (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
		2434	* (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
		2435	* (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
		2436	* (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
		2437	*/
		2438	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
		2439	{
		2440	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
		2441	}
		2442
		2443	/**
		2444	* @brief Get ADC group injected conversion trigger source internal (SW start)
		2445	or external
		2446	* @note In case of group injected trigger source set to external trigger,
		2447	* to determine which peripheral is selected as external trigger,
		2448	* use function @ref LL_ADC_INJ_GetTriggerSource.
		2449	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
		2450	* @param ADCx ADC instance
		2451	* @retval Value "0" if trigger source external trigger
		2452	* Value "1" if trigger source SW start.
		2453	*/
		2454	__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
		2455	{
		2456	return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
		2457	}
		2458
		2459	/**
		2460	* @brief Set ADC group injected sequencer length and scan direction.
		2461	* @note This function performs configuration of:
		2462	* - Sequence length: Number of ranks in the scan sequence.
		2463	* - Sequence direction: Unless specified in parameters, sequencer
		2464	* scan direction is forward (from rank 1 to rank n).
		2465	* @note On this STM32 serie, group injected sequencer configuration
		2466	* is conditioned to ADC instance sequencer mode.
		2467	* If ADC instance sequencer mode is disabled, sequencers of
		2468	* all groups (group regular, group injected) can be configured
		2469	* but their execution is disabled (limited to rank 1).
		2470	* Refer to function @ref LL_ADC_SetSequencersScanMode().
		2471	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
		2472	* ADC conversion on only 1 channel.
		2473	* @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
		2474	* @param ADCx ADC instance
		2475	* @param SequencerNbRanks This parameter can be one of the following values:
		2476	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
		2477	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
		2478	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
		2479	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
		2480	* @retval None
		2481	*/
		2482	__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
		2483	{
		2484	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
		2485	}
		2486
		2487	/**
		2488	* @brief Get ADC group injected sequencer length and scan direction.
		2489	* @note This function retrieves:
		2490	* - Sequence length: Number of ranks in the scan sequence.
		2491	* - Sequence direction: Unless specified in parameters, sequencer
		2492	* scan direction is forward (from rank 1 to rank n).
		2493	* @note On this STM32 serie, group injected sequencer configuration
		2494	* is conditioned to ADC instance sequencer mode.
		2495	* If ADC instance sequencer mode is disabled, sequencers of
		2496	* all groups (group regular, group injected) can be configured
		2497	* but their execution is disabled (limited to rank 1).
		2498	* Refer to function @ref LL_ADC_SetSequencersScanMode().
		2499	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
		2500	* ADC conversion on only 1 channel.
		2501	* @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
		2502	* @param ADCx ADC instance
		2503	* @retval Returned value can be one of the following values:
		2504	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
		2505	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
		2506	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
		2507	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
		2508	*/
		2509	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
		2510	{
		2511	return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
		2512	}
		2513
		2514	/**
		2515	* @brief Set ADC group injected sequencer discontinuous mode:
		2516	* sequence subdivided and scan conversions interrupted every selected
		2517	* number of ranks.
		2518	* @note It is not possible to enable both ADC group injected
		2519	* auto-injected mode and sequencer discontinuous mode.
		2520	* @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
		2521	* @param ADCx ADC instance
		2522	* @param SeqDiscont This parameter can be one of the following values:
		2523	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
		2524	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
		2525	* @retval None
		2526	*/
		2527	__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
		2528	{
		2529	MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
		2530	}
		2531
		2532	/**
		2533	* @brief Get ADC group injected sequencer discontinuous mode:
		2534	* sequence subdivided and scan conversions interrupted every selected
		2535	* number of ranks.
		2536	* @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
		2537	* @param ADCx ADC instance
		2538	* @retval Returned value can be one of the following values:
		2539	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
		2540	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
		2541	*/
		2542	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
		2543	{
		2544	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
		2545	}
		2546
		2547	/**
		2548	* @brief Set ADC group injected sequence: channel on the selected
		2549	* sequence rank.
		2550	* @note Depending on devices and packages, some channels may not be available.
		2551	* Refer to device datasheet for channels availability.
		2552	* @note On this STM32 serie, to measure internal channels (VrefInt,
		2553	* TempSensor, ...), measurement paths to internal channels must be
		2554	* enabled separately.
		2555	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
		2556	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
		2557	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
		2558	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
		2559	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
		2560	* @param ADCx ADC instance
		2561	* @param Rank This parameter can be one of the following values:
		2562	* @arg @ref LL_ADC_INJ_RANK_1
		2563	* @arg @ref LL_ADC_INJ_RANK_2
		2564	* @arg @ref LL_ADC_INJ_RANK_3
		2565	* @arg @ref LL_ADC_INJ_RANK_4
		2566	* @param Channel This parameter can be one of the following values:
		2567	* @arg @ref LL_ADC_CHANNEL_0
		2568	* @arg @ref LL_ADC_CHANNEL_1
		2569	* @arg @ref LL_ADC_CHANNEL_2
		2570	* @arg @ref LL_ADC_CHANNEL_3
		2571	* @arg @ref LL_ADC_CHANNEL_4
		2572	* @arg @ref LL_ADC_CHANNEL_5
		2573	* @arg @ref LL_ADC_CHANNEL_6
		2574	* @arg @ref LL_ADC_CHANNEL_7
		2575	* @arg @ref LL_ADC_CHANNEL_8
		2576	* @arg @ref LL_ADC_CHANNEL_9
		2577	* @arg @ref LL_ADC_CHANNEL_10
		2578	* @arg @ref LL_ADC_CHANNEL_11
		2579	* @arg @ref LL_ADC_CHANNEL_12
		2580	* @arg @ref LL_ADC_CHANNEL_13
		2581	* @arg @ref LL_ADC_CHANNEL_14
		2582	* @arg @ref LL_ADC_CHANNEL_15
		2583	* @arg @ref LL_ADC_CHANNEL_16
		2584	* @arg @ref LL_ADC_CHANNEL_17
		2585	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		2586	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		2587	*
		2588	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		2589	* @retval None
		2590	*/
		2591	__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
		2592	{
		2593	/* Set bits with content of parameter "Channel" with bits position */
		2594	/* in register depending on parameter "Rank". */
		2595	/* Parameters "Rank" and "Channel" are used with masks because containing */
		2596	/* other bits reserved for other purpose. */
		2597	register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
		2598
		2599	MODIFY_REG(ADCx->JSQR,
		2600	ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
		2601	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
		2602	}
		2603
		2604	/**
		2605	* @brief Get ADC group injected sequence: channel on the selected
		2606	* sequence rank.
		2607	* @note Depending on devices and packages, some channels may not be available.
		2608	* Refer to device datasheet for channels availability.
		2609	* @note Usage of the returned channel number:
		2610	* - To reinject this channel into another function LL_ADC_xxx:
		2611	* the returned channel number is only partly formatted on definition
		2612	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
		2613	* with parts of literals LL_ADC_CHANNEL_x or using
		2614	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
		2615	* Then the selected literal LL_ADC_CHANNEL_x can be used
		2616	* as parameter for another function.
		2617	* - To get the channel number in decimal format:
		2618	* process the returned value with the helper macro
		2619	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
		2620	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
		2621	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
		2622	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
		2623	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
		2624	* @param ADCx ADC instance
		2625	* @param Rank This parameter can be one of the following values:
		2626	* @arg @ref LL_ADC_INJ_RANK_1
		2627	* @arg @ref LL_ADC_INJ_RANK_2
		2628	* @arg @ref LL_ADC_INJ_RANK_3
		2629	* @arg @ref LL_ADC_INJ_RANK_4
		2630	* @retval Returned value can be one of the following values:
		2631	* @arg @ref LL_ADC_CHANNEL_0
		2632	* @arg @ref LL_ADC_CHANNEL_1
		2633	* @arg @ref LL_ADC_CHANNEL_2
		2634	* @arg @ref LL_ADC_CHANNEL_3
		2635	* @arg @ref LL_ADC_CHANNEL_4
		2636	* @arg @ref LL_ADC_CHANNEL_5
		2637	* @arg @ref LL_ADC_CHANNEL_6
		2638	* @arg @ref LL_ADC_CHANNEL_7
		2639	* @arg @ref LL_ADC_CHANNEL_8
		2640	* @arg @ref LL_ADC_CHANNEL_9
		2641	* @arg @ref LL_ADC_CHANNEL_10
		2642	* @arg @ref LL_ADC_CHANNEL_11
		2643	* @arg @ref LL_ADC_CHANNEL_12
		2644	* @arg @ref LL_ADC_CHANNEL_13
		2645	* @arg @ref LL_ADC_CHANNEL_14
		2646	* @arg @ref LL_ADC_CHANNEL_15
		2647	* @arg @ref LL_ADC_CHANNEL_16
		2648	* @arg @ref LL_ADC_CHANNEL_17
		2649	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		2650	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		2651	*
		2652	* (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
		2653	* (1) For ADC channel read back from ADC register,
		2654	* comparison with internal channel parameter to be done
		2655	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
		2656	*/
		2657	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
		2658	{
		2659	register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
		2660
		2661	return (uint32_t)(READ_BIT(ADCx->JSQR,
		2662	ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
		2663	>> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
		2664	);
		2665	}
		2666
		2667	/**
		2668	* @brief Set ADC group injected conversion trigger:
		2669	* independent or from ADC group regular.
		2670	* @note This mode can be used to extend number of data registers
		2671	* updated after one ADC conversion trigger and with data
		2672	* permanently kept (not erased by successive conversions of scan of
		2673	* ADC sequencer ranks), up to 5 data registers:
		2674	* 1 data register on ADC group regular, 4 data registers
		2675	* on ADC group injected.
		2676	* @note If ADC group injected injected trigger source is set to an
		2677	* external trigger, this feature must be must be set to
		2678	* independent trigger.
		2679	* ADC group injected automatic trigger is compliant only with
		2680	* group injected trigger source set to SW start, without any
		2681	* further action on ADC group injected conversion start or stop:
		2682	* in this case, ADC group injected is controlled only
		2683	* from ADC group regular.
		2684	* @note It is not possible to enable both ADC group injected
		2685	* auto-injected mode and sequencer discontinuous mode.
		2686	* @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
		2687	* @param ADCx ADC instance
		2688	* @param TrigAuto This parameter can be one of the following values:
		2689	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
		2690	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
		2691	* @retval None
		2692	*/
		2693	__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
		2694	{
		2695	MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
		2696	}
		2697
		2698	/**
		2699	* @brief Get ADC group injected conversion trigger:
		2700	* independent or from ADC group regular.
		2701	* @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
		2702	* @param ADCx ADC instance
		2703	* @retval Returned value can be one of the following values:
		2704	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
		2705	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
		2706	*/
		2707	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
		2708	{
		2709	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
		2710	}
		2711
		2712	/**
		2713	* @brief Set ADC group injected offset.
		2714	* @note It sets:
		2715	* - ADC group injected rank to which the offset programmed
		2716	* will be applied
		2717	* - Offset level (offset to be subtracted from the raw
		2718	* converted data).
		2719	* Caution: Offset format is dependent to ADC resolution:
		2720	* offset has to be left-aligned on bit 11, the LSB (right bits)
		2721	* are set to 0.
		2722	* @note Offset cannot be enabled or disabled.
		2723	* To emulate offset disabled, set an offset value equal to 0.
		2724	* @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
		2725	* JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
		2726	* JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
		2727	* JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
		2728	* @param ADCx ADC instance
		2729	* @param Rank This parameter can be one of the following values:
		2730	* @arg @ref LL_ADC_INJ_RANK_1
		2731	* @arg @ref LL_ADC_INJ_RANK_2
		2732	* @arg @ref LL_ADC_INJ_RANK_3
		2733	* @arg @ref LL_ADC_INJ_RANK_4
		2734	* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
		2735	* @retval None
		2736	*/
		2737	__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
		2738	{
		2739	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
		2740
		2741	MODIFY_REG(*preg,
		2742	ADC_JOFR1_JOFFSET1,
		2743	OffsetLevel);
		2744	}
		2745
		2746	/**
		2747	* @brief Get ADC group injected offset.
		2748	* @note It gives offset level (offset to be subtracted from the raw converted data).
		2749	* Caution: Offset format is dependent to ADC resolution:
		2750	* offset has to be left-aligned on bit 11, the LSB (right bits)
		2751	* are set to 0.
		2752	* @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
		2753	* JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
		2754	* JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
		2755	* JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
		2756	* @param ADCx ADC instance
		2757	* @param Rank This parameter can be one of the following values:
		2758	* @arg @ref LL_ADC_INJ_RANK_1
		2759	* @arg @ref LL_ADC_INJ_RANK_2
		2760	* @arg @ref LL_ADC_INJ_RANK_3
		2761	* @arg @ref LL_ADC_INJ_RANK_4
		2762	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		2763	*/
		2764	__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
		2765	{
		2766	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
		2767
		2768	return (uint32_t)(READ_BIT(*preg,
		2769	ADC_JOFR1_JOFFSET1)
		2770	);
		2771	}
		2772
		2773	/**
		2774	* @}
		2775	*/
		2776
		2777	/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
		2778	* @{
		2779	*/
		2780
		2781	/**
		2782	* @brief Set sampling time of the selected ADC channel
		2783	* Unit: ADC clock cycles.
		2784	* @note On this device, sampling time is on channel scope: independently
		2785	* of channel mapped on ADC group regular or injected.
		2786	* @note In case of internal channel (VrefInt, TempSensor, ...) to be
		2787	* converted:
		2788	* sampling time constraints must be respected (sampling time can be
		2789	* adjusted in function of ADC clock frequency and sampling time
		2790	* setting).
		2791	* Refer to device datasheet for timings values (parameters TS_vrefint,
		2792	* TS_temp, ...).
		2793	* @note Conversion time is the addition of sampling time and processing time.
		2794	* Refer to reference manual for ADC processing time of
		2795	* this STM32 serie.
		2796	* @note In case of ADC conversion of internal channel (VrefInt,
		2797	* temperature sensor, ...), a sampling time minimum value
		2798	* is required.
		2799	* Refer to device datasheet.
		2800	* @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
		2801	* SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
		2802	* SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
		2803	* SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
		2804	* SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
		2805	* SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
		2806	* SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
		2807	* SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
		2808	* SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
		2809	* SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
		2810	* SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
		2811	* SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
		2812	* SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
		2813	* SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
		2814	* SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
		2815	* SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
		2816	* SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
		2817	* SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
		2818	* @param ADCx ADC instance
		2819	* @param Channel This parameter can be one of the following values:
		2820	* @arg @ref LL_ADC_CHANNEL_0
		2821	* @arg @ref LL_ADC_CHANNEL_1
		2822	* @arg @ref LL_ADC_CHANNEL_2
		2823	* @arg @ref LL_ADC_CHANNEL_3
		2824	* @arg @ref LL_ADC_CHANNEL_4
		2825	* @arg @ref LL_ADC_CHANNEL_5
		2826	* @arg @ref LL_ADC_CHANNEL_6
		2827	* @arg @ref LL_ADC_CHANNEL_7
		2828	* @arg @ref LL_ADC_CHANNEL_8
		2829	* @arg @ref LL_ADC_CHANNEL_9
		2830	* @arg @ref LL_ADC_CHANNEL_10
		2831	* @arg @ref LL_ADC_CHANNEL_11
		2832	* @arg @ref LL_ADC_CHANNEL_12
		2833	* @arg @ref LL_ADC_CHANNEL_13
		2834	* @arg @ref LL_ADC_CHANNEL_14
		2835	* @arg @ref LL_ADC_CHANNEL_15
		2836	* @arg @ref LL_ADC_CHANNEL_16
		2837	* @arg @ref LL_ADC_CHANNEL_17
		2838	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		2839	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		2840	*
		2841	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		2842	* @param SamplingTime This parameter can be one of the following values:
		2843	* @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
		2844	* @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
		2845	* @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
		2846	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
		2847	* @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
		2848	* @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
		2849	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
		2850	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
		2851	* @retval None
		2852	*/
		2853	__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
		2854	{
		2855	/* Set bits with content of parameter "SamplingTime" with bits position */
		2856	/* in register and register position depending on parameter "Channel". */
		2857	/* Parameter "Channel" is used with masks because containing */
		2858	/* other bits reserved for other purpose. */
		2859	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
		2860
		2861	MODIFY_REG(*preg,
		2862	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
		2863	SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
		2864	}
		2865
		2866	/**
		2867	* @brief Get sampling time of the selected ADC channel
		2868	* Unit: ADC clock cycles.
		2869	* @note On this device, sampling time is on channel scope: independently
		2870	* of channel mapped on ADC group regular or injected.
		2871	* @note Conversion time is the addition of sampling time and processing time.
		2872	* Refer to reference manual for ADC processing time of
		2873	* this STM32 serie.
		2874	* @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
		2875	* SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
		2876	* SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
		2877	* SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
		2878	* SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
		2879	* SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
		2880	* SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
		2881	* SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
		2882	* SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
		2883	* SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
		2884	* SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
		2885	* SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
		2886	* SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
		2887	* SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
		2888	* SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
		2889	* SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
		2890	* SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
		2891	* SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
		2892	* @param ADCx ADC instance
		2893	* @param Channel This parameter can be one of the following values:
		2894	* @arg @ref LL_ADC_CHANNEL_0
		2895	* @arg @ref LL_ADC_CHANNEL_1
		2896	* @arg @ref LL_ADC_CHANNEL_2
		2897	* @arg @ref LL_ADC_CHANNEL_3
		2898	* @arg @ref LL_ADC_CHANNEL_4
		2899	* @arg @ref LL_ADC_CHANNEL_5
		2900	* @arg @ref LL_ADC_CHANNEL_6
		2901	* @arg @ref LL_ADC_CHANNEL_7
		2902	* @arg @ref LL_ADC_CHANNEL_8
		2903	* @arg @ref LL_ADC_CHANNEL_9
		2904	* @arg @ref LL_ADC_CHANNEL_10
		2905	* @arg @ref LL_ADC_CHANNEL_11
		2906	* @arg @ref LL_ADC_CHANNEL_12
		2907	* @arg @ref LL_ADC_CHANNEL_13
		2908	* @arg @ref LL_ADC_CHANNEL_14
		2909	* @arg @ref LL_ADC_CHANNEL_15
		2910	* @arg @ref LL_ADC_CHANNEL_16
		2911	* @arg @ref LL_ADC_CHANNEL_17
		2912	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
		2913	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
		2914	*
		2915	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		2916	* @retval Returned value can be one of the following values:
		2917	* @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
		2918	* @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
		2919	* @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
		2920	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
		2921	* @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
		2922	* @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
		2923	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
		2924	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
		2925	*/
		2926	__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
		2927	{
		2928	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
		2929
		2930	return (uint32_t)(READ_BIT(*preg,
		2931	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
		2932	>> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
		2933	);
		2934	}
		2935
		2936	/**
		2937	* @}
		2938	*/
		2939
		2940	/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
		2941	* @{
		2942	*/
		2943
		2944	/**
		2945	* @brief Set ADC analog watchdog monitored channels:
		2946	* a single channel or all channels,
		2947	* on ADC groups regular and-or injected.
		2948	* @note Once monitored channels are selected, analog watchdog
		2949	* is enabled.
		2950	* @note In case of need to define a single channel to monitor
		2951	* with analog watchdog from sequencer channel definition,
		2952	* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
		2953	* @note On this STM32 serie, there is only 1 kind of analog watchdog
		2954	* instance:
		2955	* - AWD standard (instance AWD1):
		2956	* - channels monitored: can monitor 1 channel or all channels.
		2957	* - groups monitored: ADC groups regular and-or injected.
		2958	* - resolution: resolution is not limited (corresponds to
		2959	* ADC resolution configured).
		2960	* @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
		2961	* CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
		2962	* CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
		2963	* @param ADCx ADC instance
		2964	* @param AWDChannelGroup This parameter can be one of the following values:
		2965	* @arg @ref LL_ADC_AWD_DISABLE
		2966	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
		2967	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
		2968	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
		2969	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
		2970	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
		2971	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
		2972	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
		2973	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
		2974	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
		2975	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
		2976	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
		2977	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
		2978	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
		2979	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
		2980	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
		2981	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
		2982	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
		2983	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
		2984	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
		2985	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
		2986	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
		2987	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
		2988	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
		2989	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
		2990	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
		2991	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
		2992	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
		2993	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
		2994	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
		2995	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
		2996	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
		2997	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
		2998	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
		2999	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
		3000	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
		3001	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
		3002	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
		3003	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
		3004	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
		3005	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
		3006	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
		3007	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
		3008	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
		3009	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
		3010	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
		3011	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
		3012	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
		3013	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
		3014	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
		3015	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
		3016	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
		3017	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
		3018	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
		3019	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
		3020	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
		3021	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
		3022	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
		3023	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
		3024	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
		3025	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
		3026	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
		3027	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
		3028	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
		3029	*
		3030	* (1) On STM32F1, parameter available only on ADC instance: ADC1.
		3031	* @retval None
		3032	*/
		3033	__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
		3034	{
		3035	MODIFY_REG(ADCx->CR1,
		3036	(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL \| ADC_CR1_AWDCH),
		3037	AWDChannelGroup);
		3038	}
		3039
		3040	/**
		3041	* @brief Get ADC analog watchdog monitored channel.
		3042	* @note Usage of the returned channel number:
		3043	* - To reinject this channel into another function LL_ADC_xxx:
		3044	* the returned channel number is only partly formatted on definition
		3045	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
		3046	* with parts of literals LL_ADC_CHANNEL_x or using
		3047	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
		3048	* Then the selected literal LL_ADC_CHANNEL_x can be used
		3049	* as parameter for another function.
		3050	* - To get the channel number in decimal format:
		3051	* process the returned value with the helper macro
		3052	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
		3053	* Applicable only when the analog watchdog is set to monitor
		3054	* one channel.
		3055	* @note On this STM32 serie, there is only 1 kind of analog watchdog
		3056	* instance:
		3057	* - AWD standard (instance AWD1):
		3058	* - channels monitored: can monitor 1 channel or all channels.
		3059	* - groups monitored: ADC groups regular and-or injected.
		3060	* - resolution: resolution is not limited (corresponds to
		3061	* ADC resolution configured).
		3062	* @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
		3063	* CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
		3064	* CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
		3065	* @param ADCx ADC instance
		3066	* @retval Returned value can be one of the following values:
		3067	* @arg @ref LL_ADC_AWD_DISABLE
		3068	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
		3069	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
		3070	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
		3071	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
		3072	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
		3073	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
		3074	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
		3075	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
		3076	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
		3077	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
		3078	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
		3079	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
		3080	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
		3081	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
		3082	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
		3083	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
		3084	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
		3085	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
		3086	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
		3087	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
		3088	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
		3089	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
		3090	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
		3091	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
		3092	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
		3093	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
		3094	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
		3095	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
		3096	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
		3097	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
		3098	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
		3099	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
		3100	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
		3101	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
		3102	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
		3103	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
		3104	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
		3105	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
		3106	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
		3107	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
		3108	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
		3109	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
		3110	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
		3111	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
		3112	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
		3113	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
		3114	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
		3115	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
		3116	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
		3117	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
		3118	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
		3119	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
		3120	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
		3121	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
		3122	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
		3123	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
		3124	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
		3125	*/
		3126	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
		3127	{
		3128	return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL \| ADC_CR1_AWDCH)));
		3129	}
		3130
		3131	/**
		3132	* @brief Set ADC analog watchdog threshold value of threshold
		3133	* high or low.
		3134	* @note On this STM32 serie, there is only 1 kind of analog watchdog
		3135	* instance:
		3136	* - AWD standard (instance AWD1):
		3137	* - channels monitored: can monitor 1 channel or all channels.
		3138	* - groups monitored: ADC groups regular and-or injected.
		3139	* - resolution: resolution is not limited (corresponds to
		3140	* ADC resolution configured).
		3141	* @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
		3142	* LTR LT LL_ADC_SetAnalogWDThresholds
		3143	* @param ADCx ADC instance
		3144	* @param AWDThresholdsHighLow This parameter can be one of the following values:
		3145	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
		3146	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
		3147	* @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
		3148	* @retval None
		3149	*/
		3150	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
		3151	{
		3152	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
		3153
		3154	MODIFY_REG(*preg,
		3155	ADC_HTR_HT,
		3156	AWDThresholdValue);
		3157	}
		3158
		3159	/**
		3160	* @brief Get ADC analog watchdog threshold value of threshold high or
		3161	* threshold low.
		3162	* @note In case of ADC resolution different of 12 bits,
		3163	* analog watchdog thresholds data require a specific shift.
		3164	* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
		3165	* @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
		3166	* LTR LT LL_ADC_GetAnalogWDThresholds
		3167	* @param ADCx ADC instance
		3168	* @param AWDThresholdsHighLow This parameter can be one of the following values:
		3169	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
		3170	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
		3171	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		3172	*/
		3173	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
		3174	{
		3175	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
		3176
		3177	return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
		3178	}
		3179
		3180	/**
		3181	* @}
		3182	*/
		3183
		3184	/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
		3185	* @{
		3186	*/
		3187
		3188	#if defined(ADC_MULTIMODE_SUPPORT)
		3189	/**
		3190	* @brief Set ADC multimode configuration to operate in independent mode
		3191	* or multimode (for devices with several ADC instances).
		3192	* @note If multimode configuration: the selected ADC instance is
		3193	* either master or slave depending on hardware.
		3194	* Refer to reference manual.
		3195	* @rmtoll CR1 DUALMOD LL_ADC_SetMultimode
		3196	* @param ADCxy_COMMON ADC common instance
		3197	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		3198	* @param Multimode This parameter can be one of the following values:
		3199	* @arg @ref LL_ADC_MULTI_INDEPENDENT
		3200	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
		3201	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
		3202	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
		3203	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
		3204	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
		3205	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
		3206	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
		3207	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
		3208	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
		3209	* @retval None
		3210	*/
		3211	__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
		3212	{
		3213	MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode);
		3214	}
		3215
		3216	/**
		3217	* @brief Get ADC multimode configuration to operate in independent mode
		3218	* or multimode (for devices with several ADC instances).
		3219	* @note If multimode configuration: the selected ADC instance is
		3220	* either master or slave depending on hardware.
		3221	* Refer to reference manual.
		3222	* @rmtoll CR1 DUALMOD LL_ADC_GetMultimode
		3223	* @param ADCxy_COMMON ADC common instance
		3224	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		3225	* @retval Returned value can be one of the following values:
		3226	* @arg @ref LL_ADC_MULTI_INDEPENDENT
		3227	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
		3228	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
		3229	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
		3230	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
		3231	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
		3232	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
		3233	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
		3234	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
		3235	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
		3236	*/
		3237	__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
		3238	{
		3239	return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD));
		3240	}
		3241
		3242	#endif /* ADC_MULTIMODE_SUPPORT */
		3243
		3244	/**
		3245	* @}
		3246	*/
		3247	/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
		3248	* @{
		3249	*/
		3250
		3251	/**
		3252	* @brief Enable the selected ADC instance.
		3253	* @note On this STM32 serie, after ADC enable, a delay for
		3254	* ADC internal analog stabilization is required before performing a
		3255	* ADC conversion start.
		3256	* Refer to device datasheet, parameter tSTAB.
		3257	* @rmtoll CR2 ADON LL_ADC_Enable
		3258	* @param ADCx ADC instance
		3259	* @retval None
		3260	*/
		3261	__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
		3262	{
		3263	SET_BIT(ADCx->CR2, ADC_CR2_ADON);
		3264	}
		3265
		3266	/**
		3267	* @brief Disable the selected ADC instance.
		3268	* @rmtoll CR2 ADON LL_ADC_Disable
		3269	* @param ADCx ADC instance
		3270	* @retval None
		3271	*/
		3272	__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
		3273	{
		3274	CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
		3275	}
		3276
		3277	/**
		3278	* @brief Get the selected ADC instance enable state.
		3279	* @rmtoll CR2 ADON LL_ADC_IsEnabled
		3280	* @param ADCx ADC instance
		3281	* @retval 0: ADC is disabled, 1: ADC is enabled.
		3282	*/
		3283	__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
		3284	{
		3285	return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
		3286	}
		3287
		3288	/**
		3289	* @brief Start ADC calibration in the mode single-ended
		3290	* or differential (for devices with differential mode available).
		3291	* @note On this STM32 serie, before starting a calibration,
		3292	* ADC must be disabled.
		3293	* A minimum number of ADC clock cycles are required
		3294	* between ADC disable state and calibration start.
		3295	* Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
		3296	* @note On this STM32 serie, hardware prerequisite before starting a calibration:
		3297	the ADC must have been in power-on state for at least
		3298	two ADC clock cycles.
		3299	* @rmtoll CR2 CAL LL_ADC_StartCalibration
		3300	* @param ADCx ADC instance
		3301	* @retval None
		3302	*/
		3303	__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
		3304	{
		3305	SET_BIT(ADCx->CR2, ADC_CR2_CAL);
		3306	}
		3307
		3308	/**
		3309	* @brief Get ADC calibration state.
		3310	* @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing
		3311	* @param ADCx ADC instance
		3312	* @retval 0: calibration complete, 1: calibration in progress.
		3313	*/
		3314	__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
		3315	{
		3316	return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
		3317	}
		3318
		3319	/**
		3320	* @}
		3321	*/
		3322
		3323	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
		3324	* @{
		3325	*/
		3326
		3327	/**
		3328	* @brief Start ADC group regular conversion.
		3329	* @note On this STM32 serie, this function is relevant only for
		3330	* internal trigger (SW start), not for external trigger:
		3331	* - If ADC trigger has been set to software start, ADC conversion
		3332	* starts immediately.
		3333	* - If ADC trigger has been set to external trigger, ADC conversion
		3334	* start must be performed using function
		3335	* @ref LL_ADC_REG_StartConversionExtTrig().
		3336	* (if external trigger edge would have been set during ADC other
		3337	* settings, ADC conversion would start at trigger event
		3338	* as soon as ADC is enabled).
		3339	* @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
		3340	* @param ADCx ADC instance
		3341	* @retval None
		3342	*/
		3343	__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
		3344	{
		3345	SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
		3346	}
		3347
		3348	/**
		3349	* @brief Start ADC group regular conversion from external trigger.
		3350	* @note ADC conversion will start at next trigger event (on the selected
		3351	* trigger edge) following the ADC start conversion command.
		3352	* @note On this STM32 serie, this function is relevant for
		3353	* ADC conversion start from external trigger.
		3354	* If internal trigger (SW start) is needed, perform ADC conversion
		3355	* start using function @ref LL_ADC_REG_StartConversionSWStart().
		3356	* @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
		3357	* @param ExternalTriggerEdge This parameter can be one of the following values:
		3358	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
		3359	* @param ADCx ADC instance
		3360	* @retval None
		3361	*/
		3362	__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
		3363	{
		3364	SET_BIT(ADCx->CR2, ExternalTriggerEdge);
		3365	}
		3366
		3367	/**
		3368	* @brief Stop ADC group regular conversion from external trigger.
		3369	* @note No more ADC conversion will start at next trigger event
		3370	* following the ADC stop conversion command.
		3371	* If a conversion is on-going, it will be completed.
		3372	* @note On this STM32 serie, there is no specific command
		3373	* to stop a conversion on-going or to stop ADC converting
		3374	* in continuous mode. These actions can be performed
		3375	* using function @ref LL_ADC_Disable().
		3376	* @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
		3377	* @param ADCx ADC instance
		3378	* @retval None
		3379	*/
		3380	__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
		3381	{
		3382	CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTSEL);
		3383	}
		3384
		3385	/**
		3386	* @brief Get ADC group regular conversion data, range fit for
		3387	* all ADC configurations: all ADC resolutions and
		3388	* all oversampling increased data width (for devices
		3389	* with feature oversampling).
		3390	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
		3391	* @param ADCx ADC instance
		3392	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
		3393	*/
		3394	__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
		3395	{
		3396	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
		3397	}
		3398
		3399	/**
		3400	* @brief Get ADC group regular conversion data, range fit for
		3401	* ADC resolution 12 bits.
		3402	* @note For devices with feature oversampling: Oversampling
		3403	* can increase data width, function for extended range
		3404	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
		3405	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
		3406	* @param ADCx ADC instance
		3407	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		3408	*/
		3409	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
		3410	{
		3411	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
		3412	}
		3413
		3414	#if defined(ADC_MULTIMODE_SUPPORT)
		3415	/**
		3416	* @brief Get ADC multimode conversion data of ADC master, ADC slave
		3417	* or raw data with ADC master and slave concatenated.
		3418	* @note If raw data with ADC master and slave concatenated is retrieved,
		3419	* a macro is available to get the conversion data of
		3420	* ADC master or ADC slave: see helper macro
		3421	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
		3422	* (however this macro is mainly intended for multimode
		3423	* transfer by DMA, because this function can do the same
		3424	* by getting multimode conversion data of ADC master or ADC slave
		3425	* separately).
		3426	* @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n
		3427	* DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32
		3428	* @param ADCx ADC instance
		3429	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		3430	* @param ConversionData This parameter can be one of the following values:
		3431	* @arg @ref LL_ADC_MULTI_MASTER
		3432	* @arg @ref LL_ADC_MULTI_SLAVE
		3433	* @arg @ref LL_ADC_MULTI_MASTER_SLAVE
		3434	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
		3435	*/
		3436	__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData)
		3437	{
		3438	return (uint32_t)(READ_BIT(ADCx->DR,
		3439	ADC_DR_ADC2DATA)
		3440	>> POSITION_VAL(ConversionData)
		3441	);
		3442	}
		3443	#endif /* ADC_MULTIMODE_SUPPORT */
		3444
		3445	/**
		3446	* @}
		3447	*/
		3448
		3449	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
		3450	* @{
		3451	*/
		3452
		3453	/**
		3454	* @brief Start ADC group injected conversion.
		3455	* @note On this STM32 serie, this function is relevant only for
		3456	* internal trigger (SW start), not for external trigger:
		3457	* - If ADC trigger has been set to software start, ADC conversion
		3458	* starts immediately.
		3459	* - If ADC trigger has been set to external trigger, ADC conversion
		3460	* start must be performed using function
		3461	* @ref LL_ADC_INJ_StartConversionExtTrig().
		3462	* (if external trigger edge would have been set during ADC other
		3463	* settings, ADC conversion would start at trigger event
		3464	* as soon as ADC is enabled).
		3465	* @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
		3466	* @param ADCx ADC instance
		3467	* @retval None
		3468	*/
		3469	__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
		3470	{
		3471	SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART \| ADC_CR2_JEXTTRIG));
		3472	}
		3473
		3474	/**
		3475	* @brief Start ADC group injected conversion from external trigger.
		3476	* @note ADC conversion will start at next trigger event (on the selected
		3477	* trigger edge) following the ADC start conversion command.
		3478	* @note On this STM32 serie, this function is relevant for
		3479	* ADC conversion start from external trigger.
		3480	* If internal trigger (SW start) is needed, perform ADC conversion
		3481	* start using function @ref LL_ADC_INJ_StartConversionSWStart().
		3482	* @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
		3483	* @param ExternalTriggerEdge This parameter can be one of the following values:
		3484	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
		3485	* @param ADCx ADC instance
		3486	* @retval None
		3487	*/
		3488	__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
		3489	{
		3490	SET_BIT(ADCx->CR2, ExternalTriggerEdge);
		3491	}
		3492
		3493	/**
		3494	* @brief Stop ADC group injected conversion from external trigger.
		3495	* @note No more ADC conversion will start at next trigger event
		3496	* following the ADC stop conversion command.
		3497	* If a conversion is on-going, it will be completed.
		3498	* @note On this STM32 serie, there is no specific command
		3499	* to stop a conversion on-going or to stop ADC converting
		3500	* in continuous mode. These actions can be performed
		3501	* using function @ref LL_ADC_Disable().
		3502	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
		3503	* @param ADCx ADC instance
		3504	* @retval None
		3505	*/
		3506	__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
		3507	{
		3508	CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTSEL);
		3509	}
		3510
		3511	/**
		3512	* @brief Get ADC group regular conversion data, range fit for
		3513	* all ADC configurations: all ADC resolutions and
		3514	* all oversampling increased data width (for devices
		3515	* with feature oversampling).
		3516	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
		3517	* JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
		3518	* JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
		3519	* JDR4 JDATA LL_ADC_INJ_ReadConversionData32
		3520	* @param ADCx ADC instance
		3521	* @param Rank This parameter can be one of the following values:
		3522	* @arg @ref LL_ADC_INJ_RANK_1
		3523	* @arg @ref LL_ADC_INJ_RANK_2
		3524	* @arg @ref LL_ADC_INJ_RANK_3
		3525	* @arg @ref LL_ADC_INJ_RANK_4
		3526	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
		3527	*/
		3528	__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
		3529	{
		3530	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
		3531
		3532	return (uint32_t)(READ_BIT(*preg,
		3533	ADC_JDR1_JDATA)
		3534	);
		3535	}
		3536
		3537	/**
		3538	* @brief Get ADC group injected conversion data, range fit for
		3539	* ADC resolution 12 bits.
		3540	* @note For devices with feature oversampling: Oversampling
		3541	* can increase data width, function for extended range
		3542	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
		3543	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
		3544	* JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
		3545	* JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
		3546	* JDR4 JDATA LL_ADC_INJ_ReadConversionData12
		3547	* @param ADCx ADC instance
		3548	* @param Rank This parameter can be one of the following values:
		3549	* @arg @ref LL_ADC_INJ_RANK_1
		3550	* @arg @ref LL_ADC_INJ_RANK_2
		3551	* @arg @ref LL_ADC_INJ_RANK_3
		3552	* @arg @ref LL_ADC_INJ_RANK_4
		3553	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		3554	*/
		3555	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
		3556	{
		3557	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
		3558
		3559	return (uint16_t)(READ_BIT(*preg,
		3560	ADC_JDR1_JDATA)
		3561	);
		3562	}
		3563
		3564	/**
		3565	* @}
		3566	*/
		3567
		3568	/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
		3569	* @{
		3570	*/
		3571
		3572	/**
		3573	* @brief Get flag ADC group regular end of sequence conversions.
		3574	* @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS
		3575	* @param ADCx ADC instance
		3576	* @retval State of bit (1 or 0).
		3577	*/
		3578	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
		3579	{
		3580	/* Note: on this STM32 serie, there is no flag ADC group regular */
		3581	/* end of unitary conversion. */
		3582	/* Flag noted as "EOC" is corresponding to flag "EOS" */
		3583	/* in other STM32 families). */
		3584	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
		3585	}
		3586
		3587
		3588	/**
		3589	* @brief Get flag ADC group injected end of sequence conversions.
		3590	* @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
		3591	* @param ADCx ADC instance
		3592	* @retval State of bit (1 or 0).
		3593	*/
		3594	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
		3595	{
		3596	/* Note: on this STM32 serie, there is no flag ADC group injected */
		3597	/* end of unitary conversion. */
		3598	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
		3599	/* in other STM32 families). */
		3600	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
		3601	}
		3602
		3603	/**
		3604	* @brief Get flag ADC analog watchdog 1 flag
		3605	* @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
		3606	* @param ADCx ADC instance
		3607	* @retval State of bit (1 or 0).
		3608	*/
		3609	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
		3610	{
		3611	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
		3612	}
		3613
		3614	/**
		3615	* @brief Clear flag ADC group regular end of sequence conversions.
		3616	* @rmtoll SR EOC LL_ADC_ClearFlag_EOS
		3617	* @param ADCx ADC instance
		3618	* @retval None
		3619	*/
		3620	__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
		3621	{
		3622	/* Note: on this STM32 serie, there is no flag ADC group regular */
		3623	/* end of unitary conversion. */
		3624	/* Flag noted as "EOC" is corresponding to flag "EOS" */
		3625	/* in other STM32 families). */
		3626	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
		3627	}
		3628
		3629
		3630	/**
		3631	* @brief Clear flag ADC group injected end of sequence conversions.
		3632	* @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
		3633	* @param ADCx ADC instance
		3634	* @retval None
		3635	*/
		3636	__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
		3637	{
		3638	/* Note: on this STM32 serie, there is no flag ADC group injected */
		3639	/* end of unitary conversion. */
		3640	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
		3641	/* in other STM32 families). */
		3642	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
		3643	}
		3644
		3645	/**
		3646	* @brief Clear flag ADC analog watchdog 1.
		3647	* @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
		3648	* @param ADCx ADC instance
		3649	* @retval None
		3650	*/
		3651	__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
		3652	{
		3653	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
		3654	}
		3655
		3656	#if defined(ADC_MULTIMODE_SUPPORT)
		3657	/**
		3658	* @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
		3659	* @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS
		3660	* @param ADCxy_COMMON ADC common instance
		3661	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		3662	* @retval State of bit (1 or 0).
		3663	*/
		3664	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
		3665	{
		3666	/* Note: on this STM32 serie, there is no flag ADC group regular */
		3667	/* end of unitary conversion. */
		3668	/* Flag noted as "EOC" is corresponding to flag "EOS" */
		3669	/* in other STM32 families). */
		3670	return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC));
		3671	}
		3672
		3673	/**
		3674	* @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
		3675	* @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS
		3676	* @param ADCxy_COMMON ADC common instance
		3677	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		3678	* @retval State of bit (1 or 0).
		3679	*/
		3680	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
		3681	{
		3682	/* Note: on this STM32 serie, there is no flag ADC group regular */
		3683	/* end of unitary conversion. */
		3684	/* Flag noted as "EOC" is corresponding to flag "EOS" */
		3685	/* in other STM32 families). */
		3686
		3687	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
		3688
		3689	return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
		3690	}
		3691
		3692
		3693	/**
		3694	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
		3695	* @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS
		3696	* @param ADCxy_COMMON ADC common instance
		3697	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		3698	* @retval State of bit (1 or 0).
		3699	*/
		3700	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
		3701	{
		3702	/* Note: on this STM32 serie, there is no flag ADC group injected */
		3703	/* end of unitary conversion. */
		3704	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
		3705	/* in other STM32 families). */
		3706	return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC));
		3707	}
		3708
		3709	/**
		3710	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
		3711	* @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS
		3712	* @param ADCxy_COMMON ADC common instance
		3713	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		3714	* @retval State of bit (1 or 0).
		3715	*/
		3716	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
		3717	{
		3718	/* Note: on this STM32 serie, there is no flag ADC group injected */
		3719	/* end of unitary conversion. */
		3720	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
		3721	/* in other STM32 families). */
		3722
		3723	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
		3724
		3725	return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
		3726	}
		3727
		3728	/**
		3729	* @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
		3730	* @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1
		3731	* @param ADCxy_COMMON ADC common instance
		3732	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		3733	* @retval State of bit (1 or 0).
		3734	*/
		3735	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
		3736	{
		3737	return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
		3738	}
		3739
		3740	/**
		3741	* @brief Get flag multimode analog watchdog 1 of the ADC slave.
		3742	* @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1
		3743	* @param ADCxy_COMMON ADC common instance
		3744	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		3745	* @retval State of bit (1 or 0).
		3746	*/
		3747	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
		3748	{
		3749	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
		3750
		3751	return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
		3752	}
		3753
		3754	#endif /* ADC_MULTIMODE_SUPPORT */
		3755
		3756	/**
		3757	* @}
		3758	*/
		3759
		3760	/** @defgroup ADC_LL_EF_IT_Management ADC IT management
		3761	* @{
		3762	*/
		3763
		3764	/**
		3765	* @brief Enable interruption ADC group regular end of sequence conversions.
		3766	* @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS
		3767	* @param ADCx ADC instance
		3768	* @retval None
		3769	*/
		3770	__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
		3771	{
		3772	/* Note: on this STM32 serie, there is no flag ADC group regular */
		3773	/* end of unitary conversion. */
		3774	/* Flag noted as "EOC" is corresponding to flag "EOS" */
		3775	/* in other STM32 families). */
		3776	SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
		3777	}
		3778
		3779
		3780	/**
		3781	* @brief Enable interruption ADC group injected end of sequence conversions.
		3782	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
		3783	* @param ADCx ADC instance
		3784	* @retval None
		3785	*/
		3786	__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
		3787	{
		3788	/* Note: on this STM32 serie, there is no flag ADC group injected */
		3789	/* end of unitary conversion. */
		3790	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
		3791	/* in other STM32 families). */
		3792	SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
		3793	}
		3794
		3795	/**
		3796	* @brief Enable interruption ADC analog watchdog 1.
		3797	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
		3798	* @param ADCx ADC instance
		3799	* @retval None
		3800	*/
		3801	__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
		3802	{
		3803	SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
		3804	}
		3805
		3806	/**
		3807	* @brief Disable interruption ADC group regular end of sequence conversions.
		3808	* @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS
		3809	* @param ADCx ADC instance
		3810	* @retval None
		3811	*/
		3812	__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
		3813	{
		3814	/* Note: on this STM32 serie, there is no flag ADC group regular */
		3815	/* end of unitary conversion. */
		3816	/* Flag noted as "EOC" is corresponding to flag "EOS" */
		3817	/* in other STM32 families). */
		3818	CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
		3819	}
		3820
		3821
		3822	/**
		3823	* @brief Disable interruption ADC group injected end of sequence conversions.
		3824	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
		3825	* @param ADCx ADC instance
		3826	* @retval None
		3827	*/
		3828	__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
		3829	{
		3830	/* Note: on this STM32 serie, there is no flag ADC group injected */
		3831	/* end of unitary conversion. */
		3832	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
		3833	/* in other STM32 families). */
		3834	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
		3835	}
		3836
		3837	/**
		3838	* @brief Disable interruption ADC analog watchdog 1.
		3839	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
		3840	* @param ADCx ADC instance
		3841	* @retval None
		3842	*/
		3843	__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
		3844	{
		3845	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
		3846	}
		3847
		3848	/**
		3849	* @brief Get state of interruption ADC group regular end of sequence conversions
		3850	* (0: interrupt disabled, 1: interrupt enabled).
		3851	* @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS
		3852	* @param ADCx ADC instance
		3853	* @retval State of bit (1 or 0).
		3854	*/
		3855	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
		3856	{
		3857	/* Note: on this STM32 serie, there is no flag ADC group regular */
		3858	/* end of unitary conversion. */
		3859	/* Flag noted as "EOC" is corresponding to flag "EOS" */
		3860	/* in other STM32 families). */
		3861	return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
		3862	}
		3863
		3864
		3865	/**
		3866	* @brief Get state of interruption ADC group injected end of sequence conversions
		3867	* (0: interrupt disabled, 1: interrupt enabled).
		3868	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
		3869	* @param ADCx ADC instance
		3870	* @retval State of bit (1 or 0).
		3871	*/
		3872	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
		3873	{
		3874	/* Note: on this STM32 serie, there is no flag ADC group injected */
		3875	/* end of unitary conversion. */
		3876	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
		3877	/* in other STM32 families). */
		3878	return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
		3879	}
		3880
		3881	/**
		3882	* @brief Get state of interruption ADC analog watchdog 1
		3883	* (0: interrupt disabled, 1: interrupt enabled).
		3884	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
		3885	* @param ADCx ADC instance
		3886	* @retval State of bit (1 or 0).
		3887	*/
		3888	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
		3889	{
		3890	return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
		3891	}
		3892
		3893	/**
		3894	* @}
		3895	*/
		3896
		3897	#if defined(USE_FULL_LL_DRIVER)
		3898	/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
		3899	* @{
		3900	*/
		3901
		3902	/* Initialization of some features of ADC common parameters and multimode */
		3903	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
		3904	ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef ADCxy_COMMON, LL_ADC_CommonInitTypeDef ADC_CommonInitStruct);
		3905	void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
		3906
		3907	/* De-initialization of ADC instance, ADC group regular and ADC group injected */
		3908	/* (availability of ADC group injected depends on STM32 families) */
		3909	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
		3910
		3911	/* Initialization of some features of ADC instance */
		3912	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct);
		3913	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
		3914
		3915	/* Initialization of some features of ADC instance and ADC group regular */
		3916	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct);
		3917	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
		3918
		3919	/* Initialization of some features of ADC instance and ADC group injected */
		3920	ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef ADCx, LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct);
		3921	void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
		3922
		3923	/**
		3924	* @}
		3925	*/
		3926	#endif /* USE_FULL_LL_DRIVER */
		3927
		3928	/**
		3929	* @}
		3930	*/
		3931
		3932	/**
		3933	* @}
		3934	*/
		3935
		3936	#endif /* ADC1 \|\| ADC2 \|\| ADC3 */
		3937
		3938	/**
		3939	* @}
		3940	*/
		3941
		3942	#ifdef __cplusplus
		3943	}
		3944	#endif
		3945
		3946	#endif /* __STM32F1xx_LL_ADC_H */
		3947
		3948	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h – Rev 2