WebSVN – LedShow – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM HAL module.
		6	******************************************************************************
		7	* @attention
		8	*
9	mjames	9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
2	mjames	11	*
9	mjames	12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
2	mjames	16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
9	mjames	21	#ifndef STM32F1xx_HAL_TIM_H
		22	#define STM32F1xx_HAL_TIM_H
2	mjames	23
		24	#ifdef __cplusplus
9	mjames	25	extern "C" {
2	mjames	26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f1xx_hal_def.h"
		30
		31	/** @addtogroup STM32F1xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup TIM
		36	* @{
		37	*/
		38
		39	/* Exported types ------------------------------------------------------------*/
		40	/** @defgroup TIM_Exported_Types TIM Exported Types
		41	* @{
		42	*/
9	mjames	43
2	mjames	44	/**
		45	* @brief TIM Time base Configuration Structure definition
		46	*/
		47	typedef struct
		48	{
		49	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		50	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		51
		52	uint32_t CounterMode; /*!< Specifies the counter mode.
		53	This parameter can be a value of @ref TIM_Counter_Mode */
		54
		55	uint32_t Period; /*!< Specifies the period value to be loaded into the active
		56	Auto-Reload Register at the next update event.
		57	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
		58
		59	uint32_t ClockDivision; /*!< Specifies the clock division.
		60	This parameter can be a value of @ref TIM_ClockDivision */
		61
		62	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
		63	reaches zero, an update event is generated and counting restarts
		64	from the RCR value (N).
		65	This means in PWM mode that (N+1) corresponds to:
		66	- the number of PWM periods in edge-aligned mode
		67	- the number of half PWM period in center-aligned mode
9	mjames	68	GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
		69	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
		70
2	mjames	71	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
9	mjames	72	This parameter can be a value of @ref TIM_AutoReloadPreload */
2	mjames	73	} TIM_Base_InitTypeDef;
		74
		75	/**
		76	* @brief TIM Output Compare Configuration Structure definition
		77	*/
		78	typedef struct
		79	{
		80	uint32_t OCMode; /*!< Specifies the TIM mode.
		81	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		82
		83	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		84	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		85
		86	uint32_t OCPolarity; /*!< Specifies the output polarity.
		87	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		88
		89	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		90	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
9	mjames	91	@note This parameter is valid only for timer instances supporting break feature. */
2	mjames	92
9	mjames	93	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
2	mjames	94	This parameter can be a value of @ref TIM_Output_Fast_State
		95	@note This parameter is valid only in PWM1 and PWM2 mode. */
		96
		97
		98	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		99	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
9	mjames	100	@note This parameter is valid only for timer instances supporting break feature. */
2	mjames	101
		102	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		103	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
9	mjames	104	@note This parameter is valid only for timer instances supporting break feature. */
2	mjames	105	} TIM_OC_InitTypeDef;
		106
		107	/**
		108	* @brief TIM One Pulse Mode Configuration Structure definition
		109	*/
		110	typedef struct
		111	{
		112	uint32_t OCMode; /*!< Specifies the TIM mode.
		113	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		114
		115	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		116	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		117
		118	uint32_t OCPolarity; /*!< Specifies the output polarity.
		119	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		120
		121	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		122	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
9	mjames	123	@note This parameter is valid only for timer instances supporting break feature. */
2	mjames	124
		125	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		126	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
9	mjames	127	@note This parameter is valid only for timer instances supporting break feature. */
2	mjames	128
		129	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		130	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
9	mjames	131	@note This parameter is valid only for timer instances supporting break feature. */
2	mjames	132
		133	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		134	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		135
		136	uint32_t ICSelection; /*!< Specifies the input.
		137	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		138
		139	uint32_t ICFilter; /*!< Specifies the input capture filter.
		140	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		141	} TIM_OnePulse_InitTypeDef;
		142
		143	/**
		144	* @brief TIM Input Capture Configuration Structure definition
		145	*/
		146	typedef struct
		147	{
9	mjames	148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
2	mjames	150
		151	uint32_t ICSelection; /*!< Specifies the input.
		152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		153
		154	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		155	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		156
		157	uint32_t ICFilter; /*!< Specifies the input capture filter.
		158	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		159	} TIM_IC_InitTypeDef;
		160
		161	/**
		162	* @brief TIM Encoder Configuration Structure definition
		163	*/
		164	typedef struct
		165	{
		166	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
		167	This parameter can be a value of @ref TIM_Encoder_Mode */
		168
		169	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
9	mjames	170	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
2	mjames	171
		172	uint32_t IC1Selection; /*!< Specifies the input.
		173	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		174
		175	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
		176	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		177
		178	uint32_t IC1Filter; /*!< Specifies the input capture filter.
		179	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		180
		181	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
9	mjames	182	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
2	mjames	183
		184	uint32_t IC2Selection; /*!< Specifies the input.
		185	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		186
		187	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
		188	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		189
		190	uint32_t IC2Filter; /*!< Specifies the input capture filter.
		191	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		192	} TIM_Encoder_InitTypeDef;
		193
		194	/**
9	mjames	195	* @brief Clock Configuration Handle Structure definition
2	mjames	196	*/
		197	typedef struct
		198	{
		199	uint32_t ClockSource; /*!< TIM clock sources
		200	This parameter can be a value of @ref TIM_Clock_Source */
		201	uint32_t ClockPolarity; /*!< TIM clock polarity
		202	This parameter can be a value of @ref TIM_Clock_Polarity */
		203	uint32_t ClockPrescaler; /*!< TIM clock prescaler
		204	This parameter can be a value of @ref TIM_Clock_Prescaler */
9	mjames	205	uint32_t ClockFilter; /*!< TIM clock filter
		206	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		207	} TIM_ClockConfigTypeDef;
2	mjames	208
		209	/**
		210	* @brief TIM Clear Input Configuration Handle Structure definition
		211	*/
		212	typedef struct
		213	{
		214	uint32_t ClearInputState; /*!< TIM clear Input state
		215	This parameter can be ENABLE or DISABLE */
		216	uint32_t ClearInputSource; /*!< TIM clear Input sources
		217	This parameter can be a value of @ref TIM_ClearInput_Source */
		218	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
		219	This parameter can be a value of @ref TIM_ClearInput_Polarity */
		220	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
9	mjames	221	This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
		222	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
		223	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		224	} TIM_ClearInputConfigTypeDef;
2	mjames	225
		226	/**
9	mjames	227	* @brief TIM Master configuration Structure definition
		228	*/
		229	typedef struct
		230	{
		231	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
		232	This parameter can be a value of @ref TIM_Master_Mode_Selection */
		233	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
		234	This parameter can be a value of @ref TIM_Master_Slave_Mode
		235	@note When the Master/slave mode is enabled, the effect of
		236	an event on the trigger input (TRGI) is delayed to allow a
		237	perfect synchronization between the current timer and its
		238	slaves (through TRGO). It is not mandatory in case of timer
		239	synchronization mode. */
		240	} TIM_MasterConfigTypeDef;
		241
		242	/**
2	mjames	243	* @brief TIM Slave configuration Structure definition
		244	*/
9	mjames	245	typedef struct
		246	{
		247	uint32_t SlaveMode; /*!< Slave mode selection
		248	This parameter can be a value of @ref TIM_Slave_Mode */
2	mjames	249	uint32_t InputTrigger; /*!< Input Trigger source
9	mjames	250	This parameter can be a value of @ref TIM_Trigger_Selection */
2	mjames	251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
9	mjames	252	This parameter can be a value of @ref TIM_Trigger_Polarity */
2	mjames	253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
9	mjames	254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
2	mjames	255	uint32_t TriggerFilter; /*!< Input trigger filter
9	mjames	256	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
2	mjames	257
9	mjames	258	} TIM_SlaveConfigTypeDef;
2	mjames	259
		260	/**
9	mjames	261	* @brief TIM Break input(s) and Dead time configuration Structure definition
		262	* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
		263	* filter and polarity.
		264	*/
		265	typedef struct
		266	{
		267	uint32_t OffStateRunMode; /*!< TIM off state in run mode
		268	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
		269	uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
		270	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
		271	uint32_t LockLevel; /*!< TIM Lock level
		272	This parameter can be a value of @ref TIM_Lock_level */
		273	uint32_t DeadTime; /*!< TIM dead Time
		274	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
		275	uint32_t BreakState; /*!< TIM Break State
		276	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
		277	uint32_t BreakPolarity; /*!< TIM Break input polarity
		278	This parameter can be a value of @ref TIM_Break_Polarity */
		279	uint32_t BreakFilter; /*!< Specifies the break input filter.
		280	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		281	uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
		282	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
		283	} TIM_BreakDeadTimeConfigTypeDef;
		284
		285	/**
2	mjames	286	* @brief HAL State structures definition
		287	*/
		288	typedef enum
		289	{
		290	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
		291	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
		292	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
		293	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
		294	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
9	mjames	295	} HAL_TIM_StateTypeDef;
2	mjames	296
		297	/**
9	mjames	298	* @brief TIM Channel States definition
		299	*/
		300	typedef enum
		301	{
		302	HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /!< TIM Channel initial state /
		303	HAL_TIM_CHANNEL_STATE_READY = 0x01U, /!< TIM Channel ready for use /
		304	HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /!< An internal process is ongoing on the TIM channel /
		305	} HAL_TIM_ChannelStateTypeDef;
		306
		307	/**
		308	* @brief DMA Burst States definition
		309	*/
		310	typedef enum
		311	{
		312	HAL_DMA_BURST_STATE_RESET = 0x00U, /!< DMA Burst initial state /
		313	HAL_DMA_BURST_STATE_READY = 0x01U, /!< DMA Burst ready for use /
		314	HAL_DMA_BURST_STATE_BUSY = 0x02U, /!< Ongoing DMA Burst /
		315	} HAL_TIM_DMABurstStateTypeDef;
		316
		317	/**
2	mjames	318	* @brief HAL Active channel structures definition
		319	*/
		320	typedef enum
		321	{
		322	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
		323	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
		324	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
		325	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
		326	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
9	mjames	327	} HAL_TIM_ActiveChannel;
2	mjames	328
		329	/**
		330	* @brief TIM Time Base Handle Structure definition
		331	*/
9	mjames	332	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		333	typedef struct __TIM_HandleTypeDef
		334	#else
2	mjames	335	typedef struct
9	mjames	336	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2	mjames	337	{
9	mjames	338	TIM_TypeDef Instance; /!< Register base address */
		339	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
		340	HAL_TIM_ActiveChannel Channel; /!< Active channel /
		341	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
		342	This array is accessed by a @ref DMA_Handle_index */
		343	HAL_LockTypeDef Lock; /!< Locking object /
		344	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
		345	__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /!< TIM channel operation state /
		346	__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /!< TIM complementary channel operation state /
		347	__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /!< DMA burst operation state /
2	mjames	348
9	mjames	349	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		350	void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp Init Callback */
		351	void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp DeInit Callback */
		352	void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp Init Callback */
		353	void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp DeInit Callback */
		354	void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp Init Callback */
		355	void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp DeInit Callback */
		356	void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp Init Callback */
		357	void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp DeInit Callback */
		358	void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp Init Callback */
		359	void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp DeInit Callback */
		360	void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp Init Callback */
		361	void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp DeInit Callback */
		362	void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp Init Callback */
		363	void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp DeInit Callback */
		364	void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed Callback */
		365	void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed half complete Callback */
		366	void (* TriggerCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger Callback */
		367	void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger half complete Callback */
		368	void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture Callback */
		369	void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture half complete Callback */
		370	void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Output Compare Delay Elapsed Callback */
		371	void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished Callback */
		372	void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished half complete Callback */
		373	void (* ErrorCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Error Callback */
		374	void (* CommutationCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation Callback */
		375	void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation half complete Callback */
		376	void (* BreakCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Break Callback */
		377	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		378	} TIM_HandleTypeDef;
		379
		380	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2	mjames	381	/**
9	mjames	382	* @brief HAL TIM Callback ID enumeration definition
		383	*/
		384	typedef enum
		385	{
		386	HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /!< TIM Base MspInit Callback ID /
		387	, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /!< TIM Base MspDeInit Callback ID /
		388	, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /!< TIM IC MspInit Callback ID /
		389	, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /!< TIM IC MspDeInit Callback ID /
		390	, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /!< TIM OC MspInit Callback ID /
		391	, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /!< TIM OC MspDeInit Callback ID /
		392	, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /!< TIM PWM MspInit Callback ID /
		393	, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /!< TIM PWM MspDeInit Callback ID /
		394	, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /!< TIM One Pulse MspInit Callback ID /
		395	, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /!< TIM One Pulse MspDeInit Callback ID /
		396	, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /!< TIM Encoder MspInit Callback ID /
		397	, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /!< TIM Encoder MspDeInit Callback ID /
		398	, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /!< TIM Hall Sensor MspDeInit Callback ID /
		399	, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /!< TIM Hall Sensor MspDeInit Callback ID /
		400	, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /!< TIM Period Elapsed Callback ID /
		401	, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /!< TIM Period Elapsed half complete Callback ID /
		402	, HAL_TIM_TRIGGER_CB_ID = 0x10U /!< TIM Trigger Callback ID /
		403	, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /!< TIM Trigger half complete Callback ID /
		404
		405	, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /!< TIM Input Capture Callback ID /
		406	, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /!< TIM Input Capture half complete Callback ID /
		407	, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /!< TIM Output Compare Delay Elapsed Callback ID /
		408	, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /!< TIM PWM Pulse Finished Callback ID /
		409	, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /!< TIM PWM Pulse Finished half complete Callback ID /
		410	, HAL_TIM_ERROR_CB_ID = 0x17U /!< TIM Error Callback ID /
		411	, HAL_TIM_COMMUTATION_CB_ID = 0x18U /!< TIM Commutation Callback ID /
		412	, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /!< TIM Commutation half complete Callback ID /
		413	, HAL_TIM_BREAK_CB_ID = 0x1AU /!< TIM Break Callback ID /
		414	} HAL_TIM_CallbackIDTypeDef;
		415
		416	/**
		417	* @brief HAL TIM Callback pointer definition
		418	*/
		419	typedef void (pTIM_CallbackTypeDef)(TIM_HandleTypeDef htim); /!< pointer to the TIM callback function /
		420
		421	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		422
		423	/**
2	mjames	424	* @}
		425	*/
9	mjames	426	/* End of exported types -----------------------------------------------------*/
2	mjames	427
		428	/* Exported constants --------------------------------------------------------*/
		429	/** @defgroup TIM_Exported_Constants TIM Exported Constants
		430	* @{
		431	*/
		432
9	mjames	433	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
2	mjames	434	* @{
		435	*/
9	mjames	436	#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /!< OCREF_CLR is disabled /
		437	#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /!< OCREF_CLR is connected to ETRF input /
		438	/**
		439	* @}
		440	*/
		441
		442	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
		443	* @{
		444	*/
		445	#define TIM_DMABASE_CR1 0x00000000U
		446	#define TIM_DMABASE_CR2 0x00000001U
		447	#define TIM_DMABASE_SMCR 0x00000002U
		448	#define TIM_DMABASE_DIER 0x00000003U
		449	#define TIM_DMABASE_SR 0x00000004U
		450	#define TIM_DMABASE_EGR 0x00000005U
		451	#define TIM_DMABASE_CCMR1 0x00000006U
		452	#define TIM_DMABASE_CCMR2 0x00000007U
		453	#define TIM_DMABASE_CCER 0x00000008U
		454	#define TIM_DMABASE_CNT 0x00000009U
		455	#define TIM_DMABASE_PSC 0x0000000AU
		456	#define TIM_DMABASE_ARR 0x0000000BU
		457	#define TIM_DMABASE_RCR 0x0000000CU
		458	#define TIM_DMABASE_CCR1 0x0000000DU
		459	#define TIM_DMABASE_CCR2 0x0000000EU
		460	#define TIM_DMABASE_CCR3 0x0000000FU
		461	#define TIM_DMABASE_CCR4 0x00000010U
		462	#define TIM_DMABASE_BDTR 0x00000011U
		463	#define TIM_DMABASE_DCR 0x00000012U
		464	#define TIM_DMABASE_DMAR 0x00000013U
		465	/**
		466	* @}
		467	*/
		468
		469	/** @defgroup TIM_Event_Source TIM Event Source
		470	* @{
		471	*/
		472	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
		473	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
		474	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
		475	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
		476	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
		477	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /!< A commutation event is generated /
		478	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
		479	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /!< A break event is generated /
		480	/**
		481	* @}
		482	*/
		483
		484	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
		485	* @{
		486	*/
2	mjames	487	#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /!< Polarity for TIx source /
9	mjames	488	#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /!< Polarity for TIx source /
2	mjames	489	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
		490	/**
		491	* @}
		492	*/
		493
		494	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
		495	* @{
		496	*/
9	mjames	497	#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /!< Polarity for ETR source /
2	mjames	498	#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /!< Polarity for ETR source /
		499	/**
		500	* @}
		501	*/
		502
		503	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
		504	* @{
		505	*/
		506	#define TIM_ETRPRESCALER_DIV1 0x00000000U /!< No prescaler is used /
9	mjames	507	#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR input source is divided by 2 /
		508	#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR input source is divided by 4 /
		509	#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR input source is divided by 8 /
2	mjames	510	/**
		511	* @}
		512	*/
		513
		514	/** @defgroup TIM_Counter_Mode TIM Counter Mode
		515	* @{
		516	*/
9	mjames	517	#define TIM_COUNTERMODE_UP 0x00000000U /!< Counter used as up-counter /
		518	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as down-counter /
		519	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /!< Center-aligned mode 1 /
		520	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /!< Center-aligned mode 2 /
		521	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /!< Center-aligned mode 3 /
2	mjames	522	/**
		523	* @}
		524	*/
		525
9	mjames	526	/** @defgroup TIM_ClockDivision TIM Clock Division
2	mjames	527	* @{
		528	*/
9	mjames	529	#define TIM_CLOCKDIVISION_DIV1 0x00000000U /!< Clock division: tDTS=tCK_INT /
		530	#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< Clock division: tDTS=2tCK_INT */
		531	#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< Clock division: tDTS=4tCK_INT */
2	mjames	532	/**
		533	* @}
		534	*/
		535
9	mjames	536	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
2	mjames	537	* @{
		538	*/
9	mjames	539	#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /!< Capture/Compare 1 output disabled /
		540	#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /!< Capture/Compare 1 output enabled /
2	mjames	541	/**
		542	* @}
		543	*/
		544
9	mjames	545	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
2	mjames	546	* @{
		547	*/
9	mjames	548	#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /!< TIMx_ARR register is not buffered /
		549	#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /!< TIMx_ARR register is buffered /
2	mjames	550
		551	/**
		552	* @}
		553	*/
		554
		555	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
		556	* @{
		557	*/
9	mjames	558	#define TIM_OCFAST_DISABLE 0x00000000U /!< Output Compare fast disable /
		559	#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /!< Output Compare fast enable /
2	mjames	560	/**
		561	* @}
		562	*/
		563
		564	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
		565	* @{
		566	*/
9	mjames	567	#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /!< OCxN is disabled /
		568	#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /!< OCxN is enabled /
2	mjames	569	/**
		570	* @}
		571	*/
		572
		573	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
		574	* @{
		575	*/
9	mjames	576	#define TIM_OCPOLARITY_HIGH 0x00000000U /!< Capture/Compare output polarity /
		577	#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< Capture/Compare output polarity /
2	mjames	578	/**
		579	* @}
		580	*/
		581
		582	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
		583	* @{
		584	*/
9	mjames	585	#define TIM_OCNPOLARITY_HIGH 0x00000000U /!< Capture/Compare complementary output polarity /
		586	#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /!< Capture/Compare complementary output polarity /
2	mjames	587	/**
		588	* @}
		589	*/
		590
		591	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
		592	* @{
		593	*/
9	mjames	594	#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /!< Output Idle state: OCx=1 when MOE=0 /
		595	#define TIM_OCIDLESTATE_RESET 0x00000000U /!< Output Idle state: OCx=0 when MOE=0 /
2	mjames	596	/**
		597	* @}
		598	*/
		599
		600	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
		601	* @{
		602	*/
9	mjames	603	#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /!< Complementary output Idle state: OCxN=1 when MOE=0 /
		604	#define TIM_OCNIDLESTATE_RESET 0x00000000U /!< Complementary output Idle state: OCxN=0 when MOE=0 /
2	mjames	605	/**
		606	* @}
		607	*/
		608
9	mjames	609	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
2	mjames	610	* @{
		611	*/
9	mjames	612	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Capture triggered by rising edge on timer input /
		613	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Capture triggered by falling edge on timer input /
		614	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Capture triggered by both rising and falling edges on timer input/
2	mjames	615	/**
		616	* @}
		617	*/
		618
9	mjames	619	/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
2	mjames	620	* @{
		621	*/
9	mjames	622	#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Encoder input with rising edge polarity /
		623	#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Encoder input with falling edge polarity /
2	mjames	624	/**
		625	* @}
		626	*/
		627
		628	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
		629	* @{
		630	*/
9	mjames	631	#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
		632	connected to IC1, IC2, IC3 or IC4, respectively */
		633	#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
		634	connected to IC2, IC1, IC4 or IC3, respectively */
		635	#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
2	mjames	636	/**
		637	* @}
		638	*/
		639
		640	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
		641	* @{
		642	*/
9	mjames	643	#define TIM_ICPSC_DIV1 0x00000000U /!< Capture performed each time an edge is detected on the capture input /
		644	#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /!< Capture performed once every 2 events /
		645	#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /!< Capture performed once every 4 events /
		646	#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /!< Capture performed once every 8 events /
2	mjames	647	/**
		648	* @}
		649	*/
		650
		651	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
		652	* @{
		653	*/
9	mjames	654	#define TIM_OPMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
		655	#define TIM_OPMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
2	mjames	656	/**
		657	* @}
		658	*/
		659
		660	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
		661	* @{
		662	*/
9	mjames	663	#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level /
		664	#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. /
		665	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. /
2	mjames	666	/**
		667	* @}
		668	*/
		669
9	mjames	670	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
2	mjames	671	* @{
		672	*/
9	mjames	673	#define TIM_IT_UPDATE TIM_DIER_UIE /!< Update interrupt /
		674	#define TIM_IT_CC1 TIM_DIER_CC1IE /!< Capture/Compare 1 interrupt /
		675	#define TIM_IT_CC2 TIM_DIER_CC2IE /!< Capture/Compare 2 interrupt /
		676	#define TIM_IT_CC3 TIM_DIER_CC3IE /!< Capture/Compare 3 interrupt /
		677	#define TIM_IT_CC4 TIM_DIER_CC4IE /!< Capture/Compare 4 interrupt /
		678	#define TIM_IT_COM TIM_DIER_COMIE /!< Commutation interrupt /
		679	#define TIM_IT_TRIGGER TIM_DIER_TIE /!< Trigger interrupt /
		680	#define TIM_IT_BREAK TIM_DIER_BIE /!< Break interrupt /
2	mjames	681	/**
		682	* @}
		683	*/
		684
		685	/** @defgroup TIM_Commutation_Source TIM Commutation Source
		686	* @{
		687	*/
9	mjames	688	#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input /
		689	#define TIM_COMMUTATION_SOFTWARE 0x00000000U /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit /
2	mjames	690	/**
		691	* @}
		692	*/
		693
		694	/** @defgroup TIM_DMA_sources TIM DMA Sources
		695	* @{
		696	*/
9	mjames	697	#define TIM_DMA_UPDATE TIM_DIER_UDE /!< DMA request is triggered by the update event /
		698	#define TIM_DMA_CC1 TIM_DIER_CC1DE /!< DMA request is triggered by the capture/compare macth 1 event /
		699	#define TIM_DMA_CC2 TIM_DIER_CC2DE /!< DMA request is triggered by the capture/compare macth 2 event event /
		700	#define TIM_DMA_CC3 TIM_DIER_CC3DE /!< DMA request is triggered by the capture/compare macth 3 event event /
		701	#define TIM_DMA_CC4 TIM_DIER_CC4DE /!< DMA request is triggered by the capture/compare macth 4 event event /
		702	#define TIM_DMA_COM TIM_DIER_COMDE /!< DMA request is triggered by the commutation event /
		703	#define TIM_DMA_TRIGGER TIM_DIER_TDE /!< DMA request is triggered by the trigger event /
2	mjames	704	/**
		705	* @}
		706	*/
		707
9	mjames	708	/** @defgroup TIM_Flag_definition TIM Flag Definition
2	mjames	709	* @{
		710	*/
9	mjames	711	#define TIM_FLAG_UPDATE TIM_SR_UIF /!< Update interrupt flag /
		712	#define TIM_FLAG_CC1 TIM_SR_CC1IF /!< Capture/Compare 1 interrupt flag /
		713	#define TIM_FLAG_CC2 TIM_SR_CC2IF /!< Capture/Compare 2 interrupt flag /
		714	#define TIM_FLAG_CC3 TIM_SR_CC3IF /!< Capture/Compare 3 interrupt flag /
		715	#define TIM_FLAG_CC4 TIM_SR_CC4IF /!< Capture/Compare 4 interrupt flag /
		716	#define TIM_FLAG_COM TIM_SR_COMIF /!< Commutation interrupt flag /
		717	#define TIM_FLAG_TRIGGER TIM_SR_TIF /!< Trigger interrupt flag /
		718	#define TIM_FLAG_BREAK TIM_SR_BIF /!< Break interrupt flag /
		719	#define TIM_FLAG_CC1OF TIM_SR_CC1OF /!< Capture 1 overcapture flag /
		720	#define TIM_FLAG_CC2OF TIM_SR_CC2OF /!< Capture 2 overcapture flag /
		721	#define TIM_FLAG_CC3OF TIM_SR_CC3OF /!< Capture 3 overcapture flag /
		722	#define TIM_FLAG_CC4OF TIM_SR_CC4OF /!< Capture 4 overcapture flag /
2	mjames	723	/**
		724	* @}
		725	*/
		726
9	mjames	727	/** @defgroup TIM_Channel TIM Channel
2	mjames	728	* @{
		729	*/
9	mjames	730	#define TIM_CHANNEL_1 0x00000000U /!< Capture/compare channel 1 identifier /
		731	#define TIM_CHANNEL_2 0x00000004U /!< Capture/compare channel 2 identifier /
		732	#define TIM_CHANNEL_3 0x00000008U /!< Capture/compare channel 3 identifier /
		733	#define TIM_CHANNEL_4 0x0000000CU /!< Capture/compare channel 4 identifier /
		734	#define TIM_CHANNEL_ALL 0x0000003CU /!< Global Capture/compare channel identifier /
2	mjames	735	/**
		736	* @}
		737	*/
		738
		739	/** @defgroup TIM_Clock_Source TIM Clock Source
		740	* @{
		741	*/
9	mjames	742	#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /!< External clock source mode 2 /
		743	#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /!< Internal clock source /
		744	#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /!< External clock source mode 1 (ITR0) /
		745	#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /!< External clock source mode 1 (ITR1) /
		746	#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /!< External clock source mode 1 (ITR2) /
		747	#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /!< External clock source mode 1 (ITR3) /
		748	#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /!< External clock source mode 1 (TTI1FP1 + edge detect.) /
		749	#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /!< External clock source mode 1 (TTI1FP1) /
		750	#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /!< External clock source mode 1 (TTI2FP2) /
		751	#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /!< External clock source mode 1 (ETRF) /
2	mjames	752	/**
		753	* @}
		754	*/
		755
		756	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
		757	* @{
		758	*/
		759	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
		760	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
		761	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
		762	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
		763	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
		764	/**
		765	* @}
		766	*/
		767
		768	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
		769	* @{
		770	*/
9	mjames	771	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		772	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
		773	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
		774	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
2	mjames	775	/**
		776	* @}
		777	*/
		778
9	mjames	779	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
2	mjames	780	* @{
		781	*/
9	mjames	782	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
		783	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
2	mjames	784	/**
		785	* @}
		786	*/
		787
9	mjames	788	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
2	mjames	789	* @{
		790	*/
9	mjames	791	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		792	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
		793	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
		794	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
2	mjames	795	/**
		796	* @}
		797	*/
		798
9	mjames	799	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
2	mjames	800	* @{
		801	*/
9	mjames	802	#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
		803	#define TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
2	mjames	804	/**
		805	* @}
		806	*/
		807
9	mjames	808	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
2	mjames	809	* @{
		810	*/
9	mjames	811	#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
		812	#define TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
2	mjames	813	/**
		814	* @}
		815	*/
9	mjames	816	/** @defgroup TIM_Lock_level TIM Lock level
2	mjames	817	* @{
		818	*/
9	mjames	819	#define TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF /
		820	#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
		821	#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
		822	#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
2	mjames	823	/**
		824	* @}
		825	*/
		826
9	mjames	827	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
2	mjames	828	* @{
		829	*/
9	mjames	830	#define TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break input BRK is enabled /
		831	#define TIM_BREAK_DISABLE 0x00000000U /!< Break input BRK is disabled /
2	mjames	832	/**
		833	* @}
		834	*/
		835
9	mjames	836	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
2	mjames	837	* @{
		838	*/
9	mjames	839	#define TIM_BREAKPOLARITY_LOW 0x00000000U /!< Break input BRK is active low /
		840	#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
2	mjames	841	/**
		842	* @}
		843	*/
		844
9	mjames	845	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
2	mjames	846	* @{
		847	*/
9	mjames	848	#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
		849	#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
		850	(if none of the break inputs BRK and BRK2 is active) */
2	mjames	851	/**
		852	* @}
		853	*/
9	mjames	854
		855	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
2	mjames	856	* @{
		857	*/
9	mjames	858	#define TIM_TRGO_RESET 0x00000000U /!< TIMx_EGR.UG bit is used as trigger output (TRGO) /
		859	#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< TIMx_CR1.CEN bit is used as trigger output (TRGO) /
		860	#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output (TRGO) /
		861	#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< Capture or a compare match 1 is used as trigger output (TRGO) /
		862	#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output (TRGO) /
		863	#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output(TRGO) /
		864	#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output(TRGO) /
		865	#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output(TRGO) /
2	mjames	866	/**
		867	* @}
		868	*/
		869
9	mjames	870	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
2	mjames	871	* @{
		872	*/
9	mjames	873	#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /!< No action /
		874	#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /!< Master/slave mode is selected /
2	mjames	875	/**
		876	* @}
		877	*/
		878
9	mjames	879	/** @defgroup TIM_Slave_Mode TIM Slave mode
2	mjames	880	* @{
		881	*/
9	mjames	882	#define TIM_SLAVEMODE_DISABLE 0x00000000U /!< Slave mode disabled /
		883	#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode /
		884	#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode /
		885	#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode /
		886	#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< External Clock Mode 1 /
2	mjames	887	/**
		888	* @}
		889	*/
		890
9	mjames	891	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
2	mjames	892	* @{
		893	*/
9	mjames	894	#define TIM_OCMODE_TIMING 0x00000000U /!< Frozen /
		895	#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!< Set channel to active level on match /
		896	#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!< Set channel to inactive level on match /
		897	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< Toggle /
		898	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!< PWM mode 1 /
		899	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< PWM mode 2 /
		900	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!< Force active level /
		901	#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!< Force inactive level /
2	mjames	902	/**
		903	* @}
		904	*/
		905
		906	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
		907	* @{
		908	*/
9	mjames	909	#define TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) /
		910	#define TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) /
		911	#define TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) /
		912	#define TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) /
		913	#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) /
		914	#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 1 (TI1FP1) /
		915	#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 2 (TI2FP2) /
		916	#define TIM_TS_ETRF (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered External Trigger input (ETRF) /
		917	#define TIM_TS_NONE 0x0000FFFFU /!< No trigger selected /
2	mjames	918	/**
		919	* @}
		920	*/
		921
		922	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
		923	* @{
		924	*/
9	mjames	925	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
		926	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
2	mjames	927	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		928	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		929	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
		930	/**
		931	* @}
		932	*/
		933
		934	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
		935	* @{
		936	*/
9	mjames	937	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		938	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
		939	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
		940	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
2	mjames	941	/**
		942	* @}
		943	*/
		944
		945	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
		946	* @{
		947	*/
9	mjames	948	#define TIM_TI1SELECTION_CH1 0x00000000U /!< The TIMx_CH1 pin is connected to TI1 input /
		949	#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) /
2	mjames	950	/**
		951	* @}
		952	*/
		953
		954	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
		955	* @{
		956	*/
9	mjames	957	#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA /
		958	#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		959	#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		960	#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		961	#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		962	#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		963	#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		964	#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		965	#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		966	#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		967	#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		968	#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		969	#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		970	#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		971	#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		972	#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		973	#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		974	#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
2	mjames	975	/**
		976	* @}
		977	*/
		978
9	mjames	979	/** @defgroup DMA_Handle_index TIM DMA Handle Index
2	mjames	980	* @{
		981	*/
9	mjames	982	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /!< Index of the DMA handle used for Update DMA requests /
		983	#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
		984	#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
		985	#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
		986	#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
		987	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /!< Index of the DMA handle used for Commutation DMA requests /
		988	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /!< Index of the DMA handle used for Trigger DMA requests /
2	mjames	989	/**
		990	* @}
		991	*/
		992
9	mjames	993	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
2	mjames	994	* @{
		995	*/
9	mjames	996	#define TIM_CCx_ENABLE 0x00000001U /!< Input or output channel is enabled /
		997	#define TIM_CCx_DISABLE 0x00000000U /!< Input or output channel is disabled /
		998	#define TIM_CCxN_ENABLE 0x00000004U /!< Complementary output channel is enabled /
		999	#define TIM_CCxN_DISABLE 0x00000000U /!< Complementary output channel is enabled /
2	mjames	1000	/**
		1001	* @}
		1002	*/
		1003
		1004	/**
		1005	* @}
		1006	*/
9	mjames	1007	/* End of exported constants -------------------------------------------------*/
2	mjames	1008
		1009	/* Exported macros -----------------------------------------------------------*/
		1010	/** @defgroup TIM_Exported_Macros TIM Exported Macros
		1011	* @{
		1012	*/
		1013
9	mjames	1014	/** @brief Reset TIM handle state.
		1015	* @param __HANDLE__ TIM handle.
2	mjames	1016	* @retval None
		1017	*/
9	mjames	1018	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1019	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
		1020	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
		1021	(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		1022	(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		1023	(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		1024	(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		1025	(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		1026	(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		1027	(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		1028	(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		1029	(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
		1030	(__HANDLE__)->Base_MspInitCallback = NULL; \
		1031	(__HANDLE__)->Base_MspDeInitCallback = NULL; \
		1032	(__HANDLE__)->IC_MspInitCallback = NULL; \
		1033	(__HANDLE__)->IC_MspDeInitCallback = NULL; \
		1034	(__HANDLE__)->OC_MspInitCallback = NULL; \
		1035	(__HANDLE__)->OC_MspDeInitCallback = NULL; \
		1036	(__HANDLE__)->PWM_MspInitCallback = NULL; \
		1037	(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
		1038	(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
		1039	(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
		1040	(__HANDLE__)->Encoder_MspInitCallback = NULL; \
		1041	(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
		1042	(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
		1043	(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
		1044	} while(0)
		1045	#else
		1046	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
		1047	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
		1048	(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		1049	(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		1050	(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		1051	(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		1052	(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		1053	(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		1054	(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		1055	(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		1056	(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
		1057	} while(0)
		1058	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2	mjames	1059
		1060	/**
		1061	* @brief Enable the TIM peripheral.
9	mjames	1062	* @param __HANDLE__ TIM handle
2	mjames	1063	* @retval None
9	mjames	1064	*/
2	mjames	1065	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
		1066
		1067	/**
		1068	* @brief Enable the TIM main Output.
9	mjames	1069	* @param __HANDLE__ TIM handle
2	mjames	1070	* @retval None
		1071	*/
		1072	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
		1073
		1074	/**
		1075	* @brief Disable the TIM peripheral.
9	mjames	1076	* @param __HANDLE__ TIM handle
2	mjames	1077	* @retval None
		1078	*/
		1079	#define __HAL_TIM_DISABLE(__HANDLE__) \
9	mjames	1080	do { \
		1081	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
		1082	{ \
		1083	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
		1084	{ \
		1085	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
		1086	} \
		1087	} \
		1088	} while(0)
		1089
2	mjames	1090	/**
		1091	* @brief Disable the TIM main Output.
9	mjames	1092	* @param __HANDLE__ TIM handle
2	mjames	1093	* @retval None
		1094	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
		1095	*/
		1096	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
9	mjames	1097	do { \
		1098	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
		1099	{ \
		1100	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
		1101	{ \
		1102	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
		1103	} \
		1104	} \
		1105	} while(0)
2	mjames	1106
		1107	/**
		1108	* @brief Disable the TIM main Output.
9	mjames	1109	* @param __HANDLE__ TIM handle
2	mjames	1110	* @retval None
		1111	* @note The Main Output Enable of a timer instance is disabled unconditionally
		1112	*/
		1113	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
		1114
9	mjames	1115	/** @brief Enable the specified TIM interrupt.
		1116	* @param __HANDLE__ specifies the TIM Handle.
		1117	* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
2	mjames	1118	* This parameter can be one of the following values:
		1119	* @arg TIM_IT_UPDATE: Update interrupt
9	mjames	1120	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
2	mjames	1121	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1122	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1123	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
9	mjames	1124	* @arg TIM_IT_COM: Commutation interrupt
2	mjames	1125	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1126	* @arg TIM_IT_BREAK: Break interrupt
		1127	* @retval None
		1128	*/
		1129	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
		1130
9	mjames	1131	/** @brief Disable the specified TIM interrupt.
		1132	* @param __HANDLE__ specifies the TIM Handle.
		1133	* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
2	mjames	1134	* This parameter can be one of the following values:
		1135	* @arg TIM_IT_UPDATE: Update interrupt
9	mjames	1136	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
2	mjames	1137	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1138	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1139	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
9	mjames	1140	* @arg TIM_IT_COM: Commutation interrupt
2	mjames	1141	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1142	* @arg TIM_IT_BREAK: Break interrupt
		1143	* @retval None
		1144	*/
		1145	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
		1146
9	mjames	1147	/** @brief Enable the specified DMA request.
		1148	* @param __HANDLE__ specifies the TIM Handle.
		1149	* @param __DMA__ specifies the TIM DMA request to enable.
2	mjames	1150	* This parameter can be one of the following values:
		1151	* @arg TIM_DMA_UPDATE: Update DMA request
9	mjames	1152	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
2	mjames	1153	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		1154	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		1155	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
9	mjames	1156	* @arg TIM_DMA_COM: Commutation DMA request
2	mjames	1157	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		1158	* @retval None
		1159	*/
		1160	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
		1161
9	mjames	1162	/** @brief Disable the specified DMA request.
		1163	* @param __HANDLE__ specifies the TIM Handle.
		1164	* @param __DMA__ specifies the TIM DMA request to disable.
2	mjames	1165	* This parameter can be one of the following values:
		1166	* @arg TIM_DMA_UPDATE: Update DMA request
9	mjames	1167	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
2	mjames	1168	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		1169	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		1170	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
9	mjames	1171	* @arg TIM_DMA_COM: Commutation DMA request
2	mjames	1172	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		1173	* @retval None
		1174	*/
		1175	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
		1176
9	mjames	1177	/** @brief Check whether the specified TIM interrupt flag is set or not.
		1178	* @param __HANDLE__ specifies the TIM Handle.
		1179	* @param __FLAG__ specifies the TIM interrupt flag to check.
2	mjames	1180	* This parameter can be one of the following values:
		1181	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		1182	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		1183	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		1184	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		1185	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		1186	* @arg TIM_FLAG_COM: Commutation interrupt flag
		1187	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
9	mjames	1188	* @arg TIM_FLAG_BREAK: Break interrupt flag
2	mjames	1189	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		1190	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		1191	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		1192	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		1193	* @retval The new state of __FLAG__ (TRUE or FALSE).
		1194	*/
		1195	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
		1196
9	mjames	1197	/** @brief Clear the specified TIM interrupt flag.
		1198	* @param __HANDLE__ specifies the TIM Handle.
		1199	* @param __FLAG__ specifies the TIM interrupt flag to clear.
2	mjames	1200	* This parameter can be one of the following values:
		1201	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		1202	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		1203	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		1204	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		1205	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		1206	* @arg TIM_FLAG_COM: Commutation interrupt flag
		1207	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
9	mjames	1208	* @arg TIM_FLAG_BREAK: Break interrupt flag
2	mjames	1209	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		1210	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		1211	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		1212	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		1213	* @retval The new state of __FLAG__ (TRUE or FALSE).
		1214	*/
		1215	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
		1216
		1217	/**
9	mjames	1218	* @brief Check whether the specified TIM interrupt source is enabled or not.
		1219	* @param __HANDLE__ TIM handle
		1220	* @param __INTERRUPT__ specifies the TIM interrupt source to check.
		1221	* This parameter can be one of the following values:
		1222	* @arg TIM_IT_UPDATE: Update interrupt
		1223	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1224	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1225	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1226	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1227	* @arg TIM_IT_COM: Commutation interrupt
		1228	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1229	* @arg TIM_IT_BREAK: Break interrupt
2	mjames	1230	* @retval The state of TIM_IT (SET or RESET).
		1231	*/
9	mjames	1232	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
		1233	== (__INTERRUPT__)) ? SET : RESET)
2	mjames	1234
9	mjames	1235	/** @brief Clear the TIM interrupt pending bits.
		1236	* @param __HANDLE__ TIM handle
		1237	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
		1238	* This parameter can be one of the following values:
		1239	* @arg TIM_IT_UPDATE: Update interrupt
		1240	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1241	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1242	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1243	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1244	* @arg TIM_IT_COM: Commutation interrupt
		1245	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1246	* @arg TIM_IT_BREAK: Break interrupt
2	mjames	1247	* @retval None
		1248	*/
9	mjames	1249	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
2	mjames	1250
		1251	/**
9	mjames	1252	* @brief Indicates whether or not the TIM Counter is used as downcounter.
		1253	* @param __HANDLE__ TIM handle.
2	mjames	1254	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
9	mjames	1255	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
2	mjames	1256	mode.
		1257	*/
9	mjames	1258	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
2	mjames	1259
		1260	/**
9	mjames	1261	* @brief Set the TIM Prescaler on runtime.
		1262	* @param __HANDLE__ TIM handle.
		1263	* @param __PRESC__ specifies the Prescaler new value.
2	mjames	1264	* @retval None
		1265	*/
		1266	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
		1267
		1268	/**
9	mjames	1269	* @brief Set the TIM Counter Register value on runtime.
		1270	* @param __HANDLE__ TIM handle.
		1271	* @param __COUNTER__ specifies the Counter register new value.
2	mjames	1272	* @retval None
		1273	*/
		1274	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
		1275
		1276	/**
9	mjames	1277	* @brief Get the TIM Counter Register value on runtime.
		1278	* @param __HANDLE__ TIM handle.
2	mjames	1279	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
		1280	*/
9	mjames	1281	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
2	mjames	1282
		1283	/**
9	mjames	1284	* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
		1285	* @param __HANDLE__ TIM handle.
		1286	* @param __AUTORELOAD__ specifies the Counter register new value.
2	mjames	1287	* @retval None
		1288	*/
		1289	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
9	mjames	1290	do{ \
		1291	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
		1292	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
		1293	} while(0)
2	mjames	1294
		1295	/**
9	mjames	1296	* @brief Get the TIM Autoreload Register value on runtime.
		1297	* @param __HANDLE__ TIM handle.
		1298	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
2	mjames	1299	*/
9	mjames	1300	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
2	mjames	1301
		1302	/**
9	mjames	1303	* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
		1304	* @param __HANDLE__ TIM handle.
		1305	* @param __CKD__ specifies the clock division value.
2	mjames	1306	* This parameter can be one of the following value:
		1307	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1308	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
9	mjames	1309	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
2	mjames	1310	* @retval None
		1311	*/
		1312	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
9	mjames	1313	do{ \
		1314	(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
		1315	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
		1316	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
		1317	} while(0)
2	mjames	1318
		1319	/**
9	mjames	1320	* @brief Get the TIM Clock Division value on runtime.
		1321	* @param __HANDLE__ TIM handle.
2	mjames	1322	* @retval The clock division can be one of the following values:
		1323	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1324	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
9	mjames	1325	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
2	mjames	1326	*/
9	mjames	1327	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
2	mjames	1328
		1329	/**
9	mjames	1330	* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
		1331	* @param __HANDLE__ TIM handle.
		1332	* @param __CHANNEL__ TIM Channels to be configured.
2	mjames	1333	* This parameter can be one of the following values:
		1334	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1335	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1336	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1337	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
9	mjames	1338	* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
2	mjames	1339	* This parameter can be one of the following values:
		1340	* @arg TIM_ICPSC_DIV1: no prescaler
		1341	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1342	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1343	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
		1344	* @retval None
		1345	*/
		1346	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
9	mjames	1347	do{ \
		1348	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
		1349	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
		1350	} while(0)
2	mjames	1351
		1352	/**
9	mjames	1353	* @brief Get the TIM Input Capture prescaler on runtime.
		1354	* @param __HANDLE__ TIM handle.
		1355	* @param __CHANNEL__ TIM Channels to be configured.
2	mjames	1356	* This parameter can be one of the following values:
		1357	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
		1358	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
		1359	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
		1360	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
		1361	* @retval The input capture prescaler can be one of the following values:
		1362	* @arg TIM_ICPSC_DIV1: no prescaler
		1363	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1364	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1365	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
		1366	*/
		1367	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
		1368	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
		1369	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
		1370	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
		1371	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
		1372
		1373	/**
9	mjames	1374	* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
		1375	* @param __HANDLE__ TIM handle.
		1376	* @param __CHANNEL__ TIM Channels to be configured.
		1377	* This parameter can be one of the following values:
		1378	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1379	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1380	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1381	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1382	* @param __COMPARE__ specifies the Capture Compare register new value.
		1383	* @retval None
		1384	*/
		1385	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
		1386	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
		1387	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
		1388	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
		1389	((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
		1390
		1391	/**
		1392	* @brief Get the TIM Capture Compare Register value on runtime.
		1393	* @param __HANDLE__ TIM handle.
		1394	* @param __CHANNEL__ TIM Channel associated with the capture compare register
		1395	* This parameter can be one of the following values:
		1396	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
		1397	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
		1398	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
		1399	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
		1400	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
		1401	*/
		1402	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
		1403	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
		1404	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
		1405	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
		1406	((__HANDLE__)->Instance->CCR4))
		1407
		1408	/**
		1409	* @brief Set the TIM Output compare preload.
		1410	* @param __HANDLE__ TIM handle.
		1411	* @param __CHANNEL__ TIM Channels to be configured.
		1412	* This parameter can be one of the following values:
		1413	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1414	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1415	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1416	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1417	* @retval None
		1418	*/
		1419	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1420	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
		1421	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
		1422	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
		1423	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE))
		1424
		1425	/**
		1426	* @brief Reset the TIM Output compare preload.
		1427	* @param __HANDLE__ TIM handle.
		1428	* @param __CHANNEL__ TIM Channels to be configured.
		1429	* This parameter can be one of the following values:
		1430	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1431	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1432	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1433	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1434	* @retval None
		1435	*/
		1436	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1437	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
		1438	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
		1439	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
		1440	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
		1441
		1442	/**
		1443	* @brief Enable fast mode for a given channel.
		1444	* @param __HANDLE__ TIM handle.
		1445	* @param __CHANNEL__ TIM Channels to be configured.
		1446	* This parameter can be one of the following values:
		1447	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1448	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1449	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1450	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1451	* @note When fast mode is enabled an active edge on the trigger input acts
		1452	* like a compare match on CCx output. Delay to sample the trigger
		1453	* input and to activate CCx output is reduced to 3 clock cycles.
		1454	* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
		1455	* @retval None
		1456	*/
		1457	#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1458	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1FE) :\
		1459	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2FE) :\
		1460	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3FE) :\
		1461	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4FE))
		1462
		1463	/**
		1464	* @brief Disable fast mode for a given channel.
		1465	* @param __HANDLE__ TIM handle.
		1466	* @param __CHANNEL__ TIM Channels to be configured.
		1467	* This parameter can be one of the following values:
		1468	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1469	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1470	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1471	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1472	* @note When fast mode is disabled CCx output behaves normally depending
		1473	* on counter and CCRx values even when the trigger is ON. The minimum
		1474	* delay to activate CCx output when an active edge occurs on the
		1475	* trigger input is 5 clock cycles.
		1476	* @retval None
		1477	*/
		1478	#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1479	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
		1480	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
		1481	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
		1482	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
		1483
		1484	/**
		1485	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
		1486	* @param __HANDLE__ TIM handle.
		1487	* @note When the URS bit of the TIMx_CR1 register is set, only counter
2	mjames	1488	* overflow/underflow generates an update interrupt or DMA request (if
		1489	* enabled)
		1490	* @retval None
		1491	*/
9	mjames	1492	#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|= TIM_CR1_URS)
2	mjames	1493
		1494	/**
9	mjames	1495	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
		1496	* @param __HANDLE__ TIM handle.
		1497	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
2	mjames	1498	* following events generate an update interrupt or DMA request (if
		1499	* enabled):
9	mjames	1500	* _ Counter overflow underflow
		1501	* _ Setting the UG bit
		1502	* _ Update generation through the slave mode controller
2	mjames	1503	* @retval None
		1504	*/
9	mjames	1505	#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
2	mjames	1506
		1507	/**
9	mjames	1508	* @brief Set the TIM Capture x input polarity on runtime.
		1509	* @param __HANDLE__ TIM handle.
		1510	* @param __CHANNEL__ TIM Channels to be configured.
2	mjames	1511	* This parameter can be one of the following values:
		1512	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1513	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1514	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1515	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
9	mjames	1516	* @param __POLARITY__ Polarity for TIx source
2	mjames	1517	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
		1518	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
		1519	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
		1520	* @retval None
		1521	*/
		1522	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
9	mjames	1523	do{ \
		1524	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
		1525	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
		1526	}while(0)
2	mjames	1527
		1528	/**
		1529	* @}
		1530	*/
9	mjames	1531	/* End of exported macros ----------------------------------------------------*/
2	mjames	1532
9	mjames	1533	/* Private constants ---------------------------------------------------------*/
		1534	/** @defgroup TIM_Private_Constants TIM Private Constants
		1535	* @{
		1536	*/
		1537	/* The counter of a timer instance is disabled only if all the CCx and CCxN
		1538	channels have been disabled */
		1539	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
		1540	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
		1541	/**
		1542	* @}
		1543	*/
		1544	/* End of private constants --------------------------------------------------*/
		1545
		1546	/* Private macros ------------------------------------------------------------*/
		1547	/** @defgroup TIM_Private_Macros TIM Private Macros
		1548	* @{
		1549	*/
		1550	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
		1551	((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
		1552
		1553	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
		1554	((__BASE__) == TIM_DMABASE_CR2) \|\| \
		1555	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
		1556	((__BASE__) == TIM_DMABASE_DIER) \|\| \
		1557	((__BASE__) == TIM_DMABASE_SR) \|\| \
		1558	((__BASE__) == TIM_DMABASE_EGR) \|\| \
		1559	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
		1560	((__BASE__) == TIM_DMABASE_CCMR2) \|\| \
		1561	((__BASE__) == TIM_DMABASE_CCER) \|\| \
		1562	((__BASE__) == TIM_DMABASE_CNT) \|\| \
		1563	((__BASE__) == TIM_DMABASE_PSC) \|\| \
		1564	((__BASE__) == TIM_DMABASE_ARR) \|\| \
		1565	((__BASE__) == TIM_DMABASE_RCR) \|\| \
		1566	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
		1567	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
		1568	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
		1569	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
		1570	((__BASE__) == TIM_DMABASE_BDTR))
		1571
		1572	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1573
		1574	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
		1575	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
		1576	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
		1577	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
		1578	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
		1579
		1580	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
		1581	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
		1582	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
		1583
		1584	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
		1585	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
		1586
		1587	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
		1588	((__STATE__) == TIM_OCFAST_ENABLE))
		1589
		1590	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
		1591	((__POLARITY__) == TIM_OCPOLARITY_LOW))
		1592
		1593	#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) \|\| \
		1594	((__POLARITY__) == TIM_OCNPOLARITY_LOW))
		1595
		1596	#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) \|\| \
		1597	((__STATE__) == TIM_OCIDLESTATE_RESET))
		1598
		1599	#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) \|\| \
		1600	((__STATE__) == TIM_OCNIDLESTATE_RESET))
		1601
		1602	#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) \|\| \
		1603	((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
		1604
		1605	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
		1606	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
		1607	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
		1608
		1609	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
		1610	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
		1611	((__SELECTION__) == TIM_ICSELECTION_TRC))
		1612
		1613	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
		1614	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
		1615	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
		1616	((__PRESCALER__) == TIM_ICPSC_DIV8))
		1617
		1618	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
		1619	((__MODE__) == TIM_OPMODE_REPETITIVE))
		1620
		1621	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
		1622	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
		1623	((__MODE__) == TIM_ENCODERMODE_TI12))
		1624
		1625	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1626
		1627	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1628	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
		1629	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
		1630	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
		1631	((__CHANNEL__) == TIM_CHANNEL_ALL))
		1632
		1633	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1634	((__CHANNEL__) == TIM_CHANNEL_2))
		1635
		1636	#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1637	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
		1638	((__CHANNEL__) == TIM_CHANNEL_3))
		1639
		1640	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
		1641	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
		1642	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
		1643	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
		1644	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
		1645	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
		1646	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
		1647	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
		1648	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
		1649	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
		1650
		1651	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
		1652	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
		1653	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
		1654	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
		1655	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
		1656
		1657	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
		1658	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
		1659	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
		1660	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
		1661
		1662	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1663
		1664	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
		1665	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
		1666
		1667	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
		1668	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
		1669	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
		1670	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
		1671
		1672	#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1673
		1674	#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) \|\| \
		1675	((__STATE__) == TIM_OSSR_DISABLE))
		1676
		1677	#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) \|\| \
		1678	((__STATE__) == TIM_OSSI_DISABLE))
		1679
		1680	#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) \|\| \
		1681	((__LEVEL__) == TIM_LOCKLEVEL_1) \|\| \
		1682	((__LEVEL__) == TIM_LOCKLEVEL_2) \|\| \
		1683	((__LEVEL__) == TIM_LOCKLEVEL_3))
		1684
		1685	#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
		1686
		1687
		1688	#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) \|\| \
		1689	((__STATE__) == TIM_BREAK_DISABLE))
		1690
		1691	#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) \|\| \
		1692	((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
		1693
		1694	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
		1695	((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
		1696
		1697	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
		1698	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
		1699	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
		1700	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
		1701	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
		1702	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
		1703	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
		1704	((__SOURCE__) == TIM_TRGO_OC4REF))
		1705
		1706	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
		1707	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
		1708
		1709	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
		1710	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
		1711	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
		1712	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
		1713	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
		1714
		1715	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
		1716	((__MODE__) == TIM_OCMODE_PWM2))
		1717
		1718	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
		1719	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
		1720	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
		1721	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
		1722	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
		1723	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
		1724
		1725	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1726	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1727	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1728	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1729	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
		1730	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
		1731	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
		1732	((__SELECTION__) == TIM_TS_ETRF))
		1733
		1734	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1735	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1736	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1737	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1738	((__SELECTION__) == TIM_TS_NONE))
		1739
		1740	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
		1741	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
		1742	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
		1743	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
		1744	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
		1745
		1746	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
		1747	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
		1748	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
		1749	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
		1750
		1751	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1752
		1753	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
		1754	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
		1755
		1756	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
		1757	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
		1758	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
		1759	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
		1760	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
		1761	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
		1762	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
		1763	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
		1764	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
		1765	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
		1766	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
		1767	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
		1768	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
		1769	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
		1770	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
		1771	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
		1772	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
		1773	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
		1774
		1775	#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
		1776
		1777	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1778
		1779	#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
		1780
		1781	#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
		1782
		1783	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
		1784	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
		1785	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
		1786	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
		1787	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
		1788
		1789	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
		1790	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
		1791	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
		1792	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
		1793	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
		1794
		1795	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
		1796	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
		1797	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
		1798	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
		1799	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U))))
		1800
		1801	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
		1802	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
		1803	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
		1804	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
		1805	((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
		1806
		1807	#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
		1808	(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
		1809	((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
		1810	((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
		1811	(__HANDLE__)->ChannelState[3])
		1812
		1813	#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
		1814	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
		1815	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
		1816	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
		1817	((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
		1818
		1819	#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
		1820	(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
		1821	(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
		1822	(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
		1823	(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
		1824	} while(0)
		1825
		1826	#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
		1827	(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
		1828	((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
		1829	((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
		1830	(__HANDLE__)->ChannelNState[3])
		1831
		1832	#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
		1833	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
		1834	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
		1835	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
		1836	((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
		1837
		1838	#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
		1839	(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
		1840	(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
		1841	(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
		1842	(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
		1843	} while(0)
		1844
		1845	/**
		1846	* @}
		1847	*/
		1848	/* End of private macros -----------------------------------------------------*/
		1849
		1850	/* Include TIM HAL Extended module */
2	mjames	1851	#include "stm32f1xx_hal_tim_ex.h"
		1852
		1853	/* Exported functions --------------------------------------------------------*/
9	mjames	1854	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
2	mjames	1855	* @{
		1856	*/
		1857
9	mjames	1858	/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
		1859	* @brief Time Base functions
		1860	* @{
		1861	*/
2	mjames	1862	/* Time Base functions ********************************************************/
		1863	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
		1864	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
		1865	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
		1866	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
		1867	/* Blocking mode: Polling */
		1868	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
		1869	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
		1870	/* Non-Blocking mode: Interrupt */
		1871	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
		1872	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
		1873	/* Non-Blocking mode: DMA */
		1874	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
		1875	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
		1876	/**
		1877	* @}
		1878	*/
		1879
9	mjames	1880	/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
		1881	* @brief TIM Output Compare functions
		1882	* @{
		1883	*/
		1884	/* Timer Output Compare functions *********************************************/
2	mjames	1885	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
		1886	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
		1887	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
		1888	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
		1889	/* Blocking mode: Polling */
		1890	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1891	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1892	/* Non-Blocking mode: Interrupt */
		1893	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1894	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1895	/* Non-Blocking mode: DMA */
		1896	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1897	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1898	/**
		1899	* @}
		1900	*/
		1901
9	mjames	1902	/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
		1903	* @brief TIM PWM functions
		1904	* @{
		1905	*/
		1906	/* Timer PWM functions ********************************************************/
2	mjames	1907	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
		1908	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
		1909	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
		1910	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
		1911	/* Blocking mode: Polling */
		1912	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1913	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1914	/* Non-Blocking mode: Interrupt */
		1915	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1916	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1917	/* Non-Blocking mode: DMA */
		1918	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1919	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1920	/**
		1921	* @}
		1922	*/
		1923
9	mjames	1924	/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
		1925	* @brief TIM Input Capture functions
		1926	* @{
		1927	*/
		1928	/* Timer Input Capture functions **********************************************/
2	mjames	1929	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
		1930	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
		1931	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
		1932	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
		1933	/* Blocking mode: Polling */
		1934	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1935	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1936	/* Non-Blocking mode: Interrupt */
		1937	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1938	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1939	/* Non-Blocking mode: DMA */
		1940	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1941	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1942	/**
		1943	* @}
		1944	*/
		1945
9	mjames	1946	/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
		1947	* @brief TIM One Pulse functions
		1948	* @{
		1949	*/
		1950	/* Timer One Pulse functions **************************************************/
2	mjames	1951	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
		1952	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
		1953	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
		1954	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
		1955	/* Blocking mode: Polling */
		1956	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1957	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1958	/* Non-Blocking mode: Interrupt */
		1959	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1960	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1961	/**
		1962	* @}
		1963	*/
		1964
9	mjames	1965	/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
		1966	* @brief TIM Encoder functions
		1967	* @{
		1968	*/
		1969	/* Timer Encoder functions ****************************************************/
		1970	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
2	mjames	1971	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
		1972	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
		1973	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
9	mjames	1974	/* Blocking mode: Polling */
2	mjames	1975	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1976	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1977	/* Non-Blocking mode: Interrupt */
		1978	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1979	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1980	/* Non-Blocking mode: DMA */
9	mjames	1981	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1,
		1982	uint32_t *pData2, uint16_t Length);
2	mjames	1983	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1984	/**
		1985	* @}
		1986	*/
		1987
9	mjames	1988	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
		1989	* @brief IRQ handler management
		1990	* @{
		1991	*/
		1992	/* Interrupt Handler functions ***********************************************/
2	mjames	1993	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
		1994	/**
		1995	* @}
		1996	*/
		1997
9	mjames	1998	/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
		1999	* @brief Peripheral Control functions
		2000	* @{
		2001	*/
2	mjames	2002	/* Control functions *********************************************************/
9	mjames	2003	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		2004	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		2005	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
		2006	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig,
		2007	uint32_t OutputChannel, uint32_t InputChannel);
		2008	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig,
		2009	uint32_t Channel);
		2010	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
2	mjames	2011	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
9	mjames	2012	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		2013	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		2014	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		2015	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		2016	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		2017	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
		2018	uint32_t DataLength);
2	mjames	2019	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
9	mjames	2020	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		2021	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		2022	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		2023	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
		2024	uint32_t DataLength);
2	mjames	2025	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
		2026	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
		2027	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
		2028	/**
		2029	* @}
		2030	*/
		2031
9	mjames	2032	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
		2033	* @brief TIM Callbacks functions
		2034	* @{
		2035	*/
2	mjames	2036	/* Callback in non blocking modes (Interrupt and DMA) *************************/
		2037	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
9	mjames	2038	void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2	mjames	2039	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
		2040	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
9	mjames	2041	void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2	mjames	2042	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
9	mjames	2043	void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2	mjames	2044	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
9	mjames	2045	void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2	mjames	2046	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
9	mjames	2047
		2048	/* Callbacks Register/UnRegister functions ***********************************/
		2049	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2050	HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
		2051	pTIM_CallbackTypeDef pCallback);
		2052	HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
		2053	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2054
2	mjames	2055	/**
		2056	* @}
		2057	*/
		2058
9	mjames	2059	/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
		2060	* @brief Peripheral State functions
		2061	* @{
		2062	*/
		2063	/* Peripheral State functions ************************************************/
2	mjames	2064	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
		2065	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
		2066	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
		2067	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
		2068	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
		2069	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
		2070
9	mjames	2071	/* Peripheral Channel state functions ************************************************/
		2072	HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
		2073	HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
		2074	HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
2	mjames	2075	/**
		2076	* @}
		2077	*/
		2078
		2079	/**
		2080	* @}
		2081	*/
9	mjames	2082	/* End of exported functions -------------------------------------------------*/
2	mjames	2083
9	mjames	2084	/* Private functions----------------------------------------------------------*/
		2085	/** @defgroup TIM_Private_Functions TIM Private Functions
		2086	* @{
		2087	*/
		2088	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
		2089	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
		2090	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		2091	void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
		2092	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
		2093
		2094	void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
		2095	void TIM_DMAError(DMA_HandleTypeDef *hdma);
		2096	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
		2097	void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
		2098	void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
		2099
		2100	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2101	void TIM_ResetCallback(TIM_HandleTypeDef *htim);
		2102	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2103
2	mjames	2104	/**
		2105	* @}
		2106	*/
9	mjames	2107	/* End of private functions --------------------------------------------------*/
2	mjames	2108
		2109	/**
		2110	* @}
		2111	*/
		2112
9	mjames	2113	/**
		2114	* @}
		2115	*/
		2116
2	mjames	2117	#ifdef __cplusplus
		2118	}
		2119	#endif
		2120
9	mjames	2121	#endif /* STM32F1xx_HAL_TIM_H */
2	mjames	2122
		2123	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h – Rev 9