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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_tim.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of TIM HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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| 10 | * |
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| 11 | * Redistribution and use in source and binary forms, with or without modification, |
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| 12 | * are permitted provided that the following conditions are met: |
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| 13 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 14 | * this list of conditions and the following disclaimer. |
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| 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 16 | * this list of conditions and the following disclaimer in the documentation |
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| 17 | * and/or other materials provided with the distribution. |
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| 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 19 | * may be used to endorse or promote products derived from this software |
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| 20 | * without specific prior written permission. |
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| 21 | * |
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| 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 32 | * |
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| 33 | ****************************************************************************** |
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| 34 | */ |
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| 35 | |||
| 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 37 | #ifndef __STM32F1xx_HAL_TIM_H |
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| 38 | #define __STM32F1xx_HAL_TIM_H |
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| 39 | |||
| 40 | #ifdef __cplusplus |
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| 41 | extern "C" { |
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| 42 | #endif |
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| 43 | |||
| 44 | /* Includes ------------------------------------------------------------------*/ |
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| 45 | #include "stm32f1xx_hal_def.h" |
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| 46 | |||
| 47 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 48 | * @{ |
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| 49 | */ |
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| 50 | |||
| 51 | /** @addtogroup TIM |
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| 52 | * @{ |
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| 53 | */ |
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| 54 | |||
| 55 | /* Exported types ------------------------------------------------------------*/ |
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| 56 | /** @defgroup TIM_Exported_Types TIM Exported Types |
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| 57 | * @{ |
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| 58 | */ |
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| 59 | /** |
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| 60 | * @brief TIM Time base Configuration Structure definition |
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| 61 | */ |
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| 62 | typedef struct |
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| 63 | { |
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| 64 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
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| 65 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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| 66 | |||
| 67 | uint32_t CounterMode; /*!< Specifies the counter mode. |
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| 68 | This parameter can be a value of @ref TIM_Counter_Mode */ |
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| 69 | |||
| 70 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
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| 71 | Auto-Reload Register at the next update event. |
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| 72 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
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| 73 | |||
| 74 | uint32_t ClockDivision; /*!< Specifies the clock division. |
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| 75 | This parameter can be a value of @ref TIM_ClockDivision */ |
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| 76 | |||
| 77 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
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| 78 | reaches zero, an update event is generated and counting restarts |
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| 79 | from the RCR value (N). |
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| 80 | This means in PWM mode that (N+1) corresponds to: |
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| 81 | - the number of PWM periods in edge-aligned mode |
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| 82 | - the number of half PWM period in center-aligned mode |
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| 83 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
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| 84 | @note This parameter is valid only for TIM1 and TIM8. */ |
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| 85 | |||
| 86 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
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| 87 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
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| 88 | } TIM_Base_InitTypeDef; |
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| 89 | |||
| 90 | /** |
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| 91 | * @brief TIM Output Compare Configuration Structure definition |
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| 92 | */ |
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| 93 | typedef struct |
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| 94 | { |
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| 95 | uint32_t OCMode; /*!< Specifies the TIM mode. |
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| 96 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
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| 97 | |||
| 98 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
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| 99 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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| 100 | |||
| 101 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
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| 102 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
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| 103 | |||
| 104 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
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| 105 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
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| 106 | @note This parameter is valid only for TIM1 and TIM8. */ |
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| 107 | |||
| 108 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
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| 109 | This parameter can be a value of @ref TIM_Output_Fast_State |
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| 110 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
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| 111 | |||
| 112 | |||
| 113 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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| 114 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
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| 115 | @note This parameter is valid only for TIM1 and TIM8. */ |
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| 116 | |||
| 117 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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| 118 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
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| 119 | @note This parameter is valid only for TIM1 and TIM8. */ |
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| 120 | } TIM_OC_InitTypeDef; |
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| 121 | |||
| 122 | /** |
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| 123 | * @brief TIM One Pulse Mode Configuration Structure definition |
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| 124 | */ |
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| 125 | typedef struct |
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| 126 | { |
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| 127 | uint32_t OCMode; /*!< Specifies the TIM mode. |
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| 128 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
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| 129 | |||
| 130 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
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| 131 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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| 132 | |||
| 133 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
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| 134 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
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| 135 | |||
| 136 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
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| 137 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
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| 138 | @note This parameter is valid only for TIM1 and TIM8. */ |
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| 139 | |||
| 140 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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| 141 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
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| 142 | @note This parameter is valid only for TIM1 and TIM8. */ |
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| 143 | |||
| 144 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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| 145 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
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| 146 | @note This parameter is valid only for TIM1 and TIM8. */ |
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| 147 | |||
| 148 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
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| 149 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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| 150 | |||
| 151 | uint32_t ICSelection; /*!< Specifies the input. |
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| 152 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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| 153 | |||
| 154 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
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| 155 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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| 156 | } TIM_OnePulse_InitTypeDef; |
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| 157 | |||
| 158 | |||
| 159 | /** |
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| 160 | * @brief TIM Input Capture Configuration Structure definition |
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| 161 | */ |
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| 162 | typedef struct |
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| 163 | { |
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| 164 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
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| 165 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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| 166 | |||
| 167 | uint32_t ICSelection; /*!< Specifies the input. |
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| 168 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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| 169 | |||
| 170 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
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| 171 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
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| 172 | |||
| 173 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
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| 174 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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| 175 | } TIM_IC_InitTypeDef; |
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| 176 | |||
| 177 | /** |
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| 178 | * @brief TIM Encoder Configuration Structure definition |
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| 179 | */ |
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| 180 | typedef struct |
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| 181 | { |
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| 182 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
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| 183 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
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| 184 | |||
| 185 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
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| 186 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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| 187 | |||
| 188 | uint32_t IC1Selection; /*!< Specifies the input. |
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| 189 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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| 190 | |||
| 191 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
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| 192 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
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| 193 | |||
| 194 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
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| 195 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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| 196 | |||
| 197 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
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| 198 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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| 199 | |||
| 200 | uint32_t IC2Selection; /*!< Specifies the input. |
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| 201 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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| 202 | |||
| 203 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
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| 204 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
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| 205 | |||
| 206 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
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| 207 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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| 208 | } TIM_Encoder_InitTypeDef; |
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| 209 | |||
| 210 | |||
| 211 | /** |
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| 212 | * @brief TIM Clock Configuration Handle Structure definition |
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| 213 | */ |
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| 214 | typedef struct |
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| 215 | { |
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| 216 | uint32_t ClockSource; /*!< TIM clock sources |
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| 217 | This parameter can be a value of @ref TIM_Clock_Source */ |
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| 218 | uint32_t ClockPolarity; /*!< TIM clock polarity |
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| 219 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
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| 220 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
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| 221 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
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| 222 | uint32_t ClockFilter; /*!< TIM clock filter |
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| 223 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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| 224 | }TIM_ClockConfigTypeDef; |
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| 225 | |||
| 226 | /** |
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| 227 | * @brief TIM Clear Input Configuration Handle Structure definition |
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| 228 | */ |
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| 229 | typedef struct |
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| 230 | { |
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| 231 | uint32_t ClearInputState; /*!< TIM clear Input state |
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| 232 | This parameter can be ENABLE or DISABLE */ |
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| 233 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
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| 234 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
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| 235 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
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| 236 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
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| 237 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
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| 238 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
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| 239 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
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| 240 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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| 241 | }TIM_ClearInputConfigTypeDef; |
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| 242 | |||
| 243 | /** |
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| 244 | * @brief TIM Slave configuration Structure definition |
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| 245 | */ |
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| 246 | typedef struct { |
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| 247 | uint32_t SlaveMode; /*!< Slave mode selection |
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| 248 | This parameter can be a value of @ref TIM_Slave_Mode */ |
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| 249 | uint32_t InputTrigger; /*!< Input Trigger source |
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| 250 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
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| 251 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
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| 252 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
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| 253 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
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| 254 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
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| 255 | uint32_t TriggerFilter; /*!< Input trigger filter |
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| 256 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
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| 257 | |||
| 258 | }TIM_SlaveConfigTypeDef; |
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| 259 | |||
| 260 | /** |
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| 261 | * @brief HAL State structures definition |
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| 262 | */ |
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| 263 | typedef enum |
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| 264 | { |
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| 265 | HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ |
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| 266 | HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
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| 267 | HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
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| 268 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
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| 269 | HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
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| 270 | }HAL_TIM_StateTypeDef; |
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| 271 | |||
| 272 | /** |
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| 273 | * @brief HAL Active channel structures definition |
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| 274 | */ |
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| 275 | typedef enum |
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| 276 | { |
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| 277 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
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| 278 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ |
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| 279 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ |
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| 280 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ |
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| 281 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ |
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| 282 | }HAL_TIM_ActiveChannel; |
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| 283 | |||
| 284 | /** |
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| 285 | * @brief TIM Time Base Handle Structure definition |
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| 286 | */ |
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| 287 | typedef struct |
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| 288 | { |
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| 289 | TIM_TypeDef *Instance; /*!< Register base address */ |
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| 290 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
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| 291 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
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| 292 | DMA_HandleTypeDef *hdma[7U]; /*!< DMA Handlers array |
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| 293 | This array is accessed by a @ref TIM_DMA_Handle_index */ |
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| 294 | HAL_LockTypeDef Lock; /*!< Locking object */ |
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| 295 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
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| 296 | }TIM_HandleTypeDef; |
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| 297 | |||
| 298 | /** |
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| 299 | * @} |
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| 300 | */ |
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| 301 | |||
| 302 | /* Exported constants --------------------------------------------------------*/ |
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| 303 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
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| 304 | * @{ |
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| 305 | */ |
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| 306 | |||
| 307 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity |
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| 308 | * @{ |
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| 309 | */ |
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| 310 | #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ |
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| 311 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
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| 312 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
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| 313 | /** |
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| 314 | * @} |
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| 315 | */ |
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| 316 | |||
| 317 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
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| 318 | * @{ |
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| 319 | */ |
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| 320 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
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| 321 | #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ |
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| 322 | /** |
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| 323 | * @} |
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| 324 | */ |
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| 325 | |||
| 326 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
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| 327 | * @{ |
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| 328 | */ |
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| 329 | #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ |
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| 330 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
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| 331 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
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| 332 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
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| 333 | /** |
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| 334 | * @} |
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| 335 | */ |
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| 336 | |||
| 337 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
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| 338 | * @{ |
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| 339 | */ |
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| 340 | #define TIM_COUNTERMODE_UP 0x00000000U |
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| 341 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
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| 342 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
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| 343 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
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| 344 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
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| 345 | /** |
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| 346 | * @} |
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| 347 | */ |
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| 348 | |||
| 349 | /** @defgroup TIM_ClockDivision TIM ClockDivision |
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| 350 | * @{ |
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| 351 | */ |
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| 352 | #define TIM_CLOCKDIVISION_DIV1 0x00000000U |
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| 353 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
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| 354 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
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| 355 | /** |
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| 356 | * @} |
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| 357 | */ |
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| 358 | |||
| 359 | /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload |
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| 360 | * @{ |
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| 361 | */ |
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| 362 | #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /*!< TIMx_ARR register is not buffered */ |
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| 363 | #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ |
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| 364 | /** |
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| 365 | * @} |
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| 366 | */ |
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| 367 | |||
| 368 | /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes |
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| 369 | * @{ |
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| 370 | */ |
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| 371 | #define TIM_OCMODE_TIMING 0x00000000U |
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| 372 | #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) |
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| 373 | #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) |
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| 374 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) |
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| 375 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
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| 376 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) |
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| 377 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
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| 378 | #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) |
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| 379 | /** |
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| 380 | * @} |
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| 381 | */ |
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| 382 | |||
| 383 | /** @defgroup TIM_Output_Compare_State TIM Output Compare State |
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| 384 | * @{ |
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| 385 | */ |
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| 386 | #define TIM_OUTPUTSTATE_DISABLE 0x00000000U |
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| 387 | #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) |
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| 388 | /** |
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| 389 | * @} |
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| 390 | */ |
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| 391 | |||
| 392 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
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| 393 | * @{ |
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| 394 | */ |
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| 395 | #define TIM_OCFAST_DISABLE 0x00000000U |
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| 396 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
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| 397 | /** |
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| 398 | * @} |
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| 399 | */ |
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| 400 | |||
| 401 | /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State |
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| 402 | * @{ |
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| 403 | */ |
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| 404 | #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U |
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| 405 | #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) |
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| 406 | /** |
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| 407 | * @} |
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| 408 | */ |
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| 409 | |||
| 410 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
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| 411 | * @{ |
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| 412 | */ |
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| 413 | #define TIM_OCPOLARITY_HIGH 0x00000000U |
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| 414 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
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| 415 | /** |
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| 416 | * @} |
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| 417 | */ |
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| 418 | |||
| 419 | /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity |
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| 420 | * @{ |
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| 421 | */ |
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| 422 | #define TIM_OCNPOLARITY_HIGH 0x00000000U |
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| 423 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) |
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| 424 | /** |
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| 425 | * @} |
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| 426 | */ |
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| 427 | |||
| 428 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
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| 429 | * @{ |
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| 430 | */ |
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| 431 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
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| 432 | #define TIM_OCIDLESTATE_RESET 0x00000000U |
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| 433 | /** |
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| 434 | * @} |
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| 435 | */ |
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| 436 | |||
| 437 | /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State |
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| 438 | * @{ |
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| 439 | */ |
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| 440 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) |
||
| 441 | #define TIM_OCNIDLESTATE_RESET 0x00000000U |
||
| 442 | /** |
||
| 443 | * @} |
||
| 444 | */ |
||
| 445 | |||
| 446 | /** @defgroup TIM_Channel TIM Channel |
||
| 447 | * @{ |
||
| 448 | */ |
||
| 449 | #define TIM_CHANNEL_1 0x00000000U |
||
| 450 | #define TIM_CHANNEL_2 0x00000004U |
||
| 451 | #define TIM_CHANNEL_3 0x00000008U |
||
| 452 | #define TIM_CHANNEL_4 0x0000000CU |
||
| 453 | #define TIM_CHANNEL_ALL 0x00000018U |
||
| 454 | /** |
||
| 455 | * @} |
||
| 456 | */ |
||
| 457 | |||
| 458 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
||
| 459 | * @{ |
||
| 460 | */ |
||
| 461 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ |
||
| 462 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ |
||
| 463 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input */ |
||
| 464 | /** |
||
| 465 | * @} |
||
| 466 | */ |
||
| 467 | |||
| 468 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
||
| 469 | * @{ |
||
| 470 | */ |
||
| 471 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
||
| 472 | connected to IC1, IC2, IC3 or IC4, respectively */ |
||
| 473 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
||
| 474 | connected to IC2, IC1, IC4 or IC3, respectively */ |
||
| 475 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
||
| 476 | /** |
||
| 477 | * @} |
||
| 478 | */ |
||
| 479 | |||
| 480 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
||
| 481 | * @{ |
||
| 482 | */ |
||
| 483 | #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ |
||
| 484 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
||
| 485 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
||
| 486 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
||
| 487 | /** |
||
| 488 | * @} |
||
| 489 | */ |
||
| 490 | |||
| 491 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
||
| 492 | * @{ |
||
| 493 | */ |
||
| 494 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
||
| 495 | #define TIM_OPMODE_REPETITIVE 0x00000000U |
||
| 496 | /** |
||
| 497 | * @} |
||
| 498 | */ |
||
| 499 | |||
| 500 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
||
| 501 | * @{ |
||
| 502 | */ |
||
| 503 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
||
| 504 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
||
| 505 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
||
| 506 | /** |
||
| 507 | * @} |
||
| 508 | */ |
||
| 509 | |||
| 510 | /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition |
||
| 511 | * @{ |
||
| 512 | */ |
||
| 513 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
||
| 514 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
||
| 515 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
||
| 516 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
||
| 517 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
||
| 518 | #define TIM_IT_COM (TIM_DIER_COMIE) |
||
| 519 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
||
| 520 | #define TIM_IT_BREAK (TIM_DIER_BIE) |
||
| 521 | /** |
||
| 522 | * @} |
||
| 523 | */ |
||
| 524 | |||
| 525 | /** @defgroup TIM_Commutation_Source TIM Commutation Source |
||
| 526 | * @{ |
||
| 527 | */ |
||
| 528 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) |
||
| 529 | #define TIM_COMMUTATION_SOFTWARE 0x00000000U |
||
| 530 | |||
| 531 | /** |
||
| 532 | * @} |
||
| 533 | */ |
||
| 534 | |||
| 535 | /** @defgroup TIM_DMA_sources TIM DMA Sources |
||
| 536 | * @{ |
||
| 537 | */ |
||
| 538 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
||
| 539 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
||
| 540 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
||
| 541 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
||
| 542 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
||
| 543 | #define TIM_DMA_COM (TIM_DIER_COMDE) |
||
| 544 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
||
| 545 | /** |
||
| 546 | * @} |
||
| 547 | */ |
||
| 548 | |||
| 549 | /** @defgroup TIM_Event_Source TIM Event Source |
||
| 550 | * @{ |
||
| 551 | */ |
||
| 552 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG |
||
| 553 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G |
||
| 554 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G |
||
| 555 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G |
||
| 556 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G |
||
| 557 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG |
||
| 558 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG |
||
| 559 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG |
||
| 560 | /** |
||
| 561 | * @} |
||
| 562 | */ |
||
| 563 | |||
| 564 | /** @defgroup TIM_Flag_definition TIM Flag Definition |
||
| 565 | * @{ |
||
| 566 | */ |
||
| 567 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
||
| 568 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
||
| 569 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
||
| 570 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
||
| 571 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
||
| 572 | #define TIM_FLAG_COM (TIM_SR_COMIF) |
||
| 573 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
||
| 574 | #define TIM_FLAG_BREAK (TIM_SR_BIF) |
||
| 575 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
||
| 576 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
||
| 577 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
||
| 578 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
||
| 579 | /** |
||
| 580 | * @} |
||
| 581 | */ |
||
| 582 | |||
| 583 | /** @defgroup TIM_Clock_Source TIM Clock Source |
||
| 584 | * @{ |
||
| 585 | */ |
||
| 586 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
||
| 587 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
||
| 588 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) |
||
| 589 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
||
| 590 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
||
| 591 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
||
| 592 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
||
| 593 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
||
| 594 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
||
| 595 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
||
| 596 | /** |
||
| 597 | * @} |
||
| 598 | */ |
||
| 599 | |||
| 600 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
||
| 601 | * @{ |
||
| 602 | */ |
||
| 603 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
||
| 604 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
||
| 605 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
||
| 606 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
||
| 607 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
||
| 608 | /** |
||
| 609 | * @} |
||
| 610 | */ |
||
| 611 | |||
| 612 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
||
| 613 | * @{ |
||
| 614 | */ |
||
| 615 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
||
| 616 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
||
| 617 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
||
| 618 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
||
| 619 | /** |
||
| 620 | * @} |
||
| 621 | */ |
||
| 622 | |||
| 623 | /** @defgroup TIM_ClearInput_Source TIM ClearInput Source |
||
| 624 | * @{ |
||
| 625 | */ |
||
| 626 | #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U |
||
| 627 | #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U |
||
| 628 | /** |
||
| 629 | * @} |
||
| 630 | */ |
||
| 631 | |||
| 632 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
||
| 633 | * @{ |
||
| 634 | */ |
||
| 635 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
||
| 636 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
||
| 637 | /** |
||
| 638 | * @} |
||
| 639 | */ |
||
| 640 | |||
| 641 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
||
| 642 | * @{ |
||
| 643 | */ |
||
| 644 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
||
| 645 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
||
| 646 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
||
| 647 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
||
| 648 | /** |
||
| 649 | * @} |
||
| 650 | */ |
||
| 651 | |||
| 652 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state |
||
| 653 | * @{ |
||
| 654 | */ |
||
| 655 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
||
| 656 | #define TIM_OSSR_DISABLE 0x00000000U |
||
| 657 | /** |
||
| 658 | * @} |
||
| 659 | */ |
||
| 660 | |||
| 661 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state |
||
| 662 | * @{ |
||
| 663 | */ |
||
| 664 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
||
| 665 | #define TIM_OSSI_DISABLE 0x00000000U |
||
| 666 | /** |
||
| 667 | * @} |
||
| 668 | */ |
||
| 669 | |||
| 670 | /** @defgroup TIM_Lock_level TIM Lock level |
||
| 671 | * @{ |
||
| 672 | */ |
||
| 673 | #define TIM_LOCKLEVEL_OFF 0x00000000U |
||
| 674 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
||
| 675 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
||
| 676 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
||
| 677 | /** |
||
| 678 | * @} |
||
| 679 | */ |
||
| 680 | |||
| 681 | /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable |
||
| 682 | * @{ |
||
| 683 | */ |
||
| 684 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) |
||
| 685 | #define TIM_BREAK_DISABLE 0x00000000U |
||
| 686 | /** |
||
| 687 | * @} |
||
| 688 | */ |
||
| 689 | |||
| 690 | /** @defgroup TIM_Break_Polarity TIM Break Input Polarity |
||
| 691 | * @{ |
||
| 692 | */ |
||
| 693 | #define TIM_BREAKPOLARITY_LOW 0x00000000U |
||
| 694 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) |
||
| 695 | /** |
||
| 696 | * @} |
||
| 697 | */ |
||
| 698 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable |
||
| 699 | * @{ |
||
| 700 | */ |
||
| 701 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
||
| 702 | #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U |
||
| 703 | /** |
||
| 704 | * @} |
||
| 705 | */ |
||
| 706 | |||
| 707 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
||
| 708 | * @{ |
||
| 709 | */ |
||
| 710 | #define TIM_TRGO_RESET 0x00000000U |
||
| 711 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
||
| 712 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
||
| 713 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
||
| 714 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
||
| 715 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
||
| 716 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
||
| 717 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
||
| 718 | /** |
||
| 719 | * @} |
||
| 720 | */ |
||
| 721 | |||
| 722 | /** @defgroup TIM_Slave_Mode TIM Slave Mode |
||
| 723 | * @{ |
||
| 724 | */ |
||
| 725 | #define TIM_SLAVEMODE_DISABLE 0x00000000U |
||
| 726 | #define TIM_SLAVEMODE_RESET 0x00000004U |
||
| 727 | #define TIM_SLAVEMODE_GATED 0x00000005U |
||
| 728 | #define TIM_SLAVEMODE_TRIGGER 0x00000006U |
||
| 729 | #define TIM_SLAVEMODE_EXTERNAL1 0x00000007U |
||
| 730 | /** |
||
| 731 | * @} |
||
| 732 | */ |
||
| 733 | |||
| 734 | /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode |
||
| 735 | * @{ |
||
| 736 | */ |
||
| 737 | #define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U |
||
| 738 | #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U |
||
| 739 | /** |
||
| 740 | * @} |
||
| 741 | */ |
||
| 742 | |||
| 743 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
||
| 744 | * @{ |
||
| 745 | */ |
||
| 746 | #define TIM_TS_ITR0 0x00000000U |
||
| 747 | #define TIM_TS_ITR1 0x00000010U |
||
| 748 | #define TIM_TS_ITR2 0x00000020U |
||
| 749 | #define TIM_TS_ITR3 0x00000030U |
||
| 750 | #define TIM_TS_TI1F_ED 0x00000040U |
||
| 751 | #define TIM_TS_TI1FP1 0x00000050U |
||
| 752 | #define TIM_TS_TI2FP2 0x00000060U |
||
| 753 | #define TIM_TS_ETRF 0x00000070U |
||
| 754 | #define TIM_TS_NONE 0x0000FFFFU |
||
| 755 | /** |
||
| 756 | * @} |
||
| 757 | */ |
||
| 758 | |||
| 759 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
||
| 760 | * @{ |
||
| 761 | */ |
||
| 762 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
||
| 763 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
||
| 764 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
||
| 765 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
||
| 766 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
||
| 767 | /** |
||
| 768 | * @} |
||
| 769 | */ |
||
| 770 | |||
| 771 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
||
| 772 | * @{ |
||
| 773 | */ |
||
| 774 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
||
| 775 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
||
| 776 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
||
| 777 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
||
| 778 | /** |
||
| 779 | * @} |
||
| 780 | */ |
||
| 781 | |||
| 782 | /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection |
||
| 783 | * @{ |
||
| 784 | */ |
||
| 785 | #define TIM_TI1SELECTION_CH1 0x00000000U |
||
| 786 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
||
| 787 | /** |
||
| 788 | * @} |
||
| 789 | */ |
||
| 790 | |||
| 791 | /** @defgroup TIM_DMA_Base_address TIM DMA Base Address |
||
| 792 | * @{ |
||
| 793 | */ |
||
| 794 | #define TIM_DMABASE_CR1 0x00000000U |
||
| 795 | #define TIM_DMABASE_CR2 0x00000001U |
||
| 796 | #define TIM_DMABASE_SMCR 0x00000002U |
||
| 797 | #define TIM_DMABASE_DIER 0x00000003U |
||
| 798 | #define TIM_DMABASE_SR 0x00000004U |
||
| 799 | #define TIM_DMABASE_EGR 0x00000005U |
||
| 800 | #define TIM_DMABASE_CCMR1 0x00000006U |
||
| 801 | #define TIM_DMABASE_CCMR2 0x00000007U |
||
| 802 | #define TIM_DMABASE_CCER 0x00000008U |
||
| 803 | #define TIM_DMABASE_CNT 0x00000009U |
||
| 804 | #define TIM_DMABASE_PSC 0x0000000AU |
||
| 805 | #define TIM_DMABASE_ARR 0x0000000BU |
||
| 806 | #define TIM_DMABASE_RCR 0x0000000CU |
||
| 807 | #define TIM_DMABASE_CCR1 0x0000000DU |
||
| 808 | #define TIM_DMABASE_CCR2 0x0000000EU |
||
| 809 | #define TIM_DMABASE_CCR3 0x0000000FU |
||
| 810 | #define TIM_DMABASE_CCR4 0x00000010U |
||
| 811 | #define TIM_DMABASE_BDTR 0x00000011U |
||
| 812 | #define TIM_DMABASE_DCR 0x00000012U |
||
| 813 | /** |
||
| 814 | * @} |
||
| 815 | */ |
||
| 816 | |||
| 817 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
||
| 818 | * @{ |
||
| 819 | */ |
||
| 820 | #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U |
||
| 821 | #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U |
||
| 822 | #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U |
||
| 823 | #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U |
||
| 824 | #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U |
||
| 825 | #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U |
||
| 826 | #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U |
||
| 827 | #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U |
||
| 828 | #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U |
||
| 829 | #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U |
||
| 830 | #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U |
||
| 831 | #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U |
||
| 832 | #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U |
||
| 833 | #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U |
||
| 834 | #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U |
||
| 835 | #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U |
||
| 836 | #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U |
||
| 837 | #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U |
||
| 838 | /** |
||
| 839 | * @} |
||
| 840 | */ |
||
| 841 | |||
| 842 | /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index |
||
| 843 | * @{ |
||
| 844 | */ |
||
| 845 | #define TIM_DMA_ID_UPDATE ((uint16_t)0x0) /*!< Index of the DMA handle used for Update DMA requests */ |
||
| 846 | #define TIM_DMA_ID_CC1 ((uint16_t)0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
||
| 847 | #define TIM_DMA_ID_CC2 ((uint16_t)0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
||
| 848 | #define TIM_DMA_ID_CC3 ((uint16_t)0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
||
| 849 | #define TIM_DMA_ID_CC4 ((uint16_t)0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
||
| 850 | #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ |
||
| 851 | #define TIM_DMA_ID_TRIGGER ((uint16_t)0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ |
||
| 852 | /** |
||
| 853 | * @} |
||
| 854 | */ |
||
| 855 | |||
| 856 | /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State |
||
| 857 | * @{ |
||
| 858 | */ |
||
| 859 | #define TIM_CCx_ENABLE 0x00000001U |
||
| 860 | #define TIM_CCx_DISABLE 0x00000000U |
||
| 861 | #define TIM_CCxN_ENABLE 0x00000004U |
||
| 862 | #define TIM_CCxN_DISABLE 0x00000000U |
||
| 863 | /** |
||
| 864 | * @} |
||
| 865 | */ |
||
| 866 | |||
| 867 | /** |
||
| 868 | * @} |
||
| 869 | */ |
||
| 870 | |||
| 871 | /* Private Constants -----------------------------------------------------------*/ |
||
| 872 | /** @defgroup TIM_Private_Constants TIM Private Constants |
||
| 873 | * @{ |
||
| 874 | */ |
||
| 875 | |||
| 876 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
||
| 877 | channels have been disabled */ |
||
| 878 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
||
| 879 | #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
||
| 880 | |||
| 881 | /** |
||
| 882 | * @} |
||
| 883 | */ |
||
| 884 | |||
| 885 | /* Private Macros -----------------------------------------------------------*/ |
||
| 886 | /** @defgroup TIM_Private_Macros TIM Private Macros |
||
| 887 | * @{ |
||
| 888 | */ |
||
| 889 | |||
| 890 | #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ |
||
| 891 | ((MODE) == TIM_COUNTERMODE_DOWN) || \ |
||
| 892 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
||
| 893 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
||
| 894 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) |
||
| 895 | |||
| 896 | #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ |
||
| 897 | ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ |
||
| 898 | ((DIV) == TIM_CLOCKDIVISION_DIV4)) |
||
| 899 | |||
| 900 | #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ |
||
| 901 | ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) |
||
| 902 | |||
| 903 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
||
| 904 | ((MODE) == TIM_OCMODE_PWM2)) |
||
| 905 | |||
| 906 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
||
| 907 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
||
| 908 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
||
| 909 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
||
| 910 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
||
| 911 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) |
||
| 912 | |||
| 913 | #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ |
||
| 914 | ((STATE) == TIM_OCFAST_ENABLE)) |
||
| 915 | |||
| 916 | #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ |
||
| 917 | ((POLARITY) == TIM_OCPOLARITY_LOW)) |
||
| 918 | |||
| 919 | #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ |
||
| 920 | ((POLARITY) == TIM_OCNPOLARITY_LOW)) |
||
| 921 | |||
| 922 | #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ |
||
| 923 | ((STATE) == TIM_OCIDLESTATE_RESET)) |
||
| 924 | |||
| 925 | #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ |
||
| 926 | ((STATE) == TIM_OCNIDLESTATE_RESET)) |
||
| 927 | |||
| 928 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 929 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 930 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 931 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
||
| 932 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
||
| 933 | |||
| 934 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 935 | ((CHANNEL) == TIM_CHANNEL_2)) |
||
| 936 | |||
| 937 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 938 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 939 | ((CHANNEL) == TIM_CHANNEL_3)) |
||
| 940 | |||
| 941 | #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ |
||
| 942 | ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ |
||
| 943 | ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) |
||
| 944 | |||
| 945 | #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ |
||
| 946 | ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ |
||
| 947 | ((SELECTION) == TIM_ICSELECTION_TRC)) |
||
| 948 | |||
| 949 | #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ |
||
| 950 | ((PRESCALER) == TIM_ICPSC_DIV2) || \ |
||
| 951 | ((PRESCALER) == TIM_ICPSC_DIV4) || \ |
||
| 952 | ((PRESCALER) == TIM_ICPSC_DIV8)) |
||
| 953 | |||
| 954 | #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ |
||
| 955 | ((MODE) == TIM_OPMODE_REPETITIVE)) |
||
| 956 | |||
| 957 | #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ |
||
| 958 | ((MODE) == TIM_ENCODERMODE_TI2) || \ |
||
| 959 | ((MODE) == TIM_ENCODERMODE_TI12)) |
||
| 960 | |||
| 961 | #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
||
| 962 | |||
| 963 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
||
| 964 | |||
| 965 | #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ |
||
| 966 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
||
| 967 | ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ |
||
| 968 | ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ |
||
| 969 | ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ |
||
| 970 | ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ |
||
| 971 | ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ |
||
| 972 | ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ |
||
| 973 | ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ |
||
| 974 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) |
||
| 975 | |||
| 976 | #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ |
||
| 977 | ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
||
| 978 | ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ |
||
| 979 | ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ |
||
| 980 | ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
||
| 981 | |||
| 982 | #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ |
||
| 983 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ |
||
| 984 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ |
||
| 985 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) |
||
| 986 | |||
| 987 | #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) |
||
| 988 | |||
| 989 | #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ |
||
| 990 | ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) |
||
| 991 | |||
| 992 | #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
||
| 993 | ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
||
| 994 | |||
| 995 | #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
||
| 996 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
||
| 997 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
||
| 998 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) |
||
| 999 | |||
| 1000 | #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) |
||
| 1001 | |||
| 1002 | #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ |
||
| 1003 | ((STATE) == TIM_OSSR_DISABLE)) |
||
| 1004 | |||
| 1005 | #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ |
||
| 1006 | ((STATE) == TIM_OSSI_DISABLE)) |
||
| 1007 | |||
| 1008 | #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ |
||
| 1009 | ((LEVEL) == TIM_LOCKLEVEL_1) || \ |
||
| 1010 | ((LEVEL) == TIM_LOCKLEVEL_2) || \ |
||
| 1011 | ((LEVEL) == TIM_LOCKLEVEL_3)) |
||
| 1012 | |||
| 1013 | #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ |
||
| 1014 | ((STATE) == TIM_BREAK_DISABLE)) |
||
| 1015 | |||
| 1016 | #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ |
||
| 1017 | ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) |
||
| 1018 | |||
| 1019 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
||
| 1020 | ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) |
||
| 1021 | |||
| 1022 | #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ |
||
| 1023 | ((SOURCE) == TIM_TRGO_ENABLE) || \ |
||
| 1024 | ((SOURCE) == TIM_TRGO_UPDATE) || \ |
||
| 1025 | ((SOURCE) == TIM_TRGO_OC1) || \ |
||
| 1026 | ((SOURCE) == TIM_TRGO_OC1REF) || \ |
||
| 1027 | ((SOURCE) == TIM_TRGO_OC2REF) || \ |
||
| 1028 | ((SOURCE) == TIM_TRGO_OC3REF) || \ |
||
| 1029 | ((SOURCE) == TIM_TRGO_OC4REF)) |
||
| 1030 | |||
| 1031 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
||
| 1032 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
||
| 1033 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
||
| 1034 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
||
| 1035 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) |
||
| 1036 | |||
| 1037 | #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
||
| 1038 | ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) |
||
| 1039 | |||
| 1040 | #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
||
| 1041 | ((SELECTION) == TIM_TS_ITR1) || \ |
||
| 1042 | ((SELECTION) == TIM_TS_ITR2) || \ |
||
| 1043 | ((SELECTION) == TIM_TS_ITR3) || \ |
||
| 1044 | ((SELECTION) == TIM_TS_TI1F_ED) || \ |
||
| 1045 | ((SELECTION) == TIM_TS_TI1FP1) || \ |
||
| 1046 | ((SELECTION) == TIM_TS_TI2FP2) || \ |
||
| 1047 | ((SELECTION) == TIM_TS_ETRF)) |
||
| 1048 | |||
| 1049 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
||
| 1050 | ((SELECTION) == TIM_TS_ITR1) || \ |
||
| 1051 | ((SELECTION) == TIM_TS_ITR2) || \ |
||
| 1052 | ((SELECTION) == TIM_TS_ITR3) || \ |
||
| 1053 | ((SELECTION) == TIM_TS_NONE)) |
||
| 1054 | |||
| 1055 | #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
||
| 1056 | ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
||
| 1057 | ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ |
||
| 1058 | ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
||
| 1059 | ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
||
| 1060 | |||
| 1061 | #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ |
||
| 1062 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ |
||
| 1063 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ |
||
| 1064 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) |
||
| 1065 | |||
| 1066 | #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) |
||
| 1067 | |||
| 1068 | #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ |
||
| 1069 | ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) |
||
| 1070 | |||
| 1071 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ |
||
| 1072 | ((BASE) == TIM_DMABASE_CR2) || \ |
||
| 1073 | ((BASE) == TIM_DMABASE_SMCR) || \ |
||
| 1074 | ((BASE) == TIM_DMABASE_DIER) || \ |
||
| 1075 | ((BASE) == TIM_DMABASE_SR) || \ |
||
| 1076 | ((BASE) == TIM_DMABASE_EGR) || \ |
||
| 1077 | ((BASE) == TIM_DMABASE_CCMR1) || \ |
||
| 1078 | ((BASE) == TIM_DMABASE_CCMR2) || \ |
||
| 1079 | ((BASE) == TIM_DMABASE_CCER) || \ |
||
| 1080 | ((BASE) == TIM_DMABASE_CNT) || \ |
||
| 1081 | ((BASE) == TIM_DMABASE_PSC) || \ |
||
| 1082 | ((BASE) == TIM_DMABASE_ARR) || \ |
||
| 1083 | ((BASE) == TIM_DMABASE_RCR) || \ |
||
| 1084 | ((BASE) == TIM_DMABASE_CCR1) || \ |
||
| 1085 | ((BASE) == TIM_DMABASE_CCR2) || \ |
||
| 1086 | ((BASE) == TIM_DMABASE_CCR3) || \ |
||
| 1087 | ((BASE) == TIM_DMABASE_CCR4) || \ |
||
| 1088 | ((BASE) == TIM_DMABASE_BDTR) || \ |
||
| 1089 | ((BASE) == TIM_DMABASE_DCR)) |
||
| 1090 | |||
| 1091 | #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
||
| 1092 | ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
||
| 1093 | ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
||
| 1094 | ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
||
| 1095 | ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
||
| 1096 | ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
||
| 1097 | ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
||
| 1098 | ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
||
| 1099 | ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
||
| 1100 | ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
||
| 1101 | ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
||
| 1102 | ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
||
| 1103 | ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
||
| 1104 | ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
||
| 1105 | ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
||
| 1106 | ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
||
| 1107 | ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
||
| 1108 | ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
||
| 1109 | |||
| 1110 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) |
||
| 1111 | |||
| 1112 | /** @brief Set TIM IC prescaler |
||
| 1113 | * @param __HANDLE__: TIM handle |
||
| 1114 | * @param __CHANNEL__: specifies TIM Channel |
||
| 1115 | * @param __ICPSC__: specifies the prescaler value. |
||
| 1116 | * @retval None |
||
| 1117 | */ |
||
| 1118 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
||
| 1119 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
||
| 1120 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ |
||
| 1121 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
||
| 1122 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) |
||
| 1123 | |||
| 1124 | /** @brief Reset TIM IC prescaler |
||
| 1125 | * @param __HANDLE__: TIM handle |
||
| 1126 | * @param __CHANNEL__: specifies TIM Channel |
||
| 1127 | * @retval None |
||
| 1128 | */ |
||
| 1129 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
||
| 1130 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ |
||
| 1131 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ |
||
| 1132 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ |
||
| 1133 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) |
||
| 1134 | |||
| 1135 | |||
| 1136 | /** @brief Set TIM IC polarity |
||
| 1137 | * @param __HANDLE__: TIM handle |
||
| 1138 | * @param __CHANNEL__: specifies TIM Channel |
||
| 1139 | * @param __POLARITY__: specifies TIM Channel Polarity |
||
| 1140 | * @retval None |
||
| 1141 | */ |
||
| 1142 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
||
| 1143 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
||
| 1144 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ |
||
| 1145 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ |
||
| 1146 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P))) |
||
| 1147 | |||
| 1148 | /** @brief Reset TIM IC polarity |
||
| 1149 | * @param __HANDLE__: TIM handle |
||
| 1150 | * @param __CHANNEL__: specifies TIM Channel |
||
| 1151 | * @retval None |
||
| 1152 | */ |
||
| 1153 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
||
| 1154 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
||
| 1155 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
||
| 1156 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
||
| 1157 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) |
||
| 1158 | |||
| 1159 | /** |
||
| 1160 | * @} |
||
| 1161 | */ |
||
| 1162 | |||
| 1163 | /* Private Functions --------------------------------------------------------*/ |
||
| 1164 | /** @addtogroup TIM_Private_Functions |
||
| 1165 | * @{ |
||
| 1166 | */ |
||
| 1167 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
||
| 1168 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
||
| 1169 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
||
| 1170 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
||
| 1171 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
||
| 1172 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
||
| 1173 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
||
| 1174 | /** |
||
| 1175 | * @} |
||
| 1176 | */ |
||
| 1177 | |||
| 1178 | /* Exported macros -----------------------------------------------------------*/ |
||
| 1179 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
||
| 1180 | * @{ |
||
| 1181 | */ |
||
| 1182 | |||
| 1183 | /** @brief Reset TIM handle state |
||
| 1184 | * @param __HANDLE__: TIM handle. |
||
| 1185 | * @retval None |
||
| 1186 | */ |
||
| 1187 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
||
| 1188 | |||
| 1189 | /** |
||
| 1190 | * @brief Enable the TIM peripheral. |
||
| 1191 | * @param __HANDLE__: TIM handle |
||
| 1192 | * @retval None |
||
| 1193 | */ |
||
| 1194 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
||
| 1195 | |||
| 1196 | /** |
||
| 1197 | * @brief Enable the TIM main Output. |
||
| 1198 | * @param __HANDLE__: TIM handle |
||
| 1199 | * @retval None |
||
| 1200 | */ |
||
| 1201 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
||
| 1202 | |||
| 1203 | /** |
||
| 1204 | * @brief Disable the TIM peripheral. |
||
| 1205 | * @param __HANDLE__: TIM handle |
||
| 1206 | * @retval None |
||
| 1207 | */ |
||
| 1208 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
||
| 1209 | do { \ |
||
| 1210 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ |
||
| 1211 | { \ |
||
| 1212 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ |
||
| 1213 | { \ |
||
| 1214 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
||
| 1215 | } \ |
||
| 1216 | } \ |
||
| 1217 | } while(0U) |
||
| 1218 | /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN |
||
| 1219 | channels have been disabled */ |
||
| 1220 | /** |
||
| 1221 | * @brief Disable the TIM main Output. |
||
| 1222 | * @param __HANDLE__: TIM handle |
||
| 1223 | * @retval None |
||
| 1224 | * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled |
||
| 1225 | */ |
||
| 1226 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
||
| 1227 | do { \ |
||
| 1228 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ |
||
| 1229 | { \ |
||
| 1230 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ |
||
| 1231 | { \ |
||
| 1232 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ |
||
| 1233 | } \ |
||
| 1234 | } \ |
||
| 1235 | } while(0U) |
||
| 1236 | |||
| 1237 | /** |
||
| 1238 | * @brief Disable the TIM main Output. |
||
| 1239 | * @param __HANDLE__: TIM handle |
||
| 1240 | * @retval None |
||
| 1241 | * @note The Main Output Enable of a timer instance is disabled unconditionally |
||
| 1242 | */ |
||
| 1243 | #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) |
||
| 1244 | |||
| 1245 | /** |
||
| 1246 | * @brief Enables the specified TIM interrupt. |
||
| 1247 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1248 | * @param __INTERRUPT__: specifies the TIM interrupt source to enable. |
||
| 1249 | * This parameter can be one of the following values: |
||
| 1250 | * @arg TIM_IT_UPDATE: Update interrupt |
||
| 1251 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
||
| 1252 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
||
| 1253 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
||
| 1254 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
||
| 1255 | * @arg TIM_IT_COM: Commutation interrupt |
||
| 1256 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
||
| 1257 | * @arg TIM_IT_BREAK: Break interrupt |
||
| 1258 | * @retval None |
||
| 1259 | */ |
||
| 1260 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
||
| 1261 | |||
| 1262 | /** |
||
| 1263 | * @brief Disables the specified TIM interrupt. |
||
| 1264 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1265 | * @param __INTERRUPT__: specifies the TIM interrupt source to disable. |
||
| 1266 | * This parameter can be one of the following values: |
||
| 1267 | * @arg TIM_IT_UPDATE: Update interrupt |
||
| 1268 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
||
| 1269 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
||
| 1270 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
||
| 1271 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
||
| 1272 | * @arg TIM_IT_COM: Commutation interrupt |
||
| 1273 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
||
| 1274 | * @arg TIM_IT_BREAK: Break interrupt |
||
| 1275 | * @retval None |
||
| 1276 | */ |
||
| 1277 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
||
| 1278 | |||
| 1279 | /** |
||
| 1280 | * @brief Enables the specified DMA request. |
||
| 1281 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1282 | * @param __DMA__: specifies the TIM DMA request to enable. |
||
| 1283 | * This parameter can be one of the following values: |
||
| 1284 | * @arg TIM_DMA_UPDATE: Update DMA request |
||
| 1285 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
||
| 1286 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
||
| 1287 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
||
| 1288 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
||
| 1289 | * @arg TIM_DMA_COM: Commutation DMA request |
||
| 1290 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
||
| 1291 | * @retval None |
||
| 1292 | */ |
||
| 1293 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
||
| 1294 | |||
| 1295 | /** |
||
| 1296 | * @brief Disables the specified DMA request. |
||
| 1297 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1298 | * @param __DMA__: specifies the TIM DMA request to disable. |
||
| 1299 | * This parameter can be one of the following values: |
||
| 1300 | * @arg TIM_DMA_UPDATE: Update DMA request |
||
| 1301 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
||
| 1302 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
||
| 1303 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
||
| 1304 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
||
| 1305 | * @arg TIM_DMA_COM: Commutation DMA request |
||
| 1306 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
||
| 1307 | * @retval None |
||
| 1308 | */ |
||
| 1309 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
||
| 1310 | |||
| 1311 | /** |
||
| 1312 | * @brief Checks whether the specified TIM interrupt flag is set or not. |
||
| 1313 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1314 | * @param __FLAG__: specifies the TIM interrupt flag to check. |
||
| 1315 | * This parameter can be one of the following values: |
||
| 1316 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
||
| 1317 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
||
| 1318 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
||
| 1319 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
||
| 1320 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
||
| 1321 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
||
| 1322 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
||
| 1323 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
||
| 1324 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
||
| 1325 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
||
| 1326 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
||
| 1327 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
||
| 1328 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
||
| 1329 | */ |
||
| 1330 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
||
| 1331 | |||
| 1332 | /** |
||
| 1333 | * @brief Clears the specified TIM interrupt flag. |
||
| 1334 | * @param __HANDLE__: specifies the TIM Handle. |
||
| 1335 | * @param __FLAG__: specifies the TIM interrupt flag to clear. |
||
| 1336 | * This parameter can be one of the following values: |
||
| 1337 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
||
| 1338 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
||
| 1339 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
||
| 1340 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
||
| 1341 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
||
| 1342 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
||
| 1343 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
||
| 1344 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
||
| 1345 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
||
| 1346 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
||
| 1347 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
||
| 1348 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
||
| 1349 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
||
| 1350 | */ |
||
| 1351 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
||
| 1352 | |||
| 1353 | /** |
||
| 1354 | * @brief Checks whether the specified TIM interrupt has occurred or not. |
||
| 1355 | * @param __HANDLE__: TIM handle |
||
| 1356 | * @param __INTERRUPT__: specifies the TIM interrupt source to check. |
||
| 1357 | * @retval The state of TIM_IT (SET or RESET). |
||
| 1358 | */ |
||
| 1359 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||
| 1360 | |||
| 1361 | /** |
||
| 1362 | * @brief Clear the TIM interrupt pending bits |
||
| 1363 | * @param __HANDLE__: TIM handle |
||
| 1364 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
||
| 1365 | * @retval None |
||
| 1366 | */ |
||
| 1367 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
||
| 1368 | |||
| 1369 | /** |
||
| 1370 | * @brief Indicates whether or not the TIM Counter is used as downcounter |
||
| 1371 | * @param __HANDLE__: TIM handle. |
||
| 1372 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
||
| 1373 | * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder |
||
| 1374 | mode. |
||
| 1375 | */ |
||
| 1376 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
||
| 1377 | |||
| 1378 | /** |
||
| 1379 | * @brief Sets the TIM active prescaler register value on update event. |
||
| 1380 | * @param __HANDLE__: TIM handle. |
||
| 1381 | * @param __PRESC__: specifies the active prescaler register new value. |
||
| 1382 | * @retval None |
||
| 1383 | */ |
||
| 1384 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
||
| 1385 | |||
| 1386 | /** |
||
| 1387 | * @brief Sets the TIM Capture Compare Register value on runtime without |
||
| 1388 | * calling another time ConfigChannel function. |
||
| 1389 | * @param __HANDLE__: TIM handle. |
||
| 1390 | * @param __CHANNEL__ : TIM Channels to be configured. |
||
| 1391 | * This parameter can be one of the following values: |
||
| 1392 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
||
| 1393 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
||
| 1394 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
||
| 1395 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
||
| 1396 | * @param __COMPARE__: specifies the Capture Compare register new value. |
||
| 1397 | * @retval None |
||
| 1398 | */ |
||
| 1399 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
||
| 1400 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) |
||
| 1401 | |||
| 1402 | /** |
||
| 1403 | * @brief Gets the TIM Capture Compare Register value on runtime |
||
| 1404 | * @param __HANDLE__: TIM handle. |
||
| 1405 | * @param __CHANNEL__ : TIM Channel associated with the capture compare register |
||
| 1406 | * This parameter can be one of the following values: |
||
| 1407 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
||
| 1408 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
||
| 1409 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
||
| 1410 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
||
| 1411 | * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) |
||
| 1412 | */ |
||
| 1413 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
||
| 1414 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) |
||
| 1415 | |||
| 1416 | /** |
||
| 1417 | * @brief Sets the TIM Counter Register value on runtime. |
||
| 1418 | * @param __HANDLE__: TIM handle. |
||
| 1419 | * @param __COUNTER__: specifies the Counter register new value. |
||
| 1420 | * @retval None |
||
| 1421 | */ |
||
| 1422 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
||
| 1423 | |||
| 1424 | /** |
||
| 1425 | * @brief Gets the TIM Counter Register value on runtime. |
||
| 1426 | * @param __HANDLE__: TIM handle. |
||
| 1427 | * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) |
||
| 1428 | */ |
||
| 1429 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ |
||
| 1430 | ((__HANDLE__)->Instance->CNT) |
||
| 1431 | |||
| 1432 | /** |
||
| 1433 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
||
| 1434 | * another time any Init function. |
||
| 1435 | * @param __HANDLE__: TIM handle. |
||
| 1436 | * @param __AUTORELOAD__: specifies the Counter register new value. |
||
| 1437 | * @retval None |
||
| 1438 | */ |
||
| 1439 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
||
| 1440 | do{ \ |
||
| 1441 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
||
| 1442 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
||
| 1443 | } while(0U) |
||
| 1444 | |||
| 1445 | /** |
||
| 1446 | * @brief Gets the TIM Autoreload Register value on runtime |
||
| 1447 | * @param __HANDLE__: TIM handle. |
||
| 1448 | * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) |
||
| 1449 | */ |
||
| 1450 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ |
||
| 1451 | ((__HANDLE__)->Instance->ARR) |
||
| 1452 | |||
| 1453 | /** |
||
| 1454 | * @brief Sets the TIM Clock Division value on runtime without calling |
||
| 1455 | * another time any Init function. |
||
| 1456 | * @param __HANDLE__: TIM handle. |
||
| 1457 | * @param __CKD__: specifies the clock division value. |
||
| 1458 | * This parameter can be one of the following value: |
||
| 1459 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
||
| 1460 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
||
| 1461 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
||
| 1462 | * @retval None |
||
| 1463 | */ |
||
| 1464 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
||
| 1465 | do{ \ |
||
| 1466 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
||
| 1467 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
||
| 1468 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
||
| 1469 | } while(0U) |
||
| 1470 | |||
| 1471 | /** |
||
| 1472 | * @brief Gets the TIM Clock Division value on runtime |
||
| 1473 | * @param __HANDLE__: TIM handle. |
||
| 1474 | * @retval The clock division can be one of the following values: |
||
| 1475 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
||
| 1476 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
||
| 1477 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
||
| 1478 | */ |
||
| 1479 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ |
||
| 1480 | ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
||
| 1481 | |||
| 1482 | /** |
||
| 1483 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
||
| 1484 | * another time HAL_TIM_IC_ConfigChannel() function. |
||
| 1485 | * @param __HANDLE__: TIM handle. |
||
| 1486 | * @param __CHANNEL__ : TIM Channels to be configured. |
||
| 1487 | * This parameter can be one of the following values: |
||
| 1488 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
||
| 1489 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
||
| 1490 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
||
| 1491 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
||
| 1492 | * @param __ICPSC__: specifies the Input Capture4 prescaler new value. |
||
| 1493 | * This parameter can be one of the following values: |
||
| 1494 | * @arg TIM_ICPSC_DIV1: no prescaler |
||
| 1495 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
||
| 1496 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
||
| 1497 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
||
| 1498 | * @retval None |
||
| 1499 | */ |
||
| 1500 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
||
| 1501 | do{ \ |
||
| 1502 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
||
| 1503 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
||
| 1504 | } while(0U) |
||
| 1505 | |||
| 1506 | /** |
||
| 1507 | * @brief Gets the TIM Input Capture prescaler on runtime |
||
| 1508 | * @param __HANDLE__: TIM handle. |
||
| 1509 | * @param __CHANNEL__: TIM Channels to be configured. |
||
| 1510 | * This parameter can be one of the following values: |
||
| 1511 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
||
| 1512 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
||
| 1513 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
||
| 1514 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
||
| 1515 | * @retval The input capture prescaler can be one of the following values: |
||
| 1516 | * @arg TIM_ICPSC_DIV1: no prescaler |
||
| 1517 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
||
| 1518 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
||
| 1519 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
||
| 1520 | */ |
||
| 1521 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
||
| 1522 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
||
| 1523 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ |
||
| 1524 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
||
| 1525 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) |
||
| 1526 | |||
| 1527 | /** |
||
| 1528 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register |
||
| 1529 | * @param __HANDLE__: TIM handle. |
||
| 1530 | * @note When the USR bit of the TIMx_CR1 register is set, only counter |
||
| 1531 | * overflow/underflow generates an update interrupt or DMA request (if |
||
| 1532 | * enabled) |
||
| 1533 | * @retval None |
||
| 1534 | */ |
||
| 1535 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ |
||
| 1536 | ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) |
||
| 1537 | |||
| 1538 | /** |
||
| 1539 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register |
||
| 1540 | * @param __HANDLE__: TIM handle. |
||
| 1541 | * @note When the USR bit of the TIMx_CR1 register is reset, any of the |
||
| 1542 | * following events generate an update interrupt or DMA request (if |
||
| 1543 | * enabled): |
||
| 1544 | * (+) Counter overflow/underflow |
||
| 1545 | * (+) Setting the UG bit |
||
| 1546 | * (+) Update generation through the slave mode controller |
||
| 1547 | * @retval None |
||
| 1548 | */ |
||
| 1549 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ |
||
| 1550 | ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
||
| 1551 | |||
| 1552 | /** |
||
| 1553 | * @brief Sets the TIM Capture x input polarity on runtime. |
||
| 1554 | * @param __HANDLE__: TIM handle. |
||
| 1555 | * @param __CHANNEL__: TIM Channels to be configured. |
||
| 1556 | * This parameter can be one of the following values: |
||
| 1557 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
||
| 1558 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
||
| 1559 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
||
| 1560 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
||
| 1561 | * @param __POLARITY__: Polarity for TIx source |
||
| 1562 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
||
| 1563 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
||
| 1564 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
||
| 1565 | * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. |
||
| 1566 | * @retval None |
||
| 1567 | */ |
||
| 1568 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
||
| 1569 | do{ \ |
||
| 1570 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
||
| 1571 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
||
| 1572 | }while(0U) |
||
| 1573 | |||
| 1574 | /** |
||
| 1575 | * @} |
||
| 1576 | */ |
||
| 1577 | |||
| 1578 | /* Include TIM HAL Extension module */ |
||
| 1579 | #include "stm32f1xx_hal_tim_ex.h" |
||
| 1580 | |||
| 1581 | /* Exported functions --------------------------------------------------------*/ |
||
| 1582 | /** @addtogroup TIM_Exported_Functions |
||
| 1583 | * @{ |
||
| 1584 | */ |
||
| 1585 | |||
| 1586 | /** @addtogroup TIM_Exported_Functions_Group1 |
||
| 1587 | * @{ |
||
| 1588 | */ |
||
| 1589 | /* Time Base functions ********************************************************/ |
||
| 1590 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
||
| 1591 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
||
| 1592 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
||
| 1593 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1594 | /* Blocking mode: Polling */ |
||
| 1595 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
||
| 1596 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
||
| 1597 | /* Non-Blocking mode: Interrupt */ |
||
| 1598 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
||
| 1599 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
||
| 1600 | /* Non-Blocking mode: DMA */ |
||
| 1601 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
||
| 1602 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
||
| 1603 | /** |
||
| 1604 | * @} |
||
| 1605 | */ |
||
| 1606 | |||
| 1607 | /** @addtogroup TIM_Exported_Functions_Group2 |
||
| 1608 | * @{ |
||
| 1609 | */ |
||
| 1610 | /* Timer Output Compare functions **********************************************/ |
||
| 1611 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
||
| 1612 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
||
| 1613 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
||
| 1614 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1615 | /* Blocking mode: Polling */ |
||
| 1616 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1617 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1618 | /* Non-Blocking mode: Interrupt */ |
||
| 1619 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1620 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1621 | /* Non-Blocking mode: DMA */ |
||
| 1622 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
||
| 1623 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1624 | |||
| 1625 | /** |
||
| 1626 | * @} |
||
| 1627 | */ |
||
| 1628 | |||
| 1629 | /** @addtogroup TIM_Exported_Functions_Group3 |
||
| 1630 | * @{ |
||
| 1631 | */ |
||
| 1632 | /* Timer PWM functions *********************************************************/ |
||
| 1633 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
||
| 1634 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
||
| 1635 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
||
| 1636 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1637 | /* Blocking mode: Polling */ |
||
| 1638 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1639 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1640 | /* Non-Blocking mode: Interrupt */ |
||
| 1641 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1642 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1643 | /* Non-Blocking mode: DMA */ |
||
| 1644 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
||
| 1645 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1646 | /** |
||
| 1647 | * @} |
||
| 1648 | */ |
||
| 1649 | |||
| 1650 | /** @addtogroup TIM_Exported_Functions_Group4 |
||
| 1651 | * @{ |
||
| 1652 | */ |
||
| 1653 | /* Timer Input Capture functions ***********************************************/ |
||
| 1654 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
||
| 1655 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
||
| 1656 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
||
| 1657 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1658 | /* Blocking mode: Polling */ |
||
| 1659 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1660 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1661 | /* Non-Blocking mode: Interrupt */ |
||
| 1662 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1663 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1664 | /* Non-Blocking mode: DMA */ |
||
| 1665 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
||
| 1666 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1667 | /** |
||
| 1668 | * @} |
||
| 1669 | */ |
||
| 1670 | |||
| 1671 | /** @addtogroup TIM_Exported_Functions_Group5 |
||
| 1672 | * @{ |
||
| 1673 | */ |
||
| 1674 | /* Timer One Pulse functions ***************************************************/ |
||
| 1675 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
||
| 1676 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
||
| 1677 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
||
| 1678 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1679 | /* Blocking mode: Polling */ |
||
| 1680 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||
| 1681 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||
| 1682 | /* Non-Blocking mode: Interrupt */ |
||
| 1683 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||
| 1684 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||
| 1685 | /** |
||
| 1686 | * @} |
||
| 1687 | */ |
||
| 1688 | |||
| 1689 | /** @addtogroup TIM_Exported_Functions_Group6 |
||
| 1690 | * @{ |
||
| 1691 | */ |
||
| 1692 | /* Timer Encoder functions *****************************************************/ |
||
| 1693 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
||
| 1694 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
||
| 1695 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
||
| 1696 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
||
| 1697 | /* Blocking mode: Polling */ |
||
| 1698 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1699 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1700 | /* Non-Blocking mode: Interrupt */ |
||
| 1701 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1702 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1703 | /* Non-Blocking mode: DMA */ |
||
| 1704 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
||
| 1705 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1706 | |||
| 1707 | /** |
||
| 1708 | * @} |
||
| 1709 | */ |
||
| 1710 | |||
| 1711 | /** @addtogroup TIM_Exported_Functions_Group7 |
||
| 1712 | * @{ |
||
| 1713 | */ |
||
| 1714 | /* Interrupt Handler functions **********************************************/ |
||
| 1715 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
||
| 1716 | /** |
||
| 1717 | * @} |
||
| 1718 | */ |
||
| 1719 | |||
| 1720 | /** @addtogroup TIM_Exported_Functions_Group8 |
||
| 1721 | * @{ |
||
| 1722 | */ |
||
| 1723 | /* Control functions *********************************************************/ |
||
| 1724 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
||
| 1725 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
||
| 1726 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
||
| 1727 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
||
| 1728 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
||
| 1729 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
||
| 1730 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
||
| 1731 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
||
| 1732 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
||
| 1733 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
||
| 1734 | uint32_t *BurstBuffer, uint32_t BurstLength); |
||
| 1735 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
||
| 1736 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
||
| 1737 | uint32_t *BurstBuffer, uint32_t BurstLength); |
||
| 1738 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
||
| 1739 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
||
| 1740 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
||
| 1741 | |||
| 1742 | /** |
||
| 1743 | * @} |
||
| 1744 | */ |
||
| 1745 | |||
| 1746 | /** @addtogroup TIM_Exported_Functions_Group9 |
||
| 1747 | * @{ |
||
| 1748 | */ |
||
| 1749 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
||
| 1750 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
||
| 1751 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
||
| 1752 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
||
| 1753 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
||
| 1754 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
||
| 1755 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
||
| 1756 | /** |
||
| 1757 | * @} |
||
| 1758 | */ |
||
| 1759 | |||
| 1760 | /** @addtogroup TIM_Exported_Functions_Group10 |
||
| 1761 | * @{ |
||
| 1762 | */ |
||
| 1763 | /* Peripheral State functions **************************************************/ |
||
| 1764 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
||
| 1765 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
||
| 1766 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
||
| 1767 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
||
| 1768 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
||
| 1769 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
||
| 1770 | |||
| 1771 | /** |
||
| 1772 | * @} |
||
| 1773 | */ |
||
| 1774 | |||
| 1775 | /** |
||
| 1776 | * @} |
||
| 1777 | */ |
||
| 1778 | |||
| 1779 | /** |
||
| 1780 | * @} |
||
| 1781 | */ |
||
| 1782 | |||
| 1783 | /** |
||
| 1784 | * @} |
||
| 1785 | */ |
||
| 1786 | |||
| 1787 | #ifdef __cplusplus |
||
| 1788 | } |
||
| 1789 | #endif |
||
| 1790 | |||
| 1791 | #endif /* __STM32F1xx_HAL_TIM_H */ |
||
| 1792 | |||
| 1793 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |