WebSVN – EDIS_Ignition – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM HAL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef STM32F1xx_HAL_TIM_H
		22	#define STM32F1xx_HAL_TIM_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f1xx_hal_def.h"
		30
		31	/** @addtogroup STM32F1xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup TIM
		36	* @{
		37	*/
		38
		39	/* Exported types ------------------------------------------------------------*/
		40	/** @defgroup TIM_Exported_Types TIM Exported Types
		41	* @{
		42	*/
		43
		44	/**
		45	* @brief TIM Time base Configuration Structure definition
		46	*/
		47	typedef struct
		48	{
		49	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		50	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		51
		52	uint32_t CounterMode; /*!< Specifies the counter mode.
		53	This parameter can be a value of @ref TIM_Counter_Mode */
		54
		55	uint32_t Period; /*!< Specifies the period value to be loaded into the active
		56	Auto-Reload Register at the next update event.
		57	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
		58
		59	uint32_t ClockDivision; /*!< Specifies the clock division.
		60	This parameter can be a value of @ref TIM_ClockDivision */
		61
		62	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
		63	reaches zero, an update event is generated and counting restarts
		64	from the RCR value (N).
		65	This means in PWM mode that (N+1) corresponds to:
		66	- the number of PWM periods in edge-aligned mode
		67	- the number of half PWM period in center-aligned mode
		68	GP timers: this parameter must be a number between Min_Data = 0x00 and
		69	Max_Data = 0xFF.
		70	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
		71	Max_Data = 0xFFFF. */
		72
		73	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
		74	This parameter can be a value of @ref TIM_AutoReloadPreload */
		75	} TIM_Base_InitTypeDef;
		76
		77	/**
		78	* @brief TIM Output Compare Configuration Structure definition
		79	*/
		80	typedef struct
		81	{
		82	uint32_t OCMode; /*!< Specifies the TIM mode.
		83	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		84
		85	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		86	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		87
		88	uint32_t OCPolarity; /*!< Specifies the output polarity.
		89	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		90
		91	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		92	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
		93	@note This parameter is valid only for timer instances supporting break feature. */
		94
		95	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
		96	This parameter can be a value of @ref TIM_Output_Fast_State
		97	@note This parameter is valid only in PWM1 and PWM2 mode. */
		98
		99
		100	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		101	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
		102	@note This parameter is valid only for timer instances supporting break feature. */
		103
		104	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		105	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
		106	@note This parameter is valid only for timer instances supporting break feature. */
		107	} TIM_OC_InitTypeDef;
		108
		109	/**
		110	* @brief TIM One Pulse Mode Configuration Structure definition
		111	*/
		112	typedef struct
		113	{
		114	uint32_t OCMode; /*!< Specifies the TIM mode.
		115	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		116
		117	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		118	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		119
		120	uint32_t OCPolarity; /*!< Specifies the output polarity.
		121	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		122
		123	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		124	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
		125	@note This parameter is valid only for timer instances supporting break feature. */
		126
		127	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		128	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
		129	@note This parameter is valid only for timer instances supporting break feature. */
		130
		131	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		132	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
		133	@note This parameter is valid only for timer instances supporting break feature. */
		134
		135	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		136	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		137
		138	uint32_t ICSelection; /*!< Specifies the input.
		139	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		140
		141	uint32_t ICFilter; /*!< Specifies the input capture filter.
		142	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		143	} TIM_OnePulse_InitTypeDef;
		144
		145	/**
		146	* @brief TIM Input Capture Configuration Structure definition
		147	*/
		148	typedef struct
		149	{
		150	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		151	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		152
		153	uint32_t ICSelection; /*!< Specifies the input.
		154	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		155
		156	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		157	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		158
		159	uint32_t ICFilter; /*!< Specifies the input capture filter.
		160	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		161	} TIM_IC_InitTypeDef;
		162
		163	/**
		164	* @brief TIM Encoder Configuration Structure definition
		165	*/
		166	typedef struct
		167	{
		168	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
		169	This parameter can be a value of @ref TIM_Encoder_Mode */
		170
		171	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
		172	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
		173
		174	uint32_t IC1Selection; /*!< Specifies the input.
		175	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		176
		177	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
		178	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		179
		180	uint32_t IC1Filter; /*!< Specifies the input capture filter.
		181	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		182
		183	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
		184	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
		185
		186	uint32_t IC2Selection; /*!< Specifies the input.
		187	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		188
		189	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
		190	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		191
		192	uint32_t IC2Filter; /*!< Specifies the input capture filter.
		193	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		194	} TIM_Encoder_InitTypeDef;
		195
		196	/**
		197	* @brief Clock Configuration Handle Structure definition
		198	*/
		199	typedef struct
		200	{
		201	uint32_t ClockSource; /*!< TIM clock sources
		202	This parameter can be a value of @ref TIM_Clock_Source */
		203	uint32_t ClockPolarity; /*!< TIM clock polarity
		204	This parameter can be a value of @ref TIM_Clock_Polarity */
		205	uint32_t ClockPrescaler; /*!< TIM clock prescaler
		206	This parameter can be a value of @ref TIM_Clock_Prescaler */
		207	uint32_t ClockFilter; /*!< TIM clock filter
		208	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		209	} TIM_ClockConfigTypeDef;
		210
		211	/**
		212	* @brief TIM Clear Input Configuration Handle Structure definition
		213	*/
		214	typedef struct
		215	{
		216	uint32_t ClearInputState; /*!< TIM clear Input state
		217	This parameter can be ENABLE or DISABLE */
		218	uint32_t ClearInputSource; /*!< TIM clear Input sources
		219	This parameter can be a value of @ref TIM_ClearInput_Source */
		220	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
		221	This parameter can be a value of @ref TIM_ClearInput_Polarity */
		222	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
		223	This parameter must be 0: When OCRef clear feature is used with ETR source,
		224	ETR prescaler must be off */
		225	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
		226	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		227	} TIM_ClearInputConfigTypeDef;
		228
		229	/**
		230	* @brief TIM Master configuration Structure definition
		231	*/
		232	typedef struct
		233	{
		234	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
		235	This parameter can be a value of @ref TIM_Master_Mode_Selection */
		236	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
		237	This parameter can be a value of @ref TIM_Master_Slave_Mode
		238	@note When the Master/slave mode is enabled, the effect of
		239	an event on the trigger input (TRGI) is delayed to allow a
		240	perfect synchronization between the current timer and its
		241	slaves (through TRGO). It is not mandatory in case of timer
		242	synchronization mode. */
		243	} TIM_MasterConfigTypeDef;
		244
		245	/**
		246	* @brief TIM Slave configuration Structure definition
		247	*/
		248	typedef struct
		249	{
		250	uint32_t SlaveMode; /*!< Slave mode selection
		251	This parameter can be a value of @ref TIM_Slave_Mode */
		252	uint32_t InputTrigger; /*!< Input Trigger source
		253	This parameter can be a value of @ref TIM_Trigger_Selection */
		254	uint32_t TriggerPolarity; /*!< Input Trigger polarity
		255	This parameter can be a value of @ref TIM_Trigger_Polarity */
		256	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
		257	This parameter can be a value of @ref TIM_Trigger_Prescaler */
		258	uint32_t TriggerFilter; /*!< Input trigger filter
		259	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		260
		261	} TIM_SlaveConfigTypeDef;
		262
		263	/**
		264	* @brief TIM Break input(s) and Dead time configuration Structure definition
		265	* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
		266	* filter and polarity.
		267	*/
		268	typedef struct
		269	{
		270	uint32_t OffStateRunMode; /!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state /
		271
		272	uint32_t OffStateIDLEMode; /!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state /
		273
		274	uint32_t LockLevel; /!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level /
		275
		276	uint32_t DeadTime; /!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF /
		277
		278	uint32_t BreakState; /!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable /
		279
		280	uint32_t BreakPolarity; /!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity /
		281
		282	uint32_t BreakFilter; /!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF /
		283
		284	uint32_t AutomaticOutput; /!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset /
		285
		286	} TIM_BreakDeadTimeConfigTypeDef;
		287
		288	/**
		289	* @brief HAL State structures definition
		290	*/
		291	typedef enum
		292	{
		293	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
		294	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
		295	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
		296	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
		297	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
		298	} HAL_TIM_StateTypeDef;
		299
		300	/**
		301	* @brief TIM Channel States definition
		302	*/
		303	typedef enum
		304	{
		305	HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /!< TIM Channel initial state /
		306	HAL_TIM_CHANNEL_STATE_READY = 0x01U, /!< TIM Channel ready for use /
		307	HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /!< An internal process is ongoing on the TIM channel /
		308	} HAL_TIM_ChannelStateTypeDef;
		309
		310	/**
		311	* @brief DMA Burst States definition
		312	*/
		313	typedef enum
		314	{
		315	HAL_DMA_BURST_STATE_RESET = 0x00U, /!< DMA Burst initial state /
		316	HAL_DMA_BURST_STATE_READY = 0x01U, /!< DMA Burst ready for use /
		317	HAL_DMA_BURST_STATE_BUSY = 0x02U, /!< Ongoing DMA Burst /
		318	} HAL_TIM_DMABurstStateTypeDef;
		319
		320	/**
		321	* @brief HAL Active channel structures definition
		322	*/
		323	typedef enum
		324	{
		325	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
		326	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
		327	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
		328	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
		329	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
		330	} HAL_TIM_ActiveChannel;
		331
		332	/**
		333	* @brief TIM Time Base Handle Structure definition
		334	*/
		335	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		336	typedef struct __TIM_HandleTypeDef
		337	#else
		338	typedef struct
		339	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		340	{
		341	TIM_TypeDef Instance; /!< Register base address */
		342	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
		343	HAL_TIM_ActiveChannel Channel; /!< Active channel /
		344	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
		345	This array is accessed by a @ref DMA_Handle_index */
		346	HAL_LockTypeDef Lock; /!< Locking object /
		347	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
		348	__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /!< TIM channel operation state /
		349	__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /!< TIM complementary channel operation state /
		350	__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /!< DMA burst operation state /
		351
		352	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		353	void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp Init Callback */
		354	void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp DeInit Callback */
		355	void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp Init Callback */
		356	void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp DeInit Callback */
		357	void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp Init Callback */
		358	void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp DeInit Callback */
		359	void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp Init Callback */
		360	void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp DeInit Callback */
		361	void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp Init Callback */
		362	void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp DeInit Callback */
		363	void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp Init Callback */
		364	void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp DeInit Callback */
		365	void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp Init Callback */
		366	void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp DeInit Callback */
		367	void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed Callback */
		368	void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed half complete Callback */
		369	void (* TriggerCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger Callback */
		370	void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger half complete Callback */
		371	void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture Callback */
		372	void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture half complete Callback */
		373	void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Output Compare Delay Elapsed Callback */
		374	void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished Callback */
		375	void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished half complete Callback */
		376	void (* ErrorCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Error Callback */
		377	void (* CommutationCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation Callback */
		378	void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation half complete Callback */
		379	void (* BreakCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Break Callback */
		380	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		381	} TIM_HandleTypeDef;
		382
		383	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		384	/**
		385	* @brief HAL TIM Callback ID enumeration definition
		386	*/
		387	typedef enum
		388	{
		389	HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /!< TIM Base MspInit Callback ID /
		390	, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /!< TIM Base MspDeInit Callback ID /
		391	, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /!< TIM IC MspInit Callback ID /
		392	, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /!< TIM IC MspDeInit Callback ID /
		393	, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /!< TIM OC MspInit Callback ID /
		394	, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /!< TIM OC MspDeInit Callback ID /
		395	, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /!< TIM PWM MspInit Callback ID /
		396	, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /!< TIM PWM MspDeInit Callback ID /
		397	, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /!< TIM One Pulse MspInit Callback ID /
		398	, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /!< TIM One Pulse MspDeInit Callback ID /
		399	, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /!< TIM Encoder MspInit Callback ID /
		400	, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /!< TIM Encoder MspDeInit Callback ID /
		401	, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /!< TIM Hall Sensor MspDeInit Callback ID /
		402	, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /!< TIM Hall Sensor MspDeInit Callback ID /
		403	, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /!< TIM Period Elapsed Callback ID /
		404	, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /!< TIM Period Elapsed half complete Callback ID /
		405	, HAL_TIM_TRIGGER_CB_ID = 0x10U /!< TIM Trigger Callback ID /
		406	, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /!< TIM Trigger half complete Callback ID /
		407
		408	, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /!< TIM Input Capture Callback ID /
		409	, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /!< TIM Input Capture half complete Callback ID /
		410	, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /!< TIM Output Compare Delay Elapsed Callback ID /
		411	, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /!< TIM PWM Pulse Finished Callback ID /
		412	, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /!< TIM PWM Pulse Finished half complete Callback ID /
		413	, HAL_TIM_ERROR_CB_ID = 0x17U /!< TIM Error Callback ID /
		414	, HAL_TIM_COMMUTATION_CB_ID = 0x18U /!< TIM Commutation Callback ID /
		415	, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /!< TIM Commutation half complete Callback ID /
		416	, HAL_TIM_BREAK_CB_ID = 0x1AU /!< TIM Break Callback ID /
		417	} HAL_TIM_CallbackIDTypeDef;
		418
		419	/**
		420	* @brief HAL TIM Callback pointer definition
		421	*/
		422	typedef void (pTIM_CallbackTypeDef)(TIM_HandleTypeDef htim); /!< pointer to the TIM callback function /
		423
		424	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		425
		426	/**
		427	* @}
		428	*/
		429	/* End of exported types -----------------------------------------------------*/
		430
		431	/* Exported constants --------------------------------------------------------*/
		432	/** @defgroup TIM_Exported_Constants TIM Exported Constants
		433	* @{
		434	*/
		435
		436	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
		437	* @{
		438	*/
		439	#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /!< OCREF_CLR is disabled /
		440	#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /!< OCREF_CLR is connected to ETRF input /
		441	/**
		442	* @}
		443	*/
		444
		445	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
		446	* @{
		447	*/
		448	#define TIM_DMABASE_CR1 0x00000000U
		449	#define TIM_DMABASE_CR2 0x00000001U
		450	#define TIM_DMABASE_SMCR 0x00000002U
		451	#define TIM_DMABASE_DIER 0x00000003U
		452	#define TIM_DMABASE_SR 0x00000004U
		453	#define TIM_DMABASE_EGR 0x00000005U
		454	#define TIM_DMABASE_CCMR1 0x00000006U
		455	#define TIM_DMABASE_CCMR2 0x00000007U
		456	#define TIM_DMABASE_CCER 0x00000008U
		457	#define TIM_DMABASE_CNT 0x00000009U
		458	#define TIM_DMABASE_PSC 0x0000000AU
		459	#define TIM_DMABASE_ARR 0x0000000BU
		460	#define TIM_DMABASE_RCR 0x0000000CU
		461	#define TIM_DMABASE_CCR1 0x0000000DU
		462	#define TIM_DMABASE_CCR2 0x0000000EU
		463	#define TIM_DMABASE_CCR3 0x0000000FU
		464	#define TIM_DMABASE_CCR4 0x00000010U
		465	#define TIM_DMABASE_BDTR 0x00000011U
		466	#define TIM_DMABASE_DCR 0x00000012U
		467	#define TIM_DMABASE_DMAR 0x00000013U
		468	/**
		469	* @}
		470	*/
		471
		472	/** @defgroup TIM_Event_Source TIM Event Source
		473	* @{
		474	*/
		475	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
		476	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
		477	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
		478	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
		479	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
		480	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /!< A commutation event is generated /
		481	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
		482	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /!< A break event is generated /
		483	/**
		484	* @}
		485	*/
		486
		487	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
		488	* @{
		489	*/
		490	#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /!< Polarity for TIx source /
		491	#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /!< Polarity for TIx source /
		492	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
		493	/**
		494	* @}
		495	*/
		496
		497	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
		498	* @{
		499	*/
		500	#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /!< Polarity for ETR source /
		501	#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /!< Polarity for ETR source /
		502	/**
		503	* @}
		504	*/
		505
		506	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
		507	* @{
		508	*/
		509	#define TIM_ETRPRESCALER_DIV1 0x00000000U /!< No prescaler is used /
		510	#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR input source is divided by 2 /
		511	#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR input source is divided by 4 /
		512	#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR input source is divided by 8 /
		513	/**
		514	* @}
		515	*/
		516
		517	/** @defgroup TIM_Counter_Mode TIM Counter Mode
		518	* @{
		519	*/
		520	#define TIM_COUNTERMODE_UP 0x00000000U /!< Counter used as up-counter /
		521	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as down-counter /
		522	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /!< Center-aligned mode 1 /
		523	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /!< Center-aligned mode 2 /
		524	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /!< Center-aligned mode 3 /
		525	/**
		526	* @}
		527	*/
		528
		529	/** @defgroup TIM_ClockDivision TIM Clock Division
		530	* @{
		531	*/
		532	#define TIM_CLOCKDIVISION_DIV1 0x00000000U /!< Clock division: tDTS=tCK_INT /
		533	#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< Clock division: tDTS=2tCK_INT */
		534	#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< Clock division: tDTS=4tCK_INT */
		535	/**
		536	* @}
		537	*/
		538
		539	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
		540	* @{
		541	*/
		542	#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /!< Capture/Compare 1 output disabled /
		543	#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /!< Capture/Compare 1 output enabled /
		544	/**
		545	* @}
		546	*/
		547
		548	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
		549	* @{
		550	*/
		551	#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /!< TIMx_ARR register is not buffered /
		552	#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /!< TIMx_ARR register is buffered /
		553
		554	/**
		555	* @}
		556	*/
		557
		558	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
		559	* @{
		560	*/
		561	#define TIM_OCFAST_DISABLE 0x00000000U /!< Output Compare fast disable /
		562	#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /!< Output Compare fast enable /
		563	/**
		564	* @}
		565	*/
		566
		567	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
		568	* @{
		569	*/
		570	#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /!< OCxN is disabled /
		571	#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /!< OCxN is enabled /
		572	/**
		573	* @}
		574	*/
		575
		576	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
		577	* @{
		578	*/
		579	#define TIM_OCPOLARITY_HIGH 0x00000000U /!< Capture/Compare output polarity /
		580	#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< Capture/Compare output polarity /
		581	/**
		582	* @}
		583	*/
		584
		585	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
		586	* @{
		587	*/
		588	#define TIM_OCNPOLARITY_HIGH 0x00000000U /!< Capture/Compare complementary output polarity /
		589	#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /!< Capture/Compare complementary output polarity /
		590	/**
		591	* @}
		592	*/
		593
		594	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
		595	* @{
		596	*/
		597	#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /!< Output Idle state: OCx=1 when MOE=0 /
		598	#define TIM_OCIDLESTATE_RESET 0x00000000U /!< Output Idle state: OCx=0 when MOE=0 /
		599	/**
		600	* @}
		601	*/
		602
		603	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
		604	* @{
		605	*/
		606	#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /!< Complementary output Idle state: OCxN=1 when MOE=0 /
		607	#define TIM_OCNIDLESTATE_RESET 0x00000000U /!< Complementary output Idle state: OCxN=0 when MOE=0 /
		608	/**
		609	* @}
		610	*/
		611
		612	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
		613	* @{
		614	*/
		615	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Capture triggered by rising edge on timer input /
		616	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Capture triggered by falling edge on timer input /
		617	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Capture triggered by both rising and falling edges on timer input/
		618	/**
		619	* @}
		620	*/
		621
		622	/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
		623	* @{
		624	*/
		625	#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Encoder input with rising edge polarity /
		626	#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Encoder input with falling edge polarity /
		627	/**
		628	* @}
		629	*/
		630
		631	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
		632	* @{
		633	*/
		634	#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively /
		635	#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively /
		636	#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
		637	/**
		638	* @}
		639	*/
		640
		641	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
		642	* @{
		643	*/
		644	#define TIM_ICPSC_DIV1 0x00000000U /!< Capture performed each time an edge is detected on the capture input /
		645	#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /!< Capture performed once every 2 events /
		646	#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /!< Capture performed once every 4 events /
		647	#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /!< Capture performed once every 8 events /
		648	/**
		649	* @}
		650	*/
		651
		652	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
		653	* @{
		654	*/
		655	#define TIM_OPMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
		656	#define TIM_OPMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
		657	/**
		658	* @}
		659	*/
		660
		661	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
		662	* @{
		663	*/
		664	#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level /
		665	#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. /
		666	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. /
		667	/**
		668	* @}
		669	*/
		670
		671	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
		672	* @{
		673	*/
		674	#define TIM_IT_UPDATE TIM_DIER_UIE /!< Update interrupt /
		675	#define TIM_IT_CC1 TIM_DIER_CC1IE /!< Capture/Compare 1 interrupt /
		676	#define TIM_IT_CC2 TIM_DIER_CC2IE /!< Capture/Compare 2 interrupt /
		677	#define TIM_IT_CC3 TIM_DIER_CC3IE /!< Capture/Compare 3 interrupt /
		678	#define TIM_IT_CC4 TIM_DIER_CC4IE /!< Capture/Compare 4 interrupt /
		679	#define TIM_IT_COM TIM_DIER_COMIE /!< Commutation interrupt /
		680	#define TIM_IT_TRIGGER TIM_DIER_TIE /!< Trigger interrupt /
		681	#define TIM_IT_BREAK TIM_DIER_BIE /!< Break interrupt /
		682	/**
		683	* @}
		684	*/
		685
		686	/** @defgroup TIM_Commutation_Source TIM Commutation Source
		687	* @{
		688	*/
		689	#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input /
		690	#define TIM_COMMUTATION_SOFTWARE 0x00000000U /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit /
		691	/**
		692	* @}
		693	*/
		694
		695	/** @defgroup TIM_DMA_sources TIM DMA Sources
		696	* @{
		697	*/
		698	#define TIM_DMA_UPDATE TIM_DIER_UDE /!< DMA request is triggered by the update event /
		699	#define TIM_DMA_CC1 TIM_DIER_CC1DE /!< DMA request is triggered by the capture/compare macth 1 event /
		700	#define TIM_DMA_CC2 TIM_DIER_CC2DE /!< DMA request is triggered by the capture/compare macth 2 event event /
		701	#define TIM_DMA_CC3 TIM_DIER_CC3DE /!< DMA request is triggered by the capture/compare macth 3 event event /
		702	#define TIM_DMA_CC4 TIM_DIER_CC4DE /!< DMA request is triggered by the capture/compare macth 4 event event /
		703	#define TIM_DMA_COM TIM_DIER_COMDE /!< DMA request is triggered by the commutation event /
		704	#define TIM_DMA_TRIGGER TIM_DIER_TDE /!< DMA request is triggered by the trigger event /
		705	/**
		706	* @}
		707	*/
		708
		709	/** @defgroup TIM_Flag_definition TIM Flag Definition
		710	* @{
		711	*/
		712	#define TIM_FLAG_UPDATE TIM_SR_UIF /!< Update interrupt flag /
		713	#define TIM_FLAG_CC1 TIM_SR_CC1IF /!< Capture/Compare 1 interrupt flag /
		714	#define TIM_FLAG_CC2 TIM_SR_CC2IF /!< Capture/Compare 2 interrupt flag /
		715	#define TIM_FLAG_CC3 TIM_SR_CC3IF /!< Capture/Compare 3 interrupt flag /
		716	#define TIM_FLAG_CC4 TIM_SR_CC4IF /!< Capture/Compare 4 interrupt flag /
		717	#define TIM_FLAG_COM TIM_SR_COMIF /!< Commutation interrupt flag /
		718	#define TIM_FLAG_TRIGGER TIM_SR_TIF /!< Trigger interrupt flag /
		719	#define TIM_FLAG_BREAK TIM_SR_BIF /!< Break interrupt flag /
		720	#define TIM_FLAG_CC1OF TIM_SR_CC1OF /!< Capture 1 overcapture flag /
		721	#define TIM_FLAG_CC2OF TIM_SR_CC2OF /!< Capture 2 overcapture flag /
		722	#define TIM_FLAG_CC3OF TIM_SR_CC3OF /!< Capture 3 overcapture flag /
		723	#define TIM_FLAG_CC4OF TIM_SR_CC4OF /!< Capture 4 overcapture flag /
		724	/**
		725	* @}
		726	*/
		727
		728	/** @defgroup TIM_Channel TIM Channel
		729	* @{
		730	*/
		731	#define TIM_CHANNEL_1 0x00000000U /!< Capture/compare channel 1 identifier /
		732	#define TIM_CHANNEL_2 0x00000004U /!< Capture/compare channel 2 identifier /
		733	#define TIM_CHANNEL_3 0x00000008U /!< Capture/compare channel 3 identifier /
		734	#define TIM_CHANNEL_4 0x0000000CU /!< Capture/compare channel 4 identifier /
		735	#define TIM_CHANNEL_ALL 0x0000003CU /!< Global Capture/compare channel identifier /
		736	/**
		737	* @}
		738	*/
		739
		740	/** @defgroup TIM_Clock_Source TIM Clock Source
		741	* @{
		742	*/
		743	#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /!< External clock source mode 2 /
		744	#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /!< Internal clock source /
		745	#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /!< External clock source mode 1 (ITR0) /
		746	#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /!< External clock source mode 1 (ITR1) /
		747	#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /!< External clock source mode 1 (ITR2) /
		748	#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /!< External clock source mode 1 (ITR3) /
		749	#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /!< External clock source mode 1 (TTI1FP1 + edge detect.) /
		750	#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /!< External clock source mode 1 (TTI1FP1) /
		751	#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /!< External clock source mode 1 (TTI2FP2) /
		752	#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /!< External clock source mode 1 (ETRF) /
		753	/**
		754	* @}
		755	*/
		756
		757	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
		758	* @{
		759	*/
		760	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
		761	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
		762	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
		763	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
		764	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
		765	/**
		766	* @}
		767	*/
		768
		769	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
		770	* @{
		771	*/
		772	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		773	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
		774	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
		775	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
		776	/**
		777	* @}
		778	*/
		779
		780	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
		781	* @{
		782	*/
		783	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
		784	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
		785	/**
		786	* @}
		787	*/
		788
		789	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
		790	* @{
		791	*/
		792	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		793	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
		794	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
		795	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
		796	/**
		797	* @}
		798	*/
		799
		800	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
		801	* @{
		802	*/
		803	#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
		804	#define TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
		805	/**
		806	* @}
		807	*/
		808
		809	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
		810	* @{
		811	*/
		812	#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
		813	#define TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
		814	/**
		815	* @}
		816	*/
		817	/** @defgroup TIM_Lock_level TIM Lock level
		818	* @{
		819	*/
		820	#define TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF /
		821	#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
		822	#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
		823	#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
		824	/**
		825	* @}
		826	*/
		827
		828	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
		829	* @{
		830	*/
		831	#define TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break input BRK is enabled /
		832	#define TIM_BREAK_DISABLE 0x00000000U /!< Break input BRK is disabled /
		833	/**
		834	* @}
		835	*/
		836
		837	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
		838	* @{
		839	*/
		840	#define TIM_BREAKPOLARITY_LOW 0x00000000U /!< Break input BRK is active low /
		841	#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
		842	/**
		843	* @}
		844	*/
		845
		846	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
		847	* @{
		848	*/
		849	#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
		850	#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) /
		851	/**
		852	* @}
		853	*/
		854
		855	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
		856	* @{
		857	*/
		858	#define TIM_TRGO_RESET 0x00000000U /!< TIMx_EGR.UG bit is used as trigger output (TRGO) /
		859	#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< TIMx_CR1.CEN bit is used as trigger output (TRGO) /
		860	#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output (TRGO) /
		861	#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< Capture or a compare match 1 is used as trigger output (TRGO) /
		862	#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output (TRGO) /
		863	#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output(TRGO) /
		864	#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output(TRGO) /
		865	#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output(TRGO) /
		866	/**
		867	* @}
		868	*/
		869
		870	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
		871	* @{
		872	*/
		873	#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /!< No action /
		874	#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /!< Master/slave mode is selected /
		875	/**
		876	* @}
		877	*/
		878
		879	/** @defgroup TIM_Slave_Mode TIM Slave mode
		880	* @{
		881	*/
		882	#define TIM_SLAVEMODE_DISABLE 0x00000000U /!< Slave mode disabled /
		883	#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode /
		884	#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode /
		885	#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode /
		886	#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< External Clock Mode 1 /
		887	/**
		888	* @}
		889	*/
		890
		891	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
		892	* @{
		893	*/
		894	#define TIM_OCMODE_TIMING 0x00000000U /!< Frozen /
		895	#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!< Set channel to active level on match /
		896	#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!< Set channel to inactive level on match /
		897	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< Toggle /
		898	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!< PWM mode 1 /
		899	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< PWM mode 2 /
		900	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!< Force active level /
		901	#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!< Force inactive level /
		902	/**
		903	* @}
		904	*/
		905
		906	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
		907	* @{
		908	*/
		909	#define TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) /
		910	#define TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) /
		911	#define TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) /
		912	#define TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) /
		913	#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) /
		914	#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 1 (TI1FP1) /
		915	#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 2 (TI2FP2) /
		916	#define TIM_TS_ETRF (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered External Trigger input (ETRF) /
		917	#define TIM_TS_NONE 0x0000FFFFU /!< No trigger selected /
		918	/**
		919	* @}
		920	*/
		921
		922	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
		923	* @{
		924	*/
		925	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
		926	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
		927	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		928	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		929	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
		930	/**
		931	* @}
		932	*/
		933
		934	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
		935	* @{
		936	*/
		937	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		938	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
		939	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
		940	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
		941	/**
		942	* @}
		943	*/
		944
		945	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
		946	* @{
		947	*/
		948	#define TIM_TI1SELECTION_CH1 0x00000000U /!< The TIMx_CH1 pin is connected to TI1 input /
		949	#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) /
		950	/**
		951	* @}
		952	*/
		953
		954	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
		955	* @{
		956	*/
		957	#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA /
		958	#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		959	#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		960	#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		961	#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		962	#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		963	#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		964	#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		965	#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		966	#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		967	#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		968	#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		969	#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		970	#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		971	#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		972	#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		973	#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		974	#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		975	/**
		976	* @}
		977	*/
		978
		979	/** @defgroup DMA_Handle_index TIM DMA Handle Index
		980	* @{
		981	*/
		982	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /!< Index of the DMA handle used for Update DMA requests /
		983	#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
		984	#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
		985	#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
		986	#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
		987	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /!< Index of the DMA handle used for Commutation DMA requests /
		988	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /!< Index of the DMA handle used for Trigger DMA requests /
		989	/**
		990	* @}
		991	*/
		992
		993	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
		994	* @{
		995	*/
		996	#define TIM_CCx_ENABLE 0x00000001U /!< Input or output channel is enabled /
		997	#define TIM_CCx_DISABLE 0x00000000U /!< Input or output channel is disabled /
		998	#define TIM_CCxN_ENABLE 0x00000004U /!< Complementary output channel is enabled /
		999	#define TIM_CCxN_DISABLE 0x00000000U /!< Complementary output channel is enabled /
		1000	/**
		1001	* @}
		1002	*/
		1003
		1004	/**
		1005	* @}
		1006	*/
		1007	/* End of exported constants -------------------------------------------------*/
		1008
		1009	/* Exported macros -----------------------------------------------------------*/
		1010	/** @defgroup TIM_Exported_Macros TIM Exported Macros
		1011	* @{
		1012	*/
		1013
		1014	/** @brief Reset TIM handle state.
		1015	* @param __HANDLE__ TIM handle.
		1016	* @retval None
		1017	*/
		1018	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1019	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
		1020	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
		1021	(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		1022	(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		1023	(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		1024	(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		1025	(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		1026	(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		1027	(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		1028	(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		1029	(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
		1030	(__HANDLE__)->Base_MspInitCallback = NULL; \
		1031	(__HANDLE__)->Base_MspDeInitCallback = NULL; \
		1032	(__HANDLE__)->IC_MspInitCallback = NULL; \
		1033	(__HANDLE__)->IC_MspDeInitCallback = NULL; \
		1034	(__HANDLE__)->OC_MspInitCallback = NULL; \
		1035	(__HANDLE__)->OC_MspDeInitCallback = NULL; \
		1036	(__HANDLE__)->PWM_MspInitCallback = NULL; \
		1037	(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
		1038	(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
		1039	(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
		1040	(__HANDLE__)->Encoder_MspInitCallback = NULL; \
		1041	(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
		1042	(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
		1043	(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
		1044	} while(0)
		1045	#else
		1046	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
		1047	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
		1048	(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		1049	(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		1050	(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		1051	(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		1052	(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		1053	(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		1054	(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		1055	(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		1056	(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
		1057	} while(0)
		1058	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1059
		1060	/**
		1061	* @brief Enable the TIM peripheral.
		1062	* @param __HANDLE__ TIM handle
		1063	* @retval None
		1064	*/
		1065	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
		1066
		1067	/**
		1068	* @brief Enable the TIM main Output.
		1069	* @param __HANDLE__ TIM handle
		1070	* @retval None
		1071	*/
		1072	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
		1073
		1074	/**
		1075	* @brief Disable the TIM peripheral.
		1076	* @param __HANDLE__ TIM handle
		1077	* @retval None
		1078	*/
		1079	#define __HAL_TIM_DISABLE(__HANDLE__) \
		1080	do { \
		1081	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
		1082	{ \
		1083	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
		1084	{ \
		1085	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
		1086	} \
		1087	} \
		1088	} while(0)
		1089
		1090	/**
		1091	* @brief Disable the TIM main Output.
		1092	* @param __HANDLE__ TIM handle
		1093	* @retval None
		1094	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
		1095	* disabled
		1096	*/
		1097	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
		1098	do { \
		1099	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
		1100	{ \
		1101	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
		1102	{ \
		1103	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
		1104	} \
		1105	} \
		1106	} while(0)
		1107
		1108	/**
		1109	* @brief Disable the TIM main Output.
		1110	* @param __HANDLE__ TIM handle
		1111	* @retval None
		1112	* @note The Main Output Enable of a timer instance is disabled unconditionally
		1113	*/
		1114	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
		1115
		1116	/** @brief Enable the specified TIM interrupt.
		1117	* @param __HANDLE__ specifies the TIM Handle.
		1118	* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
		1119	* This parameter can be one of the following values:
		1120	* @arg TIM_IT_UPDATE: Update interrupt
		1121	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1122	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1123	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1124	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1125	* @arg TIM_IT_COM: Commutation interrupt
		1126	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1127	* @arg TIM_IT_BREAK: Break interrupt
		1128	* @retval None
		1129	*/
		1130	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
		1131
		1132	/** @brief Disable the specified TIM interrupt.
		1133	* @param __HANDLE__ specifies the TIM Handle.
		1134	* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
		1135	* This parameter can be one of the following values:
		1136	* @arg TIM_IT_UPDATE: Update interrupt
		1137	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1138	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1139	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1140	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1141	* @arg TIM_IT_COM: Commutation interrupt
		1142	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1143	* @arg TIM_IT_BREAK: Break interrupt
		1144	* @retval None
		1145	*/
		1146	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
		1147
		1148	/** @brief Enable the specified DMA request.
		1149	* @param __HANDLE__ specifies the TIM Handle.
		1150	* @param __DMA__ specifies the TIM DMA request to enable.
		1151	* This parameter can be one of the following values:
		1152	* @arg TIM_DMA_UPDATE: Update DMA request
		1153	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
		1154	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		1155	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		1156	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
		1157	* @arg TIM_DMA_COM: Commutation DMA request
		1158	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		1159	* @retval None
		1160	*/
		1161	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
		1162
		1163	/** @brief Disable the specified DMA request.
		1164	* @param __HANDLE__ specifies the TIM Handle.
		1165	* @param __DMA__ specifies the TIM DMA request to disable.
		1166	* This parameter can be one of the following values:
		1167	* @arg TIM_DMA_UPDATE: Update DMA request
		1168	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
		1169	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		1170	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		1171	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
		1172	* @arg TIM_DMA_COM: Commutation DMA request
		1173	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		1174	* @retval None
		1175	*/
		1176	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
		1177
		1178	/** @brief Check whether the specified TIM interrupt flag is set or not.
		1179	* @param __HANDLE__ specifies the TIM Handle.
		1180	* @param __FLAG__ specifies the TIM interrupt flag to check.
		1181	* This parameter can be one of the following values:
		1182	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		1183	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		1184	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		1185	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		1186	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		1187	* @arg TIM_FLAG_COM: Commutation interrupt flag
		1188	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
		1189	* @arg TIM_FLAG_BREAK: Break interrupt flag
		1190	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		1191	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		1192	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		1193	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		1194	* @retval The new state of __FLAG__ (TRUE or FALSE).
		1195	*/
		1196	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
		1197
		1198	/** @brief Clear the specified TIM interrupt flag.
		1199	* @param __HANDLE__ specifies the TIM Handle.
		1200	* @param __FLAG__ specifies the TIM interrupt flag to clear.
		1201	* This parameter can be one of the following values:
		1202	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		1203	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		1204	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		1205	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		1206	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		1207	* @arg TIM_FLAG_COM: Commutation interrupt flag
		1208	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
		1209	* @arg TIM_FLAG_BREAK: Break interrupt flag
		1210	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		1211	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		1212	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		1213	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		1214	* @retval The new state of __FLAG__ (TRUE or FALSE).
		1215	*/
		1216	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
		1217
		1218	/**
		1219	* @brief Check whether the specified TIM interrupt source is enabled or not.
		1220	* @param __HANDLE__ TIM handle
		1221	* @param __INTERRUPT__ specifies the TIM interrupt source to check.
		1222	* This parameter can be one of the following values:
		1223	* @arg TIM_IT_UPDATE: Update interrupt
		1224	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1225	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1226	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1227	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1228	* @arg TIM_IT_COM: Commutation interrupt
		1229	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1230	* @arg TIM_IT_BREAK: Break interrupt
		1231	* @retval The state of TIM_IT (SET or RESET).
		1232	*/
		1233	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
		1234	== (__INTERRUPT__)) ? SET : RESET)
		1235
		1236	/** @brief Clear the TIM interrupt pending bits.
		1237	* @param __HANDLE__ TIM handle
		1238	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
		1239	* This parameter can be one of the following values:
		1240	* @arg TIM_IT_UPDATE: Update interrupt
		1241	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1242	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1243	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1244	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1245	* @arg TIM_IT_COM: Commutation interrupt
		1246	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1247	* @arg TIM_IT_BREAK: Break interrupt
		1248	* @retval None
		1249	*/
		1250	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
		1251
		1252	/**
		1253	* @brief Indicates whether or not the TIM Counter is used as downcounter.
		1254	* @param __HANDLE__ TIM handle.
		1255	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
		1256	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
		1257	* or Encoder mode.
		1258	*/
		1259	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
		1260
		1261	/**
		1262	* @brief Set the TIM Prescaler on runtime.
		1263	* @param __HANDLE__ TIM handle.
		1264	* @param __PRESC__ specifies the Prescaler new value.
		1265	* @retval None
		1266	*/
		1267	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
		1268
		1269	/**
		1270	* @brief Set the TIM Counter Register value on runtime.
		1271	* @param __HANDLE__ TIM handle.
		1272	* @param __COUNTER__ specifies the Counter register new value.
		1273	* @retval None
		1274	*/
		1275	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
		1276
		1277	/**
		1278	* @brief Get the TIM Counter Register value on runtime.
		1279	* @param __HANDLE__ TIM handle.
		1280	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
		1281	*/
		1282	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
		1283
		1284	/**
		1285	* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
		1286	* @param __HANDLE__ TIM handle.
		1287	* @param __AUTORELOAD__ specifies the Counter register new value.
		1288	* @retval None
		1289	*/
		1290	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
		1291	do{ \
		1292	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
		1293	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
		1294	} while(0)
		1295
		1296	/**
		1297	* @brief Get the TIM Autoreload Register value on runtime.
		1298	* @param __HANDLE__ TIM handle.
		1299	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
		1300	*/
		1301	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
		1302
		1303	/**
		1304	* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
		1305	* @param __HANDLE__ TIM handle.
		1306	* @param __CKD__ specifies the clock division value.
		1307	* This parameter can be one of the following value:
		1308	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1309	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
		1310	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
		1311	* @retval None
		1312	*/
		1313	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
		1314	do{ \
		1315	(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
		1316	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
		1317	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
		1318	} while(0)
		1319
		1320	/**
		1321	* @brief Get the TIM Clock Division value on runtime.
		1322	* @param __HANDLE__ TIM handle.
		1323	* @retval The clock division can be one of the following values:
		1324	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1325	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
		1326	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
		1327	*/
		1328	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
		1329
		1330	/**
		1331	* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
		1332	* function.
		1333	* @param __HANDLE__ TIM handle.
		1334	* @param __CHANNEL__ TIM Channels to be configured.
		1335	* This parameter can be one of the following values:
		1336	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1337	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1338	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1339	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1340	* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
		1341	* This parameter can be one of the following values:
		1342	* @arg TIM_ICPSC_DIV1: no prescaler
		1343	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1344	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1345	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
		1346	* @retval None
		1347	*/
		1348	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
		1349	do{ \
		1350	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
		1351	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
		1352	} while(0)
		1353
		1354	/**
		1355	* @brief Get the TIM Input Capture prescaler on runtime.
		1356	* @param __HANDLE__ TIM handle.
		1357	* @param __CHANNEL__ TIM Channels to be configured.
		1358	* This parameter can be one of the following values:
		1359	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
		1360	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
		1361	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
		1362	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
		1363	* @retval The input capture prescaler can be one of the following values:
		1364	* @arg TIM_ICPSC_DIV1: no prescaler
		1365	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1366	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1367	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
		1368	*/
		1369	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
		1370	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
		1371	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
		1372	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
		1373	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
		1374
		1375	/**
		1376	* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
		1377	* @param __HANDLE__ TIM handle.
		1378	* @param __CHANNEL__ TIM Channels to be configured.
		1379	* This parameter can be one of the following values:
		1380	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1381	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1382	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1383	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1384	* @param __COMPARE__ specifies the Capture Compare register new value.
		1385	* @retval None
		1386	*/
		1387	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
		1388	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
		1389	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
		1390	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
		1391	((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
		1392
		1393	/**
		1394	* @brief Get the TIM Capture Compare Register value on runtime.
		1395	* @param __HANDLE__ TIM handle.
		1396	* @param __CHANNEL__ TIM Channel associated with the capture compare register
		1397	* This parameter can be one of the following values:
		1398	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
		1399	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
		1400	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
		1401	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
		1402	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
		1403	*/
		1404	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
		1405	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
		1406	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
		1407	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
		1408	((__HANDLE__)->Instance->CCR4))
		1409
		1410	/**
		1411	* @brief Set the TIM Output compare preload.
		1412	* @param __HANDLE__ TIM handle.
		1413	* @param __CHANNEL__ TIM Channels to be configured.
		1414	* This parameter can be one of the following values:
		1415	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1416	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1417	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1418	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1419	* @retval None
		1420	*/
		1421	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1422	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
		1423	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
		1424	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
		1425	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE))
		1426
		1427	/**
		1428	* @brief Reset the TIM Output compare preload.
		1429	* @param __HANDLE__ TIM handle.
		1430	* @param __CHANNEL__ TIM Channels to be configured.
		1431	* This parameter can be one of the following values:
		1432	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1433	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1434	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1435	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1436	* @retval None
		1437	*/
		1438	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1439	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
		1440	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
		1441	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
		1442	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
		1443
		1444	/**
		1445	* @brief Enable fast mode for a given channel.
		1446	* @param __HANDLE__ TIM handle.
		1447	* @param __CHANNEL__ TIM Channels to be configured.
		1448	* This parameter can be one of the following values:
		1449	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1450	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1451	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1452	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1453	* @note When fast mode is enabled an active edge on the trigger input acts
		1454	* like a compare match on CCx output. Delay to sample the trigger
		1455	* input and to activate CCx output is reduced to 3 clock cycles.
		1456	* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
		1457	* @retval None
		1458	*/
		1459	#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1460	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1FE) :\
		1461	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2FE) :\
		1462	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3FE) :\
		1463	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4FE))
		1464
		1465	/**
		1466	* @brief Disable fast mode for a given channel.
		1467	* @param __HANDLE__ TIM handle.
		1468	* @param __CHANNEL__ TIM Channels to be configured.
		1469	* This parameter can be one of the following values:
		1470	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1471	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1472	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1473	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1474	* @note When fast mode is disabled CCx output behaves normally depending
		1475	* on counter and CCRx values even when the trigger is ON. The minimum
		1476	* delay to activate CCx output when an active edge occurs on the
		1477	* trigger input is 5 clock cycles.
		1478	* @retval None
		1479	*/
		1480	#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1481	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
		1482	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
		1483	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
		1484	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
		1485
		1486	/**
		1487	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
		1488	* @param __HANDLE__ TIM handle.
		1489	* @note When the URS bit of the TIMx_CR1 register is set, only counter
		1490	* overflow/underflow generates an update interrupt or DMA request (if
		1491	* enabled)
		1492	* @retval None
		1493	*/
		1494	#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|= TIM_CR1_URS)
		1495
		1496	/**
		1497	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
		1498	* @param __HANDLE__ TIM handle.
		1499	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
		1500	* following events generate an update interrupt or DMA request (if
		1501	* enabled):
		1502	* _ Counter overflow underflow
		1503	* _ Setting the UG bit
		1504	* _ Update generation through the slave mode controller
		1505	* @retval None
		1506	*/
		1507	#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
		1508
		1509	/**
		1510	* @brief Set the TIM Capture x input polarity on runtime.
		1511	* @param __HANDLE__ TIM handle.
		1512	* @param __CHANNEL__ TIM Channels to be configured.
		1513	* This parameter can be one of the following values:
		1514	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1515	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1516	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1517	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1518	* @param __POLARITY__ Polarity for TIx source
		1519	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
		1520	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
		1521	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
		1522	* @retval None
		1523	*/
		1524	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
		1525	do{ \
		1526	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
		1527	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
		1528	}while(0)
		1529
		1530	/**
		1531	* @}
		1532	*/
		1533	/* End of exported macros ----------------------------------------------------*/
		1534
		1535	/* Private constants ---------------------------------------------------------*/
		1536	/** @defgroup TIM_Private_Constants TIM Private Constants
		1537	* @{
		1538	*/
		1539	/* The counter of a timer instance is disabled only if all the CCx and CCxN
		1540	channels have been disabled */
		1541	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
		1542	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
		1543	/**
		1544	* @}
		1545	*/
		1546	/* End of private constants --------------------------------------------------*/
		1547
		1548	/* Private macros ------------------------------------------------------------*/
		1549	/** @defgroup TIM_Private_Macros TIM Private Macros
		1550	* @{
		1551	*/
		1552	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
		1553	((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
		1554
		1555	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
		1556	((__BASE__) == TIM_DMABASE_CR2) \|\| \
		1557	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
		1558	((__BASE__) == TIM_DMABASE_DIER) \|\| \
		1559	((__BASE__) == TIM_DMABASE_SR) \|\| \
		1560	((__BASE__) == TIM_DMABASE_EGR) \|\| \
		1561	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
		1562	((__BASE__) == TIM_DMABASE_CCMR2) \|\| \
		1563	((__BASE__) == TIM_DMABASE_CCER) \|\| \
		1564	((__BASE__) == TIM_DMABASE_CNT) \|\| \
		1565	((__BASE__) == TIM_DMABASE_PSC) \|\| \
		1566	((__BASE__) == TIM_DMABASE_ARR) \|\| \
		1567	((__BASE__) == TIM_DMABASE_RCR) \|\| \
		1568	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
		1569	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
		1570	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
		1571	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
		1572	((__BASE__) == TIM_DMABASE_BDTR))
		1573
		1574	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1575
		1576	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
		1577	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
		1578	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
		1579	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
		1580	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
		1581
		1582	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
		1583	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
		1584	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
		1585
		1586	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
		1587	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
		1588
		1589	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
		1590	((__STATE__) == TIM_OCFAST_ENABLE))
		1591
		1592	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
		1593	((__POLARITY__) == TIM_OCPOLARITY_LOW))
		1594
		1595	#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) \|\| \
		1596	((__POLARITY__) == TIM_OCNPOLARITY_LOW))
		1597
		1598	#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) \|\| \
		1599	((__STATE__) == TIM_OCIDLESTATE_RESET))
		1600
		1601	#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) \|\| \
		1602	((__STATE__) == TIM_OCNIDLESTATE_RESET))
		1603
		1604	#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) \|\| \
		1605	((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
		1606
		1607	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
		1608	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
		1609	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
		1610
		1611	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
		1612	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
		1613	((__SELECTION__) == TIM_ICSELECTION_TRC))
		1614
		1615	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
		1616	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
		1617	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
		1618	((__PRESCALER__) == TIM_ICPSC_DIV8))
		1619
		1620	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
		1621	((__MODE__) == TIM_OPMODE_REPETITIVE))
		1622
		1623	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
		1624	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
		1625	((__MODE__) == TIM_ENCODERMODE_TI12))
		1626
		1627	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1628
		1629	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1630	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
		1631	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
		1632	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
		1633	((__CHANNEL__) == TIM_CHANNEL_ALL))
		1634
		1635	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1636	((__CHANNEL__) == TIM_CHANNEL_2))
		1637
		1638	#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1639	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
		1640	((__CHANNEL__) == TIM_CHANNEL_3))
		1641
		1642	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
		1643	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
		1644	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
		1645	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
		1646	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
		1647	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
		1648	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
		1649	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
		1650	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
		1651	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
		1652
		1653	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
		1654	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
		1655	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
		1656	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
		1657	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
		1658
		1659	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
		1660	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
		1661	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
		1662	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
		1663
		1664	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1665
		1666	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
		1667	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
		1668
		1669	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
		1670	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
		1671	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
		1672	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
		1673
		1674	#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1675
		1676	#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) \|\| \
		1677	((__STATE__) == TIM_OSSR_DISABLE))
		1678
		1679	#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) \|\| \
		1680	((__STATE__) == TIM_OSSI_DISABLE))
		1681
		1682	#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) \|\| \
		1683	((__LEVEL__) == TIM_LOCKLEVEL_1) \|\| \
		1684	((__LEVEL__) == TIM_LOCKLEVEL_2) \|\| \
		1685	((__LEVEL__) == TIM_LOCKLEVEL_3))
		1686
		1687	#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
		1688
		1689
		1690	#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) \|\| \
		1691	((__STATE__) == TIM_BREAK_DISABLE))
		1692
		1693	#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) \|\| \
		1694	((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
		1695
		1696	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
		1697	((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
		1698
		1699	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
		1700	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
		1701	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
		1702	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
		1703	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
		1704	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
		1705	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
		1706	((__SOURCE__) == TIM_TRGO_OC4REF))
		1707
		1708	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
		1709	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
		1710
		1711	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
		1712	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
		1713	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
		1714	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
		1715	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
		1716
		1717	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
		1718	((__MODE__) == TIM_OCMODE_PWM2))
		1719
		1720	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
		1721	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
		1722	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
		1723	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
		1724	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
		1725	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
		1726
		1727	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1728	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1729	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1730	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1731	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
		1732	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
		1733	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
		1734	((__SELECTION__) == TIM_TS_ETRF))
		1735
		1736	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1737	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1738	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1739	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1740	((__SELECTION__) == TIM_TS_NONE))
		1741
		1742	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
		1743	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
		1744	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
		1745	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
		1746	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
		1747
		1748	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
		1749	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
		1750	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
		1751	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
		1752
		1753	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1754
		1755	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
		1756	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
		1757
		1758	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
		1759	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
		1760	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
		1761	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
		1762	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
		1763	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
		1764	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
		1765	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
		1766	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
		1767	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
		1768	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
		1769	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
		1770	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
		1771	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
		1772	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
		1773	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
		1774	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
		1775	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
		1776
		1777	#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
		1778
		1779	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1780
		1781	#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
		1782
		1783	#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
		1784
		1785	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
		1786	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
		1787	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
		1788	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
		1789	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
		1790
		1791	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
		1792	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
		1793	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
		1794	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
		1795	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
		1796
		1797	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
		1798	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
		1799	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
		1800	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
		1801	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U))))
		1802
		1803	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
		1804	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
		1805	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
		1806	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
		1807	((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
		1808
		1809	#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
		1810	(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
		1811	((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
		1812	((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
		1813	(__HANDLE__)->ChannelState[3])
		1814
		1815	#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
		1816	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
		1817	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
		1818	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
		1819	((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
		1820
		1821	#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
		1822	(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
		1823	(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
		1824	(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
		1825	(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
		1826	} while(0)
		1827
		1828	#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
		1829	(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
		1830	((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
		1831	((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
		1832	(__HANDLE__)->ChannelNState[3])
		1833
		1834	#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
		1835	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
		1836	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
		1837	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
		1838	((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
		1839
		1840	#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
		1841	(__HANDLE__)->ChannelNState[0] = \
		1842	(__CHANNEL_STATE__); \
		1843	(__HANDLE__)->ChannelNState[1] = \
		1844	(__CHANNEL_STATE__); \
		1845	(__HANDLE__)->ChannelNState[2] = \
		1846	(__CHANNEL_STATE__); \
		1847	(__HANDLE__)->ChannelNState[3] = \
		1848	(__CHANNEL_STATE__); \
		1849	} while(0)
		1850
		1851	/**
		1852	* @}
		1853	*/
		1854	/* End of private macros -----------------------------------------------------*/
		1855
		1856	/* Include TIM HAL Extended module */
		1857	#include "stm32f1xx_hal_tim_ex.h"
		1858
		1859	/* Exported functions --------------------------------------------------------*/
		1860	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
		1861	* @{
		1862	*/
		1863
		1864	/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
		1865	* @brief Time Base functions
		1866	* @{
		1867	*/
		1868	/* Time Base functions ********************************************************/
		1869	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
		1870	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
		1871	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
		1872	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
		1873	/* Blocking mode: Polling */
		1874	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
		1875	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
		1876	/* Non-Blocking mode: Interrupt */
		1877	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
		1878	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
		1879	/* Non-Blocking mode: DMA */
		1880	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
		1881	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
		1882	/**
		1883	* @}
		1884	*/
		1885
		1886	/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
		1887	* @brief TIM Output Compare functions
		1888	* @{
		1889	*/
		1890	/* Timer Output Compare functions *********************************************/
		1891	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
		1892	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
		1893	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
		1894	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
		1895	/* Blocking mode: Polling */
		1896	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1897	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1898	/* Non-Blocking mode: Interrupt */
		1899	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1900	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1901	/* Non-Blocking mode: DMA */
		1902	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1903	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1904	/**
		1905	* @}
		1906	*/
		1907
		1908	/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
		1909	* @brief TIM PWM functions
		1910	* @{
		1911	*/
		1912	/* Timer PWM functions ********************************************************/
		1913	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
		1914	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
		1915	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
		1916	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
		1917	/* Blocking mode: Polling */
		1918	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1919	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1920	/* Non-Blocking mode: Interrupt */
		1921	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1922	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1923	/* Non-Blocking mode: DMA */
		1924	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1925	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1926	/**
		1927	* @}
		1928	*/
		1929
		1930	/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
		1931	* @brief TIM Input Capture functions
		1932	* @{
		1933	*/
		1934	/* Timer Input Capture functions **********************************************/
		1935	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
		1936	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
		1937	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
		1938	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
		1939	/* Blocking mode: Polling */
		1940	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1941	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1942	/* Non-Blocking mode: Interrupt */
		1943	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1944	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1945	/* Non-Blocking mode: DMA */
		1946	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1947	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1948	/**
		1949	* @}
		1950	*/
		1951
		1952	/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
		1953	* @brief TIM One Pulse functions
		1954	* @{
		1955	*/
		1956	/* Timer One Pulse functions **************************************************/
		1957	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
		1958	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
		1959	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
		1960	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
		1961	/* Blocking mode: Polling */
		1962	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1963	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1964	/* Non-Blocking mode: Interrupt */
		1965	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1966	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1967	/**
		1968	* @}
		1969	*/
		1970
		1971	/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
		1972	* @brief TIM Encoder functions
		1973	* @{
		1974	*/
		1975	/* Timer Encoder functions ****************************************************/
		1976	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
		1977	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
		1978	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
		1979	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
		1980	/* Blocking mode: Polling */
		1981	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1982	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1983	/* Non-Blocking mode: Interrupt */
		1984	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1985	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1986	/* Non-Blocking mode: DMA */
		1987	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1,
		1988	uint32_t *pData2, uint16_t Length);
		1989	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1990	/**
		1991	* @}
		1992	*/
		1993
		1994	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
		1995	* @brief IRQ handler management
		1996	* @{
		1997	*/
		1998	/* Interrupt Handler functions ***********************************************/
		1999	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
		2000	/**
		2001	* @}
		2002	*/
		2003
		2004	/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
		2005	* @brief Peripheral Control functions
		2006	* @{
		2007	*/
		2008	/* Control functions *********************************************************/
		2009	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		2010	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		2011	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
		2012	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig,
		2013	uint32_t OutputChannel, uint32_t InputChannel);
		2014	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig,
		2015	uint32_t Channel);
		2016	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
		2017	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
		2018	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		2019	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		2020	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		2021	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		2022	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		2023	uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
		2024	uint32_t BurstLength, uint32_t DataLength);
		2025	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
		2026	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		2027	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		2028	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		2029	uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
		2030	uint32_t BurstLength, uint32_t DataLength);
		2031	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
		2032	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
		2033	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
		2034	/**
		2035	* @}
		2036	*/
		2037
		2038	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
		2039	* @brief TIM Callbacks functions
		2040	* @{
		2041	*/
		2042	/* Callback in non blocking modes (Interrupt and DMA) *************************/
		2043	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
		2044	void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
		2045	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
		2046	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
		2047	void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
		2048	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
		2049	void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
		2050	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
		2051	void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
		2052	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
		2053
		2054	/* Callbacks Register/UnRegister functions ***********************************/
		2055	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2056	HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
		2057	pTIM_CallbackTypeDef pCallback);
		2058	HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
		2059	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2060
		2061	/**
		2062	* @}
		2063	*/
		2064
		2065	/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
		2066	* @brief Peripheral State functions
		2067	* @{
		2068	*/
		2069	/* Peripheral State functions ************************************************/
		2070	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
		2071	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
		2072	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
		2073	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
		2074	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
		2075	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
		2076
		2077	/* Peripheral Channel state functions ************************************************/
		2078	HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
		2079	HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
		2080	HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
		2081	/**
		2082	* @}
		2083	*/
		2084
		2085	/**
		2086	* @}
		2087	*/
		2088	/* End of exported functions -------------------------------------------------*/
		2089
		2090	/* Private functions----------------------------------------------------------*/
		2091	/** @defgroup TIM_Private_Functions TIM Private Functions
		2092	* @{
		2093	*/
		2094	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
		2095	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
		2096	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		2097	void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
		2098	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
		2099
		2100	void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
		2101	void TIM_DMAError(DMA_HandleTypeDef *hdma);
		2102	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
		2103	void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
		2104	void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
		2105
		2106	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2107	void TIM_ResetCallback(TIM_HandleTypeDef *htim);
		2108	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2109
		2110	/**
		2111	* @}
		2112	*/
		2113	/* End of private functions --------------------------------------------------*/
		2114
		2115	/**
		2116	* @}
		2117	*/
		2118
		2119	/**
		2120	* @}
		2121	*/
		2122
		2123	#ifdef __cplusplus
		2124	}
		2125	#endif
		2126
		2127	#endif /* STM32F1xx_HAL_TIM_H */
		2128
		2129	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h – Rev 2