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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f1xx_hal_spi.h |
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4 | * @author MCD Application Team |
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5 | mjames | 5 | * @version V1.0.4 |
6 | * @date 29-April-2016 |
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2 | mjames | 7 | * @brief Header file of SPI HAL module. |
8 | ****************************************************************************** |
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9 | * @attention |
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10 | * |
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5 | mjames | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
2 | mjames | 12 | * |
13 | * Redistribution and use in source and binary forms, with or without modification, |
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14 | * are permitted provided that the following conditions are met: |
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15 | * 1. Redistributions of source code must retain the above copyright notice, |
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16 | * this list of conditions and the following disclaimer. |
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17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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18 | * this list of conditions and the following disclaimer in the documentation |
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19 | * and/or other materials provided with the distribution. |
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20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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21 | * may be used to endorse or promote products derived from this software |
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22 | * without specific prior written permission. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | ****************************************************************************** |
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36 | */ |
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37 | |||
38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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39 | #ifndef __STM32F1xx_HAL_SPI_H |
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40 | #define __STM32F1xx_HAL_SPI_H |
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41 | |||
42 | #ifdef __cplusplus |
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43 | extern "C" { |
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44 | #endif |
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45 | |||
46 | /* Includes ------------------------------------------------------------------*/ |
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47 | #include "stm32f1xx_hal_def.h" |
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48 | |||
49 | /** @addtogroup STM32F1xx_HAL_Driver |
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50 | * @{ |
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51 | */ |
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52 | |||
53 | /** @addtogroup SPI |
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54 | * @{ |
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55 | */ |
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56 | |||
57 | /* Exported types ------------------------------------------------------------*/ |
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58 | /** @defgroup SPI_Exported_Types SPI Exported Types |
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59 | * @{ |
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60 | */ |
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61 | |||
62 | /** |
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63 | * @brief SPI Configuration Structure definition |
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64 | */ |
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65 | typedef struct |
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66 | { |
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67 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
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68 | This parameter can be a value of @ref SPI_mode */ |
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69 | |||
70 | uint32_t Direction; /*!< Specifies the SPI Directional mode state. |
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71 | This parameter can be a value of @ref SPI_Direction_mode */ |
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72 | |||
73 | uint32_t DataSize; /*!< Specifies the SPI data size. |
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74 | This parameter can be a value of @ref SPI_data_size */ |
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75 | |||
76 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
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77 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
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78 | |||
79 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
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80 | This parameter can be a value of @ref SPI_Clock_Phase */ |
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81 | |||
82 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
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83 | hardware (NSS pin) or by software using the SSI bit. |
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84 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
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85 | |||
86 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
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87 | used to configure the transmit and receive SCK clock. |
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88 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
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89 | @note The communication clock is derived from the master |
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90 | clock. The slave clock does not need to be set */ |
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91 | |||
92 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
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93 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
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94 | |||
95 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
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96 | This parameter can be a value of @ref SPI_TI_mode */ |
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97 | |||
98 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
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99 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
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100 | |||
101 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
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102 | This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ |
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103 | |||
104 | }SPI_InitTypeDef; |
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105 | |||
106 | /** |
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107 | * @brief HAL SPI State structure definition |
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108 | */ |
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109 | typedef enum |
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110 | { |
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111 | HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ |
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112 | HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ |
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113 | HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ |
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114 | HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ |
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115 | HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ |
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116 | HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ |
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117 | HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ |
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118 | |||
119 | }HAL_SPI_StateTypeDef; |
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120 | |||
121 | |||
122 | /** |
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123 | * @brief SPI handle Structure definition |
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124 | */ |
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125 | typedef struct __SPI_HandleTypeDef |
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126 | { |
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127 | SPI_TypeDef *Instance; /*!< SPI registers base address */ |
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128 | |||
129 | SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
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130 | |||
131 | uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
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132 | |||
133 | uint16_t TxXferSize; /*!< SPI Tx transfer size */ |
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134 | |||
135 | uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
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136 | |||
137 | uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
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138 | |||
139 | uint16_t RxXferSize; /*!< SPI Rx transfer size */ |
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140 | |||
141 | uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
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142 | |||
143 | DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ |
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144 | |||
145 | DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ |
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146 | |||
147 | void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ |
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148 | |||
149 | void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ |
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150 | |||
151 | HAL_LockTypeDef Lock; /*!< SPI locking object */ |
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152 | |||
153 | __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
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154 | |||
155 | __IO uint32_t ErrorCode; /*!< SPI Error code */ |
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156 | |||
157 | }SPI_HandleTypeDef; |
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158 | /** |
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159 | * @} |
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160 | */ |
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161 | |||
162 | |||
163 | /* Exported constants --------------------------------------------------------*/ |
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164 | |||
165 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
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166 | * @{ |
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167 | */ |
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168 | |||
169 | /** @defgroup SPI_Error_Codes SPI Error Codes |
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170 | * @{ |
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171 | */ |
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172 | #define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
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173 | #define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */ |
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174 | #define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */ |
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175 | #define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */ |
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176 | #define HAL_SPI_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ |
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177 | #define HAL_SPI_ERROR_FLAG ((uint32_t)0x10) /*!< Flag: RXNE,TXE, BSY */ |
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178 | /** |
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179 | * @} |
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180 | */ |
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181 | |||
182 | |||
183 | |||
184 | |||
185 | /** @defgroup SPI_mode SPI mode |
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186 | * @{ |
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187 | */ |
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188 | #define SPI_MODE_SLAVE ((uint32_t)0x00000000) |
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189 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
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190 | |||
191 | /** |
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192 | * @} |
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193 | */ |
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194 | |||
195 | /** @defgroup SPI_Direction_mode SPI Direction mode |
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196 | * @{ |
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197 | */ |
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198 | #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) |
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199 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
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200 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
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201 | |||
202 | /** |
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203 | * @} |
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204 | */ |
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205 | |||
206 | /** @defgroup SPI_data_size SPI data size |
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207 | * @{ |
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208 | */ |
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209 | #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) |
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210 | #define SPI_DATASIZE_16BIT SPI_CR1_DFF |
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211 | |||
212 | /** |
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213 | * @} |
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214 | */ |
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215 | |||
216 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
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217 | * @{ |
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218 | */ |
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219 | #define SPI_POLARITY_LOW ((uint32_t)0x00000000) |
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220 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
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221 | |||
222 | /** |
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223 | * @} |
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224 | */ |
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225 | |||
226 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
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227 | * @{ |
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228 | */ |
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229 | #define SPI_PHASE_1EDGE ((uint32_t)0x00000000) |
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230 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
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231 | |||
232 | /** |
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233 | * @} |
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234 | */ |
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235 | |||
236 | /** @defgroup SPI_Slave_Select_management SPI Slave Select management |
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237 | * @{ |
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238 | */ |
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239 | #define SPI_NSS_SOFT SPI_CR1_SSM |
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240 | #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) |
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241 | #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) |
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242 | |||
243 | /** |
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244 | * @} |
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245 | */ |
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246 | |||
247 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
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248 | * @{ |
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249 | */ |
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250 | #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) |
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251 | #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) |
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252 | #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) |
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253 | #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) |
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254 | #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) |
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255 | #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) |
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256 | #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) |
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257 | #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
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258 | |||
259 | /** |
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260 | * @} |
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261 | */ |
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262 | |||
263 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission |
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264 | * @{ |
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265 | */ |
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266 | #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) |
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267 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
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268 | |||
269 | /** |
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270 | * @} |
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271 | */ |
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272 | |||
273 | /** @defgroup SPI_TI_mode SPI TI mode disable |
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274 | * @brief SPI TI Mode not supported for STM32F1xx family |
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275 | * @{ |
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276 | */ |
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277 | #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) |
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278 | |||
279 | /** |
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280 | * @} |
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281 | */ |
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282 | |||
283 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
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284 | * @{ |
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285 | */ |
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286 | #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) |
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287 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
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288 | |||
289 | /** |
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290 | * @} |
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291 | */ |
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292 | |||
293 | /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition |
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294 | * @{ |
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295 | */ |
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296 | #define SPI_IT_TXE SPI_CR2_TXEIE |
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297 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
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298 | #define SPI_IT_ERR SPI_CR2_ERRIE |
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299 | /** |
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300 | * @} |
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301 | */ |
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302 | |||
303 | /** @defgroup SPI_Flag_definition SPI Flag definition |
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304 | * @{ |
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305 | */ |
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306 | #define SPI_FLAG_RXNE SPI_SR_RXNE |
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307 | #define SPI_FLAG_TXE SPI_SR_TXE |
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308 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR |
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309 | #define SPI_FLAG_MODF SPI_SR_MODF |
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310 | #define SPI_FLAG_OVR SPI_SR_OVR |
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311 | #define SPI_FLAG_BSY SPI_SR_BSY |
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312 | |||
313 | /** |
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314 | * @} |
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315 | */ |
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316 | |||
317 | /** |
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318 | * @} |
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319 | */ |
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320 | |||
321 | |||
322 | /* Private constants ---------------------------------------------------------*/ |
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323 | /** @defgroup SPI_Private_Constants SPI Private Constants |
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324 | * @{ |
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325 | */ |
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326 | #define SPI_INVALID_CRC_ERROR 0 /* CRC error wrongly detected */ |
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327 | #define SPI_VALID_CRC_ERROR 1 /* CRC error is true */ |
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328 | /** |
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329 | * @} |
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330 | */ |
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331 | |||
332 | |||
333 | /* Exported macro ------------------------------------------------------------*/ |
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334 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
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335 | * @{ |
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336 | */ |
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337 | |||
338 | /** @brief Reset SPI handle state |
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339 | * @param __HANDLE__: specifies the SPI handle. |
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340 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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341 | * @retval None |
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342 | */ |
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343 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
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344 | |||
345 | /** @brief Enable the specified SPI interrupts. |
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346 | * @param __HANDLE__: specifies the SPI handle. |
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347 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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348 | * @param __INTERRUPT__: specifies the interrupt source to enable. |
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349 | * This parameter can be one of the following values: |
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350 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
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351 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
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352 | * @arg SPI_IT_ERR: Error interrupt enable |
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353 | * @retval None |
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354 | */ |
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355 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
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356 | |||
357 | /** @brief Disable the specified SPI interrupts. |
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358 | * @param __HANDLE__: specifies the SPI handle. |
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359 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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360 | * @param __INTERRUPT__: specifies the interrupt source to disable. |
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361 | * This parameter can be one of the following values: |
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362 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
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363 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
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364 | * @arg SPI_IT_ERR: Error interrupt enable |
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365 | * @retval None |
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366 | */ |
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367 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
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368 | |||
369 | /** @brief Check if the specified SPI interrupt source is enabled or disabled. |
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370 | * @param __HANDLE__: specifies the SPI handle. |
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371 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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372 | * @param __INTERRUPT__: specifies the SPI interrupt source to check. |
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373 | * This parameter can be one of the following values: |
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374 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
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375 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
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376 | * @arg SPI_IT_ERR: Error interrupt enable |
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377 | * @retval The new state of __IT__ (TRUE or FALSE). |
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378 | */ |
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379 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
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380 | |||
381 | /** @brief Check whether the specified SPI flag is set or not. |
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382 | * @param __HANDLE__: specifies the SPI handle. |
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383 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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384 | * @param __FLAG__: specifies the flag to check. |
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385 | * This parameter can be one of the following values: |
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386 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
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387 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
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388 | * @arg SPI_FLAG_CRCERR: CRC error flag |
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389 | * @arg SPI_FLAG_MODF: Mode fault flag |
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390 | * @arg SPI_FLAG_OVR: Overrun flag |
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391 | * @arg SPI_FLAG_BSY: Busy flag |
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392 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
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393 | */ |
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394 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
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395 | |||
396 | /** @brief Clear the SPI CRCERR pending flag. |
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397 | * @param __HANDLE__: specifies the SPI handle. |
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398 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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399 | * @retval None |
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400 | */ |
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401 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) |
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402 | |||
403 | /** @brief Clear the SPI MODF pending flag. |
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404 | * @param __HANDLE__: specifies the SPI handle. |
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405 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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406 | * @retval None |
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407 | */ |
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408 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
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409 | do{ \ |
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410 | __IO uint32_t tmpreg; \ |
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411 | tmpreg = (__HANDLE__)->Instance->SR; \ |
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412 | tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ |
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413 | UNUSED(tmpreg); \ |
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414 | }while(0) |
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415 | |||
416 | /** @brief Clear the SPI OVR pending flag. |
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417 | * @param __HANDLE__: specifies the SPI handle. |
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418 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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419 | * @retval None |
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420 | */ |
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421 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
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422 | do{ \ |
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423 | __IO uint32_t tmpreg; \ |
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424 | tmpreg = (__HANDLE__)->Instance->DR; \ |
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425 | tmpreg = (__HANDLE__)->Instance->SR; \ |
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426 | UNUSED(tmpreg); \ |
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427 | }while(0) |
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428 | |||
429 | |||
430 | /** @brief Enables the SPI. |
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431 | * @param __HANDLE__: specifies the SPI Handle. |
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432 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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433 | * @retval None |
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434 | */ |
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435 | #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
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436 | |||
437 | /** @brief Disables the SPI. |
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438 | * @param __HANDLE__: specifies the SPI Handle. |
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439 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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440 | * @retval None |
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441 | */ |
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442 | #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
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443 | |||
444 | /** |
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445 | * @} |
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446 | */ |
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447 | |||
448 | |||
449 | /* Private macros -----------------------------------------------------------*/ |
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450 | /** @defgroup SPI_Private_Macros SPI Private Macros |
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451 | * @{ |
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452 | */ |
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453 | |||
454 | /** @brief Checks if SPI Mode parameter is in allowed range. |
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455 | * @param __MODE__: specifies the SPI Mode. |
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456 | * This parameter can be a value of @ref SPI_mode |
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457 | * @retval None |
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458 | */ |
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459 | #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) |
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460 | |||
461 | /** @brief Checks if SPI Direction Mode parameter is in allowed range. |
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462 | * @param __MODE__: specifies the SPI Direction Mode. |
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463 | * This parameter can be a value of @ref SPI_Direction_mode |
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464 | * @retval None |
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465 | */ |
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466 | #define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
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467 | ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ |
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468 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
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469 | |||
470 | /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. |
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471 | * @param __MODE__: specifies the SPI Direction Mode. |
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472 | * @retval None |
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473 | */ |
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474 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
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475 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
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476 | |||
477 | /** @brief Checks if SPI Direction Mode parameter is 2 lines. |
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478 | * @param __MODE__: specifies the SPI Direction Mode. |
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479 | * @retval None |
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480 | */ |
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481 | #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
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482 | |||
483 | /** @brief Checks if SPI Data Size parameter is in allowed range. |
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484 | * @param __DATASIZE__: specifies the SPI Data Size. |
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485 | * This parameter can be a value of @ref SPI_data_size |
||
486 | * @retval None |
||
487 | */ |
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488 | #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
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489 | ((__DATASIZE__) == SPI_DATASIZE_8BIT)) |
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490 | |||
491 | /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. |
||
492 | * @param __CPOL__: specifies the SPI serial clock steady state. |
||
493 | * This parameter can be a value of @ref SPI_Clock_Polarity |
||
494 | * @retval None |
||
495 | */ |
||
496 | #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
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497 | ((__CPOL__) == SPI_POLARITY_HIGH)) |
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498 | |||
499 | /** @brief Checks if SPI Clock Phase parameter is in allowed range. |
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500 | * @param __CPHA__: specifies the SPI Clock Phase. |
||
501 | * This parameter can be a value of @ref SPI_Clock_Phase |
||
502 | * @retval None |
||
503 | */ |
||
504 | #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
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505 | ((__CPHA__) == SPI_PHASE_2EDGE)) |
||
506 | |||
507 | /** @brief Checks if SPI Slave select parameter is in allowed range. |
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508 | * @param __NSS__: specifies the SPI Slave Slelect management parameter. |
||
509 | * This parameter can be a value of @ref SPI_Slave_Select_management |
||
510 | * @retval None |
||
511 | */ |
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512 | #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
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513 | ((__NSS__) == SPI_NSS_HARD_INPUT) || \ |
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514 | ((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
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515 | |||
516 | /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. |
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517 | * @param __PRESCALER__: specifies the SPI Baudrate prescaler. |
||
518 | * This parameter can be a value of @ref SPI_BaudRate_Prescaler |
||
519 | * @retval None |
||
520 | */ |
||
521 | #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
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522 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ |
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523 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ |
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524 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ |
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525 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ |
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526 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ |
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527 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ |
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528 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
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529 | |||
530 | /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. |
||
531 | * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
||
532 | * This parameter can be a value of @ref SPI_MSB_LSB_transmission |
||
533 | * @retval None |
||
534 | */ |
||
535 | #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
||
536 | ((__BIT__) == SPI_FIRSTBIT_LSB)) |
||
537 | |||
538 | /** @brief Checks if SPI TI mode parameter is in allowed range. |
||
539 | * @param __MODE__: specifies the SPI TI mode. |
||
540 | * This parameter can be a value of @ref SPI_TI_mode |
||
541 | * @retval None |
||
542 | */ |
||
543 | #define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) |
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544 | |||
545 | /** @brief Checks if SPI CRC calculation enabled state is in allowed range. |
||
546 | * @param __CALCULATION__: specifies the SPI CRC calculation enable state. |
||
547 | * This parameter can be a value of @ref SPI_CRC_Calculation |
||
548 | * @retval None |
||
549 | */ |
||
550 | #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
||
551 | ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
||
552 | |||
553 | /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. |
||
554 | * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. |
||
555 | * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 |
||
556 | * @retval None |
||
557 | */ |
||
558 | #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF)) |
||
559 | |||
560 | /** @brief Sets the SPI transmit-only mode. |
||
561 | * @param __HANDLE__: specifies the SPI Handle. |
||
562 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
563 | * @retval None |
||
564 | */ |
||
565 | #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
||
566 | |||
567 | /** @brief Sets the SPI receive-only mode. |
||
568 | * @param __HANDLE__: specifies the SPI Handle. |
||
569 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
570 | * @retval None |
||
571 | */ |
||
572 | #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
||
573 | |||
574 | /** @brief Resets the CRC calculation of the SPI. |
||
575 | * @param __HANDLE__: specifies the SPI Handle. |
||
576 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
577 | * @retval None |
||
578 | */ |
||
579 | #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
||
580 | SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) |
||
581 | |||
582 | /** |
||
583 | * @} |
||
584 | */ |
||
585 | |||
586 | /* Exported functions --------------------------------------------------------*/ |
||
587 | /** @addtogroup SPI_Exported_Functions |
||
588 | * @{ |
||
589 | */ |
||
590 | |||
591 | /* Initialization/de-initialization functions **********************************/ |
||
592 | /** @addtogroup SPI_Exported_Functions_Group1 |
||
593 | * @{ |
||
594 | */ |
||
595 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
||
596 | HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); |
||
597 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
||
598 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
||
599 | /** |
||
600 | * @} |
||
601 | */ |
||
602 | |||
603 | /* I/O operation functions *****************************************************/ |
||
604 | /** @addtogroup SPI_Exported_Functions_Group2 |
||
605 | * @{ |
||
606 | */ |
||
607 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||
608 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||
609 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); |
||
610 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||
611 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||
612 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
||
613 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||
614 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||
615 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
||
616 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
||
617 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
||
618 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
||
619 | |||
620 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
||
621 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
||
622 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
||
623 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
||
624 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
||
625 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
||
626 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
||
627 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
||
628 | /** |
||
629 | * @} |
||
630 | */ |
||
631 | |||
632 | |||
633 | /* Peripheral State and Control functions **************************************/ |
||
634 | /** @addtogroup SPI_Exported_Functions_Group3 |
||
635 | * @{ |
||
636 | */ |
||
637 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
||
638 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
||
639 | |||
640 | /** |
||
641 | * @} |
||
642 | */ |
||
643 | |||
644 | /** |
||
645 | * @} |
||
646 | */ |
||
647 | |||
648 | |||
649 | /* Private functions --------------------------------------------------------*/ |
||
650 | /** @addtogroup SPI_Private_Functions |
||
651 | * @{ |
||
652 | */ |
||
653 | uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi); |
||
654 | |||
655 | /** |
||
656 | * @} |
||
657 | */ |
||
658 | |||
659 | |||
660 | /** |
||
661 | * @} |
||
662 | */ |
||
663 | |||
664 | /** |
||
665 | * @} |
||
666 | */ |
||
667 | |||
668 | #ifdef __cplusplus |
||
669 | } |
||
670 | #endif |
||
671 | |||
672 | #endif /* __STM32F1xx_HAL_SPI_H */ |
||
673 | |||
674 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |