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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_rcc_ex.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of RCC HAL Extension module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32F1xx_HAL_RCC_EX_H |
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| 22 | #define __STM32F1xx_HAL_RCC_EX_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f1xx_hal_def.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | /** @addtogroup RCCEx |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |||
| 39 | /** @addtogroup RCCEx_Private_Constants |
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| 40 | * @{ |
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| 41 | */ |
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| 42 | |||
| 43 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 44 | |||
| 45 | /* Alias word address of PLLI2SON bit */ |
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| 46 | #define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos |
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| 47 | #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) |
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| 48 | /* Alias word address of PLL2ON bit */ |
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| 49 | #define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos |
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| 50 | #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) |
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| 51 | |||
| 52 | #define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ |
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| 53 | #define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ |
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| 54 | |||
| 55 | #endif /* STM32F105xC || STM32F107xC */ |
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| 56 | |||
| 57 | |||
| 58 | #define CR_REG_INDEX ((uint8_t)1) |
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| 59 | |||
| 60 | /** |
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| 61 | * @} |
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| 62 | */ |
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| 63 | |||
| 64 | /** @addtogroup RCCEx_Private_Macros |
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| 65 | * @{ |
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| 66 | */ |
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| 67 | |||
| 68 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 69 | #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ |
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| 70 | ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) |
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| 71 | #endif /* STM32F105xC || STM32F107xC */ |
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| 72 | |||
| 73 | #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ |
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| 74 | || defined(STM32F100xE) |
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| 75 | #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ |
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| 76 | ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ |
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| 77 | ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ |
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| 78 | ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ |
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| 79 | ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ |
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| 80 | ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ |
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| 81 | ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ |
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| 82 | ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) |
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| 83 | |||
| 84 | #else |
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| 85 | #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) |
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| 86 | #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ |
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| 87 | |||
| 88 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 89 | #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ |
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| 90 | ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ |
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| 91 | ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ |
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| 92 | ((__MUL__) == RCC_PLL_MUL6_5)) |
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| 93 | |||
| 94 | #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ |
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| 95 | || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ |
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| 96 | || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ |
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| 97 | || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ |
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| 98 | || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) |
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| 99 | |||
| 100 | #else |
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| 101 | #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ |
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| 102 | ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ |
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| 103 | ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ |
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| 104 | ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ |
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| 105 | ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ |
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| 106 | ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ |
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| 107 | ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ |
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| 108 | ((__MUL__) == RCC_PLL_MUL16)) |
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| 109 | |||
| 110 | #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ |
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| 111 | || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ |
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| 112 | || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) |
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| 113 | |||
| 114 | #endif /* STM32F105xC || STM32F107xC*/ |
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| 115 | |||
| 116 | #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ |
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| 117 | ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) |
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| 118 | |||
| 119 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 120 | #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) |
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| 121 | |||
| 122 | #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) |
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| 123 | |||
| 124 | #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) |
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| 125 | |||
| 126 | #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ |
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| 127 | ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ |
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| 128 | ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ |
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| 129 | ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ |
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| 130 | ((__MUL__) == RCC_PLLI2S_MUL20)) |
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| 131 | |||
| 132 | #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ |
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| 133 | ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ |
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| 134 | ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ |
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| 135 | ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ |
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| 136 | ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ |
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| 137 | ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ |
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| 138 | ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ |
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| 139 | ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) |
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| 140 | |||
| 141 | #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ |
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| 142 | ((__PLL__) == RCC_PLL2_ON)) |
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| 143 | |||
| 144 | #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ |
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| 145 | ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ |
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| 146 | ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ |
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| 147 | ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ |
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| 148 | ((__MUL__) == RCC_PLL2_MUL20)) |
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| 149 | |||
| 150 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
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| 151 | ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
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| 152 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
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| 153 | (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ |
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| 154 | (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ |
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| 155 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) |
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| 156 | |||
| 157 | #elif defined(STM32F103xE) || defined(STM32F103xG) |
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| 158 | |||
| 159 | #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) |
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| 160 | |||
| 161 | #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) |
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| 162 | |||
| 163 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
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| 164 | ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
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| 165 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
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| 166 | (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ |
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| 167 | (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ |
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| 168 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) |
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| 169 | |||
| 170 | |||
| 171 | #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
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| 172 | || defined(STM32F103xB) |
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| 173 | |||
| 174 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
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| 175 | ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
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| 176 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
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| 177 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) |
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| 178 | |||
| 179 | #else |
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| 180 | |||
| 181 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
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| 182 | ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
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| 183 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) |
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| 184 | |||
| 185 | #endif /* STM32F105xC || STM32F107xC */ |
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| 186 | |||
| 187 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
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| 188 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) |
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| 189 | |||
| 190 | #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) |
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| 191 | |||
| 192 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ |
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| 193 | |||
| 194 | /** |
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| 195 | * @} |
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| 196 | */ |
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| 197 | |||
| 198 | /* Exported types ------------------------------------------------------------*/ |
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| 199 | |||
| 200 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
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| 201 | * @{ |
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| 202 | */ |
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| 203 | |||
| 204 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 205 | /** |
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| 206 | * @brief RCC PLL2 configuration structure definition |
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| 207 | */ |
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| 208 | typedef struct |
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| 209 | { |
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| 210 | uint32_t PLL2State; /*!< The new state of the PLL2. |
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| 211 | This parameter can be a value of @ref RCCEx_PLL2_Config */ |
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| 212 | |||
| 213 | uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock |
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| 214 | This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ |
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| 215 | |||
| 216 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 217 | uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. |
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| 218 | This parameter can be a value of @ref RCCEx_Prediv2_Factor */ |
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| 219 | |||
| 220 | #endif /* STM32F105xC || STM32F107xC */ |
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| 221 | } RCC_PLL2InitTypeDef; |
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| 222 | |||
| 223 | #endif /* STM32F105xC || STM32F107xC */ |
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| 224 | |||
| 225 | /** |
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| 226 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
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| 227 | */ |
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| 228 | typedef struct |
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| 229 | { |
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| 230 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
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| 231 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
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| 232 | |||
| 233 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 234 | uint32_t Prediv1Source; /*!< The Prediv1 source value. |
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| 235 | This parameter can be a value of @ref RCCEx_Prediv1_Source */ |
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| 236 | #endif /* STM32F105xC || STM32F107xC */ |
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| 237 | |||
| 238 | uint32_t HSEState; /*!< The new state of the HSE. |
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| 239 | This parameter can be a value of @ref RCC_HSE_Config */ |
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| 240 | |||
| 241 | uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) |
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| 242 | This parameter can be a value of @ref RCCEx_Prediv1_Factor */ |
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| 243 | |||
| 244 | uint32_t LSEState; /*!< The new state of the LSE. |
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| 245 | This parameter can be a value of @ref RCC_LSE_Config */ |
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| 246 | |||
| 247 | uint32_t HSIState; /*!< The new state of the HSI. |
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| 248 | This parameter can be a value of @ref RCC_HSI_Config */ |
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| 249 | |||
| 250 | uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). |
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| 251 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
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| 252 | |||
| 253 | uint32_t LSIState; /*!< The new state of the LSI. |
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| 254 | This parameter can be a value of @ref RCC_LSI_Config */ |
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| 255 | |||
| 256 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
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| 257 | |||
| 258 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 259 | RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ |
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| 260 | #endif /* STM32F105xC || STM32F107xC */ |
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| 261 | } RCC_OscInitTypeDef; |
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| 262 | |||
| 263 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 264 | /** |
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| 265 | * @brief RCC PLLI2S configuration structure definition |
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| 266 | */ |
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| 267 | typedef struct |
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| 268 | { |
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| 269 | uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock |
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| 270 | This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ |
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| 271 | |||
| 272 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 273 | uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. |
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| 274 | This parameter can be a value of @ref RCCEx_Prediv2_Factor */ |
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| 275 | |||
| 276 | #endif /* STM32F105xC || STM32F107xC */ |
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| 277 | } RCC_PLLI2SInitTypeDef; |
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| 278 | #endif /* STM32F105xC || STM32F107xC */ |
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| 279 | |||
| 280 | /** |
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| 281 | * @brief RCC extended clocks structure definition |
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| 282 | */ |
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| 283 | typedef struct |
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| 284 | { |
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| 285 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
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| 286 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
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| 287 | |||
| 288 | uint32_t RTCClockSelection; /*!< specifies the RTC clock source. |
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| 289 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
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| 290 | |||
| 291 | uint32_t AdcClockSelection; /*!< ADC clock source |
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| 292 | This parameter can be a value of @ref RCCEx_ADC_Prescaler */ |
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| 293 | |||
| 294 | #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ |
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| 295 | || defined(STM32F107xC) |
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| 296 | uint32_t I2s2ClockSelection; /*!< I2S2 clock source |
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| 297 | This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ |
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| 298 | |||
| 299 | uint32_t I2s3ClockSelection; /*!< I2S3 clock source |
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| 300 | This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ |
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| 301 | |||
| 302 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 303 | RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters |
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| 304 | This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ |
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| 305 | |||
| 306 | #endif /* STM32F105xC || STM32F107xC */ |
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| 307 | #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
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| 308 | |||
| 309 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
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| 310 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
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| 311 | || defined(STM32F105xC) || defined(STM32F107xC) |
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| 312 | uint32_t UsbClockSelection; /*!< USB clock source |
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| 313 | This parameter can be a value of @ref RCCEx_USB_Prescaler */ |
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| 314 | |||
| 315 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
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| 316 | } RCC_PeriphCLKInitTypeDef; |
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| 317 | |||
| 318 | /** |
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| 319 | * @} |
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| 320 | */ |
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| 321 | |||
| 322 | /* Exported constants --------------------------------------------------------*/ |
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| 323 | |||
| 324 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
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| 325 | * @{ |
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| 326 | */ |
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| 327 | |||
| 328 | /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection |
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| 329 | * @{ |
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| 330 | */ |
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| 331 | #define RCC_PERIPHCLK_RTC 0x00000001U |
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| 332 | #define RCC_PERIPHCLK_ADC 0x00000002U |
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| 333 | #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ |
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| 334 | || defined(STM32F107xC) |
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| 335 | #define RCC_PERIPHCLK_I2S2 0x00000004U |
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| 336 | #define RCC_PERIPHCLK_I2S3 0x00000008U |
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| 337 | #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
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| 338 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
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| 339 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
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| 340 | || defined(STM32F105xC) || defined(STM32F107xC) |
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| 341 | #define RCC_PERIPHCLK_USB 0x00000010U |
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| 342 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
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| 343 | |||
| 344 | /** |
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| 345 | * @} |
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| 346 | */ |
||
| 347 | |||
| 348 | /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler |
||
| 349 | * @{ |
||
| 350 | */ |
||
| 351 | #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 |
||
| 352 | #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 |
||
| 353 | #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 |
||
| 354 | #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 |
||
| 355 | |||
| 356 | /** |
||
| 357 | * @} |
||
| 358 | */ |
||
| 359 | |||
| 360 | #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ |
||
| 361 | || defined(STM32F107xC) |
||
| 362 | /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source |
||
| 363 | * @{ |
||
| 364 | */ |
||
| 365 | #define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U |
||
| 366 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 367 | #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC |
||
| 368 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 369 | |||
| 370 | /** |
||
| 371 | * @} |
||
| 372 | */ |
||
| 373 | |||
| 374 | /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source |
||
| 375 | * @{ |
||
| 376 | */ |
||
| 377 | #define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U |
||
| 378 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 379 | #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC |
||
| 380 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 381 | |||
| 382 | /** |
||
| 383 | * @} |
||
| 384 | */ |
||
| 385 | |||
| 386 | #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||
| 387 | |||
| 388 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
||
| 389 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) |
||
| 390 | |||
| 391 | /** @defgroup RCCEx_USB_Prescaler USB Prescaler |
||
| 392 | * @{ |
||
| 393 | */ |
||
| 394 | #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE |
||
| 395 | #define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U |
||
| 396 | |||
| 397 | /** |
||
| 398 | * @} |
||
| 399 | */ |
||
| 400 | |||
| 401 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ |
||
| 402 | |||
| 403 | |||
| 404 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 405 | /** @defgroup RCCEx_USB_Prescaler USB Prescaler |
||
| 406 | * @{ |
||
| 407 | */ |
||
| 408 | #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE |
||
| 409 | #define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U |
||
| 410 | |||
| 411 | /** |
||
| 412 | * @} |
||
| 413 | */ |
||
| 414 | |||
| 415 | /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor |
||
| 416 | * @{ |
||
| 417 | */ |
||
| 418 | |||
| 419 | #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ |
||
| 420 | #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ |
||
| 421 | #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ |
||
| 422 | #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ |
||
| 423 | #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ |
||
| 424 | #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ |
||
| 425 | #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ |
||
| 426 | #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ |
||
| 427 | #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ |
||
| 428 | |||
| 429 | /** |
||
| 430 | * @} |
||
| 431 | */ |
||
| 432 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 433 | |||
| 434 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 435 | /** @defgroup RCCEx_Prediv1_Source Prediv1 Source |
||
| 436 | * @{ |
||
| 437 | */ |
||
| 438 | |||
| 439 | #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE |
||
| 440 | #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 |
||
| 441 | |||
| 442 | /** |
||
| 443 | * @} |
||
| 444 | */ |
||
| 445 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 446 | |||
| 447 | /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor |
||
| 448 | * @{ |
||
| 449 | */ |
||
| 450 | |||
| 451 | #define RCC_HSE_PREDIV_DIV1 0x00000000U |
||
| 452 | |||
| 453 | #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ |
||
| 454 | || defined(STM32F100xE) |
||
| 455 | #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 |
||
| 456 | #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 |
||
| 457 | #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 |
||
| 458 | #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 |
||
| 459 | #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 |
||
| 460 | #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 |
||
| 461 | #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 |
||
| 462 | #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 |
||
| 463 | #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 |
||
| 464 | #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 |
||
| 465 | #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 |
||
| 466 | #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 |
||
| 467 | #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 |
||
| 468 | #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 |
||
| 469 | #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 |
||
| 470 | #else |
||
| 471 | #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE |
||
| 472 | #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ |
||
| 473 | |||
| 474 | /** |
||
| 475 | * @} |
||
| 476 | */ |
||
| 477 | |||
| 478 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 479 | /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor |
||
| 480 | * @{ |
||
| 481 | */ |
||
| 482 | |||
| 483 | #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ |
||
| 484 | #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ |
||
| 485 | #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ |
||
| 486 | #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ |
||
| 487 | #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ |
||
| 488 | #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ |
||
| 489 | #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ |
||
| 490 | #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ |
||
| 491 | #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ |
||
| 492 | #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ |
||
| 493 | #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ |
||
| 494 | #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ |
||
| 495 | #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ |
||
| 496 | #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ |
||
| 497 | #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ |
||
| 498 | #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ |
||
| 499 | |||
| 500 | /** |
||
| 501 | * @} |
||
| 502 | */ |
||
| 503 | |||
| 504 | /** @defgroup RCCEx_PLL2_Config PLL Config |
||
| 505 | * @{ |
||
| 506 | */ |
||
| 507 | #define RCC_PLL2_NONE 0x00000000U |
||
| 508 | #define RCC_PLL2_OFF 0x00000001U |
||
| 509 | #define RCC_PLL2_ON 0x00000002U |
||
| 510 | |||
| 511 | /** |
||
| 512 | * @} |
||
| 513 | */ |
||
| 514 | |||
| 515 | /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor |
||
| 516 | * @{ |
||
| 517 | */ |
||
| 518 | |||
| 519 | #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ |
||
| 520 | #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ |
||
| 521 | #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ |
||
| 522 | #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ |
||
| 523 | #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ |
||
| 524 | #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ |
||
| 525 | #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ |
||
| 526 | #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ |
||
| 527 | #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ |
||
| 528 | |||
| 529 | /** |
||
| 530 | * @} |
||
| 531 | */ |
||
| 532 | |||
| 533 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 534 | |||
| 535 | /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor |
||
| 536 | * @{ |
||
| 537 | */ |
||
| 538 | |||
| 539 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 540 | #else |
||
| 541 | #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 |
||
| 542 | #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 |
||
| 543 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 544 | #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 |
||
| 545 | #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 |
||
| 546 | #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 |
||
| 547 | #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 |
||
| 548 | #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 |
||
| 549 | #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 |
||
| 550 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 551 | #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 |
||
| 552 | #else |
||
| 553 | #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 |
||
| 554 | #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 |
||
| 555 | #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 |
||
| 556 | #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 |
||
| 557 | #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 |
||
| 558 | #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 |
||
| 559 | #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 |
||
| 560 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 561 | |||
| 562 | /** |
||
| 563 | * @} |
||
| 564 | */ |
||
| 565 | |||
| 566 | /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source |
||
| 567 | * @{ |
||
| 568 | */ |
||
| 569 | #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) |
||
| 570 | #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) |
||
| 571 | #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) |
||
| 572 | #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) |
||
| 573 | #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) |
||
| 574 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 575 | #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) |
||
| 576 | #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) |
||
| 577 | #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) |
||
| 578 | #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) |
||
| 579 | #endif /* STM32F105xC || STM32F107xC*/ |
||
| 580 | /** |
||
| 581 | * @} |
||
| 582 | */ |
||
| 583 | |||
| 584 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 585 | /** @defgroup RCCEx_Interrupt RCCEx Interrupt |
||
| 586 | * @{ |
||
| 587 | */ |
||
| 588 | #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) |
||
| 589 | #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) |
||
| 590 | /** |
||
| 591 | * @} |
||
| 592 | */ |
||
| 593 | |||
| 594 | /** @defgroup RCCEx_Flag RCCEx Flag |
||
| 595 | * Elements values convention: 0XXYYYYYb |
||
| 596 | * - YYYYY : Flag position in the register |
||
| 597 | * - XX : Register index |
||
| 598 | * - 01: CR register |
||
| 599 | * @{ |
||
| 600 | */ |
||
| 601 | /* Flags in the CR register */ |
||
| 602 | #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) |
||
| 603 | #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) |
||
| 604 | /** |
||
| 605 | * @} |
||
| 606 | */ |
||
| 607 | #endif /* STM32F105xC || STM32F107xC*/ |
||
| 608 | |||
| 609 | /** |
||
| 610 | * @} |
||
| 611 | */ |
||
| 612 | |||
| 613 | /* Exported macro ------------------------------------------------------------*/ |
||
| 614 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
||
| 615 | * @{ |
||
| 616 | */ |
||
| 617 | |||
| 618 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable |
||
| 619 | * @brief Enable or disable the AHB1 peripheral clock. |
||
| 620 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 621 | * is disabled and the application software has to enable this clock before |
||
| 622 | * using it. |
||
| 623 | * @{ |
||
| 624 | */ |
||
| 625 | |||
| 626 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 627 | || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ |
||
| 628 | || defined (STM32F100xE) |
||
| 629 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
||
| 630 | __IO uint32_t tmpreg; \ |
||
| 631 | SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
||
| 632 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 633 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
||
| 634 | UNUSED(tmpreg); \ |
||
| 635 | } while(0U) |
||
| 636 | |||
| 637 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) |
||
| 638 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ |
||
| 639 | |||
| 640 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 641 | || defined(STM32F103xG) || defined (STM32F100xE) |
||
| 642 | #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ |
||
| 643 | __IO uint32_t tmpreg; \ |
||
| 644 | SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ |
||
| 645 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 646 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ |
||
| 647 | UNUSED(tmpreg); \ |
||
| 648 | } while(0U) |
||
| 649 | |||
| 650 | #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) |
||
| 651 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ |
||
| 652 | |||
| 653 | #if defined(STM32F103xE) || defined(STM32F103xG) |
||
| 654 | #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ |
||
| 655 | __IO uint32_t tmpreg; \ |
||
| 656 | SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ |
||
| 657 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 658 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ |
||
| 659 | UNUSED(tmpreg); \ |
||
| 660 | } while(0U) |
||
| 661 | |||
| 662 | |||
| 663 | #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) |
||
| 664 | #endif /* STM32F103xE || STM32F103xG */ |
||
| 665 | |||
| 666 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 667 | #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ |
||
| 668 | __IO uint32_t tmpreg; \ |
||
| 669 | SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ |
||
| 670 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 671 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ |
||
| 672 | UNUSED(tmpreg); \ |
||
| 673 | } while(0U) |
||
| 674 | |||
| 675 | |||
| 676 | #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) |
||
| 677 | #endif /* STM32F105xC || STM32F107xC*/ |
||
| 678 | |||
| 679 | #if defined(STM32F107xC) |
||
| 680 | #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ |
||
| 681 | __IO uint32_t tmpreg; \ |
||
| 682 | SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ |
||
| 683 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 684 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ |
||
| 685 | UNUSED(tmpreg); \ |
||
| 686 | } while(0U) |
||
| 687 | |||
| 688 | #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ |
||
| 689 | __IO uint32_t tmpreg; \ |
||
| 690 | SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ |
||
| 691 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 692 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ |
||
| 693 | UNUSED(tmpreg); \ |
||
| 694 | } while(0U) |
||
| 695 | |||
| 696 | #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ |
||
| 697 | __IO uint32_t tmpreg; \ |
||
| 698 | SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ |
||
| 699 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 700 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ |
||
| 701 | UNUSED(tmpreg); \ |
||
| 702 | } while(0U) |
||
| 703 | |||
| 704 | #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) |
||
| 705 | #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) |
||
| 706 | #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) |
||
| 707 | |||
| 708 | /** |
||
| 709 | * @brief Enable ETHERNET clock. |
||
| 710 | */ |
||
| 711 | #define __HAL_RCC_ETH_CLK_ENABLE() do { \ |
||
| 712 | __HAL_RCC_ETHMAC_CLK_ENABLE(); \ |
||
| 713 | __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ |
||
| 714 | __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ |
||
| 715 | } while(0U) |
||
| 716 | /** |
||
| 717 | * @brief Disable ETHERNET clock. |
||
| 718 | */ |
||
| 719 | #define __HAL_RCC_ETH_CLK_DISABLE() do { \ |
||
| 720 | __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ |
||
| 721 | __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ |
||
| 722 | __HAL_RCC_ETHMAC_CLK_DISABLE(); \ |
||
| 723 | } while(0U) |
||
| 724 | |||
| 725 | #endif /* STM32F107xC*/ |
||
| 726 | |||
| 727 | /** |
||
| 728 | * @} |
||
| 729 | */ |
||
| 730 | |||
| 731 | /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status |
||
| 732 | * @brief Get the enable or disable status of the AHB1 peripheral clock. |
||
| 733 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 734 | * is disabled and the application software has to enable this clock before |
||
| 735 | * using it. |
||
| 736 | * @{ |
||
| 737 | */ |
||
| 738 | |||
| 739 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 740 | || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ |
||
| 741 | || defined (STM32F100xE) |
||
| 742 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) |
||
| 743 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) |
||
| 744 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ |
||
| 745 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 746 | || defined(STM32F103xG) || defined (STM32F100xE) |
||
| 747 | #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) |
||
| 748 | #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) |
||
| 749 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ |
||
| 750 | #if defined(STM32F103xE) || defined(STM32F103xG) |
||
| 751 | #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) |
||
| 752 | #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) |
||
| 753 | #endif /* STM32F103xE || STM32F103xG */ |
||
| 754 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 755 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) |
||
| 756 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) |
||
| 757 | #endif /* STM32F105xC || STM32F107xC*/ |
||
| 758 | #if defined(STM32F107xC) |
||
| 759 | #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) |
||
| 760 | #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) |
||
| 761 | #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) |
||
| 762 | #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) |
||
| 763 | #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) |
||
| 764 | #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) |
||
| 765 | #endif /* STM32F107xC*/ |
||
| 766 | |||
| 767 | /** |
||
| 768 | * @} |
||
| 769 | */ |
||
| 770 | |||
| 771 | /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable |
||
| 772 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
||
| 773 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 774 | * is disabled and the application software has to enable this clock before |
||
| 775 | * using it. |
||
| 776 | * @{ |
||
| 777 | */ |
||
| 778 | |||
| 779 | #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ |
||
| 780 | || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) |
||
| 781 | #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
||
| 782 | __IO uint32_t tmpreg; \ |
||
| 783 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
||
| 784 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 785 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
||
| 786 | UNUSED(tmpreg); \ |
||
| 787 | } while(0U) |
||
| 788 | |||
| 789 | #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
||
| 790 | #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||
| 791 | |||
| 792 | #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ |
||
| 793 | || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ |
||
| 794 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
||
| 795 | || defined(STM32F105xC) || defined(STM32F107xC) |
||
| 796 | #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ |
||
| 797 | __IO uint32_t tmpreg; \ |
||
| 798 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
||
| 799 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 800 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
||
| 801 | UNUSED(tmpreg); \ |
||
| 802 | } while(0U) |
||
| 803 | |||
| 804 | #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ |
||
| 805 | __IO uint32_t tmpreg; \ |
||
| 806 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
||
| 807 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 808 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
||
| 809 | UNUSED(tmpreg); \ |
||
| 810 | } while(0U) |
||
| 811 | |||
| 812 | #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
||
| 813 | __IO uint32_t tmpreg; \ |
||
| 814 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
||
| 815 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 816 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
||
| 817 | UNUSED(tmpreg); \ |
||
| 818 | } while(0U) |
||
| 819 | |||
| 820 | #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ |
||
| 821 | __IO uint32_t tmpreg; \ |
||
| 822 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
||
| 823 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 824 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
||
| 825 | UNUSED(tmpreg); \ |
||
| 826 | } while(0U) |
||
| 827 | |||
| 828 | #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
||
| 829 | #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
||
| 830 | #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
||
| 831 | #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
||
| 832 | #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ |
||
| 833 | |||
| 834 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
||
| 835 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) |
||
| 836 | #define __HAL_RCC_USB_CLK_ENABLE() do { \ |
||
| 837 | __IO uint32_t tmpreg; \ |
||
| 838 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ |
||
| 839 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 840 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ |
||
| 841 | UNUSED(tmpreg); \ |
||
| 842 | } while(0U) |
||
| 843 | |||
| 844 | #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) |
||
| 845 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ |
||
| 846 | |||
| 847 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 848 | || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) |
||
| 849 | #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ |
||
| 850 | __IO uint32_t tmpreg; \ |
||
| 851 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
||
| 852 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 853 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
||
| 854 | UNUSED(tmpreg); \ |
||
| 855 | } while(0U) |
||
| 856 | |||
| 857 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
||
| 858 | __IO uint32_t tmpreg; \ |
||
| 859 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
||
| 860 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 861 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
||
| 862 | UNUSED(tmpreg); \ |
||
| 863 | } while(0U) |
||
| 864 | |||
| 865 | #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
||
| 866 | __IO uint32_t tmpreg; \ |
||
| 867 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
||
| 868 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 869 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
||
| 870 | UNUSED(tmpreg); \ |
||
| 871 | } while(0U) |
||
| 872 | |||
| 873 | #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
||
| 874 | __IO uint32_t tmpreg; \ |
||
| 875 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
||
| 876 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 877 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
||
| 878 | UNUSED(tmpreg); \ |
||
| 879 | } while(0U) |
||
| 880 | |||
| 881 | #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
||
| 882 | __IO uint32_t tmpreg; \ |
||
| 883 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
||
| 884 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 885 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
||
| 886 | UNUSED(tmpreg); \ |
||
| 887 | } while(0U) |
||
| 888 | |||
| 889 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
||
| 890 | __IO uint32_t tmpreg; \ |
||
| 891 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
||
| 892 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 893 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
||
| 894 | UNUSED(tmpreg); \ |
||
| 895 | } while(0U) |
||
| 896 | |||
| 897 | #define __HAL_RCC_DAC_CLK_ENABLE() do { \ |
||
| 898 | __IO uint32_t tmpreg; \ |
||
| 899 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
||
| 900 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 901 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
||
| 902 | UNUSED(tmpreg); \ |
||
| 903 | } while(0U) |
||
| 904 | |||
| 905 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
||
| 906 | #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
||
| 907 | #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
||
| 908 | #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
||
| 909 | #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
||
| 910 | #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
||
| 911 | #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
||
| 912 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ |
||
| 913 | |||
| 914 | #if defined(STM32F100xB) || defined (STM32F100xE) |
||
| 915 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
||
| 916 | __IO uint32_t tmpreg; \ |
||
| 917 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
||
| 918 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 919 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
||
| 920 | UNUSED(tmpreg); \ |
||
| 921 | } while(0U) |
||
| 922 | |||
| 923 | #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
||
| 924 | __IO uint32_t tmpreg; \ |
||
| 925 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
||
| 926 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 927 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
||
| 928 | UNUSED(tmpreg); \ |
||
| 929 | } while(0U) |
||
| 930 | |||
| 931 | #define __HAL_RCC_DAC_CLK_ENABLE() do { \ |
||
| 932 | __IO uint32_t tmpreg; \ |
||
| 933 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
||
| 934 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 935 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
||
| 936 | UNUSED(tmpreg); \ |
||
| 937 | } while(0U) |
||
| 938 | |||
| 939 | #define __HAL_RCC_CEC_CLK_ENABLE() do { \ |
||
| 940 | __IO uint32_t tmpreg; \ |
||
| 941 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
||
| 942 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 943 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
||
| 944 | UNUSED(tmpreg); \ |
||
| 945 | } while(0U) |
||
| 946 | |||
| 947 | #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
||
| 948 | #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
||
| 949 | #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
||
| 950 | #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) |
||
| 951 | #endif /* STM32F100xB || STM32F100xE */ |
||
| 952 | |||
| 953 | #ifdef STM32F100xE |
||
| 954 | #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ |
||
| 955 | __IO uint32_t tmpreg; \ |
||
| 956 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
||
| 957 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 958 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
||
| 959 | UNUSED(tmpreg); \ |
||
| 960 | } while(0U) |
||
| 961 | |||
| 962 | #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ |
||
| 963 | __IO uint32_t tmpreg; \ |
||
| 964 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
||
| 965 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 966 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
||
| 967 | UNUSED(tmpreg); \ |
||
| 968 | } while(0U) |
||
| 969 | |||
| 970 | #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ |
||
| 971 | __IO uint32_t tmpreg; \ |
||
| 972 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
||
| 973 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 974 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
||
| 975 | UNUSED(tmpreg); \ |
||
| 976 | } while(0U) |
||
| 977 | |||
| 978 | #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
||
| 979 | __IO uint32_t tmpreg; \ |
||
| 980 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
||
| 981 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 982 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
||
| 983 | UNUSED(tmpreg); \ |
||
| 984 | } while(0U) |
||
| 985 | |||
| 986 | #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
||
| 987 | __IO uint32_t tmpreg; \ |
||
| 988 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
||
| 989 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 990 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
||
| 991 | UNUSED(tmpreg); \ |
||
| 992 | } while(0U) |
||
| 993 | |||
| 994 | #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
||
| 995 | __IO uint32_t tmpreg; \ |
||
| 996 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
||
| 997 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 998 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
||
| 999 | UNUSED(tmpreg); \ |
||
| 1000 | } while(0U) |
||
| 1001 | |||
| 1002 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
||
| 1003 | __IO uint32_t tmpreg; \ |
||
| 1004 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
||
| 1005 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1006 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
||
| 1007 | UNUSED(tmpreg); \ |
||
| 1008 | } while(0U) |
||
| 1009 | |||
| 1010 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
||
| 1011 | #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
||
| 1012 | #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
||
| 1013 | #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
||
| 1014 | #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
||
| 1015 | #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
||
| 1016 | #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
||
| 1017 | #endif /* STM32F100xE */ |
||
| 1018 | |||
| 1019 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1020 | #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ |
||
| 1021 | __IO uint32_t tmpreg; \ |
||
| 1022 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
||
| 1023 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1024 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
||
| 1025 | UNUSED(tmpreg); \ |
||
| 1026 | } while(0U) |
||
| 1027 | |||
| 1028 | #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
||
| 1029 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 1030 | |||
| 1031 | #if defined(STM32F101xG) || defined(STM32F103xG) |
||
| 1032 | #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ |
||
| 1033 | __IO uint32_t tmpreg; \ |
||
| 1034 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
||
| 1035 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1036 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
||
| 1037 | UNUSED(tmpreg); \ |
||
| 1038 | } while(0U) |
||
| 1039 | |||
| 1040 | #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ |
||
| 1041 | __IO uint32_t tmpreg; \ |
||
| 1042 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
||
| 1043 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1044 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
||
| 1045 | UNUSED(tmpreg); \ |
||
| 1046 | } while(0U) |
||
| 1047 | |||
| 1048 | #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
||
| 1049 | __IO uint32_t tmpreg; \ |
||
| 1050 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
||
| 1051 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1052 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
||
| 1053 | UNUSED(tmpreg); \ |
||
| 1054 | } while(0U) |
||
| 1055 | |||
| 1056 | #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
||
| 1057 | #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
||
| 1058 | #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
||
| 1059 | #endif /* STM32F101xG || STM32F103xG*/ |
||
| 1060 | |||
| 1061 | /** |
||
| 1062 | * @} |
||
| 1063 | */ |
||
| 1064 | |||
| 1065 | /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
||
| 1066 | * @brief Get the enable or disable status of the APB1 peripheral clock. |
||
| 1067 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 1068 | * is disabled and the application software has to enable this clock before |
||
| 1069 | * using it. |
||
| 1070 | * @{ |
||
| 1071 | */ |
||
| 1072 | |||
| 1073 | #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ |
||
| 1074 | || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) |
||
| 1075 | #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) |
||
| 1076 | #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) |
||
| 1077 | #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||
| 1078 | #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ |
||
| 1079 | || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ |
||
| 1080 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
||
| 1081 | || defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1082 | #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) |
||
| 1083 | #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) |
||
| 1084 | #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) |
||
| 1085 | #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) |
||
| 1086 | #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) |
||
| 1087 | #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) |
||
| 1088 | #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) |
||
| 1089 | #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) |
||
| 1090 | #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ |
||
| 1091 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
||
| 1092 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) |
||
| 1093 | #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) |
||
| 1094 | #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) |
||
| 1095 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ |
||
| 1096 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 1097 | || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1098 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) |
||
| 1099 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) |
||
| 1100 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
||
| 1101 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
||
| 1102 | #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) |
||
| 1103 | #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) |
||
| 1104 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) |
||
| 1105 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) |
||
| 1106 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) |
||
| 1107 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) |
||
| 1108 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) |
||
| 1109 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) |
||
| 1110 | #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) |
||
| 1111 | #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) |
||
| 1112 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ |
||
| 1113 | #if defined(STM32F100xB) || defined (STM32F100xE) |
||
| 1114 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
||
| 1115 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
||
| 1116 | #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) |
||
| 1117 | #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) |
||
| 1118 | #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) |
||
| 1119 | #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) |
||
| 1120 | #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) |
||
| 1121 | #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) |
||
| 1122 | #endif /* STM32F100xB || STM32F100xE */ |
||
| 1123 | #ifdef STM32F100xE |
||
| 1124 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) |
||
| 1125 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) |
||
| 1126 | #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) |
||
| 1127 | #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) |
||
| 1128 | #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) |
||
| 1129 | #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) |
||
| 1130 | #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) |
||
| 1131 | #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) |
||
| 1132 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) |
||
| 1133 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) |
||
| 1134 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) |
||
| 1135 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) |
||
| 1136 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) |
||
| 1137 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) |
||
| 1138 | #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) |
||
| 1139 | #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) |
||
| 1140 | #endif /* STM32F100xE */ |
||
| 1141 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1142 | #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) |
||
| 1143 | #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) |
||
| 1144 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 1145 | #if defined(STM32F101xG) || defined(STM32F103xG) |
||
| 1146 | #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) |
||
| 1147 | #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) |
||
| 1148 | #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) |
||
| 1149 | #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) |
||
| 1150 | #endif /* STM32F101xG || STM32F103xG*/ |
||
| 1151 | |||
| 1152 | /** |
||
| 1153 | * @} |
||
| 1154 | */ |
||
| 1155 | |||
| 1156 | /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable |
||
| 1157 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
||
| 1158 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 1159 | * is disabled and the application software has to enable this clock before |
||
| 1160 | * using it. |
||
| 1161 | * @{ |
||
| 1162 | */ |
||
| 1163 | |||
| 1164 | #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ |
||
| 1165 | || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ |
||
| 1166 | || defined(STM32F103xG) |
||
| 1167 | #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ |
||
| 1168 | __IO uint32_t tmpreg; \ |
||
| 1169 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
||
| 1170 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1171 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
||
| 1172 | UNUSED(tmpreg); \ |
||
| 1173 | } while(0U) |
||
| 1174 | |||
| 1175 | #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
||
| 1176 | #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ |
||
| 1177 | |||
| 1178 | #if defined(STM32F100xB) || defined(STM32F100xE) |
||
| 1179 | #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ |
||
| 1180 | __IO uint32_t tmpreg; \ |
||
| 1181 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
||
| 1182 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1183 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
||
| 1184 | UNUSED(tmpreg); \ |
||
| 1185 | } while(0U) |
||
| 1186 | |||
| 1187 | #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ |
||
| 1188 | __IO uint32_t tmpreg; \ |
||
| 1189 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ |
||
| 1190 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1191 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ |
||
| 1192 | UNUSED(tmpreg); \ |
||
| 1193 | } while(0U) |
||
| 1194 | |||
| 1195 | #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ |
||
| 1196 | __IO uint32_t tmpreg; \ |
||
| 1197 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ |
||
| 1198 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1199 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ |
||
| 1200 | UNUSED(tmpreg); \ |
||
| 1201 | } while(0U) |
||
| 1202 | |||
| 1203 | #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) |
||
| 1204 | #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) |
||
| 1205 | #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) |
||
| 1206 | #endif /* STM32F100xB || STM32F100xE */ |
||
| 1207 | |||
| 1208 | #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ |
||
| 1209 | || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ |
||
| 1210 | || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ |
||
| 1211 | || defined(STM32F107xC) |
||
| 1212 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
||
| 1213 | __IO uint32_t tmpreg; \ |
||
| 1214 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ |
||
| 1215 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1216 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ |
||
| 1217 | UNUSED(tmpreg); \ |
||
| 1218 | } while(0U) |
||
| 1219 | |||
| 1220 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) |
||
| 1221 | #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ |
||
| 1222 | |||
| 1223 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 1224 | || defined(STM32F103xG) |
||
| 1225 | #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
||
| 1226 | __IO uint32_t tmpreg; \ |
||
| 1227 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ |
||
| 1228 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1229 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ |
||
| 1230 | UNUSED(tmpreg); \ |
||
| 1231 | } while(0U) |
||
| 1232 | |||
| 1233 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
||
| 1234 | __IO uint32_t tmpreg; \ |
||
| 1235 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ |
||
| 1236 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1237 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ |
||
| 1238 | UNUSED(tmpreg); \ |
||
| 1239 | } while(0U) |
||
| 1240 | |||
| 1241 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) |
||
| 1242 | #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) |
||
| 1243 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ |
||
| 1244 | |||
| 1245 | #if defined(STM32F103xE) || defined(STM32F103xG) |
||
| 1246 | #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ |
||
| 1247 | __IO uint32_t tmpreg; \ |
||
| 1248 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
||
| 1249 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1250 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
||
| 1251 | UNUSED(tmpreg); \ |
||
| 1252 | } while(0U) |
||
| 1253 | |||
| 1254 | #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ |
||
| 1255 | __IO uint32_t tmpreg; \ |
||
| 1256 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
||
| 1257 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1258 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
||
| 1259 | UNUSED(tmpreg); \ |
||
| 1260 | } while(0U) |
||
| 1261 | |||
| 1262 | #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
||
| 1263 | #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
||
| 1264 | #endif /* STM32F103xE || STM32F103xG */ |
||
| 1265 | |||
| 1266 | #if defined(STM32F100xE) |
||
| 1267 | #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
||
| 1268 | __IO uint32_t tmpreg; \ |
||
| 1269 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ |
||
| 1270 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1271 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ |
||
| 1272 | UNUSED(tmpreg); \ |
||
| 1273 | } while(0U) |
||
| 1274 | |||
| 1275 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
||
| 1276 | __IO uint32_t tmpreg; \ |
||
| 1277 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ |
||
| 1278 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1279 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ |
||
| 1280 | UNUSED(tmpreg); \ |
||
| 1281 | } while(0U) |
||
| 1282 | |||
| 1283 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) |
||
| 1284 | #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) |
||
| 1285 | #endif /* STM32F100xE */ |
||
| 1286 | |||
| 1287 | #if defined(STM32F101xG) || defined(STM32F103xG) |
||
| 1288 | #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ |
||
| 1289 | __IO uint32_t tmpreg; \ |
||
| 1290 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
||
| 1291 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1292 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
||
| 1293 | UNUSED(tmpreg); \ |
||
| 1294 | } while(0U) |
||
| 1295 | |||
| 1296 | #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ |
||
| 1297 | __IO uint32_t tmpreg; \ |
||
| 1298 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
||
| 1299 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1300 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
||
| 1301 | UNUSED(tmpreg); \ |
||
| 1302 | } while(0U) |
||
| 1303 | |||
| 1304 | #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ |
||
| 1305 | __IO uint32_t tmpreg; \ |
||
| 1306 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
||
| 1307 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1308 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
||
| 1309 | UNUSED(tmpreg); \ |
||
| 1310 | } while(0U) |
||
| 1311 | |||
| 1312 | #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) |
||
| 1313 | #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) |
||
| 1314 | #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) |
||
| 1315 | #endif /* STM32F101xG || STM32F103xG */ |
||
| 1316 | |||
| 1317 | /** |
||
| 1318 | * @} |
||
| 1319 | */ |
||
| 1320 | |||
| 1321 | /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status |
||
| 1322 | * @brief Get the enable or disable status of the APB2 peripheral clock. |
||
| 1323 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 1324 | * is disabled and the application software has to enable this clock before |
||
| 1325 | * using it. |
||
| 1326 | * @{ |
||
| 1327 | */ |
||
| 1328 | |||
| 1329 | #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ |
||
| 1330 | || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ |
||
| 1331 | || defined(STM32F103xG) |
||
| 1332 | #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) |
||
| 1333 | #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) |
||
| 1334 | #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ |
||
| 1335 | #if defined(STM32F100xB) || defined(STM32F100xE) |
||
| 1336 | #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) |
||
| 1337 | #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) |
||
| 1338 | #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) |
||
| 1339 | #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) |
||
| 1340 | #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) |
||
| 1341 | #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) |
||
| 1342 | #endif /* STM32F100xB || STM32F100xE */ |
||
| 1343 | #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ |
||
| 1344 | || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ |
||
| 1345 | || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ |
||
| 1346 | || defined(STM32F107xC) |
||
| 1347 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) |
||
| 1348 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) |
||
| 1349 | #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ |
||
| 1350 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 1351 | || defined(STM32F103xG) |
||
| 1352 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) |
||
| 1353 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) |
||
| 1354 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) |
||
| 1355 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) |
||
| 1356 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ |
||
| 1357 | #if defined(STM32F103xE) || defined(STM32F103xG) |
||
| 1358 | #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) |
||
| 1359 | #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) |
||
| 1360 | #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) |
||
| 1361 | #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) |
||
| 1362 | #endif /* STM32F103xE || STM32F103xG */ |
||
| 1363 | #if defined(STM32F100xE) |
||
| 1364 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) |
||
| 1365 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) |
||
| 1366 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) |
||
| 1367 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) |
||
| 1368 | #endif /* STM32F100xE */ |
||
| 1369 | #if defined(STM32F101xG) || defined(STM32F103xG) |
||
| 1370 | #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) |
||
| 1371 | #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) |
||
| 1372 | #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) |
||
| 1373 | #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) |
||
| 1374 | #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) |
||
| 1375 | #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) |
||
| 1376 | #endif /* STM32F101xG || STM32F103xG */ |
||
| 1377 | |||
| 1378 | /** |
||
| 1379 | * @} |
||
| 1380 | */ |
||
| 1381 | |||
| 1382 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1383 | /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release |
||
| 1384 | * @brief Force or release AHB peripheral reset. |
||
| 1385 | * @{ |
||
| 1386 | */ |
||
| 1387 | #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) |
||
| 1388 | #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) |
||
| 1389 | #if defined(STM32F107xC) |
||
| 1390 | #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) |
||
| 1391 | #endif /* STM32F107xC */ |
||
| 1392 | |||
| 1393 | #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) |
||
| 1394 | #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) |
||
| 1395 | #if defined(STM32F107xC) |
||
| 1396 | #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) |
||
| 1397 | #endif /* STM32F107xC */ |
||
| 1398 | |||
| 1399 | /** |
||
| 1400 | * @} |
||
| 1401 | */ |
||
| 1402 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 1403 | |||
| 1404 | /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset |
||
| 1405 | * @brief Force or release APB1 peripheral reset. |
||
| 1406 | * @{ |
||
| 1407 | */ |
||
| 1408 | |||
| 1409 | #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ |
||
| 1410 | || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) |
||
| 1411 | #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) |
||
| 1412 | |||
| 1413 | #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) |
||
| 1414 | #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||
| 1415 | |||
| 1416 | #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ |
||
| 1417 | || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ |
||
| 1418 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ |
||
| 1419 | || defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1420 | #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) |
||
| 1421 | #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
||
| 1422 | #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
||
| 1423 | #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
||
| 1424 | |||
| 1425 | #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) |
||
| 1426 | #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
||
| 1427 | #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
||
| 1428 | #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
||
| 1429 | #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ |
||
| 1430 | |||
| 1431 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
||
| 1432 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) |
||
| 1433 | #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) |
||
| 1434 | #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) |
||
| 1435 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ |
||
| 1436 | |||
| 1437 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 1438 | || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1439 | #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) |
||
| 1440 | #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
||
| 1441 | #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
||
| 1442 | #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
||
| 1443 | #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
||
| 1444 | #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
||
| 1445 | #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
||
| 1446 | |||
| 1447 | #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) |
||
| 1448 | #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
||
| 1449 | #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
||
| 1450 | #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
||
| 1451 | #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
||
| 1452 | #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
||
| 1453 | #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
||
| 1454 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ |
||
| 1455 | |||
| 1456 | #if defined(STM32F100xB) || defined (STM32F100xE) |
||
| 1457 | #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
||
| 1458 | #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
||
| 1459 | #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
||
| 1460 | #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) |
||
| 1461 | |||
| 1462 | #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
||
| 1463 | #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
||
| 1464 | #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
||
| 1465 | #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) |
||
| 1466 | #endif /* STM32F100xB || STM32F100xE */ |
||
| 1467 | |||
| 1468 | #if defined (STM32F100xE) |
||
| 1469 | #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) |
||
| 1470 | #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
||
| 1471 | #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
||
| 1472 | #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
||
| 1473 | #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
||
| 1474 | #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
||
| 1475 | #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
||
| 1476 | |||
| 1477 | #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) |
||
| 1478 | #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
||
| 1479 | #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
||
| 1480 | #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
||
| 1481 | #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
||
| 1482 | #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
||
| 1483 | #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
||
| 1484 | #endif /* STM32F100xE */ |
||
| 1485 | |||
| 1486 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1487 | #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) |
||
| 1488 | |||
| 1489 | #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) |
||
| 1490 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 1491 | |||
| 1492 | #if defined(STM32F101xG) || defined(STM32F103xG) |
||
| 1493 | #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
||
| 1494 | #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
||
| 1495 | #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
||
| 1496 | |||
| 1497 | #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
||
| 1498 | #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
||
| 1499 | #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
||
| 1500 | #endif /* STM32F101xG || STM32F103xG */ |
||
| 1501 | |||
| 1502 | /** |
||
| 1503 | * @} |
||
| 1504 | */ |
||
| 1505 | |||
| 1506 | /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset |
||
| 1507 | * @brief Force or release APB2 peripheral reset. |
||
| 1508 | * @{ |
||
| 1509 | */ |
||
| 1510 | |||
| 1511 | #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ |
||
| 1512 | || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ |
||
| 1513 | || defined(STM32F103xG) |
||
| 1514 | #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) |
||
| 1515 | |||
| 1516 | #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) |
||
| 1517 | #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ |
||
| 1518 | |||
| 1519 | #if defined(STM32F100xB) || defined(STM32F100xE) |
||
| 1520 | #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) |
||
| 1521 | #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) |
||
| 1522 | #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) |
||
| 1523 | |||
| 1524 | #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) |
||
| 1525 | #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) |
||
| 1526 | #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) |
||
| 1527 | #endif /* STM32F100xB || STM32F100xE */ |
||
| 1528 | |||
| 1529 | #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ |
||
| 1530 | || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ |
||
| 1531 | || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ |
||
| 1532 | || defined(STM32F107xC) |
||
| 1533 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) |
||
| 1534 | |||
| 1535 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) |
||
| 1536 | #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ |
||
| 1537 | |||
| 1538 | #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ |
||
| 1539 | || defined(STM32F103xG) |
||
| 1540 | #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) |
||
| 1541 | #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) |
||
| 1542 | |||
| 1543 | #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) |
||
| 1544 | #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) |
||
| 1545 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ |
||
| 1546 | |||
| 1547 | #if defined(STM32F103xE) || defined(STM32F103xG) |
||
| 1548 | #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) |
||
| 1549 | #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) |
||
| 1550 | |||
| 1551 | #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) |
||
| 1552 | #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) |
||
| 1553 | #endif /* STM32F103xE || STM32F103xG */ |
||
| 1554 | |||
| 1555 | #if defined(STM32F100xE) |
||
| 1556 | #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) |
||
| 1557 | #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) |
||
| 1558 | |||
| 1559 | #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) |
||
| 1560 | #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) |
||
| 1561 | #endif /* STM32F100xE */ |
||
| 1562 | |||
| 1563 | #if defined(STM32F101xG) || defined(STM32F103xG) |
||
| 1564 | #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) |
||
| 1565 | #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) |
||
| 1566 | #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) |
||
| 1567 | |||
| 1568 | #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) |
||
| 1569 | #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) |
||
| 1570 | #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) |
||
| 1571 | #endif /* STM32F101xG || STM32F103xG*/ |
||
| 1572 | |||
| 1573 | /** |
||
| 1574 | * @} |
||
| 1575 | */ |
||
| 1576 | |||
| 1577 | /** @defgroup RCCEx_HSE_Configuration HSE Configuration |
||
| 1578 | * @{ |
||
| 1579 | */ |
||
| 1580 | |||
| 1581 | #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ |
||
| 1582 | || defined(STM32F100xE) |
||
| 1583 | /** |
||
| 1584 | * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. |
||
| 1585 | * @note Predivision factor can not be changed if PLL is used as system clock |
||
| 1586 | * In this case, you have to select another source of the system clock, disable the PLL and |
||
| 1587 | * then change the HSE predivision factor. |
||
| 1588 | * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. |
||
| 1589 | * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. |
||
| 1590 | */ |
||
| 1591 | #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) |
||
| 1592 | #else |
||
| 1593 | /** |
||
| 1594 | * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. |
||
| 1595 | * @note Predivision factor can not be changed if PLL is used as system clock |
||
| 1596 | * In this case, you have to select another source of the system clock, disable the PLL and |
||
| 1597 | * then change the HSE predivision factor. |
||
| 1598 | * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. |
||
| 1599 | * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. |
||
| 1600 | */ |
||
| 1601 | #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ |
||
| 1602 | MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) |
||
| 1603 | |||
| 1604 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 1605 | |||
| 1606 | #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ |
||
| 1607 | || defined(STM32F100xE) |
||
| 1608 | /** |
||
| 1609 | * @brief Macro to get prediv1 factor for PLL. |
||
| 1610 | */ |
||
| 1611 | #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) |
||
| 1612 | |||
| 1613 | #else |
||
| 1614 | /** |
||
| 1615 | * @brief Macro to get prediv1 factor for PLL. |
||
| 1616 | */ |
||
| 1617 | #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) |
||
| 1618 | |||
| 1619 | #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ |
||
| 1620 | |||
| 1621 | /** |
||
| 1622 | * @} |
||
| 1623 | */ |
||
| 1624 | |||
| 1625 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1626 | /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration |
||
| 1627 | * @{ |
||
| 1628 | */ |
||
| 1629 | |||
| 1630 | /** @brief Macros to enable the main PLLI2S. |
||
| 1631 | * @note After enabling the main PLLI2S, the application software should wait on |
||
| 1632 | * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can |
||
| 1633 | * be used as system clock source. |
||
| 1634 | * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. |
||
| 1635 | */ |
||
| 1636 | #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) |
||
| 1637 | |||
| 1638 | /** @brief Macros to disable the main PLLI2S. |
||
| 1639 | * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. |
||
| 1640 | */ |
||
| 1641 | #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) |
||
| 1642 | |||
| 1643 | /** @brief macros to configure the main PLLI2S multiplication factor. |
||
| 1644 | * @note This function must be used only when the main PLLI2S is disabled. |
||
| 1645 | * |
||
| 1646 | * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock |
||
| 1647 | * This parameter can be one of the following values: |
||
| 1648 | * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 |
||
| 1649 | * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 |
||
| 1650 | * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 |
||
| 1651 | * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 |
||
| 1652 | * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 |
||
| 1653 | * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 |
||
| 1654 | * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 |
||
| 1655 | * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 |
||
| 1656 | * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 |
||
| 1657 | * |
||
| 1658 | */ |
||
| 1659 | #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ |
||
| 1660 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) |
||
| 1661 | |||
| 1662 | /** |
||
| 1663 | * @} |
||
| 1664 | */ |
||
| 1665 | |||
| 1666 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 1667 | |||
| 1668 | /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration |
||
| 1669 | * @brief Macros to configure clock source of different peripherals. |
||
| 1670 | * @{ |
||
| 1671 | */ |
||
| 1672 | |||
| 1673 | #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
||
| 1674 | || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) |
||
| 1675 | /** @brief Macro to configure the USB clock. |
||
| 1676 | * @param __USBCLKSOURCE__ specifies the USB clock source. |
||
| 1677 | * This parameter can be one of the following values: |
||
| 1678 | * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock |
||
| 1679 | * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock |
||
| 1680 | */ |
||
| 1681 | #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ |
||
| 1682 | MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) |
||
| 1683 | |||
| 1684 | /** @brief Macro to get the USB clock (USBCLK). |
||
| 1685 | * @retval The clock source can be one of the following values: |
||
| 1686 | * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock |
||
| 1687 | * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock |
||
| 1688 | */ |
||
| 1689 | #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) |
||
| 1690 | |||
| 1691 | #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ |
||
| 1692 | |||
| 1693 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1694 | |||
| 1695 | /** @brief Macro to configure the USB OTSclock. |
||
| 1696 | * @param __USBCLKSOURCE__ specifies the USB clock source. |
||
| 1697 | * This parameter can be one of the following values: |
||
| 1698 | * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock |
||
| 1699 | * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock |
||
| 1700 | */ |
||
| 1701 | #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ |
||
| 1702 | MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) |
||
| 1703 | |||
| 1704 | /** @brief Macro to get the USB clock (USBCLK). |
||
| 1705 | * @retval The clock source can be one of the following values: |
||
| 1706 | * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock |
||
| 1707 | * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock |
||
| 1708 | */ |
||
| 1709 | #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) |
||
| 1710 | |||
| 1711 | #endif /* STM32F105xC || STM32F107xC */ |
||
| 1712 | |||
| 1713 | /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). |
||
| 1714 | * @param __ADCCLKSOURCE__ specifies the ADC clock source. |
||
| 1715 | * This parameter can be one of the following values: |
||
| 1716 | * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock |
||
| 1717 | * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock |
||
| 1718 | * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock |
||
| 1719 | * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock |
||
| 1720 | */ |
||
| 1721 | #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ |
||
| 1722 | MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) |
||
| 1723 | |||
| 1724 | /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). |
||
| 1725 | * @retval The clock source can be one of the following values: |
||
| 1726 | * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock |
||
| 1727 | * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock |
||
| 1728 | * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock |
||
| 1729 | * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock |
||
| 1730 | */ |
||
| 1731 | #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) |
||
| 1732 | |||
| 1733 | /** |
||
| 1734 | * @} |
||
| 1735 | */ |
||
| 1736 | |||
| 1737 | #if defined(STM32F105xC) || defined(STM32F107xC) |
||
| 1738 | |||
| 1739 | /** @addtogroup RCCEx_HSE_Configuration |
||
| 1740 | * @{ |
||
| 1741 | */ |
||
| 1742 | |||
| 1743 | /** |
||
| 1744 | * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. |
||
| 1745 | * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock |
||
| 1746 | * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and |
||
| 1747 | * then change the PREDIV2 factor. |
||
| 1748 | * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. |
||
| 1749 | * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. |
||
| 1750 | */ |
||
| 1751 | #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ |
||
| 1752 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) |
||
| 1753 | |||
| 1754 | /** |
||
| 1755 | * @brief Macro to get prediv2 factor for PLL2 & PLL3. |
||
| 1756 | */ |
||
| 1757 | #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) |
||
| 1758 | |||
| 1759 | /** |
||
| 1760 | * @} |
||
| 1761 | */ |
||
| 1762 | |||
| 1763 | /** @addtogroup RCCEx_PLLI2S_Configuration |
||
| 1764 | * @{ |
||
| 1765 | */ |
||
| 1766 | |||
| 1767 | /** @brief Macros to enable the main PLL2. |
||
| 1768 | * @note After enabling the main PLL2, the application software should wait on |
||
| 1769 | * PLL2RDY flag to be set indicating that PLL2 clock is stable and can |
||
| 1770 | * be used as system clock source. |
||
| 1771 | * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. |
||
| 1772 | */ |
||
| 1773 | #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) |
||
| 1774 | |||
| 1775 | /** @brief Macros to disable the main PLL2. |
||
| 1776 | * @note The main PLL2 can not be disabled if it is used indirectly as system clock source |
||
| 1777 | * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. |
||
| 1778 | */ |
||
| 1779 | #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) |
||
| 1780 | |||
| 1781 | /** @brief macros to configure the main PLL2 multiplication factor. |
||
| 1782 | * @note This function must be used only when the main PLL2 is disabled. |
||
| 1783 | * |
||
| 1784 | * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock |
||
| 1785 | * This parameter can be one of the following values: |
||
| 1786 | * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 |
||
| 1787 | * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 |
||
| 1788 | * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 |
||
| 1789 | * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 |
||
| 1790 | * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 |
||
| 1791 | * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 |
||
| 1792 | * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 |
||
| 1793 | * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 |
||
| 1794 | * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 |
||
| 1795 | * |
||
| 1796 | */ |
||
| 1797 | #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ |
||
| 1798 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) |
||
| 1799 | |||
| 1800 | /** |
||
| 1801 | * @} |
||
| 1802 | */ |
||
| 1803 | |||
| 1804 | /** @defgroup RCCEx_I2S_Configuration I2S Configuration |
||
| 1805 | * @brief Macros to configure clock source of I2S peripherals. |
||
| 1806 | * @{ |
||
| 1807 | */ |
||
| 1808 | |||
| 1809 | /** @brief Macro to configure the I2S2 clock. |
||
| 1810 | * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. |
||
| 1811 | * This parameter can be one of the following values: |
||
| 1812 | * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry |
||
| 1813 | * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry |
||
| 1814 | */ |
||
| 1815 | #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ |
||
| 1816 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) |
||
| 1817 | |||
| 1818 | /** @brief Macro to get the I2S2 clock (I2S2CLK). |
||
| 1819 | * @retval The clock source can be one of the following values: |
||
| 1820 | * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry |
||
| 1821 | * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry |
||
| 1822 | */ |
||
| 1823 | #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) |
||
| 1824 | |||
| 1825 | /** @brief Macro to configure the I2S3 clock. |
||
| 1826 | * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. |
||
| 1827 | * This parameter can be one of the following values: |
||
| 1828 | * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry |
||
| 1829 | * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry |
||
| 1830 | */ |
||
| 1831 | #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ |
||
| 1832 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) |
||
| 1833 | |||
| 1834 | /** @brief Macro to get the I2S3 clock (I2S3CLK). |
||
| 1835 | * @retval The clock source can be one of the following values: |
||
| 1836 | * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry |
||
| 1837 | * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry |
||
| 1838 | */ |
||
| 1839 | #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) |
||
| 1840 | |||
| 1841 | /** |
||
| 1842 | * @} |
||
| 1843 | */ |
||
| 1844 | |||
| 1845 | #endif /* STM32F105xC || STM32F107xC */ |
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| 1846 | /** |
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| 1847 | * @} |
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| 1848 | */ |
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| 1849 | |||
| 1850 | /* Exported functions --------------------------------------------------------*/ |
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| 1851 | /** @addtogroup RCCEx_Exported_Functions |
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| 1852 | * @{ |
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| 1853 | */ |
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| 1854 | |||
| 1855 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
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| 1856 | * @{ |
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| 1857 | */ |
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| 1858 | |||
| 1859 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
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| 1860 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
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| 1861 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
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| 1862 | |||
| 1863 | /** |
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| 1864 | * @} |
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| 1865 | */ |
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| 1866 | |||
| 1867 | #if defined(STM32F105xC) || defined(STM32F107xC) |
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| 1868 | /** @addtogroup RCCEx_Exported_Functions_Group2 |
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| 1869 | * @{ |
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| 1870 | */ |
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| 1871 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); |
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| 1872 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); |
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| 1873 | |||
| 1874 | /** |
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| 1875 | * @} |
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| 1876 | */ |
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| 1877 | |||
| 1878 | /** @addtogroup RCCEx_Exported_Functions_Group3 |
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| 1879 | * @{ |
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| 1880 | */ |
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| 1881 | HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); |
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| 1882 | HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); |
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| 1883 | |||
| 1884 | /** |
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| 1885 | * @} |
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| 1886 | */ |
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| 1887 | #endif /* STM32F105xC || STM32F107xC */ |
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| 1888 | |||
| 1889 | /** |
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| 1890 | * @} |
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| 1891 | */ |
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| 1892 | |||
| 1893 | /** |
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| 1894 | * @} |
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| 1895 | */ |
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| 1896 | |||
| 1897 | /** |
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| 1898 | * @} |
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| 1899 | */ |
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| 1900 | |||
| 1901 | #ifdef __cplusplus |
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| 1902 | } |
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| 1903 | #endif |
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| 1904 | |||
| 1905 | #endif /* __STM32F1xx_HAL_RCC_EX_H */ |
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| 1906 | |||
| 1907 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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| 1908 |