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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_nor.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of NOR HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef STM32F1xx_HAL_NOR_H |
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| 22 | #define STM32F1xx_HAL_NOR_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | #if defined FSMC_BANK1 |
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| 29 | |||
| 30 | /* Includes ------------------------------------------------------------------*/ |
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| 31 | #include "stm32f1xx_ll_fsmc.h" |
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| 32 | |||
| 33 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 34 | * @{ |
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| 35 | */ |
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| 36 | |||
| 37 | /** @addtogroup NOR |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Exported typedef ----------------------------------------------------------*/ |
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| 42 | /** @defgroup NOR_Exported_Types NOR Exported Types |
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| 43 | * @{ |
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| 44 | */ |
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| 45 | |||
| 46 | /** |
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| 47 | * @brief HAL SRAM State structures definition |
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| 48 | */ |
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| 49 | typedef enum |
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| 50 | { |
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| 51 | HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ |
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| 52 | HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ |
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| 53 | HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ |
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| 54 | HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ |
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| 55 | HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ |
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| 56 | } HAL_NOR_StateTypeDef; |
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| 57 | |||
| 58 | /** |
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| 59 | * @brief FSMC NOR Status typedef |
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| 60 | */ |
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| 61 | typedef enum |
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| 62 | { |
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| 63 | HAL_NOR_STATUS_SUCCESS = 0U, |
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| 64 | HAL_NOR_STATUS_ONGOING, |
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| 65 | HAL_NOR_STATUS_ERROR, |
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| 66 | HAL_NOR_STATUS_TIMEOUT |
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| 67 | } HAL_NOR_StatusTypeDef; |
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| 68 | |||
| 69 | /** |
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| 70 | * @brief FSMC NOR ID typedef |
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| 71 | */ |
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| 72 | typedef struct |
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| 73 | { |
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| 74 | uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ |
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| 75 | |||
| 76 | uint16_t Device_Code1; |
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| 77 | |||
| 78 | uint16_t Device_Code2; |
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| 79 | |||
| 80 | uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. |
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| 81 | These codes can be accessed by performing read operations with specific |
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| 82 | control signals and addresses set.They can also be accessed by issuing |
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| 83 | an Auto Select command */ |
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| 84 | } NOR_IDTypeDef; |
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| 85 | |||
| 86 | /** |
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| 87 | * @brief FSMC NOR CFI typedef |
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| 88 | */ |
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| 89 | typedef struct |
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| 90 | { |
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| 91 | /*!< Defines the information stored in the memory's Common flash interface |
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| 92 | which contains a description of various electrical and timing parameters, |
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| 93 | density information and functions supported by the memory */ |
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| 94 | |||
| 95 | uint16_t CFI_1; |
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| 96 | |||
| 97 | uint16_t CFI_2; |
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| 98 | |||
| 99 | uint16_t CFI_3; |
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| 100 | |||
| 101 | uint16_t CFI_4; |
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| 102 | } NOR_CFITypeDef; |
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| 103 | |||
| 104 | /** |
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| 105 | * @brief NOR handle Structure definition |
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| 106 | */ |
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| 107 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 108 | typedef struct __NOR_HandleTypeDef |
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| 109 | #else |
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| 110 | typedef struct |
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| 111 | #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
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| 112 | |||
| 113 | { |
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| 114 | FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
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| 115 | |||
| 116 | FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
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| 117 | |||
| 118 | FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ |
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| 119 | |||
| 120 | HAL_LockTypeDef Lock; /*!< NOR locking object */ |
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| 121 | |||
| 122 | __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ |
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| 123 | |||
| 124 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 125 | void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */ |
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| 126 | void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */ |
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| 127 | #endif |
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| 128 | } NOR_HandleTypeDef; |
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| 129 | |||
| 130 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 131 | /** |
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| 132 | * @brief HAL NOR Callback ID enumeration definition |
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| 133 | */ |
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| 134 | typedef enum |
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| 135 | { |
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| 136 | HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ |
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| 137 | HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ |
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| 138 | }HAL_NOR_CallbackIDTypeDef; |
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| 139 | |||
| 140 | /** |
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| 141 | * @brief HAL NOR Callback pointer definition |
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| 142 | */ |
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| 143 | typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); |
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| 144 | #endif |
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| 145 | /** |
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| 146 | * @} |
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| 147 | */ |
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| 148 | |||
| 149 | /* Exported constants --------------------------------------------------------*/ |
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| 150 | /* Exported macro ------------------------------------------------------------*/ |
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| 151 | /** @defgroup NOR_Exported_Macros NOR Exported Macros |
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| 152 | * @{ |
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| 153 | */ |
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| 154 | /** @brief Reset NOR handle state |
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| 155 | * @param __HANDLE__ specifies the NOR handle. |
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| 156 | * @retval None |
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| 157 | */ |
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| 158 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 159 | #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \ |
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| 160 | (__HANDLE__)->State = HAL_NOR_STATE_RESET; \ |
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| 161 | (__HANDLE__)->MspInitCallback = NULL; \ |
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| 162 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
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| 163 | } while(0) |
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| 164 | #else |
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| 165 | #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) |
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| 166 | #endif |
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| 167 | /** |
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| 168 | * @} |
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| 169 | */ |
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| 170 | |||
| 171 | /* Exported functions --------------------------------------------------------*/ |
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| 172 | /** @addtogroup NOR_Exported_Functions NOR Exported Functions |
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| 173 | * @{ |
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| 174 | */ |
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| 175 | |||
| 176 | /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 177 | * @{ |
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| 178 | */ |
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| 179 | |||
| 180 | /* Initialization/de-initialization functions ********************************/ |
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| 181 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); |
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| 182 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); |
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| 183 | void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); |
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| 184 | void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); |
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| 185 | void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); |
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| 186 | /** |
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| 187 | * @} |
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| 188 | */ |
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| 189 | |||
| 190 | /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions |
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| 191 | * @{ |
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| 192 | */ |
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| 193 | |||
| 194 | /* I/O operation functions ***************************************************/ |
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| 195 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); |
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| 196 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); |
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| 197 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
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| 198 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
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| 199 | |||
| 200 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); |
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| 201 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); |
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| 202 | |||
| 203 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); |
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| 204 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); |
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| 205 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); |
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| 206 | |||
| 207 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 208 | /* NOR callback registering/unregistering */ |
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| 209 | HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback); |
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| 210 | HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); |
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| 211 | #endif |
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| 212 | /** |
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| 213 | * @} |
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| 214 | */ |
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| 215 | |||
| 216 | /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions |
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| 217 | * @{ |
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| 218 | */ |
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| 219 | |||
| 220 | /* NOR Control functions *****************************************************/ |
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| 221 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); |
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| 222 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); |
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| 223 | /** |
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| 224 | * @} |
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| 225 | */ |
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| 226 | |||
| 227 | /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions |
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| 228 | * @{ |
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| 229 | */ |
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| 230 | |||
| 231 | /* NOR State functions ********************************************************/ |
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| 232 | HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); |
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| 233 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); |
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| 234 | /** |
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| 235 | * @} |
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| 236 | */ |
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| 237 | |||
| 238 | /** |
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| 239 | * @} |
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| 240 | */ |
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| 241 | |||
| 242 | /* Private types -------------------------------------------------------------*/ |
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| 243 | /* Private variables ---------------------------------------------------------*/ |
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| 244 | /* Private constants ---------------------------------------------------------*/ |
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| 245 | /** @defgroup NOR_Private_Constants NOR Private Constants |
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| 246 | * @{ |
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| 247 | */ |
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| 248 | /* NOR device IDs addresses */ |
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| 249 | #define MC_ADDRESS ((uint16_t)0x0000U) |
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| 250 | #define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) |
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| 251 | #define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) |
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| 252 | #define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) |
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| 253 | |||
| 254 | /* NOR CFI IDs addresses */ |
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| 255 | #define CFI1_ADDRESS ((uint16_t)0x61U) |
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| 256 | #define CFI2_ADDRESS ((uint16_t)0x62U) |
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| 257 | #define CFI3_ADDRESS ((uint16_t)0x63U) |
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| 258 | #define CFI4_ADDRESS ((uint16_t)0x64U) |
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| 259 | |||
| 260 | /* NOR operation wait timeout */ |
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| 261 | #define NOR_TMEOUT ((uint16_t)0xFFFFU) |
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| 262 | |||
| 263 | /* NOR memory data width */ |
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| 264 | #define NOR_MEMORY_8B ((uint8_t)0x0U) |
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| 265 | #define NOR_MEMORY_16B ((uint8_t)0x1U) |
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| 266 | |||
| 267 | /* NOR memory device read/write start address */ |
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| 268 | #define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) |
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| 269 | #define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) |
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| 270 | #define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) |
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| 271 | #define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) |
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| 272 | /** |
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| 273 | * @} |
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| 274 | */ |
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| 275 | |||
| 276 | /* Private macros ------------------------------------------------------------*/ |
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| 277 | /** @defgroup NOR_Private_Macros NOR Private Macros |
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| 278 | * @{ |
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| 279 | */ |
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| 280 | /** |
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| 281 | * @brief NOR memory address shifting. |
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| 282 | * @param __NOR_ADDRESS NOR base address |
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| 283 | * @param __NOR_MEMORY_WIDTH_ NOR memory width |
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| 284 | * @param __ADDRESS__ NOR memory address |
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| 285 | * @retval NOR shifted address value |
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| 286 | */ |
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| 287 | #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ |
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| 288 | ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ |
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| 289 | ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ |
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| 290 | ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) |
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| 291 | |||
| 292 | /** |
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| 293 | * @brief NOR memory write data to specified address. |
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| 294 | * @param __ADDRESS__ NOR memory address |
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| 295 | * @param __DATA__ Data to write |
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| 296 | * @retval None |
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| 297 | */ |
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| 298 | #define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ |
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| 299 | (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ |
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| 300 | __DSB(); \ |
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| 301 | } while(0) |
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| 302 | |||
| 303 | /** |
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| 304 | * @} |
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| 305 | */ |
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| 306 | |||
| 307 | /** |
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| 308 | * @} |
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| 309 | */ |
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| 310 | |||
| 311 | /** |
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| 312 | * @} |
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| 313 | */ |
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| 314 | |||
| 315 | #endif /* FSMC_BANK1 */ |
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| 316 | |||
| 317 | #ifdef __cplusplus |
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| 318 | } |
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| 319 | #endif |
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| 320 | |||
| 321 | #endif /* STM32F1xx_HAL_NOR_H */ |
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| 322 | |||
| 323 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |