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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_nor.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of NOR HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | mjames | 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
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| 2 | mjames | 11 | * |
| 9 | mjames | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 2 | mjames | 16 | * |
| 17 | ****************************************************************************** |
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| 9 | mjames | 18 | */ |
| 2 | mjames | 19 | |
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 9 | mjames | 21 | #ifndef STM32F1xx_HAL_NOR_H |
| 22 | #define STM32F1xx_HAL_NOR_H |
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| 2 | mjames | 23 | |
| 24 | #ifdef __cplusplus |
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| 9 | mjames | 25 | extern "C" { |
| 2 | mjames | 26 | #endif |
| 27 | |||
| 9 | mjames | 28 | #if defined FSMC_BANK1 |
| 29 | |||
| 2 | mjames | 30 | /* Includes ------------------------------------------------------------------*/ |
| 31 | #include "stm32f1xx_ll_fsmc.h" |
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| 32 | |||
| 33 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 34 | * @{ |
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| 35 | */ |
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| 36 | |||
| 37 | /** @addtogroup NOR |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 9 | mjames | 41 | /* Exported typedef ----------------------------------------------------------*/ |
| 42 | /** @defgroup NOR_Exported_Types NOR Exported Types |
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| 2 | mjames | 43 | * @{ |
| 44 | */ |
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| 45 | |||
| 46 | /** |
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| 9 | mjames | 47 | * @brief HAL SRAM State structures definition |
| 2 | mjames | 48 | */ |
| 49 | typedef enum |
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| 9 | mjames | 50 | { |
| 2 | mjames | 51 | HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ |
| 52 | HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ |
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| 53 | HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ |
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| 9 | mjames | 54 | HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ |
| 55 | HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ |
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| 56 | } HAL_NOR_StateTypeDef; |
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| 2 | mjames | 57 | |
| 58 | /** |
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| 59 | * @brief FSMC NOR Status typedef |
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| 60 | */ |
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| 61 | typedef enum |
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| 62 | { |
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| 9 | mjames | 63 | HAL_NOR_STATUS_SUCCESS = 0U, |
| 2 | mjames | 64 | HAL_NOR_STATUS_ONGOING, |
| 65 | HAL_NOR_STATUS_ERROR, |
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| 66 | HAL_NOR_STATUS_TIMEOUT |
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| 9 | mjames | 67 | } HAL_NOR_StatusTypeDef; |
| 2 | mjames | 68 | |
| 69 | /** |
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| 70 | * @brief FSMC NOR ID typedef |
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| 71 | */ |
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| 72 | typedef struct |
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| 73 | { |
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| 74 | uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ |
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| 9 | mjames | 75 | |
| 2 | mjames | 76 | uint16_t Device_Code1; |
| 9 | mjames | 77 | |
| 2 | mjames | 78 | uint16_t Device_Code2; |
| 79 | |||
| 9 | mjames | 80 | uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. |
| 81 | These codes can be accessed by performing read operations with specific |
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| 82 | control signals and addresses set.They can also be accessed by issuing |
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| 83 | an Auto Select command */ |
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| 84 | } NOR_IDTypeDef; |
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| 85 | |||
| 2 | mjames | 86 | /** |
| 87 | * @brief FSMC NOR CFI typedef |
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| 88 | */ |
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| 89 | typedef struct |
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| 90 | { |
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| 91 | /*!< Defines the information stored in the memory's Common flash interface |
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| 9 | mjames | 92 | which contains a description of various electrical and timing parameters, |
| 2 | mjames | 93 | density information and functions supported by the memory */ |
| 9 | mjames | 94 | |
| 2 | mjames | 95 | uint16_t CFI_1; |
| 9 | mjames | 96 | |
| 2 | mjames | 97 | uint16_t CFI_2; |
| 9 | mjames | 98 | |
| 2 | mjames | 99 | uint16_t CFI_3; |
| 9 | mjames | 100 | |
| 2 | mjames | 101 | uint16_t CFI_4; |
| 9 | mjames | 102 | } NOR_CFITypeDef; |
| 2 | mjames | 103 | |
| 9 | mjames | 104 | /** |
| 105 | * @brief NOR handle Structure definition |
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| 106 | */ |
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| 107 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 108 | typedef struct __NOR_HandleTypeDef |
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| 109 | #else |
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| 2 | mjames | 110 | typedef struct |
| 9 | mjames | 111 | #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
| 112 | |||
| 2 | mjames | 113 | { |
| 9 | mjames | 114 | FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
| 2 | mjames | 115 | |
| 9 | mjames | 116 | FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
| 117 | |||
| 118 | FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ |
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| 119 | |||
| 120 | HAL_LockTypeDef Lock; /*!< NOR locking object */ |
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| 121 | |||
| 2 | mjames | 122 | __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ |
| 123 | |||
| 9 | mjames | 124 | uint32_t CommandSet; /*!< NOR algorithm command set and control */ |
| 125 | |||
| 126 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 127 | void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ |
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| 128 | void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ |
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| 129 | #endif |
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| 130 | } NOR_HandleTypeDef; |
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| 131 | |||
| 132 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 2 | mjames | 133 | /** |
| 9 | mjames | 134 | * @brief HAL NOR Callback ID enumeration definition |
| 135 | */ |
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| 136 | typedef enum |
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| 137 | { |
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| 138 | HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ |
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| 139 | HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ |
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| 140 | } HAL_NOR_CallbackIDTypeDef; |
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| 141 | |||
| 142 | /** |
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| 143 | * @brief HAL NOR Callback pointer definition |
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| 144 | */ |
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| 145 | typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); |
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| 146 | #endif |
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| 147 | /** |
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| 2 | mjames | 148 | * @} |
| 149 | */ |
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| 150 | |||
| 151 | /* Exported constants --------------------------------------------------------*/ |
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| 152 | /* Exported macro ------------------------------------------------------------*/ |
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| 9 | mjames | 153 | /** @defgroup NOR_Exported_Macros NOR Exported Macros |
| 2 | mjames | 154 | * @{ |
| 155 | */ |
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| 156 | /** @brief Reset NOR handle state |
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| 9 | mjames | 157 | * @param __HANDLE__ specifies the NOR handle. |
| 2 | mjames | 158 | * @retval None |
| 159 | */ |
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| 9 | mjames | 160 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
| 161 | #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \ |
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| 162 | (__HANDLE__)->State = HAL_NOR_STATE_RESET; \ |
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| 163 | (__HANDLE__)->MspInitCallback = NULL; \ |
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| 164 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
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| 165 | } while(0) |
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| 166 | #else |
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| 2 | mjames | 167 | #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) |
| 9 | mjames | 168 | #endif |
| 2 | mjames | 169 | /** |
| 170 | * @} |
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| 171 | */ |
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| 172 | |||
| 173 | /* Exported functions --------------------------------------------------------*/ |
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| 174 | /** @addtogroup NOR_Exported_Functions NOR Exported Functions |
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| 9 | mjames | 175 | * @{ |
| 176 | */ |
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| 2 | mjames | 177 | |
| 9 | mjames | 178 | /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions |
| 179 | * @{ |
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| 180 | */ |
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| 2 | mjames | 181 | |
| 9 | mjames | 182 | /* Initialization/de-initialization functions ********************************/ |
| 183 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, |
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| 184 | FSMC_NORSRAM_TimingTypeDef *ExtTiming); |
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| 2 | mjames | 185 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); |
| 9 | mjames | 186 | void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); |
| 187 | void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); |
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| 188 | void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); |
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| 2 | mjames | 189 | /** |
| 190 | * @} |
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| 191 | */ |
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| 192 | |||
| 9 | mjames | 193 | /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions |
| 194 | * @{ |
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| 195 | */ |
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| 196 | |||
| 2 | mjames | 197 | /* I/O operation functions ***************************************************/ |
| 198 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); |
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| 199 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); |
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| 200 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
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| 201 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
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| 202 | |||
| 9 | mjames | 203 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, |
| 204 | uint32_t uwBufferSize); |
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| 205 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, |
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| 206 | uint32_t uwBufferSize); |
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| 2 | mjames | 207 | |
| 208 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); |
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| 209 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); |
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| 210 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); |
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| 211 | |||
| 9 | mjames | 212 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
| 213 | /* NOR callback registering/unregistering */ |
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| 214 | HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, |
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| 215 | pNOR_CallbackTypeDef pCallback); |
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| 216 | HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); |
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| 217 | #endif |
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| 2 | mjames | 218 | /** |
| 219 | * @} |
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| 220 | */ |
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| 221 | |||
| 9 | mjames | 222 | /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions |
| 223 | * @{ |
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| 224 | */ |
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| 225 | |||
| 2 | mjames | 226 | /* NOR Control functions *****************************************************/ |
| 227 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); |
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| 228 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); |
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| 229 | /** |
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| 230 | * @} |
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| 231 | */ |
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| 232 | |||
| 9 | mjames | 233 | /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions |
| 234 | * @{ |
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| 235 | */ |
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| 236 | |||
| 2 | mjames | 237 | /* NOR State functions ********************************************************/ |
| 238 | HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); |
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| 239 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); |
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| 9 | mjames | 240 | /** |
| 241 | * @} |
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| 242 | */ |
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| 2 | mjames | 243 | |
| 244 | /** |
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| 245 | * @} |
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| 246 | */ |
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| 9 | mjames | 247 | |
| 248 | /* Private types -------------------------------------------------------------*/ |
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| 249 | /* Private variables ---------------------------------------------------------*/ |
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| 250 | /* Private constants ---------------------------------------------------------*/ |
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| 251 | /** @defgroup NOR_Private_Constants NOR Private Constants |
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| 252 | * @{ |
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| 253 | */ |
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| 254 | /* NOR device IDs addresses */ |
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| 255 | #define MC_ADDRESS ((uint16_t)0x0000) |
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| 256 | #define DEVICE_CODE1_ADDR ((uint16_t)0x0001) |
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| 257 | #define DEVICE_CODE2_ADDR ((uint16_t)0x000E) |
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| 258 | #define DEVICE_CODE3_ADDR ((uint16_t)0x000F) |
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| 259 | |||
| 260 | /* NOR CFI IDs addresses */ |
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| 261 | #define CFI1_ADDRESS ((uint16_t)0x61) |
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| 262 | #define CFI2_ADDRESS ((uint16_t)0x62) |
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| 263 | #define CFI3_ADDRESS ((uint16_t)0x63) |
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| 264 | #define CFI4_ADDRESS ((uint16_t)0x64) |
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| 265 | |||
| 266 | /* NOR operation wait timeout */ |
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| 267 | #define NOR_TMEOUT ((uint16_t)0xFFFF) |
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| 268 | |||
| 269 | /* NOR memory data width */ |
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| 270 | #define NOR_MEMORY_8B ((uint8_t)0x0) |
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| 271 | #define NOR_MEMORY_16B ((uint8_t)0x1) |
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| 272 | |||
| 273 | /* NOR memory device read/write start address */ |
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| 274 | #define NOR_MEMORY_ADRESS1 (0x60000000U) |
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| 275 | #define NOR_MEMORY_ADRESS2 (0x64000000U) |
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| 276 | #define NOR_MEMORY_ADRESS3 (0x68000000U) |
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| 277 | #define NOR_MEMORY_ADRESS4 (0x6C000000U) |
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| 2 | mjames | 278 | /** |
| 279 | * @} |
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| 280 | */ |
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| 281 | |||
| 9 | mjames | 282 | /* Private macros ------------------------------------------------------------*/ |
| 283 | /** @defgroup NOR_Private_Macros NOR Private Macros |
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| 284 | * @{ |
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| 285 | */ |
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| 2 | mjames | 286 | /** |
| 9 | mjames | 287 | * @brief NOR memory address shifting. |
| 288 | * @param __NOR_ADDRESS NOR base address |
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| 289 | * @param __NOR_MEMORY_WIDTH_ NOR memory width |
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| 290 | * @param __ADDRESS__ NOR memory address |
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| 291 | * @retval NOR shifted address value |
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| 292 | */ |
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| 293 | #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ |
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| 294 | ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ |
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| 295 | ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ |
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| 296 | ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) |
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| 297 | |||
| 298 | /** |
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| 299 | * @brief NOR memory write data to specified address. |
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| 300 | * @param __ADDRESS__ NOR memory address |
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| 301 | * @param __DATA__ Data to write |
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| 302 | * @retval None |
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| 303 | */ |
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| 304 | #define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ |
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| 305 | (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ |
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| 306 | __DSB(); \ |
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| 307 | } while(0) |
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| 308 | |||
| 309 | /** |
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| 2 | mjames | 310 | * @} |
| 9 | mjames | 311 | */ |
| 2 | mjames | 312 | |
| 9 | mjames | 313 | /** |
| 314 | * @} |
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| 315 | */ |
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| 2 | mjames | 316 | |
| 317 | /** |
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| 318 | * @} |
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| 319 | */ |
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| 320 | |||
| 9 | mjames | 321 | #endif /* FSMC_BANK1 */ |
| 322 | |||
| 2 | mjames | 323 | #ifdef __cplusplus |
| 324 | } |
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| 325 | #endif |
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| 326 | |||
| 9 | mjames | 327 | #endif /* STM32F1xx_HAL_NOR_H */ |
| 2 | mjames | 328 | |
| 329 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |