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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_nor.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of NOR HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved. |
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| 11 | * |
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| 12 | * This software is licensed under terms that can be found in the LICENSE file |
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| 13 | * in the root directory of this software component. |
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| 14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | */ |
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| 18 | |||
| 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 20 | #ifndef STM32F1xx_HAL_NOR_H |
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| 21 | #define STM32F1xx_HAL_NOR_H |
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| 22 | |||
| 23 | #ifdef __cplusplus |
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| 24 | extern "C" { |
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| 25 | #endif |
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| 26 | |||
| 27 | #if defined(FSMC_BANK1) |
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| 28 | |||
| 29 | /* Includes ------------------------------------------------------------------*/ |
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| 30 | #include "stm32f1xx_ll_fsmc.h" |
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| 31 | |||
| 32 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 33 | * @{ |
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| 34 | */ |
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| 35 | |||
| 36 | /** @addtogroup NOR |
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| 37 | * @{ |
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| 38 | */ |
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| 39 | |||
| 40 | /* Exported typedef ----------------------------------------------------------*/ |
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| 41 | /** @defgroup NOR_Exported_Types NOR Exported Types |
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| 42 | * @{ |
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| 43 | */ |
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| 44 | |||
| 45 | /** |
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| 46 | * @brief HAL SRAM State structures definition |
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| 47 | */ |
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| 48 | typedef enum |
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| 49 | { |
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| 50 | HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ |
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| 51 | HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ |
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| 52 | HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ |
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| 53 | HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ |
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| 54 | HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ |
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| 55 | } HAL_NOR_StateTypeDef; |
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| 56 | |||
| 57 | /** |
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| 58 | * @brief FSMC NOR Status typedef |
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| 59 | */ |
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| 60 | typedef enum |
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| 61 | { |
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| 62 | HAL_NOR_STATUS_SUCCESS = 0U, |
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| 63 | HAL_NOR_STATUS_ONGOING, |
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| 64 | HAL_NOR_STATUS_ERROR, |
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| 65 | HAL_NOR_STATUS_TIMEOUT |
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| 66 | } HAL_NOR_StatusTypeDef; |
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| 67 | |||
| 68 | /** |
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| 69 | * @brief FSMC NOR ID typedef |
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| 70 | */ |
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| 71 | typedef struct |
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| 72 | { |
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| 73 | uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ |
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| 74 | |||
| 75 | uint16_t Device_Code1; |
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| 76 | |||
| 77 | uint16_t Device_Code2; |
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| 78 | |||
| 79 | uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. |
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| 80 | These codes can be accessed by performing read operations with specific |
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| 81 | control signals and addresses set.They can also be accessed by issuing |
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| 82 | an Auto Select command */ |
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| 83 | } NOR_IDTypeDef; |
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| 84 | |||
| 85 | /** |
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| 86 | * @brief FSMC NOR CFI typedef |
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| 87 | */ |
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| 88 | typedef struct |
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| 89 | { |
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| 90 | /*!< Defines the information stored in the memory's Common flash interface |
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| 91 | which contains a description of various electrical and timing parameters, |
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| 92 | density information and functions supported by the memory */ |
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| 93 | |||
| 94 | uint16_t CFI_1; |
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| 95 | |||
| 96 | uint16_t CFI_2; |
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| 97 | |||
| 98 | uint16_t CFI_3; |
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| 99 | |||
| 100 | uint16_t CFI_4; |
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| 101 | } NOR_CFITypeDef; |
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| 102 | |||
| 103 | /** |
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| 104 | * @brief NOR handle Structure definition |
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| 105 | */ |
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| 106 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 107 | typedef struct __NOR_HandleTypeDef |
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| 108 | #else |
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| 109 | typedef struct |
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| 110 | #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
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| 111 | |||
| 112 | { |
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| 113 | FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
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| 114 | |||
| 115 | FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
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| 116 | |||
| 117 | FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ |
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| 118 | |||
| 119 | HAL_LockTypeDef Lock; /*!< NOR locking object */ |
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| 120 | |||
| 121 | __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ |
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| 122 | |||
| 123 | uint32_t CommandSet; /*!< NOR algorithm command set and control */ |
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| 124 | |||
| 125 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 126 | void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ |
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| 127 | void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ |
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| 128 | #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
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| 129 | } NOR_HandleTypeDef; |
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| 130 | |||
| 131 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 132 | /** |
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| 133 | * @brief HAL NOR Callback ID enumeration definition |
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| 134 | */ |
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| 135 | typedef enum |
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| 136 | { |
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| 137 | HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ |
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| 138 | HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ |
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| 139 | } HAL_NOR_CallbackIDTypeDef; |
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| 140 | |||
| 141 | /** |
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| 142 | * @brief HAL NOR Callback pointer definition |
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| 143 | */ |
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| 144 | typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); |
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| 145 | #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
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| 146 | /** |
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| 147 | * @} |
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| 148 | */ |
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| 149 | |||
| 150 | /* Exported constants --------------------------------------------------------*/ |
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| 151 | /* Exported macro ------------------------------------------------------------*/ |
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| 152 | /** @defgroup NOR_Exported_Macros NOR Exported Macros |
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| 153 | * @{ |
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| 154 | */ |
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| 155 | /** @brief Reset NOR handle state |
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| 156 | * @param __HANDLE__ specifies the NOR handle. |
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| 157 | * @retval None |
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| 158 | */ |
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| 159 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 160 | #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \ |
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| 161 | (__HANDLE__)->State = HAL_NOR_STATE_RESET; \ |
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| 162 | (__HANDLE__)->MspInitCallback = NULL; \ |
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| 163 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
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| 164 | } while(0) |
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| 165 | #else |
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| 166 | #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) |
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| 167 | #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
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| 168 | /** |
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| 169 | * @} |
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| 170 | */ |
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| 171 | |||
| 172 | /* Exported functions --------------------------------------------------------*/ |
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| 173 | /** @addtogroup NOR_Exported_Functions NOR Exported Functions |
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| 174 | * @{ |
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| 175 | */ |
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| 176 | |||
| 177 | /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 178 | * @{ |
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| 179 | */ |
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| 180 | |||
| 181 | /* Initialization/de-initialization functions ********************************/ |
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| 182 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, |
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| 183 | FSMC_NORSRAM_TimingTypeDef *ExtTiming); |
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| 184 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); |
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| 185 | void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); |
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| 186 | void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); |
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| 187 | void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); |
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| 188 | /** |
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| 189 | * @} |
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| 190 | */ |
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| 191 | |||
| 192 | /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions |
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| 193 | * @{ |
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| 194 | */ |
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| 195 | |||
| 196 | /* I/O operation functions ***************************************************/ |
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| 197 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); |
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| 198 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); |
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| 199 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
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| 200 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
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| 201 | |||
| 202 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, |
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| 203 | uint32_t uwBufferSize); |
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| 204 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, |
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| 205 | uint32_t uwBufferSize); |
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| 206 | |||
| 207 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); |
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| 208 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); |
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| 209 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); |
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| 210 | |||
| 211 | #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
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| 212 | /* NOR callback registering/unregistering */ |
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| 213 | HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, |
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| 214 | pNOR_CallbackTypeDef pCallback); |
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| 215 | HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); |
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| 216 | #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
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| 217 | /** |
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| 218 | * @} |
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| 219 | */ |
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| 220 | |||
| 221 | /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions |
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| 222 | * @{ |
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| 223 | */ |
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| 224 | |||
| 225 | /* NOR Control functions *****************************************************/ |
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| 226 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); |
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| 227 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); |
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| 228 | /** |
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| 229 | * @} |
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| 230 | */ |
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| 231 | |||
| 232 | /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions |
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| 233 | * @{ |
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| 234 | */ |
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| 235 | |||
| 236 | /* NOR State functions ********************************************************/ |
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| 237 | HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor); |
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| 238 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); |
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| 239 | /** |
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| 240 | * @} |
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| 241 | */ |
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| 242 | |||
| 243 | /** |
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| 244 | * @} |
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| 245 | */ |
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| 246 | |||
| 247 | /* Private types -------------------------------------------------------------*/ |
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| 248 | /* Private variables ---------------------------------------------------------*/ |
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| 249 | /* Private constants ---------------------------------------------------------*/ |
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| 250 | /** @defgroup NOR_Private_Constants NOR Private Constants |
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| 251 | * @{ |
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| 252 | */ |
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| 253 | /* NOR device IDs addresses */ |
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| 254 | #define MC_ADDRESS ((uint16_t)0x0000) |
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| 255 | #define DEVICE_CODE1_ADDR ((uint16_t)0x0001) |
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| 256 | #define DEVICE_CODE2_ADDR ((uint16_t)0x000E) |
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| 257 | #define DEVICE_CODE3_ADDR ((uint16_t)0x000F) |
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| 258 | |||
| 259 | /* NOR CFI IDs addresses */ |
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| 260 | #define CFI1_ADDRESS ((uint16_t)0x0061) |
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| 261 | #define CFI2_ADDRESS ((uint16_t)0x0062) |
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| 262 | #define CFI3_ADDRESS ((uint16_t)0x0063) |
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| 263 | #define CFI4_ADDRESS ((uint16_t)0x0064) |
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| 264 | |||
| 265 | /* NOR operation wait timeout */ |
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| 266 | #define NOR_TMEOUT ((uint16_t)0xFFFF) |
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| 267 | |||
| 268 | /* NOR memory data width */ |
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| 269 | #define NOR_MEMORY_8B ((uint8_t)0x00) |
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| 270 | #define NOR_MEMORY_16B ((uint8_t)0x01) |
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| 271 | |||
| 272 | /* NOR memory device read/write start address */ |
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| 273 | #define NOR_MEMORY_ADRESS1 (0x60000000U) |
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| 274 | #define NOR_MEMORY_ADRESS2 (0x64000000U) |
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| 275 | #define NOR_MEMORY_ADRESS3 (0x68000000U) |
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| 276 | #define NOR_MEMORY_ADRESS4 (0x6C000000U) |
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| 277 | /** |
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| 278 | * @} |
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| 279 | */ |
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| 280 | |||
| 281 | /* Private macros ------------------------------------------------------------*/ |
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| 282 | /** @defgroup NOR_Private_Macros NOR Private Macros |
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| 283 | * @{ |
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| 284 | */ |
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| 285 | /** |
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| 286 | * @brief NOR memory address shifting. |
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| 287 | * @param __NOR_ADDRESS NOR base address |
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| 288 | * @param __NOR_MEMORY_WIDTH_ NOR memory width |
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| 289 | * @param __ADDRESS__ NOR memory address |
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| 290 | * @retval NOR shifted address value |
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| 291 | */ |
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| 292 | #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ |
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| 293 | ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ |
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| 294 | ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ |
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| 295 | ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) |
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| 296 | |||
| 297 | /** |
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| 298 | * @brief NOR memory write data to specified address. |
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| 299 | * @param __ADDRESS__ NOR memory address |
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| 300 | * @param __DATA__ Data to write |
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| 301 | * @retval None |
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| 302 | */ |
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| 303 | #define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ |
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| 304 | (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ |
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| 305 | __DSB(); \ |
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| 306 | } while(0) |
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| 307 | |||
| 308 | /** |
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| 309 | * @} |
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| 310 | */ |
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| 311 | |||
| 312 | /** |
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| 313 | * @} |
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| 314 | */ |
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| 315 | |||
| 316 | /** |
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| 317 | * @} |
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| 318 | */ |
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| 319 | |||
| 320 | #endif /* FSMC_BANK1 */ |
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| 321 | |||
| 322 | #ifdef __cplusplus |
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| 323 | } |
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| 324 | #endif |
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| 325 | |||
| 326 | #endif /* STM32F1xx_HAL_NOR_H */ |