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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_nand.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of NAND HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef STM32F1xx_HAL_NAND_H |
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| 22 | #define STM32F1xx_HAL_NAND_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | #if defined(FSMC_BANK3) |
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| 29 | |||
| 30 | /* Includes ------------------------------------------------------------------*/ |
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| 31 | #include "stm32f1xx_ll_fsmc.h" |
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| 32 | |||
| 33 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 34 | * @{ |
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| 35 | */ |
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| 36 | |||
| 37 | /** @addtogroup NAND |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Exported typedef ----------------------------------------------------------*/ |
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| 42 | /* Exported types ------------------------------------------------------------*/ |
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| 43 | /** @defgroup NAND_Exported_Types NAND Exported Types |
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| 44 | * @{ |
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| 45 | */ |
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| 46 | |||
| 47 | /** |
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| 48 | * @brief HAL NAND State structures definition |
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| 49 | */ |
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| 50 | typedef enum |
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| 51 | { |
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| 52 | HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ |
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| 53 | HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ |
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| 54 | HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ |
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| 55 | HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ |
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| 56 | } HAL_NAND_StateTypeDef; |
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| 57 | |||
| 58 | /** |
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| 59 | * @brief NAND Memory electronic signature Structure definition |
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| 60 | */ |
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| 61 | typedef struct |
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| 62 | { |
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| 63 | /*<! NAND memory electronic signature maker and device IDs */ |
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| 64 | |||
| 65 | uint8_t Maker_Id; |
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| 66 | |||
| 67 | uint8_t Device_Id; |
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| 68 | |||
| 69 | uint8_t Third_Id; |
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| 70 | |||
| 71 | uint8_t Fourth_Id; |
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| 72 | } NAND_IDTypeDef; |
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| 73 | |||
| 74 | /** |
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| 75 | * @brief NAND Memory address Structure definition |
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| 76 | */ |
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| 77 | typedef struct |
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| 78 | { |
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| 79 | uint16_t Page; /*!< NAND memory Page address */ |
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| 80 | |||
| 81 | uint16_t Plane; /*!< NAND memory Zone address */ |
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| 82 | |||
| 83 | uint16_t Block; /*!< NAND memory Block address */ |
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| 84 | |||
| 85 | } NAND_AddressTypeDef; |
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| 86 | |||
| 87 | /** |
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| 88 | * @brief NAND Memory info Structure definition |
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| 89 | */ |
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| 90 | typedef struct |
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| 91 | { |
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| 92 | uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes |
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| 93 | for 8 bits addressing or words for 16 bits addressing */ |
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| 94 | |||
| 95 | uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes |
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| 96 | for 8 bits addressing or words for 16 bits addressing */ |
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| 97 | |||
| 98 | uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ |
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| 99 | |||
| 100 | uint32_t BlockNbr; /*!< NAND memory number of total blocks */ |
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| 101 | |||
| 102 | uint32_t PlaneNbr; /*!< NAND memory number of planes */ |
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| 103 | |||
| 104 | uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ |
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| 105 | |||
| 106 | FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This |
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| 107 | parameter is mandatory for some NAND parts after the read |
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| 108 | command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. |
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| 109 | Example: Toshiba THTH58BYG3S0HBAI6. |
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| 110 | This parameter could be ENABLE or DISABLE |
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| 111 | Please check the Read Mode sequnece in the NAND device datasheet */ |
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| 112 | } NAND_DeviceConfigTypeDef; |
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| 113 | |||
| 114 | /** |
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| 115 | * @brief NAND handle Structure definition |
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| 116 | */ |
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| 117 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
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| 118 | typedef struct __NAND_HandleTypeDef |
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| 119 | #else |
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| 120 | typedef struct |
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| 121 | #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
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| 122 | { |
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| 123 | FSMC_NAND_TypeDef *Instance; /*!< Register base address */ |
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| 124 | |||
| 125 | FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ |
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| 126 | |||
| 127 | HAL_LockTypeDef Lock; /*!< NAND locking object */ |
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| 128 | |||
| 129 | __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ |
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| 130 | |||
| 131 | NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ |
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| 132 | |||
| 133 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
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| 134 | void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ |
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| 135 | void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ |
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| 136 | void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ |
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| 137 | #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
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| 138 | } NAND_HandleTypeDef; |
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| 139 | |||
| 140 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
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| 141 | /** |
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| 142 | * @brief HAL NAND Callback ID enumeration definition |
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| 143 | */ |
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| 144 | typedef enum |
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| 145 | { |
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| 146 | HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ |
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| 147 | HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ |
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| 148 | HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ |
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| 149 | } HAL_NAND_CallbackIDTypeDef; |
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| 150 | |||
| 151 | /** |
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| 152 | * @brief HAL NAND Callback pointer definition |
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| 153 | */ |
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| 154 | typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); |
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| 155 | #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
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| 156 | |||
| 157 | /** |
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| 158 | * @} |
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| 159 | */ |
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| 160 | |||
| 161 | /* Exported constants --------------------------------------------------------*/ |
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| 162 | /* Exported macro ------------------------------------------------------------*/ |
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| 163 | /** @defgroup NAND_Exported_Macros NAND Exported Macros |
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| 164 | * @{ |
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| 165 | */ |
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| 166 | |||
| 167 | /** @brief Reset NAND handle state |
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| 168 | * @param __HANDLE__ specifies the NAND handle. |
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| 169 | * @retval None |
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| 170 | */ |
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| 171 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
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| 172 | #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ |
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| 173 | (__HANDLE__)->State = HAL_NAND_STATE_RESET; \ |
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| 174 | (__HANDLE__)->MspInitCallback = NULL; \ |
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| 175 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
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| 176 | } while(0) |
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| 177 | #else |
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| 178 | #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) |
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| 179 | #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
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| 180 | |||
| 181 | /** |
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| 182 | * @} |
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| 183 | */ |
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| 184 | |||
| 185 | /* Exported functions --------------------------------------------------------*/ |
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| 186 | /** @addtogroup NAND_Exported_Functions NAND Exported Functions |
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| 187 | * @{ |
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| 188 | */ |
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| 189 | |||
| 190 | /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 191 | * @{ |
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| 192 | */ |
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| 193 | |||
| 194 | /* Initialization/de-initialization functions ********************************/ |
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| 195 | HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, |
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| 196 | FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); |
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| 197 | HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); |
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| 198 | |||
| 199 | HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); |
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| 200 | |||
| 201 | HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); |
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| 202 | |||
| 203 | void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); |
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| 204 | void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); |
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| 205 | void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); |
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| 206 | void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); |
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| 207 | |||
| 208 | /** |
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| 209 | * @} |
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| 210 | */ |
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| 211 | |||
| 212 | /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions |
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| 213 | * @{ |
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| 214 | */ |
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| 215 | |||
| 216 | /* IO operation functions ****************************************************/ |
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| 217 | HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); |
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| 218 | |||
| 219 | HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, |
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| 220 | uint32_t NumPageToRead); |
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| 221 | HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, |
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| 222 | uint32_t NumPageToWrite); |
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| 223 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, |
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| 224 | uint8_t *pBuffer, uint32_t NumSpareAreaToRead); |
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| 225 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, |
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| 226 | uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); |
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| 227 | |||
| 228 | HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, |
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| 229 | uint32_t NumPageToRead); |
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| 230 | HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, |
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| 231 | uint32_t NumPageToWrite); |
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| 232 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, |
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| 233 | uint16_t *pBuffer, uint32_t NumSpareAreaToRead); |
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| 234 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, |
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| 235 | uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); |
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| 236 | |||
| 237 | HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
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| 238 | |||
| 239 | uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
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| 240 | |||
| 241 | #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
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| 242 | /* NAND callback registering/unregistering */ |
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| 243 | HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, |
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| 244 | pNAND_CallbackTypeDef pCallback); |
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| 245 | HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); |
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| 246 | #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
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| 247 | |||
| 248 | /** |
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| 249 | * @} |
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| 250 | */ |
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| 251 | |||
| 252 | /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions |
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| 253 | * @{ |
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| 254 | */ |
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| 255 | |||
| 256 | /* NAND Control functions ****************************************************/ |
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| 257 | HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); |
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| 258 | HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); |
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| 259 | HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); |
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| 260 | |||
| 261 | /** |
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| 262 | * @} |
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| 263 | */ |
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| 264 | |||
| 265 | /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions |
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| 266 | * @{ |
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| 267 | */ |
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| 268 | /* NAND State functions *******************************************************/ |
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| 269 | HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); |
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| 270 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); |
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| 271 | /** |
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| 272 | * @} |
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| 273 | */ |
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| 274 | |||
| 275 | /** |
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| 276 | * @} |
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| 277 | */ |
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| 278 | |||
| 279 | /* Private types -------------------------------------------------------------*/ |
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| 280 | /* Private variables ---------------------------------------------------------*/ |
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| 281 | /* Private constants ---------------------------------------------------------*/ |
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| 282 | /** @defgroup NAND_Private_Constants NAND Private Constants |
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| 283 | * @{ |
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| 284 | */ |
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| 285 | #define NAND_DEVICE1 0x70000000UL |
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| 286 | #define NAND_DEVICE2 0x80000000UL |
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| 287 | #define NAND_WRITE_TIMEOUT 0x01000000UL |
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| 288 | |||
| 289 | #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ |
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| 290 | #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ |
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| 291 | |||
| 292 | #define NAND_CMD_AREA_A ((uint8_t)0x00) |
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| 293 | #define NAND_CMD_AREA_B ((uint8_t)0x01) |
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| 294 | #define NAND_CMD_AREA_C ((uint8_t)0x50) |
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| 295 | #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) |
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| 296 | |||
| 297 | #define NAND_CMD_WRITE0 ((uint8_t)0x80) |
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| 298 | #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) |
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| 299 | #define NAND_CMD_ERASE0 ((uint8_t)0x60) |
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| 300 | #define NAND_CMD_ERASE1 ((uint8_t)0xD0) |
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| 301 | #define NAND_CMD_READID ((uint8_t)0x90) |
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| 302 | #define NAND_CMD_STATUS ((uint8_t)0x70) |
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| 303 | #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) |
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| 304 | #define NAND_CMD_RESET ((uint8_t)0xFF) |
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| 305 | |||
| 306 | /* NAND memory status */ |
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| 307 | #define NAND_VALID_ADDRESS 0x00000100UL |
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| 308 | #define NAND_INVALID_ADDRESS 0x00000200UL |
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| 309 | #define NAND_TIMEOUT_ERROR 0x00000400UL |
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| 310 | #define NAND_BUSY 0x00000000UL |
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| 311 | #define NAND_ERROR 0x00000001UL |
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| 312 | #define NAND_READY 0x00000040UL |
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| 313 | /** |
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| 314 | * @} |
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| 315 | */ |
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| 316 | |||
| 317 | /* Private macros ------------------------------------------------------------*/ |
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| 318 | /** @defgroup NAND_Private_Macros NAND Private Macros |
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| 319 | * @{ |
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| 320 | */ |
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| 321 | |||
| 322 | /** |
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| 323 | * @brief NAND memory address computation. |
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| 324 | * @param __ADDRESS__ NAND memory address. |
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| 325 | * @param __HANDLE__ NAND handle. |
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| 326 | * @retval NAND Raw address value |
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| 327 | */ |
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| 328 | #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ |
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| 329 | (((__ADDRESS__)->Block + \ |
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| 330 | (((__ADDRESS__)->Plane) * \ |
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| 331 | ((__HANDLE__)->Config.PlaneSize))) * \ |
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| 332 | ((__HANDLE__)->Config.BlockSize))) |
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| 333 | |||
| 334 | /** |
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| 335 | * @brief NAND memory Column address computation. |
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| 336 | * @param __HANDLE__ NAND handle. |
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| 337 | * @retval NAND Raw address value |
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| 338 | */ |
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| 339 | #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) |
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| 340 | |||
| 341 | /** |
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| 342 | * @brief NAND memory address cycling. |
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| 343 | * @param __ADDRESS__ NAND memory address. |
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| 344 | * @retval NAND address cycling value. |
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| 345 | */ |
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| 346 | #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ |
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| 347 | #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ |
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| 348 | #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ |
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| 349 | #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ |
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| 350 | |||
| 351 | /** |
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| 352 | * @brief NAND memory Columns cycling. |
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| 353 | * @param __ADDRESS__ NAND memory address. |
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| 354 | * @retval NAND Column address cycling value. |
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| 355 | */ |
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| 356 | #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ |
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| 357 | #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ |
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| 358 | |||
| 359 | /** |
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| 360 | * @} |
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| 361 | */ |
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| 362 | |||
| 363 | /** |
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| 364 | * @} |
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| 365 | */ |
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| 366 | |||
| 367 | /** |
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| 368 | * @} |
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| 369 | */ |
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| 370 | |||
| 371 | /** |
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| 372 | * @} |
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| 373 | */ |
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| 374 | |||
| 375 | #endif /* FSMC_BANK3 */ |
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| 376 | |||
| 377 | #ifdef __cplusplus |
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| 378 | } |
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| 379 | #endif |
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| 380 | |||
| 381 | #endif /* STM32F1xx_HAL_NAND_H */ |
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| 382 | |||
| 383 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |