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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_nand.h |
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| 4 | * @author MCD Application Team |
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| 5 | mjames | 5 | * @version V1.0.4 |
| 6 | * @date 29-April-2016 |
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| 2 | mjames | 7 | * @brief Header file of NAND HAL module. |
| 8 | ****************************************************************************** |
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| 9 | * @attention |
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| 10 | * |
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| 5 | mjames | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| 2 | mjames | 12 | * |
| 13 | * Redistribution and use in source and binary forms, with or without modification, |
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| 14 | * are permitted provided that the following conditions are met: |
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| 15 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 16 | * this list of conditions and the following disclaimer. |
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| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 18 | * this list of conditions and the following disclaimer in the documentation |
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| 19 | * and/or other materials provided with the distribution. |
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| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 21 | * may be used to endorse or promote products derived from this software |
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| 22 | * without specific prior written permission. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 34 | * |
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| 35 | ****************************************************************************** |
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| 36 | */ |
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| 37 | |||
| 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 39 | #ifndef __STM32F1xx_HAL_NAND_H |
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| 40 | #define __STM32F1xx_HAL_NAND_H |
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| 41 | |||
| 42 | #ifdef __cplusplus |
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| 43 | extern "C" { |
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| 44 | #endif |
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| 45 | |||
| 46 | /* Includes ------------------------------------------------------------------*/ |
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| 47 | #include "stm32f1xx_ll_fsmc.h" |
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| 48 | |||
| 49 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 50 | * @{ |
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| 51 | */ |
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| 52 | |||
| 53 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
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| 54 | /** @addtogroup NAND |
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| 55 | * @{ |
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| 56 | */ |
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| 57 | |||
| 58 | /** @addtogroup NAND_Private_Constants |
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| 59 | * @{ |
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| 60 | */ |
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| 61 | |||
| 62 | #define NAND_DEVICE1 FSMC_BANK2 |
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| 63 | #define NAND_DEVICE2 FSMC_BANK3 |
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| 64 | #define NAND_WRITE_TIMEOUT ((uint32_t)1000) |
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| 65 | |||
| 66 | #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ |
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| 67 | #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ |
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| 68 | |||
| 69 | #define NAND_CMD_AREA_A ((uint8_t)0x00) |
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| 70 | #define NAND_CMD_AREA_B ((uint8_t)0x01) |
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| 71 | #define NAND_CMD_AREA_C ((uint8_t)0x50) |
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| 72 | #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) |
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| 73 | |||
| 74 | #define NAND_CMD_WRITE0 ((uint8_t)0x80) |
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| 75 | #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) |
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| 76 | #define NAND_CMD_ERASE0 ((uint8_t)0x60) |
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| 77 | #define NAND_CMD_ERASE1 ((uint8_t)0xD0) |
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| 78 | #define NAND_CMD_READID ((uint8_t)0x90) |
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| 79 | #define NAND_CMD_STATUS ((uint8_t)0x70) |
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| 80 | #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) |
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| 81 | #define NAND_CMD_RESET ((uint8_t)0xFF) |
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| 82 | |||
| 83 | /* NAND memory status */ |
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| 84 | #define NAND_VALID_ADDRESS ((uint32_t)0x00000100) |
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| 85 | #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200) |
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| 86 | #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400) |
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| 87 | #define NAND_BUSY ((uint32_t)0x00000000) |
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| 88 | #define NAND_ERROR ((uint32_t)0x00000001) |
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| 89 | #define NAND_READY ((uint32_t)0x00000040) |
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| 90 | |||
| 91 | /** |
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| 92 | * @} |
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| 93 | */ |
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| 94 | |||
| 95 | /** @addtogroup NAND_Private_Macros |
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| 96 | * @{ |
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| 97 | */ |
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| 98 | |||
| 99 | /** |
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| 100 | * @brief NAND memory address computation. |
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| 101 | * @param __ADDRESS__: NAND memory address. |
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| 102 | * @param __HANDLE__ : NAND handle. |
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| 103 | * @retval NAND Raw address value |
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| 104 | */ |
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| 105 | #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ |
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| 106 | (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize))) |
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| 107 | |||
| 108 | /** |
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| 109 | * @brief NAND memory address cycling. |
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| 110 | * @param __ADDRESS__: NAND memory address. |
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| 111 | * @retval NAND address cycling value. |
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| 112 | */ |
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| 113 | #define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ |
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| 114 | #define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ |
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| 115 | #define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ |
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| 116 | #define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ |
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| 117 | |||
| 118 | /** |
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| 119 | * @} |
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| 120 | */ |
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| 121 | |||
| 122 | /* Exported typedef ----------------------------------------------------------*/ |
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| 123 | /* Exported types ------------------------------------------------------------*/ |
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| 124 | /** @defgroup NAND_Exported_Types NAND Exported Types |
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| 125 | * @{ |
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| 126 | */ |
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| 127 | |||
| 128 | /** |
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| 129 | * @brief HAL NAND State structures definition |
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| 130 | */ |
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| 131 | typedef enum |
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| 132 | { |
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| 133 | HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */ |
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| 134 | HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */ |
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| 135 | HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */ |
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| 136 | HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */ |
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| 137 | }HAL_NAND_StateTypeDef; |
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| 138 | |||
| 139 | /** |
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| 140 | * @brief NAND Memory electronic signature Structure definition |
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| 141 | */ |
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| 142 | typedef struct |
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| 143 | { |
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| 144 | /*<! NAND memory electronic signature maker and device IDs */ |
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| 145 | |||
| 146 | uint8_t Maker_Id; |
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| 147 | |||
| 148 | uint8_t Device_Id; |
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| 149 | |||
| 150 | uint8_t Third_Id; |
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| 151 | |||
| 152 | uint8_t Fourth_Id; |
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| 153 | }NAND_IDTypeDef; |
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| 154 | |||
| 155 | /** |
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| 156 | * @brief NAND Memory address Structure definition |
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| 157 | */ |
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| 158 | typedef struct |
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| 159 | { |
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| 160 | uint16_t Page; /*!< NAND memory Page address */ |
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| 161 | |||
| 162 | uint16_t Zone; /*!< NAND memory Zone address */ |
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| 163 | |||
| 164 | uint16_t Block; /*!< NAND memory Block address */ |
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| 165 | |||
| 166 | }NAND_AddressTypeDef; |
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| 167 | |||
| 168 | /** |
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| 169 | * @brief NAND Memory info Structure definition |
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| 170 | */ |
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| 171 | typedef struct |
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| 172 | { |
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| 173 | uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */ |
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| 174 | |||
| 175 | uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */ |
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| 176 | |||
| 177 | uint32_t BlockSize; /*!< NAND memory block size number of pages */ |
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| 178 | |||
| 179 | uint32_t BlockNbr; /*!< NAND memory number of blocks */ |
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| 180 | |||
| 181 | uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */ |
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| 182 | }NAND_InfoTypeDef; |
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| 183 | |||
| 184 | /** |
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| 185 | * @brief NAND handle Structure definition |
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| 186 | */ |
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| 187 | typedef struct |
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| 188 | { |
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| 189 | FSMC_NAND_TypeDef *Instance; /*!< Register base address */ |
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| 190 | |||
| 191 | FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ |
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| 192 | |||
| 193 | HAL_LockTypeDef Lock; /*!< NAND locking object */ |
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| 194 | |||
| 195 | __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ |
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| 196 | |||
| 197 | NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */ |
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| 198 | }NAND_HandleTypeDef; |
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| 199 | |||
| 200 | /** |
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| 201 | * @} |
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| 202 | */ |
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| 203 | |||
| 204 | /* Exported constants --------------------------------------------------------*/ |
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| 205 | /* Exported macro ------------------------------------------------------------*/ |
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| 206 | /** @defgroup NAND_Exported_Macros NAND Exported Macros |
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| 207 | * @{ |
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| 208 | */ |
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| 209 | |||
| 210 | /** @brief Reset NAND handle state |
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| 211 | * @param __HANDLE__: specifies the NAND handle. |
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| 212 | * @retval None |
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| 213 | */ |
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| 214 | #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) |
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| 215 | |||
| 216 | /** |
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| 217 | * @} |
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| 218 | */ |
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| 219 | |||
| 220 | /* Exported functions --------------------------------------------------------*/ |
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| 221 | /** @addtogroup NAND_Exported_Functions NAND Exported Functions |
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| 222 | * @{ |
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| 223 | */ |
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| 224 | |||
| 225 | /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 226 | * @{ |
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| 227 | */ |
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| 228 | |||
| 229 | /* Initialization/de-initialization functions ********************************/ |
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| 230 | HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); |
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| 231 | HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); |
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| 232 | void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); |
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| 233 | void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); |
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| 234 | void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); |
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| 235 | void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); |
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| 236 | |||
| 237 | /** |
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| 238 | * @} |
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| 239 | */ |
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| 240 | |||
| 241 | /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions |
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| 242 | * @{ |
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| 243 | */ |
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| 244 | |||
| 245 | /* IO operation functions ****************************************************/ |
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| 246 | HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); |
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| 247 | HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); |
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| 248 | HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); |
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| 249 | HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); |
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| 250 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); |
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| 251 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); |
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| 252 | HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
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| 253 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); |
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| 254 | uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
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| 255 | |||
| 256 | /** |
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| 257 | * @} |
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| 258 | */ |
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| 259 | |||
| 260 | /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions |
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| 261 | * @{ |
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| 262 | */ |
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| 263 | |||
| 264 | /* NAND Control functions ****************************************************/ |
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| 265 | HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); |
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| 266 | HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); |
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| 267 | HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); |
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| 268 | |||
| 269 | /** |
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| 270 | * @} |
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| 271 | */ |
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| 272 | |||
| 273 | /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions |
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| 274 | * @{ |
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| 275 | */ |
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| 276 | |||
| 277 | /* NAND State functions *******************************************************/ |
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| 278 | HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); |
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| 279 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); |
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| 280 | |||
| 281 | /** |
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| 282 | * @} |
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| 283 | */ |
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| 284 | |||
| 285 | /** |
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| 286 | * @} |
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| 287 | */ |
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| 288 | |||
| 289 | /** |
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| 290 | * @} |
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| 291 | */ |
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| 292 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
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| 293 | |||
| 294 | /** |
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| 295 | * @} |
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| 296 | */ |
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| 297 | |||
| 298 | #ifdef __cplusplus |
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| 299 | } |
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| 300 | #endif |
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| 301 | |||
| 302 | #endif /* __STM32F1xx_HAL_NAND_H */ |
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| 303 | |||
| 304 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |