WebSVN – AFRtranscoder – Blame – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_i2s.h
		4	* @author MCD Application Team
		5	* @brief Header file of I2S HAL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.
		11	*
		12	* This software is licensed under terms that can be found in the LICENSE file
		13	* in the root directory of this software component.
		14	* If no LICENSE file comes with this software, it is provided AS-IS.
		15	*
		16	******************************************************************************
		17	*/
		18
		19	/* Define to prevent recursive inclusion -------------------------------------*/
		20	#ifndef STM32F1xx_HAL_I2S_H
		21	#define STM32F1xx_HAL_I2S_H
		22
		23	#ifdef __cplusplus
		24	extern "C" {
		25	#endif
		26
		27	/* Includes ------------------------------------------------------------------*/
		28	#include "stm32f1xx_hal_def.h"
		29
		30	#if defined(SPI_I2S_SUPPORT)
		31	/** @addtogroup STM32F1xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup I2S
		36	* @{
		37	*/
		38
		39	/* Exported types ------------------------------------------------------------*/
		40	/** @defgroup I2S_Exported_Types I2S Exported Types
		41	* @{
		42	*/
		43
		44	/**
		45	* @brief I2S Init structure definition
		46	*/
		47	typedef struct
		48	{
		49	uint32_t Mode; /*!< Specifies the I2S operating mode.
		50	This parameter can be a value of @ref I2S_Mode */
		51
		52	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
		53	This parameter can be a value of @ref I2S_Standard */
		54
		55	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
		56	This parameter can be a value of @ref I2S_Data_Format */
		57
		58	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
		59	This parameter can be a value of @ref I2S_MCLK_Output */
		60
		61	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
		62	This parameter can be a value of @ref I2S_Audio_Frequency */
		63
		64	uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
		65	This parameter can be a value of @ref I2S_Clock_Polarity */
		66	} I2S_InitTypeDef;
		67
		68	/**
		69	* @brief HAL State structures definition
		70	*/
		71	typedef enum
		72	{
		73	HAL_I2S_STATE_RESET = 0x00U, /!< I2S not yet initialized or disabled /
		74	HAL_I2S_STATE_READY = 0x01U, /!< I2S initialized and ready for use /
		75	HAL_I2S_STATE_BUSY = 0x02U, /!< I2S internal process is ongoing /
		76	HAL_I2S_STATE_BUSY_TX = 0x03U, /!< Data Transmission process is ongoing /
		77	HAL_I2S_STATE_BUSY_RX = 0x04U, /!< Data Reception process is ongoing /
		78	HAL_I2S_STATE_TIMEOUT = 0x06U, /!< I2S timeout state /
		79	HAL_I2S_STATE_ERROR = 0x07U /!< I2S error state /
		80	} HAL_I2S_StateTypeDef;
		81
		82	/**
		83	* @brief I2S handle Structure definition
		84	*/
		85	#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
		86	typedef struct __I2S_HandleTypeDef
		87	#else
		88	typedef struct
		89	#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
		90	{
		91	SPI_TypeDef Instance; /!< I2S registers base address */
		92
		93	I2S_InitTypeDef Init; /!< I2S communication parameters /
		94
		95	uint16_t pTxBuffPtr; /!< Pointer to I2S Tx transfer buffer */
		96
		97	__IO uint16_t TxXferSize; /!< I2S Tx transfer size /
		98
		99	__IO uint16_t TxXferCount; /!< I2S Tx transfer Counter /
		100
		101	uint16_t pRxBuffPtr; /!< Pointer to I2S Rx transfer buffer */
		102
		103	__IO uint16_t RxXferSize; /!< I2S Rx transfer size /
		104
		105	__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
		106	(This field is initialized at the
		107	same value as transfer size at the
		108	beginning of the transfer and
		109	decremented when a sample is received
		110	NbSamplesReceived = RxBufferSize-RxBufferCount) */
		111	DMA_HandleTypeDef hdmatx; /!< I2S Tx DMA handle parameters */
		112
		113	DMA_HandleTypeDef hdmarx; /!< I2S Rx DMA handle parameters */
		114
		115	__IO HAL_LockTypeDef Lock; /!< I2S locking object /
		116
		117	__IO HAL_I2S_StateTypeDef State; /!< I2S communication state /
		118
		119	__IO uint32_t ErrorCode; /*!< I2S Error code
		120	This parameter can be a value of @ref I2S_Error */
		121
		122	#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
		123	void (* TxCpltCallback)(struct __I2S_HandleTypeDef hi2s); /!< I2S Tx Completed callback */
		124	void (* RxCpltCallback)(struct __I2S_HandleTypeDef hi2s); /!< I2S Rx Completed callback */
		125	void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef hi2s); /!< I2S Tx Half Completed callback */
		126	void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef hi2s); /!< I2S Rx Half Completed callback */
		127	void (* ErrorCallback)(struct __I2S_HandleTypeDef hi2s); /!< I2S Error callback */
		128	void (* MspInitCallback)(struct __I2S_HandleTypeDef hi2s); /!< I2S Msp Init callback */
		129	void (* MspDeInitCallback)(struct __I2S_HandleTypeDef hi2s); /!< I2S Msp DeInit callback */
		130
		131	#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
		132	} I2S_HandleTypeDef;
		133
		134	#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
		135	/**
		136	* @brief HAL I2S Callback ID enumeration definition
		137	*/
		138	typedef enum
		139	{
		140	HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /!< I2S Tx Completed callback ID /
		141	HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /!< I2S Rx Completed callback ID /
		142	HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /!< I2S Tx Half Completed callback ID /
		143	HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /!< I2S Rx Half Completed callback ID /
		144	HAL_I2S_ERROR_CB_ID = 0x06U, /!< I2S Error callback ID /
		145	HAL_I2S_MSPINIT_CB_ID = 0x07U, /!< I2S Msp Init callback ID /
		146	HAL_I2S_MSPDEINIT_CB_ID = 0x08U /!< I2S Msp DeInit callback ID /
		147
		148	} HAL_I2S_CallbackIDTypeDef;
		149
		150	/**
		151	* @brief HAL I2S Callback pointer definition
		152	*/
		153	typedef void (pI2S_CallbackTypeDef)(I2S_HandleTypeDef hi2s); /!< pointer to an I2S callback function /
		154
		155	#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
		156	/**
		157	* @}
		158	*/
		159
		160	/* Exported constants --------------------------------------------------------*/
		161	/** @defgroup I2S_Exported_Constants I2S Exported Constants
		162	* @{
		163	*/
		164	/** @defgroup I2S_Error I2S Error
		165	* @{
		166	*/
		167	#define HAL_I2S_ERROR_NONE (0x00000000U) /!< No error /
		168	#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /!< Timeout error /
		169	#define HAL_I2S_ERROR_OVR (0x00000002U) /!< OVR error /
		170	#define HAL_I2S_ERROR_UDR (0x00000004U) /!< UDR error /
		171	#define HAL_I2S_ERROR_DMA (0x00000008U) /!< DMA transfer error /
		172	#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /!< Prescaler Calculation error /
		173	#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
		174	#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /!< Invalid Callback error /
		175	#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
		176	#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /!< Busy Rx Line error /
		177	/**
		178	* @}
		179	*/
		180
		181	/** @defgroup I2S_Mode I2S Mode
		182	* @{
		183	*/
		184	#define I2S_MODE_SLAVE_TX (0x00000000U)
		185	#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
		186	#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
		187	#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1))
		188	/**
		189	* @}
		190	*/
		191
		192	/** @defgroup I2S_Standard I2S Standard
		193	* @{
		194	*/
		195	#define I2S_STANDARD_PHILIPS (0x00000000U)
		196	#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
		197	#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
		198	#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1))
		199	#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC))
		200	/**
		201	* @}
		202	*/
		203
		204	/** @defgroup I2S_Data_Format I2S Data Format
		205	* @{
		206	*/
		207	#define I2S_DATAFORMAT_16B (0x00000000U)
		208	#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
		209	#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0))
		210	#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1))
		211	/**
		212	* @}
		213	*/
		214
		215	/** @defgroup I2S_MCLK_Output I2S MCLK Output
		216	* @{
		217	*/
		218	#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
		219	#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
		220	/**
		221	* @}
		222	*/
		223
		224	/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
		225	* @{
		226	*/
		227	#define I2S_AUDIOFREQ_192K (192000U)
		228	#define I2S_AUDIOFREQ_96K (96000U)
		229	#define I2S_AUDIOFREQ_48K (48000U)
		230	#define I2S_AUDIOFREQ_44K (44100U)
		231	#define I2S_AUDIOFREQ_32K (32000U)
		232	#define I2S_AUDIOFREQ_22K (22050U)
		233	#define I2S_AUDIOFREQ_16K (16000U)
		234	#define I2S_AUDIOFREQ_11K (11025U)
		235	#define I2S_AUDIOFREQ_8K (8000U)
		236	#define I2S_AUDIOFREQ_DEFAULT (2U)
		237	/**
		238	* @}
		239	*/
		240
		241	/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
		242	* @{
		243	*/
		244	#define I2S_CPOL_LOW (0x00000000U)
		245	#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
		246	/**
		247	* @}
		248	*/
		249
		250	/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
		251	* @{
		252	*/
		253	#define I2S_IT_TXE SPI_CR2_TXEIE
		254	#define I2S_IT_RXNE SPI_CR2_RXNEIE
		255	#define I2S_IT_ERR SPI_CR2_ERRIE
		256	/**
		257	* @}
		258	*/
		259
		260	/** @defgroup I2S_Flags_Definition I2S Flags Definition
		261	* @{
		262	*/
		263	#define I2S_FLAG_TXE SPI_SR_TXE
		264	#define I2S_FLAG_RXNE SPI_SR_RXNE
		265
		266	#define I2S_FLAG_UDR SPI_SR_UDR
		267	#define I2S_FLAG_OVR SPI_SR_OVR
		268	#define I2S_FLAG_FRE SPI_SR_FRE
		269
		270	#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
		271	#define I2S_FLAG_BSY SPI_SR_BSY
		272
		273	#define I2S_FLAG_MASK (SPI_SR_RXNE\
		274	\| SPI_SR_TXE \| SPI_SR_UDR \| SPI_SR_OVR \| SPI_SR_CHSIDE \| SPI_SR_BSY)
		275	/**
		276	* @}
		277	*/
		278
		279	/**
		280	* @}
		281	*/
		282
		283	/* Exported macros -----------------------------------------------------------*/
		284	/** @defgroup I2S_Exported_macros I2S Exported Macros
		285	* @{
		286	*/
		287
		288	/** @brief Reset I2S handle state
		289	* @param __HANDLE__ specifies the I2S Handle.
		290	* @retval None
		291	*/
		292	#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
		293	#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
		294	(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
		295	(__HANDLE__)->MspInitCallback = NULL; \
		296	(__HANDLE__)->MspDeInitCallback = NULL; \
		297	} while(0)
		298	#else
		299	#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
		300	#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
		301
		302	/** @brief Enable the specified SPI peripheral (in I2S mode).
		303	* @param __HANDLE__ specifies the I2S Handle.
		304	* @retval None
		305	*/
		306	#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
		307
		308	/** @brief Disable the specified SPI peripheral (in I2S mode).
		309	* @param __HANDLE__ specifies the I2S Handle.
		310	* @retval None
		311	*/
		312	#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
		313
		314	/** @brief Enable the specified I2S interrupts.
		315	* @param __HANDLE__ specifies the I2S Handle.
		316	* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
		317	* This parameter can be one of the following values:
		318	* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
		319	* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
		320	* @arg I2S_IT_ERR: Error interrupt enable
		321	* @retval None
		322	*/
		323	#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
		324
		325	/** @brief Disable the specified I2S interrupts.
		326	* @param __HANDLE__ specifies the I2S Handle.
		327	* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
		328	* This parameter can be one of the following values:
		329	* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
		330	* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
		331	* @arg I2S_IT_ERR: Error interrupt enable
		332	* @retval None
		333	*/
		334	#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
		335
		336	/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
		337	* @param __HANDLE__ specifies the I2S Handle.
		338	* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
		339	* @param __INTERRUPT__ specifies the I2S interrupt source to check.
		340	* This parameter can be one of the following values:
		341	* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
		342	* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
		343	* @arg I2S_IT_ERR: Error interrupt enable
		344	* @retval The new state of __IT__ (TRUE or FALSE).
		345	*/
		346	#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
		347	& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
		348
		349	/** @brief Checks whether the specified I2S flag is set or not.
		350	* @param __HANDLE__ specifies the I2S Handle.
		351	* @param __FLAG__ specifies the flag to check.
		352	* This parameter can be one of the following values:
		353	* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
		354	* @arg I2S_FLAG_TXE: Transmit buffer empty flag
		355	* @arg I2S_FLAG_UDR: Underrun flag
		356	* @arg I2S_FLAG_OVR: Overrun flag
		357	* @arg I2S_FLAG_FRE: Frame error flag
		358	* @arg I2S_FLAG_CHSIDE: Channel Side flag
		359	* @arg I2S_FLAG_BSY: Busy flag
		360	* @retval The new state of __FLAG__ (TRUE or FALSE).
		361	*/
		362	#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
		363
		364	/** @brief Clears the I2S OVR pending flag.
		365	* @param __HANDLE__ specifies the I2S Handle.
		366	* @retval None
		367	*/
		368	#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
		369	__IO uint32_t tmpreg_ovr = 0x00U; \
		370	tmpreg_ovr = (__HANDLE__)->Instance->DR; \
		371	tmpreg_ovr = (__HANDLE__)->Instance->SR; \
		372	UNUSED(tmpreg_ovr); \
		373	}while(0U)
		374	/** @brief Clears the I2S UDR pending flag.
		375	* @param __HANDLE__ specifies the I2S Handle.
		376	* @retval None
		377	*/
		378	#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
		379	__IO uint32_t tmpreg_udr = 0x00U;\
		380	tmpreg_udr = ((__HANDLE__)->Instance->SR);\
		381	UNUSED(tmpreg_udr); \
		382	}while(0U)
		383	/** @brief Flush the I2S DR Register.
		384	* @param __HANDLE__ specifies the I2S Handle.
		385	* @retval None
		386	*/
		387	#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
		388	__IO uint32_t tmpreg_dr = 0x00U;\
		389	tmpreg_dr = ((__HANDLE__)->Instance->DR);\
		390	UNUSED(tmpreg_dr); \
		391	}while(0U)
		392	/**
		393	* @}
		394	*/
		395
		396	/* Exported functions --------------------------------------------------------*/
		397	/** @addtogroup I2S_Exported_Functions
		398	* @{
		399	*/
		400
		401	/** @addtogroup I2S_Exported_Functions_Group1
		402	* @{
		403	*/
		404	/* Initialization/de-initialization functions ********************************/
		405	HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
		406	HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
		407	void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
		408	void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
		409
		410	/* Callbacks Register/UnRegister functions ***********************************/
		411	#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
		412	HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
		413	pI2S_CallbackTypeDef pCallback);
		414	HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
		415	#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
		416	/**
		417	* @}
		418	*/
		419
		420	/** @addtogroup I2S_Exported_Functions_Group2
		421	* @{
		422	*/
		423	/* I/O operation functions ***************************************************/
		424	/* Blocking mode: Polling */
		425	HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout);
		426	HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout);
		427
		428	/* Non-Blocking mode: Interrupt */
		429	HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size);
		430	HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size);
		431	void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
		432
		433	/* Non-Blocking mode: DMA */
		434	HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size);
		435	HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size);
		436
		437	HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
		438	HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
		439	HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
		440
		441	/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
		442	void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
		443	void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
		444	void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
		445	void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
		446	void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
		447	/**
		448	* @}
		449	*/
		450
		451	/** @addtogroup I2S_Exported_Functions_Group3
		452	* @{
		453	*/
		454	/* Peripheral Control and State functions ************************************/
		455	HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
		456	uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
		457	/**
		458	* @}
		459	*/
		460
		461	/**
		462	* @}
		463	*/
		464
		465	/* Private types -------------------------------------------------------------*/
		466	/* Private variables ---------------------------------------------------------*/
		467	/* Private constants ---------------------------------------------------------*/
		468	/* Private macros ------------------------------------------------------------*/
		469	/** @defgroup I2S_Private_Macros I2S Private Macros
		470	* @{
		471	*/
		472
		473	/** @brief Check whether the specified SPI flag is set or not.
		474	* @param __SR__ copy of I2S SR register.
		475	* @param __FLAG__ specifies the flag to check.
		476	* This parameter can be one of the following values:
		477	* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
		478	* @arg I2S_FLAG_TXE: Transmit buffer empty flag
		479	* @arg I2S_FLAG_UDR: Underrun error flag
		480	* @arg I2S_FLAG_OVR: Overrun flag
		481	* @arg I2S_FLAG_CHSIDE: Channel side flag
		482	* @arg I2S_FLAG_BSY: Busy flag
		483	* @retval SET or RESET.
		484	*/
		485	#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
		486	& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
		487
		488	/** @brief Check whether the specified SPI Interrupt is set or not.
		489	* @param __CR2__ copy of I2S CR2 register.
		490	* @param __INTERRUPT__ specifies the SPI interrupt source to check.
		491	* This parameter can be one of the following values:
		492	* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
		493	* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
		494	* @arg I2S_IT_ERR: Error interrupt enable
		495	* @retval SET or RESET.
		496	*/
		497	#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
		498	& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
		499
		500	/** @brief Checks if I2S Mode parameter is in allowed range.
		501	* @param __MODE__ specifies the I2S Mode.
		502	* This parameter can be a value of @ref I2S_Mode
		503	* @retval None
		504	*/
		505	#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) \|\| \
		506	((__MODE__) == I2S_MODE_SLAVE_RX) \|\| \
		507	((__MODE__) == I2S_MODE_MASTER_TX) \|\| \
		508	((__MODE__) == I2S_MODE_MASTER_RX))
		509
		510	#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) \|\| \
		511	((__STANDARD__) == I2S_STANDARD_MSB) \|\| \
		512	((__STANDARD__) == I2S_STANDARD_LSB) \|\| \
		513	((__STANDARD__) == I2S_STANDARD_PCM_SHORT) \|\| \
		514	((__STANDARD__) == I2S_STANDARD_PCM_LONG))
		515
		516	#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) \|\| \
		517	((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) \|\| \
		518	((__FORMAT__) == I2S_DATAFORMAT_24B) \|\| \
		519	((__FORMAT__) == I2S_DATAFORMAT_32B))
		520
		521	#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) \|\| \
		522	((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
		523
		524	#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
		525	((__FREQ__) <= I2S_AUDIOFREQ_192K)) \|\| \
		526	((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
		527
		528	/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
		529	* @param __CPOL__ specifies the I2S serial clock steady state.
		530	* This parameter can be a value of @ref I2S_Clock_Polarity
		531	* @retval None
		532	*/
		533	#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) \|\| \
		534	((__CPOL__) == I2S_CPOL_HIGH))
		535
		536	/**
		537	* @}
		538	*/
		539
		540	/**
		541	* @}
		542	*/
		543
		544	/**
		545	* @}
		546	*/
		547	#endif /* SPI_I2S_SUPPORT */
		548
		549	#ifdef __cplusplus
		550	}
		551	#endif
		552
		553	#endif /* STM32F1xx_HAL_I2S_H */
		554

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h – Rev 2