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/**

  ******************************************************************************

  * @file    stm32f1xx_hal_eth.h

  * @author  MCD Application Team

  * @version V1.0.4

  * @date    29-April-2016

  * @brief   Header file of ETH HAL module.

  ******************************************************************************

  * @attention

  *

  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

  *

  * Redistribution and use in source and binary forms, with or without modification,

  * are permitted provided that the following conditions are met:

  *   1. Redistributions of source code must retain the above copyright notice,

  *      this list of conditions and the following disclaimer.

  *   2. Redistributions in binary form must reproduce the above copyright notice,

  *      this list of conditions and the following disclaimer in the documentation

  *      and/or other materials provided with the distribution.

  *   3. Neither the name of STMicroelectronics nor the names of its contributors

  *      may be used to endorse or promote products derived from this software

  *      without specific prior written permission.

  *

  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  *

  ******************************************************************************

  */

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef __STM32F1xx_HAL_ETH_H

#define __STM32F1xx_HAL_ETH_H

#ifdef __cplusplus

 extern "C" {

#endif

/* Includes ------------------------------------------------------------------*/

#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver

  * @{

  */

#if defined (STM32F107xC) 

/** @addtogroup ETH

  * @{

  */

/** @addtogroup ETH_Private_Macros

  * @{

  */

#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)

#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \

                                     ((CMD) == ETH_AUTONEGOTIATION_DISABLE))

#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \

                             ((SPEED) == ETH_SPEED_100M))

#define IS_ETH_DUPLEX_MODE(MODE)  (((MODE) == ETH_MODE_FULLDUPLEX) || \

                                  ((MODE) == ETH_MODE_HALFDUPLEX))

#define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \

                                 ((MODE) == ETH_RXINTERRUPT_MODE))

#define IS_ETH_CHECKSUM_MODE(MODE)    (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \

                                      ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))

#define IS_ETH_MEDIA_INTERFACE(MODE)         (((MODE) == ETH_MEDIA_INTERFACE_MII) || \

                                              ((MODE) == ETH_MEDIA_INTERFACE_RMII))

#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \

                              ((CMD) == ETH_WATCHDOG_DISABLE))

#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \

                            ((CMD) == ETH_JABBER_DISABLE))

#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \

                                     ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \

                                     ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \

                                     ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \

                                     ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \

                                     ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \

                                     ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \

                                     ((GAP) == ETH_INTERFRAMEGAP_40BIT))

#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \

                                   ((CMD) == ETH_CARRIERSENCE_DISABLE))

#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \

                                 ((CMD) == ETH_RECEIVEOWN_DISABLE))

#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \

                                   ((CMD) == ETH_LOOPBACKMODE_DISABLE))

#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \

                                      ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))

#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \

                                        ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))

#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \

                                            ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))

#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \

                                     ((LIMIT) == ETH_BACKOFFLIMIT_8) || \

                                     ((LIMIT) == ETH_BACKOFFLIMIT_4) || \

                                     ((LIMIT) == ETH_BACKOFFLIMIT_1))

#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \

                                    ((CMD) == ETH_DEFFERRALCHECK_DISABLE))

#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \

                                 ((CMD) == ETH_RECEIVEAll_DISABLE))

#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \

                                        ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \

                                        ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))

#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \

                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \

                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))

#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \

                                                ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))

#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \

                                                ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))

#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \

                                      ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))

#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \

                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \

                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \

                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))

#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \

                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \

                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))

#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)

#define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \

                                        ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))

#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \

                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \

                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \

                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))

#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \

                                                ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))

#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \

                                         ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))

#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \

                                          ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))

#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \

                                                ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))

#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)

#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \

                                         ((ADDRESS) == ETH_MAC_ADDRESS1) || \

                                         ((ADDRESS) == ETH_MAC_ADDRESS2) || \

                                         ((ADDRESS) == ETH_MAC_ADDRESS3))

#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \

                                        ((ADDRESS) == ETH_MAC_ADDRESS2) || \

                                        ((ADDRESS) == ETH_MAC_ADDRESS3))

#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \

                                           ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))

#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \

                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \

                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \

                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \

                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \

                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))

#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \

                                               ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))

#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \

                                           ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))

#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \

                                         ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))

#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \

                                            ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))

#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \

                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \

                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \

                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \

                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \

                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \

                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \

                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))

#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \

                                          ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))

#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \

                                                    ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))

#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \

                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \

                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \

                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))

#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \

                                          ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))

#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \

                                           ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))

#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \

                                 ((CMD) == ETH_FIXEDBURST_DISABLE))

#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \

                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))

#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \

                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))

#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)

#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \

                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \

                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \

                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \

                                                       ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))

#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \

                                            ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))

#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \

                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \

                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \

                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))

#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)

#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \

                                          ((BUFFER) == ETH_DMARXDESC_BUFFER2))

#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \

                                           ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))

/**

  * @}

  */

/** @addtogroup ETH_Private_Constants

  * @{

  */

/* Delay to wait when writing to some Ethernet registers */

#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)

/* ETHERNET Errors */

#define  ETH_SUCCESS            ((uint32_t)0)

#define  ETH_ERROR              ((uint32_t)1)

/* ETHERNET DMA Tx descriptors Collision Count Shift */

#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT         ((uint32_t)3)

/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */

#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)

/* ETHERNET DMA Rx descriptors Frame Length Shift */

#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           ((uint32_t)16)

/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */

#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)

/* ETHERNET DMA Rx descriptors Frame length Shift */

#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            ((uint32_t)16)

/* ETHERNET MAC address offsets */

#define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40)  /* ETHERNET MAC address high offset */

#define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44)  /* ETHERNET MAC address low offset */

/* ETHERNET MACMIIAR register Mask */

#define ETH_MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3)

/* ETHERNET MACCR register Mask */

#define ETH_MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)  

/* ETHERNET MACFCR register Mask */

#define ETH_MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)

/* ETHERNET DMAOMR register Mask */

#define ETH_DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)

/* ETHERNET Remote Wake-up frame register length */

#define ETH_WAKEUP_REGISTER_LENGTH      8

/* ETHERNET Missed frames counter Shift */

#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17

 /**

  * @}

  */

/* Exported types ------------------------------------------------------------*/

/** @defgroup ETH_Exported_Types ETH Exported Types

  * @{

  */

/**

  * @brief  HAL State structures definition  

  */

typedef enum

{

  HAL_ETH_STATE_RESET             = 0x00,    /*!< Peripheral not yet Initialized or disabled         */

  HAL_ETH_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */

  HAL_ETH_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */

  HAL_ETH_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */

  HAL_ETH_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */

  HAL_ETH_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */

  HAL_ETH_STATE_BUSY_WR           = 0x42,    /*!< Write process is ongoing                           */

  HAL_ETH_STATE_BUSY_RD           = 0x82,    /*!< Read process is ongoing                            */

  HAL_ETH_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */

  HAL_ETH_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                       */

}HAL_ETH_StateTypeDef;

/**

  * @brief  ETH Init Structure definition  

  */

typedef struct

{

  uint32_t             AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY

                                                           The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)

                                                           and the mode (half/full-duplex).

                                                           This parameter can be a value of @ref ETH_AutoNegotiation */

  uint32_t             Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps.

                                                           This parameter can be a value of @ref ETH_Speed */

  uint32_t             DuplexMode;                /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode

                                                           This parameter can be a value of @ref ETH_Duplex_Mode */

  uint16_t             PhyAddress;                /*!< Ethernet PHY address.

                                                           This parameter must be a number between Min_Data = 0 and Max_Data = 32 */

  uint8_t             *MACAddr;                   /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */

  uint32_t             RxMode;                    /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.

                                                           This parameter can be a value of @ref ETH_Rx_Mode */

  uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software.

                                                         This parameter can be a value of @ref ETH_Checksum_Mode */

  uint32_t             MediaInterface    ;               /*!< Selects the media-independent interface or the reduced media-independent interface.

                                                         This parameter can be a value of @ref ETH_Media_Interface */

} ETH_InitTypeDef;

 /**

  * @brief  ETH MAC Configuration Structure definition  

  */

typedef struct

{

  uint32_t             Watchdog;                  /*!< Selects or not the Watchdog timer

                                                           When enabled, the MAC allows no more then 2048 bytes to be received.

                                                           When disabled, the MAC can receive up to 16384 bytes.

                                                           This parameter can be a value of @ref ETH_Watchdog */  

  uint32_t             Jabber;                    /*!< Selects or not Jabber timer

                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.

                                                           When disabled, the MAC can send up to 16384 bytes.

                                                           This parameter can be a value of @ref ETH_Jabber */

  uint32_t             InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission.

                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */  

  uint32_t             CarrierSense;              /*!< Selects or not the Carrier Sense.

                                                           This parameter can be a value of @ref ETH_Carrier_Sense */

  uint32_t             ReceiveOwn;                /*!< Selects or not the ReceiveOwn,

                                                           ReceiveOwn allows the reception of frames when the TX_EN signal is asserted

                                                           in Half-Duplex mode.

                                                           This parameter can be a value of @ref ETH_Receive_Own */  

  uint32_t             LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode.

                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */  

  uint32_t             ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.

                                                           This parameter can be a value of @ref ETH_Checksum_Offload */    

  uint32_t             RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,

                                                           when a collision occurs (Half-Duplex mode).

                                                           This parameter can be a value of @ref ETH_Retry_Transmission */

  uint32_t             AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping.

                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */

  uint32_t             BackOffLimit;              /*!< Selects the BackOff limit value.

                                                           This parameter can be a value of @ref ETH_Back_Off_Limit */

  uint32_t             DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode).

                                                           This parameter can be a value of @ref ETH_Deferral_Check */                                                                                                        

  uint32_t             ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering).

                                                           This parameter can be a value of @ref ETH_Receive_All */  

  uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.                                                          

                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */                  

  uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)                                                          

                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */

  uint32_t             BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames.

                                                           This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */

  uint32_t             DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames.

                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */

  uint32_t             PromiscuousMode;           /*!< Selects or not the Promiscuous Mode

                                                           This parameter can be a value of @ref ETH_Promiscuous_Mode */

  uint32_t             MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.

                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */

  uint32_t             UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.

                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */

  uint32_t             HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.

                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */

  uint32_t             HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.

                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF  */    

  uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.

                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */

  uint32_t             ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.

                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */  

  uint32_t             PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for

                                                           automatic retransmission of PAUSE Frame.

                                                           This parameter can be a value of @ref ETH_Pause_Low_Threshold */

  uint32_t             UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0

                                                           unicast address and unique multicast address).

                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */  

  uint32_t             ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and

                                                           disable its transmitter for a specified time (Pause Time)

                                                           This parameter can be a value of @ref ETH_Receive_Flow_Control */

  uint32_t             TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)

                                                           or the MAC back-pressure operation (Half-Duplex mode)

                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */    

  uint32_t             VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for

                                                           comparison and filtering.

                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */

  uint32_t             VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */

} ETH_MACInitTypeDef;

/**

  * @brief  ETH DMA Configuration Structure definition  

  */

typedef struct

{

 uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.

                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */

  uint32_t             ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.

                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */

  uint32_t             FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.

                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */

  uint32_t             TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.

                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */

  uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.

                                                             This parameter can be a value of @ref ETH_Transmit_Threshold_Control */

  uint32_t             ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames.

                                                             This parameter can be a value of @ref ETH_Forward_Error_Frames */

  uint32_t             ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error

                                                             and length less than 64 bytes) including pad-bytes and CRC)

                                                             This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */

  uint32_t             ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.

                                                             This parameter can be a value of @ref ETH_Receive_Threshold_Control */

  uint32_t             SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second

                                                             frame of Transmit data even before obtaining the status for the first frame.

                                                             This parameter can be a value of @ref ETH_Second_Frame_Operate */

  uint32_t             AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats.

                                                             This parameter can be a value of @ref ETH_Address_Aligned_Beats */

  uint32_t             FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.

                                                             This parameter can be a value of @ref ETH_Fixed_Burst */

  uint32_t             RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.

                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */

  uint32_t             TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.

                                                             This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */

  uint32_t             DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)

                                                             This parameter must be a number between Min_Data = 0 and Max_Data = 32 */                                                            

  uint32_t             DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.

                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  

} ETH_DMAInitTypeDef;

/**

  * @brief  ETH DMA Descriptors data structure definition

  */

typedef struct  

{

  __IO uint32_t   Status;           /*!< Status */

  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */

  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */

  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */

} ETH_DMADescTypeDef;

/**

  * @brief  Received Frame Informations structure definition

  */

typedef struct  

{

  ETH_DMADescTypeDef *FSRxDesc;          /*!< First Segment Rx Desc */

  ETH_DMADescTypeDef *LSRxDesc;          /*!< Last Segment Rx Desc */

  uint32_t  SegCount;                    /*!< Segment count */

  uint32_t length;                       /*!< Frame length */

  uint32_t buffer;                       /*!< Frame buffer */

} ETH_DMARxFrameInfos;

/**

  * @brief  ETH Handle Structure definition  

  */

typedef struct

{

  ETH_TypeDef                *Instance;     /*!< Register base address       */

  ETH_InitTypeDef            Init;          /*!< Ethernet Init Configuration */

  uint32_t                   LinkStatus;    /*!< Ethernet link status        */

  ETH_DMADescTypeDef         *RxDesc;       /*!< Rx descriptor to Get        */

  ETH_DMADescTypeDef         *TxDesc;       /*!< Tx descriptor to Set        */

  ETH_DMARxFrameInfos        RxFrameInfos;  /*!< last Rx frame infos         */

  __IO HAL_ETH_StateTypeDef  State;         /*!< ETH communication state     */

  HAL_LockTypeDef            Lock;          /*!< ETH Lock                    */

} ETH_HandleTypeDef;

 /**

  * @}

  */

/* Exported constants --------------------------------------------------------*/

/** @defgroup ETH_Exported_Constants ETH Exported Constants

  * @{

  */

/** @defgroup ETH_Buffers_setting ETH Buffers setting

  * @{

  */

#define ETH_MAX_PACKET_SIZE    ((uint32_t)1524)    /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */

#define ETH_HEADER               ((uint32_t)14)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */

#define ETH_CRC                   ((uint32_t)4)    /*!< Ethernet CRC */

#define ETH_EXTRA                 ((uint32_t)2)    /*!< Extra bytes in some cases */   

#define ETH_VLAN_TAG                  ((uint32_t)4)    /*!< optional 802.1q VLAN Tag */

#define ETH_MIN_ETH_PAYLOAD          ((uint32_t)46)    /*!< Minimum Ethernet payload size */

#define ETH_MAX_ETH_PAYLOAD        ((uint32_t)1500)    /*!< Maximum Ethernet payload size */

#define ETH_JUMBO_FRAME_PAYLOAD    ((uint32_t)9000)    /*!< Jumbo frame payload size */      

 /* Ethernet driver receive buffers are organized in a chained linked-list, when

    an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO

    to the driver receive buffers memory.

    Depending on the size of the received ethernet packet and the size of

    each ethernet driver receive buffer, the received packet can take one or more

    ethernet driver receive buffer.

    In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE

    and the total count of the driver receive buffers ETH_RXBUFNB.

    The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as

    example, they can be reconfigured in the application layer to fit the application

    needs */

/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet

   packet */

#ifndef ETH_RX_BUF_SIZE

 #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE 

#endif

/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/

#ifndef ETH_RXBUFNB

 #define ETH_RXBUFNB             ((uint32_t)5     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */

#endif

 /* Ethernet driver transmit buffers are organized in a chained linked-list, when

    an ethernet packet is transmitted, Tx-DMA will transfer the packet from the

    driver transmit buffers memory to the TxFIFO.

    Depending on the size of the Ethernet packet to be transmitted and the size of

    each ethernet driver transmit buffer, the packet to be transmitted can take

    one or more ethernet driver transmit buffer.

    In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE

    and the total count of the driver transmit buffers ETH_TXBUFNB.

    The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as

    example, they can be reconfigured in the application layer to fit the application

    needs */

/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet

   packet */

#ifndef ETH_TX_BUF_SIZE 

 #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE

#endif

/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/

#ifndef ETH_TXBUFNB

 #define ETH_TXBUFNB             ((uint32_t)5      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */

#endif

 /**

  * @}

  */

/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor

  * @{

  */

/*

   DMA Tx Desciptor

  -----------------------------------------------------------------------------------------------

  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |

  -----------------------------------------------------------------------------------------------

  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |

  -----------------------------------------------------------------------------------------------

  TDES2 |                         Buffer1 Address [31:0]                                         |

  -----------------------------------------------------------------------------------------------

  TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |

  -----------------------------------------------------------------------------------------------

*/

/**

  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register

  */

#define ETH_DMATXDESC_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */

#define ETH_DMATXDESC_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */

#define ETH_DMATXDESC_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */

#define ETH_DMATXDESC_FS                      ((uint32_t)0x10000000)  /*!< First Segment */

#define ETH_DMATXDESC_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */

#define ETH_DMATXDESC_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */

#define ETH_DMATXDESC_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */

#define ETH_DMATXDESC_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */

#define ETH_DMATXDESC_CIC_BYPASS              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */ 

#define ETH_DMATXDESC_CIC_IPV4HEADER          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */ 

#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 

#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 

#define ETH_DMATXDESC_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */

#define ETH_DMATXDESC_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */

#define ETH_DMATXDESC_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */

#define ETH_DMATXDESC_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */

#define ETH_DMATXDESC_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */

#define ETH_DMATXDESC_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */

#define ETH_DMATXDESC_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */

#define ETH_DMATXDESC_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */

#define ETH_DMATXDESC_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during transmission */

#define ETH_DMATXDESC_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the transceiver */

#define ETH_DMATXDESC_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */

#define ETH_DMATXDESC_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */

#define ETH_DMATXDESC_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */

#define ETH_DMATXDESC_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */

#define ETH_DMATXDESC_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */

#define ETH_DMATXDESC_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */

#define ETH_DMATXDESC_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */

/**

  * @brief  Bit definition of TDES1 register

  */

#define ETH_DMATXDESC_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */

#define ETH_DMATXDESC_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */

/**

  * @brief  Bit definition of TDES2 register

  */

#define ETH_DMATXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */

/**

  * @brief  Bit definition of TDES3 register

  */

#define ETH_DMATXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */

/**

  * @}

  */

/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor

  * @{

  */

/*

  DMA Rx Descriptor

  --------------------------------------------------------------------------------------------------------------------

  RDES0 | OWN(31) |                                             Status [30:0]                                          |

  ---------------------------------------------------------------------------------------------------------------------

  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |

  ---------------------------------------------------------------------------------------------------------------------

  RDES2 |                                       Buffer1 Address [31:0]                                                 |

  ---------------------------------------------------------------------------------------------------------------------

  RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |

  ---------------------------------------------------------------------------------------------------------------------

*/

/**

  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register

  */

#define ETH_DMARXDESC_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */

#define ETH_DMARXDESC_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */

#define ETH_DMARXDESC_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */

#define ETH_DMARXDESC_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */

#define ETH_DMARXDESC_DE          ((uint32_t)0x00004000)  /*!< Descriptor error: no more descriptors for receive frame  */

#define ETH_DMARXDESC_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */

#define ETH_DMARXDESC_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */

#define ETH_DMARXDESC_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */

#define ETH_DMARXDESC_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */

#define ETH_DMARXDESC_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */

#define ETH_DMARXDESC_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */ 

#define ETH_DMARXDESC_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    

#define ETH_DMARXDESC_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */

#define ETH_DMARXDESC_FT          ((uint32_t)0x00000020)  /*!< Frame type - Ethernet, otherwise 802.3    */

#define ETH_DMARXDESC_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */

#define ETH_DMARXDESC_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */

#define ETH_DMARXDESC_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */

#define ETH_DMARXDESC_CE          ((uint32_t)0x00000002)  /*!< CRC error */

#define ETH_DMARXDESC_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */

/**

  * @brief  Bit definition of RDES1 register

  */

#define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */

#define ETH_DMARXDESC_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */

#define ETH_DMARXDESC_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */

#define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */

#define ETH_DMARXDESC_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */

/**

  * @brief  Bit definition of RDES2 register  

  */

#define ETH_DMARXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */

/**

  * @brief  Bit definition of RDES3 register  

  */

#define ETH_DMARXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */

/**

  * @}

  */

 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation

  * @{

  */

#define ETH_AUTONEGOTIATION_ENABLE     ((uint32_t)0x00000001)

#define ETH_AUTONEGOTIATION_DISABLE    ((uint32_t)0x00000000)

/**

  * @}

  */

/** @defgroup ETH_Speed ETH Speed

  * @{

  */

#define ETH_SPEED_10M        ((uint32_t)0x00000000)

#define ETH_SPEED_100M       ((uint32_t)0x00004000)

/**

  * @}

  */

/** @defgroup ETH_Duplex_Mode ETH Duplex Mode

  * @{

  */

#define ETH_MODE_FULLDUPLEX       ((uint32_t)0x00000800)

#define ETH_MODE_HALFDUPLEX       ((uint32_t)0x00000000)

/**

  * @}

  */

/** @defgroup ETH_Rx_Mode ETH Rx Mode

  * @{

  */

#define ETH_RXPOLLING_MODE      ((uint32_t)0x00000000)

#define ETH_RXINTERRUPT_MODE    ((uint32_t)0x00000001)

/**

  * @}

  */

/** @defgroup ETH_Checksum_Mode ETH Checksum Mode

  * @{

  */

#define ETH_CHECKSUM_BY_HARDWARE      ((uint32_t)0x00000000)

#define ETH_CHECKSUM_BY_SOFTWARE      ((uint32_t)0x00000001)

/**

  * @}

  */

/** @defgroup ETH_Media_Interface ETH Media Interface

  * @{

  */

#define ETH_MEDIA_INTERFACE_MII       ((uint32_t)0x00000000)

#define ETH_MEDIA_INTERFACE_RMII      ((uint32_t)AFIO_MAPR_MII_RMII_SEL)

/**

  * @}

  */

/** @defgroup ETH_Watchdog ETH Watchdog

  * @{

  */

#define ETH_WATCHDOG_ENABLE       ((uint32_t)0x00000000)

#define ETH_WATCHDOG_DISABLE      ((uint32_t)0x00800000)

/**

  * @}

  */

/** @defgroup ETH_Jabber ETH Jabber

  * @{

  */

#define ETH_JABBER_ENABLE    ((uint32_t)0x00000000)

#define ETH_JABBER_DISABLE   ((uint32_t)0x00400000)

/**

  * @}

  */

/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap

  * @{

  */

#define ETH_INTERFRAMEGAP_96BIT   ((uint32_t)0x00000000)  /*!< minimum IFG between frames during transmission is 96Bit */

#define ETH_INTERFRAMEGAP_88BIT   ((uint32_t)0x00020000)  /*!< minimum IFG between frames during transmission is 88Bit */

#define ETH_INTERFRAMEGAP_80BIT   ((uint32_t)0x00040000)  /*!< minimum IFG between frames during transmission is 80Bit */

#define ETH_INTERFRAMEGAP_72BIT   ((uint32_t)0x00060000)  /*!< minimum IFG between frames during transmission is 72Bit */

#define ETH_INTERFRAMEGAP_64BIT   ((uint32_t)0x00080000)  /*!< minimum IFG between frames during transmission is 64Bit */

#define ETH_INTERFRAMEGAP_56BIT   ((uint32_t)0x000A0000)  /*!< minimum IFG between frames during transmission is 56Bit */

#define ETH_INTERFRAMEGAP_48BIT   ((uint32_t)0x000C0000)  /*!< minimum IFG between frames during transmission is 48Bit */

#define ETH_INTERFRAMEGAP_40BIT   ((uint32_t)0x000E0000)  /*!< minimum IFG between frames during transmission is 40Bit */

/**

  * @}

  */

/** @defgroup ETH_Carrier_Sense ETH Carrier Sense

  * @{

  */

#define ETH_CARRIERSENCE_ENABLE   ((uint32_t)0x00000000)

#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)

/**

  * @}

  */

/** @defgroup ETH_Receive_Own ETH Receive Own

  * @{

  */

#define ETH_RECEIVEOWN_ENABLE     ((uint32_t)0x00000000)

#define ETH_RECEIVEOWN_DISABLE   ((uint32_t)0x00002000)

/**

  * @}

  */

/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode

  * @{

  */

#define ETH_LOOPBACKMODE_ENABLE        ((uint32_t)0x00001000)

#define ETH_LOOPBACKMODE_DISABLE       ((uint32_t)0x00000000)

/**

  * @}

  */

/** @defgroup ETH_Checksum_Offload ETH Checksum Offload

  * @{

  */

#define ETH_CHECKSUMOFFLAOD_ENABLE     ((uint32_t)0x00000400)

#define ETH_CHECKSUMOFFLAOD_DISABLE    ((uint32_t)0x00000000)

/**

  * @}

  */

/** @defgroup ETH_Retry_Transmission ETH Retry Transmission

  * @{

  */

#define ETH_RETRYTRANSMISSION_ENABLE   ((uint32_t)0x00000000)

#define ETH_RETRYTRANSMISSION_DISABLE  ((uint32_t)0x00000200)

/**

  * @}

  */

/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip

  * @{

  */

#define ETH_AUTOMATICPADCRCSTRIP_ENABLE     ((uint32_t)0x00000080)

#define ETH_AUTOMATICPADCRCSTRIP_DISABLE    ((uint32_t)0x00000000)

/**

  * @}

  */

/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit

  * @{

  */

#define ETH_BACKOFFLIMIT_10  ((uint32_t)0x00000000)

#define ETH_BACKOFFLIMIT_8   ((uint32_t)0x00000020)

#define ETH_BACKOFFLIMIT_4   ((uint32_t)0x00000040)

#define ETH_BACKOFFLIMIT_1   ((uint32_t)0x00000060)

/**

  * @}

  */

/** @defgroup ETH_Deferral_Check ETH Deferral Check

  * @{

  */

#define ETH_DEFFERRALCHECK_ENABLE       ((uint32_t)0x00000010)

#define ETH_DEFFERRALCHECK_DISABLE      ((uint32_t)0x00000000)

/**

  * @}

  */

/** @defgroup ETH_Receive_All ETH Receive All

  * @{

  */

#define ETH_RECEIVEALL_ENABLE     ((uint32_t)0x80000000)

#define ETH_RECEIVEAll_DISABLE    ((uint32_t)0x00000000)

/**

  * @}

  */

/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter

  * @{

  */

#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       ((uint32_t)0x00000200)

#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      ((uint32_t)0x00000300)

#define ETH_SOURCEADDRFILTER_DISABLE             ((uint32_t)0x00000000)

/**

  * @}

  */

/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames

  * @{

  */

#define ETH_PASSCONTROLFRAMES_BLOCKALL                ((uint32_t)0x00000040)  /*!< MAC filters all control frames from reaching the application */

#define ETH_PASSCONTROLFRAMES_FORWARDALL              ((uint32_t)0x00000080)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */

#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0)  /*!< MAC forwards control frames that pass the Address Filter. */ 

/**

  * @}

  */

/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception

  * @{

  */

#define ETH_BROADCASTFRAMESRECEPTION_ENABLE     ((uint32_t)0x00000000)

#define ETH_BROADCASTFRAMESRECEPTION_DISABLE    ((uint32_t)0x00000020)

/**

  * @}

  */

/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter